LTC2249
1
2249fa
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
■
Sample Rate: 80Msps
■
Single 3V Supply (2.7V to 3.4V)
■
Low Power: 222mW
■
73dB SNR at 70MHz Input
■
90dB SFDR at 70MHz Input
■
No Missing Codes
■
Flexible Input: 1V
P-P
to 2V
P-P
Range
■
575MHz Full Power Bandwidth S/H
■
Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
■
Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
■
32-Pin (5mm × 5mm) QFN Package
14-Bit, 80Msps
Low Power 3V ADC
The LTC
®
2249 is a 14-bit 80Msps, low power 3V A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2249 is perfect for de-
manding imaging and communications applications with
AC performance that includes 73dB SNR and 90dB SFDR
for signals well beyond the Nyquist frequency.
DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1.2LSB
RMS
.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
SNR vs Input Frequency,
–1dB, 2V Range
APPLICATIO S
U
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Ultrasound
■
Spectral Analysis
■
Portable Instrumentation
–
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D13
•
•
•
D0
CLK
REFH
REFL
ANALOG
INPUT
2229 TA01
OVDD
OGND
INPUT FREQUENCY (MHz)
0
65
SNR (dBFS)
66
68
69
70
75
72
50 100
2249 G09
67
73
74
71
150 200
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC2249
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ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
OVDD = VDD (Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... –0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2249C ............................................... 0°C to 70°C
LTC2249I.............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ●14 Bits
Integral Linearity Error Differential Analog Input (Note 5) ●–4 ±1 4 LSB
Differential Linearity Error Differential Analog Input ●–1 ±0.5 1 LSB
Offset Error (Note 6) ●–12 ±212 mV
Gain Error External Reference ●–2.5 ±0.5 2.5 %FS
Offset Drift ±10 µV/°C
Full-Scale Drift Internal Reference ±30 ppm/°C
External Reference ±5 ppm/°C
Transition Noise SENSE = 1V 1.2 LSB
RMS
CO VERTER CHARACTERISTICS
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ORDER PART NUMBER
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1AIN+
AIN–
REFH
REFH
REFL
REFL
VDD
GND
D10
D9
D8
OVDD
OGND
D7
D6
D5
VDD
VCM
SENSE
MODE
OF
D13
D12
D11
CLK
SHDN
OE
D0
D1
D2
D3
D4
33
T
JMAX
= 125°C, θ
JA
= 34°C/W
EXPOSED PAD IS GND (PIN 33)
MUST BE SOLDERED TO PCB
LTC2249CUH
LTC2249IUH
QFN PART MARKING*
2249
LTC2249
3
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The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input 73 dB
40MHz Input ●70.8 73 dB
70MHz Input 73 dB
140MHz Input 72.6 dB
SFDR Spurious Free Dynamic Range 5MHz Input 90 dB
2nd or 3rd Harmonic 40MHz Input ●75 90 dB
70MHz Input 90 dB
140MHz Input 85 dB
SFDR Spurious Free Dynamic Range 5MHz Input 95 dB
4th Harmonic or Higher 40MHz Input ●81 95 dB
70MHz Input 95 dB
140MHz Input 90 dB
S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 72.9 dB
40MHz Input ●70.2 72.8 dB
70MHz Input 72.8 dB
140MHz Input 72.1 dB
I
MD
Intermodulation Distortion f
IN1
= 28.2MHz, f
IN2
= 26.8MHz 90 dB
Full Power Bandwidth Figure 8 Test Circuit 575 MHz
DY A IC ACCURACY
U
W
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Output Voltage I
OUT
= 0 1.475 1.500 1.525 V
V
CM
Output Tempco ±25 ppm/°C
V
CM
Line Regulation 2.7V < V
DD
< 3.4V 3 mV/V
V
CM
Output Resistance –1mA < I
OUT
< 1mA 4 Ω
I TER AL REFERE CE CHARACTERISTICS
UU U
(Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (A
IN+
– A
IN–
) 2.7V < V
DD
< 3.4V (Note 7) ●±0.5 to ±1V
V
IN,CM
Analog Input Common Mode (A
IN+
+ A
IN–
)/2 Differential Input (Note 7) ●1 1.5 1.9 V
Single Ended Input (Note 7) ●0.5 1.5 2 V
I
IN
Analog Input Leakage Current 0V < A
IN+
, A
IN–
< V
DD
●–1 1 µA
I
SENSE
SENSE Input Leakage 0V < SENSE < 1V ●–3 3 µA
I
MODE
MODE Pin Leakage ●–3 3 µA
t
AP
Sample-and-Hold Acquisition Delay Time 0 ns
t
JITTER
Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
A ALOG I PUT
UU
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
LTC2249
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DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIRE E TS
WU
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Analog Supply Voltage (Note 9) ●2.7 3 3.4 V
OV
DD
Output Supply Voltage (Note 9) ●0.5 3 3.6 V
IV
DD
Supply Current ●74 86 mA
P
DISS
Power Dissipation ●222 258 mW
P
SHDN
Shutdown Power SHDN = H, OE = H, No CLK 2 mW
P
NAP
Nap Mode Power SHDN = H, OE = L, No CLK 15 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN)
V
IH
High Level Input Voltage V
DD
= 3V ●2V
V
IL
Low Level Input Voltage V
DD
= 3V ●0.8 V
I
IN
Input Current V
IN
= 0V to V
DD
●–10 10 µA
C
IN
Input Capacitance (Note 7) 3 pF
LOGIC OUTPUTS
OV
DD
= 3V
C
OZ
Hi-Z Output Capacitance OE = High (Note 7) 3 pF
I
SOURCE
Output Source Current V
OUT
= 0V 50 mA
I
SINK
Output Sink Current V
OUT
= 3V 50 mA
V
OH
High Level Output Voltage I
O
= –10µA 2.995 V
I
O
= –200µA●2.7 2.99 V
V
OL
Low Level Output Voltage I
O
= 10µA 0.005 V
I
O
= 1.6mA ●0.09 0.4 V
OV
DD
= 2.5V
V
OH
High Level Output Voltage I
O
= –200µA 2.49 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
OV
DD
= 1.8V
V
OH
High Level Output Voltage I
O
= –200µA 1.79 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
LTC2249
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4: V
DD
= 3V, f
SAMPLE
= 80MHz, input range = 2V
P-P
with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
DD
= 3V, f
SAMPLE
= 80MHz, input range = 1V
P-P
with
differential drive.
Note 9: Recommended operating conditions.
TI I G CHARACTERISTICS
UW
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
s
Sampling Frequency (Note 9) ●1 80 MHz
t
L
CLK Low Time Duty Cycle Stabilizer Off ●5.9 6.25 500 ns
Duty Cycle Stabilizer On (Note 7) ●5 6.25 500 ns
t
H
CLK High Time Duty Cycle Stabilizer Off ●5.9 6.25 500 ns
Duty Cycle Stabilizer On (Note 7) ●5 6.25 500 ns
t
AP
Sample-and-Hold Aperture Delay 0ns
t
D
CLK to DATA Delay C
L
= 5pF (Note 7) ●1.4 2.7 5.4 ns
Data Access Time After OE↓C
L
= 5pF (Note 7) ●4.3 10 ns
BUS Relinquish Time (Note 7) ●3.3 8.5 ns
Pipeline 5 Cycles
Latency
Typical DNL, 2V Range
Typical INL, 2V Range
8192 Point FFT, fIN = 5MHz,
–1dB, 2V Range
TYPICAL PERFOR A CE CHARACTERISTICS
UW
CODE
0
INL ERROR (LSB)
0
0.5
1.0
16384
2249 G01
–0.5
–1.0
–2.0 4096 8192 12288
–1.5
2.0
1.5
CODE
0
DNL ERROR (LSB)
0.2
0.4
0.6
16384
2249 G02
0
–0.2
–1.0
4096 8192 12288
–0.6
–0.4
–0.8
1.0
0.8
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
35
2249 G03
–80
–100
–70
–50
–30
–10
–90
–110
–120 515 2510 20 30 40
LTC2249
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
8192 Point FFT, fIN = 30MHz,
–1dB, 2V Range
8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range
8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range
Grounded Input Histogram
SNR vs Input Frequency,
–1dB, 2V Range
8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range
SFDR vs Input Frequency,
–1dB, 2V Range
SNR and SFDR vs Sample Rate,
2V Range, fIN = 5MHz, –1dB
SNR and SFDR
vs Clock Duty Cycle
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
35
2249 G04
–80
–100
–70
–50
–30
–10
–90
–110
–120 515 2510 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
35
2249 G05
–80
–100
–70
–50
–30
–10
–90
–110
–120 515 2510 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
35
2249 G06
–80
–100
–70
–50
–30
–10
–90
–110
–120 515 2510 20 30 40
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
35
2249 G07
–80
–100
–70
–50
–30
–10
–90
–110
–120 515 2510 20 30 40
CODE
8201
26 178
552 1987
5194 6150
35969
8203 8205 8207 8209
COUNT
30000
40000
50000
2249 G08
20000
10000
25000
35000
45000
15000
5000
0
12558
43161
25292
INPUT FREQUENCY (MHz)
0
65
SNR (dBFS)
66
68
69
70
75
72
50 100
2249 G09
67
73
74
71
150 200
INPUT FREQUENCY (MHz)
0
85
90
100
150
2249 G10
80
75
50 100 200
70
65
95
SFDR (dBFS)
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
80
90
100
80
2249 G11
70
60
50 10 20 30 40 50 60 70 90 100 110
SFDR
SNR
CLOCK DUTY CYCLE (%)
30
SNR AND SFDR (dBFS)
85
90
60
2249 G12
80
75
40 50
35 65
45 55 70
70
95 SFDR: DCS ON
SNR: DCS ON
SNR: DCS OFF
SFDR: DCS OFF
LTC2249
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
SNR vs Input Level,
fIN = 70MHz, 2V Range
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
SFDR vs Input Level,
fIN = 70MHz, 2V Range
INPUT LEVEL (dBFS)
–50–60–70
SNR (dBc AND dBFS)
30
40
50
–20 0
2249 G13
20
10
0–40 –30
dBFS
dBc
–10
60
70
80
INPUT LEVEL (dBFS)
–80
SFDR (dBc AND dBFS)
60 dBc
dBFS
90
100
0
2249 G14
50
40
0–60 –40 –20
20
120
110
80
70
30
10
100dBc SFDR
REFERENCE LINE
SAMPLE RATE (Msps)
0
50
I
VDD
(mA)
55
65
70
75
85
10 50 70
2249 G15
60
80
40 90 100
20 30 60 80
2V RANGE
1V RANGE
SAMPLE RATE (Msps)
0
0
I
OVDD
(mA)
1
3
4
5
7
10 50 70
2249 G16
2
6
40 90 100
20 30 60 80
LTC2249
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UU
U
PI FU CTIO S
A
IN
+ (Pin 1): Positive Differential Analog Input.
A
IN
- (Pin 2): Negative Differential Analog Input.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
V
DD
(Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
25, 26, 27): Digital Outputs. D13 is the MSB.
OGND (Pin 20): Output Driver Ground.
OV
DD
(Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 V
DD
selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 V
DD
selects
2’s complement output format and turns the clock duty
cycle stabilizer on. V
DD
selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to V
CM
selects the internal reference and a ±0.5V
input range. V
DD
selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V
SENSE
. ±1V is the largest valid input range.
V
CM
(Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
LTC2249
9
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FUNCTIONAL BLOCK DIAGRA
UU
W
SHIFT REGISTER
AND CORRECTION
DIFF
REF
AMP
REF
BUF
2.2µF
1µF1µF
0.1µF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH REFL
CLK OE
MODE
OGND
OV
DD
2249 F01
INPUT
S/H
SENSE
V
CM
A
IN–
A
IN+
2.2µF
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D13
D0
•
•
•
Figure 1. Functional Block Diagram
LTC2249
10
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TI I G DIAGRA
UWW
tAP
N + 1
N + 2 N + 4
N + 3 N + 5
N
ANALOG
INPUT
tH
tD
tL
N – 4 N – 3 N – 2 N – 1
CLK
D0-D13, OF
2249 TD01
N – 5 N
LTC2249
11
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DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log (√(V2
2
+ V3
2
+ V4
2
+ . . . Vn
2
)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
APPLICATIO S I FOR ATIO
WUUU
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when CLK reaches mid-supply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
JITTER
= –20log (2π • f
IN
• t
JITTER
)
LTC2249
12
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CONVERTER OPERATION
As shown in Figure 1, the LTC2249 is a CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The CLK input is single-ended.
The LTC2249 has two phases of operation, determined by
the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2249
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (C
SAMPLE
) through
NMOS transistors. The capacitors shown attached to each
input (C
PARASITIC
) are the summation of all other capaci-
tance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
APPLICATIO S I FOR ATIO
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Figure 2. Equivalent Input Circuit
V
DD
V
DD
V
DD
15Ω
15Ω
C
PARASITIC
1pF
C
PARASITIC
1pF
C
SAMPLE
4pF
C
SAMPLE
4pF
LTC2249
A
IN
+
A
IN
–
CLK
2249 F02
LTC2249
13
2249fa
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Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
IN+
should be driven with the input signal and A
IN–
should be
connected to 1.5V or V
CM
.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The V
CM
output pin (Pin
31) may be used to provide the common mode bias level.
V
CM
can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
CM
pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2249 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2F
ENCODE
); however, this is
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2249 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
CM
, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
25Ω
25Ω
25Ω
25Ω
0.1µF
A
IN+
A
IN–
12pF
2.2µF
V
CM
LTC2249
ANALOG
INPUT
0.1µFT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2249 F03
Figure 4. Differential Drive with an Amplifier
25Ω
25Ω
12pF
2.2µF
V
CM
LTC2249
2249 F04
––
++
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER A
IN+
A
IN–
LTC2249
14
2249fa
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.5V. In
APPLICATIO S I FOR ATIO
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Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
Reference Operation
Figure 9 shows the LTC2249 reference circuitry consisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to V
DD
selects the 2V range; tying the SENSE
pin to V
CM
selects the 1V range.
Figure 5. Single-Ended Drive
25Ω
0.1µF
ANALOG
INPUT
VCM
AIN
+
AIN
–
1k
12pF
2249 F05
2.2µF
1k
25Ω
0.1µF
LTC2249
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
25Ω
25Ω12Ω
12Ω
0.1µF
A
IN+
A
IN–
8pF
2.2µF
V
CM
LTC2249
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2249 F06
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
25Ω
25Ω
0.1µF
A
IN+
A
IN–
2.2µF
V
CM
LTC2249
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2249 F07
25Ω
25Ω
0.1µF
A
IN+
A
IN–
2.2µF
V
CM
LTC2249
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
2249 F08
6.8nH
6.8nH
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
V
CM
REFH
SENSE
TIE TO V
DD
FOR 2V RANGE;
TIE TO V
CM
FOR 1V RANGE;
RANGE = 2 • V
SENSE
FOR
0.5V < V
SENSE
< 1V
1.5V
REFL
2.2µF
2.2µF
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1µF
2249 F09
LTC2249
4Ω
DIFF AMP
1µF
1µF
INTERNAL ADC
LOW REFERENCE
1.5V BANDGAP
REFERENCE
1V 0.5V
RANGE
DETECT
AND
CONTROL
Figure 9. Equivalent Reference Circuit
LTC2249
15
2249fa
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Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5.7dB.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low-jitter squaring circuit before the CLK pin (see
Figure 11).
The noise performance of the LTC2249 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, V
CM
. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
V
CM
SENSE
1.5V
0.75V
2.2µF
12k
1µF
12k
2249 F10
LTC2249
Figure 10. 1.5V Range ADC
CLK
50Ω
0.1µF
0.1µF
4.7µF
1k
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
2249 F11
NC7SVU04
LTC2249
Figure 11. Sinusoidal Single-Ended CLK Drive
LTC2249
16
2249fa
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capaci-
tor at the input may result in peaking, and depending on
transmission line length may require a 10Ω to 20Ω ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2249 is 80Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 5.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
DD
or 2/3V
DD
using external resistors.
The lower limit of the LTC2249 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2249 is 1Msps.
APPLICATIO S I FOR ATIO
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Figure 13. LVDS or PECL CLK Drive Using a TransformerFigure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
CLK
100Ω
0.1µF
4.7µF
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2249 F12
LTC2249
CLK
5pF-30pF
ETC1-1T
0.1µF
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
2249 F13
LTC2249
LTC2249
17
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DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2249 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2249 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3V
DD
selects offset
binary output format. Connecting MODE to
2/3V
DD
or V
DD
selects 2’s complement output format.
An external resistor divider can be used to set the 1/3V
DD
or 2/3V
DD
logic values. Table 2 shows the logic states for
the MODE pin.
Table 1. Output Codes vs Input Voltage
A
IN+
– A
IN–
D13 – D0 D13 – D0
(2V Range) OF (Offset Binary) (2’s Complement)
>+1.000000V 1 11 1111 1111 1111 01 1111 1111 1111
+0.999878V 0 11 1111 1111 1111 01 1111 1111 1111
+0.999756V 0 11 1111 1111 1110 01 1111 1111 1110
+0.000122V 0 10 0000 0000 0001 00 0000 0000 0001
0.000000V 0 10 0000 0000 0000 00 0000 0000 0000
–0.000122V 0 01 1111 1111 1111 11 1111 1111 1111
–0.000244V 0 01 1111 1111 1110 11 1111 1111 1110
–0.999878V 0 00 0000 0000 0001 10 0000 0000 0001
–1.000000V 0 00 0000 0000 0000 10 0000 0000 0000
<–1.000000V 1 00 0000 0000 0000 10 0000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
Figure 14. Digital Output Buffer
LTC2249
2249 F12
OV
DD
V
DD
V
DD
0.1µF
43ΩTYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Table 2. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stablizer
0 Offset Binary Off
1/3V
DD
Offset Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
LTC2249
18
2249fa
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OV
DD
should be tied to that same 1.8V supply.
OV
DD
can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OV
DD
. The logic outputs will
swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
DD
and OE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Grounding and Bypassing
The LTC2249 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
DD
, OV
DD
, V
CM
, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF ca-
pacitor between REFH and REFL can be somewhat further
away. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The LTC2249 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
Heat Transfer
Most of the heat generated by the LTC2249 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to a
ground plane of sufficient area.
APPLICATIO S I FOR ATIO
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LTC2249
19
2249fa
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable. You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the driver to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multi-
layer PCBs. The differential pairs must be close together
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
APPLICATIO S I FOR ATIO
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LTC2249
20
2249fa
APPLICATIO S I FOR ATIO
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1
2
C8
0.1µF
C11
0.1µF
3
4
5
VDD
7
VDD
VDD GND
9
32
VCM
31
30
29
33
JP2
OE
10
11
8
C7
2.2µF
C6
1µF
C9
1µF
C4
0.1µF
C2
8.2pF
VDD
VDD
VDD GND
JP1
SHDN
C15
2.2µFC16
0.1µF
C18
0.1µF
C25
4.7µF
E2
VDD
3V
E4
PWR
GND
VDD VCC
2249 TA02
C17 0.1µF
C20
0.1µF
C19
0.1µF
C14
0.1µF
R10
33Ω
E1
EXT REF
R14
1k
R15
1k
R16
1k
R7
1k
R8
49.9Ω
R3
24.9Ω
R2
12.4Ω
R6
12.4Ω
R1
OPT
R4
24.9Ω
R5
50Ω
T1
ETC1-1-13
C1
0.1µF
C3
0.1µF
J3
CLOCK
INPUT
NC7SVU04
NC7SVU04
C13
0.1µF
C10
0.1µF
C5
4.7µF
6.3V
L1
BEAD
VDD
C12
0.1µF
R9
1k
J1
ANALOG
INPUT
AIN+
AIN–
REFH
REFH
6REFL
REFL
VDD
CLK
SHDN
VDD
VCM
SENSE
MODE
GND
LTC2249
OE
D12
D11
GND
D0
D1
D2
D3
D5
D4
D6
D8
D9
D13
OF
OVDD VCC
OGND
D10
D7
26
25
12
13
14
15
17
16
18
22
23
27
28
21
20
24
19
OE1
I0
OE2
LE1
LE2
VCC
VCC
VCC
GND
GND
GND
I1
I2
I4
I3
I5
I7
I8
I12
I11
I10
I13
I14
I15
I9
O11
O10
I6
VCC
O0
GND
GND
GND
VCC
VCC
GND
34
45
39
42
25
48
24
1
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
VCC
28
74VCX16373MTD
31
21
15
18
10
4
7
RN1C 33Ω
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
GND
O1
O2
O4
O3
O5
O7
O8
O12
O13
O14
O15
O9
O6
25
23
27
29
31
33
35
37
39
21
19
15
17
13
9
7
1
3
5
2
4
11
26
24
30
28
34
32
38
40
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
3201S-40G1
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
36
A3
A2
A1
A0
SDA
WP
VCC
1
2
3
4
8
24LC025
7
6
5
SCL
22
20
16
18
14
10
8
6
12
1
2
3
5
••
4
VCM
12
VDD
VDD
34
2/3VDD
56
1/3VDD
78
GND
JP4 MODE
12
VDD
34
VCM
VDD
VCM
56
EXT REF
JP3 SENSE
RN1B 33Ω
RN1A 33Ω
RN2D 33Ω
RN2C 33Ω
RN2B 33Ω
RN2A 33Ω
RN3D 33Ω
RN3C 33Ω
RN3B 33Ω
RN3A 33Ω
RN4D 33Ω
RN4B 33Ω
RN4A 33Ω
R13
10k
R11
10k
R12
10k
RN4C 33Ω
RN1D 33Ω
C28
1µF
C27
0.01µF
VCC
VDD
NC7SV86P5X
BYP
GND
ADJ
OUT
SHDN
GND
IN
1
2
3
4
8
LT1763
7
6
5
GND
R18
100k
R17
105k
C26
10µF
6.3V
E3
GND C21
0.1µF
C22
0.1µF
C23
0.1µF
C24
0.1µF
LTC2249
21
2249fa
APPLICATIO S I FOR ATIO
WUUU
Silkscreen Top Topside
Inner Layer 2 GND
LTC2249
22
2249fa
APPLICATIO S I FOR ATIO
WUUU
Inner Layer 3 Power Bottomside
Silkscreen Bottom
LTC2249
23
2249fa
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
PACKAGE DESCRIPTIO
U
5.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
0.23 TYP
(4 SIDES)
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
(UH) QFN 0603
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.45 ±0.05
(4 SIDES)
4.10 ±0.05
5.50 ±0.05
0.25 ± 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2249
24
2249fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0106 REV A • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2225 12-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2226 12-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2227 12-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2228 12-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2229 12-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 70.6dB SNR, 90dB SFDR, 32-Pin QFN
LTC2236 10-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2237 10-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2238 10-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2239 10-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2245 14-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2246 14-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN
LTC2247 14-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2248 14-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2249 14-Bit, 80Msps, 3V ADC, Lowest Power 222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN
LTC2250 10-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2251 10-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2252 12-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2253 12-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2254 14-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
with Digitally Controlled Gain 10.5dB to 33dB in 1.5dB/Step
LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz,
Integrated LO Quadrature Generator
LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz,
Integrated LO Quadrature Generator
LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz,
Integrated LO Quadrature Generator
LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
