DP8570AVXNOPB - NATIONAL SEMICONDUCTOR

ADCS7476,ADCS7477,ADCS7478

ADCS7476 ADCS7477 ADCS7478 1MSPS, 12-/10-/8-Bit A/D Converters in

SOT-23 & LLP

Literature Number: SNAS192E

ADCS7476

ADCS7477

ADCS7478

February 17, 2010

1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP

General Description

The ADCS7476, ADCS7477, and ADCS7478 are low power,

monolithic CMOS 12-, 10- and 8-bit analog-to-digital convert-

ers that operate at 1 MSPS. The ADCS7476/77/78 are drop-

in replacements for Analog Devices' AD7476/77/78. Each

device is based on a successive approximation register ar-

chitecture with internal track-and-hold. The serial interface is

compatible with several standards, such as SPI™, QSPI™,

MICROWIRE™, and many common DSP serial interfaces.

The ADCS7476/77/78 uses the supply voltage as a refer-

ence, enabling the devices to operate with a full-scale input

range of 0 to VDD. The conversion rate is determined from the

serial clock (SCLK) speed. These converters offer a shut-

down mode, which can be used to trade throughput for power

consumption. The ADCS7476/77/78 is operated with a single

supply that can range from +2.7V to +5.25V. Normal power

consumption during continuous conversion, using a +3V or

+5V supply, is 2 mW or 10 mW respectively. The power down

feature, which is enabled by a chip select (CS) pin, reduces

the power consumption to under 5 µW using a +5V supply. All

three converters are available in a 6-lead, SOT-23 package

and in a 6-lead LLP, both of which provide an extremely small

footprint for applications where space is a critical considera-

tion. These products are designed for operation over the

automotive/extended industrial temperature range of −40°C

to +125°C.

Features

■Variable power management

■Packaged in 6-lead, SOT-23 and LLP

■Power supply used as reference

■Single +2.7V to +5.25V supply operation

■SPI™/QSPI™/MICROWIRE™/DSP compatible

Key Specifications

■Resolution with no Missing Codes 12/10/8 bits

■Conversion Rate 1 MSPS

■DNL +0.5, -0.3 LSB (typ)

■INL ± 0.4 LSB (typ)

■Power Consumption

—3V Supply 2 mW (typ)

—5V Supply 10 mW (typ)

Applications

■Automotive Navigation

■FA/ATM Equipment

■Portable Systems

■Medical Instruments

■Mobile Communications

■Instrumentation and Control Systems

Connection Diagram

20057701

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

ADCS7476/ADCS7477/ADCS7478 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP

Ordering Information

Order Code Temperature Range Description Top Mark

ADCS7476AIMF −40°C to +125°C 6-Lead SOT-23 Package, 1000 Units Tape & Reel X01A

ADCS7477AIMF −40°C to +85°C 6-Lead SOT-23 Package, 1000 Units Tape & Reel X02A

ADCS7478AIMF −40°C to +85°C 6-Lead SOT-23 Package, 1000 Units Tape & Reel X03A

ADCS7476AIMFX −40°C to +125°C 6-Lead SOT-23 Package, 3000 Units Tape & Reel X01A

ADCS7476AISDX −40°C to +125°C 6-Lead LLP, 3000 Units Tape & Reel X1A

ADCS7477AIMFX −40°C to +85°C 6-Lead SOT-23 Package, 3000 Units Tape & Reel X02A

ADCS7477AISDX −40°C to +85°C 6-Lead LLP, 3000 Units Tape & Reel X2A

ADCS7478AIMFX −40°C to +85°C 6-Lead SOT-23 Package, 3000 Units Tape & Reel X03A

ADCS7478AISDX −40°C to +85°C 6-Lead LLP, 3000 Units Tape & Reel X3A

ADCS7476AIMFE −40°C to +125°C 6-Lead SOT-23 Package, 250 Units Tape & Reel X01A

ADCS7477AIMFE −40°C to +85°C 6-Lead SOT-23 Package, 250 Units Tape & Reel X02A

ADCS7478AIMFE −40°C to +85°C 6-Lead SOT-23 Package, 250 Units Tape & Reel X03A

Pin Descriptions

Pin No. Symbol Description

ANALOG I/O

3VIN Analog input. This signal can range from 0V to VDD.

DIGITAL I/O

4 SCLK Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with guaranteed

performance at 20 MHz. This clock directly controls the conversion and readout processes.

5 SDATA Digital data output. The output words are clocked out of this pin by the SCLK pin.

6 CS Chip select. A conversion process begins on the falling edge of CS.

POWER SUPPLY

1VDD

Positive supply pin. These pins should be connected to a quiet +2.7V to +5.25V source and

bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin.

The ADCS7476/77/78 uses this power supply as a reference, so it should be thoroughly bypassed.

2 GND The ground return for the supply.

Block Diagram

20057718

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ADCS7476/ADCS7477/ADCS7478

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage VDD −0.3V to +6.5V

Voltage on Any Analog Pin to GND −0.3V to VDD +0.3V

Voltage on Any Digital Pin to GND -0.3V to 6.5V

Input Current at Any Pin (Note 3) ±10 mA

ESD Susceptibility

Human Body Model

Machine Model

3500V

200V

Soldering Temperature, Infrared,

10 seconds 215°C

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings

Operating Temperature Range TMIN = −40°C ≤ TA ≤

TMAX = +125°C

VDD Supply Voltage +2.7V to +5.25V

Digital Input Pins Voltage Range (Note

4) +2.7V to +5.25V

Package Thermal Resistance

Package θJA

6-Lead SOT-23 265°C / W

6-Lead LLP 78°C / W

ADCS7476/ADCS7477/ADCS7478 Specifications (Note 2)

ADCS7476 Converter Electrical Characteristics

The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted. Boldface

limits apply for TA = −40°C to +85°C: all other limits TA = 25°C, unless otherwise noted.

Symbol Parameter Conditions Typical Limits Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes VDD = 2.7V to 3.6V,

−40°C ≤ TA ≤ 125°C 12 Bits

INL Integral Non-Linearity

VDD = 2.7V to 3.6V,

−40°C ≤ TA ≤ 85°C ±0.4 ±1 LSB (max)

VDD = 2.7V to 3.6V,

TA = 125°C +1

-1.1

LSB (max)

LSB (min)

DNL Differential Non-Linearity

VDD = 2.7V to 3.6V,

−40°C ≤ TA ≤ 85°C

+0.5

-0.3

-0.9

LSB (max)

LSB (min)

VDD = 2.7V to 3.6V,

TA = 125°C ±1 LSB (max)

VOFF Offset Error VDD = 2.7V to 3.6V,

−40°C ≤ TA ≤ 125°C ±0.1 ±1.2 LSB (max)

GE Gain Error VDD = 2.7V to 3.6V,

−40°C ≤ TA ≤ 125°C ±0.2 ±1.2 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz, −40°C ≤ TA ≤ 125°C 72 70 dB (min)

SNR Signal-to-Noise Ratio fIN = 100 kHz, −40°C ≤ TA ≤ 85°C 72.5 70.8 dB (min)

fIN = 100 kHz, TA = 125°C 70.6 dB (min)

THD Total Harmonic Distortion fIN = 100 kHz -80 dB

SFDR Spurious-Free Dynamic Range fIN = 100 kHz 82 dB

IMD

Intermodulation Distortion, Second

Order Terms fa = 103.5 kHz, fb = 113.5 kHz -78 dB

Intermodulation Distortion, Third Order

Terms fa = 103.5 kHz, fb = 113.5 kHz -78 dB

FPBW -3 dB Full Power Bandwidth +5V Supply 11 MHz

+3V Supply 8 MHz

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ADCS7476/ADCS7477/ADCS7478

Symbol Parameter Conditions Typical Limits Units

POWER SUPPLY CHARACTERISTICS

VDD Supply Voltage −40°C ≤ TA ≤ 125°C 2.7 V (min)

5.25 V (max)

IDD

Normal Mode (Static)

VDD = +4.75V to +5.25V,

SCLK On or Off 2 mA

VDD = +2.7V to +3.6V,

SCLK On or Off 1 mA

Normal Mode (Operational)

VDD = +4.75V to +5.25V,

fSAMPLE = 1 MSPS 2.0 3.5 mA (max)

VDD = +2.7V to +3.6V,

fSAMPLE = 1 MSPS 0.6 1.6 mA (max)

Shutdown Mode VDD = +5V, SCLK Off 0.5 µA

VDD = +5V, SCLK On 60 µA

Power Consumption, Normal Mode

(Operational)

VDD = +5V, fSAMPLE = 1 MSPS 10 17.5 mW (max)

VDD = +3V, fSAMPLE = 1 MSPS 24.8 mW (max)

Power Consumption, Shutdown Mode VDD = +5V, SCLK Off 2.5 µW

VDD = +3V, SCLK Off 1.5 µW

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VDD V

IDCL DC Leakage Current ±1 µA (max)

CINA Analog Input Capacitance 30 pF

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage 2.4 V (min)

VIL Input Low Voltage VDD = +5V 0.8 V (max)

VDD = +3V 0.4 V (max)

IIN Input Current VIN = 0V or VDD ±10 nA ±1 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA,

VDD = +2.7V to +5.25V VDD −0.2 V (min)

VOL Output Low Voltage ISINK = 200 µA 0.4 V (max)

IOL TRI-STATE® Leakage Current ±10 µA (max)

COUT TRI-STATE Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

AC ELECTRICAL CHARACTERISTICS

fSCLK Clock Frequency −40°C ≤ TA ≤ 125°C 20 MHz (max)

DC SCLK Duty Cycle 40

% (min)

% (max)

tTH Track/Hold Acquisition Time 400 ns (max)

fRATE Throughput Rate See Serial Interface Section 1MSPS (max)

tAD Aperture Delay 3 ns

tAJ Aperture Jitter 30 ps

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ADCS7476/ADCS7477/ADCS7478

ADCS7477 Converter Electrical Characteristics

The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted. Boldface

limits apply for TA = −40°C to +85°C: all other limits TA = 25°C, unless otherwise noted.

Symbol Parameter Conditions Typical Limits Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 10 Bits

INL Integral Non-Linearity ±0.2 ±0.7 LSB (max)

DNL Differential Non-Linearity +0.3

-0.2 ±0.7 LSB (max)

LSB (min)

VOFF Offset Error ±0.1 ±0.7 LSB (max)

GE Gain Error ±0.2 ±1 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz 61.7 61 dBFS (min)

SNR Signal-to-Noise Ratio fIN = 100 kHz 62 dB

THD Total Harmonic Distortion fIN = 100 kHz -77 -73 dB (max)

SFDR Spurious-Free Dynamic Range fIN = 100 kHz 78 74 dB (min)

IMD

Intermodulation Distortion, Second

Order Terms fa = 103.5 kHz, fb = 113.5 kHz -78 dB

Intermodulation Distortion, Third Order

Terms fa = 103.5 kHz, fb = 113.5 kHz -78 dB

FPBW -3 dB Full Power Bandwidth +5V Supply 11 MHz

+3V Supply 8 MHz

POWER SUPPLY CHARACTERISTICS

VDD Supply Voltage 2.7

5.25

V (min)

V (max)

IDD

Normal Mode (Static)

VDD = +4.75V to +5.25V,

SCLK On or Off 2 mA

VDD = +2.7V to +3.6V,

SCLK On or Off 1 mA

Normal Mode (Operational)

VDD = +4.75V to +5.25V,

fSAMPLE = 1 MSPS 2.0 3.5 mA (max)

VDD = +2.7V to +3.6V,

fSAMPLE = 1 MSPS 0.6 1.6 mA (max)

Shutdown Mode VDD = +5V, SCLK Off 0.5 µA (max)

VDD = +5V, SCLK On 60 µA (max)

Power Consumption, Normal Mode

(Operational)

VDD = +5V, fSAMPLE = 1 MSPS 10 17.5 mW (max)

VDD = +3V, fSAMPLE = 1 MSPS 24.8 mW (max)

Power Consumption, Shutdown Mode VDD = +5V, SCLK Off 2.5 µW (max)

VDD = +3V, SCLK Off 1.5 µW (max)

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VDD V

IDCL DC Leakage Current ±1 µA (max)

CINA Analog Input Capacitance 30 pF

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ADCS7476/ADCS7477/ADCS7478

Symbol Parameter Conditions Typical Limits Units

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage 2.4 V (min)

VIL Input Low Voltage VDD = +5V 0.8 V (max)

VDD = +3V 0.4 V (max)

IIN Input Current VIN = 0V or VDD ±10 nA ±1 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA,

VDD = +2.7V to +5.25V VDD −0.2 V (min)

VOL Output Low Voltage ISINK = 200 µA 0.4 V (max)

IOL TRI-STATE Leakage Current ±10 µA (max)

COUT TRI-STATE Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

AC ELECTRICAL CHARACTERISTICS

fSCLK Clock Frequency 20 MHz (max)

DC SCLK Duty Cycle 40

% (min)

% (max)

tTH Track/Hold Acquisition Time 400 ns (max)

fRATE Throughput Rate See Serial Interface Section 1MSPS (max)

tAD Aperture Delay 3 ns

tAJ Aperture Jitter 30 ps

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ADCS7476/ADCS7477/ADCS7478

ADCS7478 Converter Electrical Characteristics

The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted. Boldface

limits apply for TA = −40°C to +85°C: all other limits TA = 25°C, unless otherwise noted.

Symbol Parameter Conditions Typical Limits Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 8Bits

INL Integral Non-Linearity ±0.05 ±0.3 LSB (max)

DNL Differential Non-Linearity ±0.07 ±0.3 LSB (max)

VOFF Offset Error ±0.03 ±0.3 LSB (max)

GE Gain Error ±0.08 ±0.4 LSB (max)

Total Unadjusted Error ±0.07 ±0.3 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz 49.7 49 dB (min)

SNR Signal-to-Noise Ratio fIN = 100 kHz 49.7 dB

THD Total Harmonic Distortion fIN = 100 kHz -77 -65 dB (max)

SFDR Spurious-Free Dynamic Range fIN = 100 kHz 69 65 dB (min)

IMD

Intermodulation Distortion, Second

Order Terms fa = 103.5 kHz, fb = 113.5 kHz -68 dB

Intermodulation Distortion, Third Order

Terms fa = 103.5 kHz, fb = 113.5 kHz -68 dB

FPBW -3 dB Full Power Bandwidth +5V Supply 11 MHz

+3V Supply 8 MHz

POWER SUPPLY CHARACTERISTICS

VDD Supply Voltage 2.7

5.25

V (min)

V (max)

IDD

Normal Mode (Static)

VDD = +4.75V to +5.25V,

SCLK On or Off 2 mA

VDD = +2.7V to +3.6V,

SCLK On or Off 1 mA

Normal Mode (Operational)

VDD = +4.75V to +5.25V,

fSAMPLE = 1 MSPS 2.0 3.5 mA (max)

VDD = +2.7V to +3.6V,

fSAMPLE = 1 MSPS 0.6 1.6 mA (max)

Shutdown Mode VDD = +5V, SCLK Off 0.5 µA (max)

VDD = +5V, SCLK On 60 µA (max)

Power Consumption, Normal Mode

(Operational)

VDD = +5V, fSAMPLE = 1 MSPS 10 17.5 mW (max)

VDD = +3V, fSAMPLE = 1 MSPS 24.8 mW (max)

Power Consumption= Shutdown Mode VDD = +5V, SCLK Off 2.5 µW (max)

VDD = +3V, SCLK Off 1.5 µW (max)

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VDD V

IDCL DC Leakage Current ±1 µA (max)

CINA Analog Input Capacitance 30 pF

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ADCS7476/ADCS7477/ADCS7478

Symbol Parameter Conditions Typical Limits Units

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage 2.4 V (min)

VIL Input Low Voltage VDD = +5V 0.8 V (max)

VDD = +3V 0.4 V (max)

IIN Digital Input Current VIN = 0V or VDD ±10 nA ±1 µA (max)

CIND Input Capacitance 2 4pF(max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA,

VDD = +2.7V to +5.25V VDD −0.2 V (min)

VOL Output Low Voltage ISINK = 200 µA 0.4 V (max)

IOL TRI-STATE Leakage Current ±10 µA (max)

COUT TRI-STATE Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

AC ELECTRICAL CHARACTERISTICS

fSCLK Clock Frequency 20 MHz (max)

DC SCLK Duty Cycle 40

% (min)

% (max)

tTH Track/Hold Acquisition Time 400 ns (max)

fRATE Throughput Rate See Applications Section 1MSPS (min)

tAD Aperture Delay 3 ns

tAJ Aperture Jitter 30 ps

Note 1: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional

operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may affect device reliability.

Note 2: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 3: Except power supply pins.

Note 4: Independent of supply voltage.

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ADCS7476/ADCS7477/ADCS7478

Timing Test Circuit

20057708

ADCS7476/ADCS7477/ADCS7478 Timing Specifications

The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, Boldface limits apply for TA = −40°C to +85°C: all

other limits TA = 25°C, unless otherwise noted. (Note 9)

Symbol Parameter Conditions Typical Limits Units

tCONVERT 16 x tSCLK

tQUIET (Note 5) 50 ns (min)

t1Minimum CS Pulse Width 10 ns (min)

t2CS to SCLK Setup Time 10 ns (min)

Delay from CS Until SDATA TRI-STATE

Disabled (Note 6) 20 ns (max)

Data Access Time after SCLK Falling

Edge(Note 7)

VDD = +2.7 to +3.6 40 ns (max)

VDD = +4.75 to +5.25 20 ns (max)

t5SCLK Low Pulse Width 0.4 x tSCLK ns (min)

t6SCLK High Pulse Width 0.4 x tSCLK ns (min)

t7SCLK to Data Valid Hold Time VDD = +2.7 to +3.6 7ns (min)

VDD = +4.75 to +5.25 5ns (min)

SCLK Falling Edge to SDATA High

Impedance (Note 8)

VDD = +2.7 to +3.6 25 ns (max)

6ns (min)

VDD = +4.75 to +5.25 25 ns (max)

5ns (min)

tPOWER-UP Power-Up Time from Full Power-Down 1 µs

Note 5: Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion

Note 6: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.

Note 7: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.

Note 8: t8 is derived from the time taken by the outputs to change by 0.5V with the loading circuit shown above. The measured number is then adjusted to remove

the effects of charging or discharging the 25pF capacitor. This means t8 is the true bus relinquish time, independent of the bus loading.

Note 9: All input signals are specified as tr = tf = 5 ns (10% to 90% VDD) and timed from 1.6V.

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ADCS7476/ADCS7477/ADCS7478

Specification Definitions

APERTURE DELAY is the time after the falling edge of CS

to when the input signal is acquired or held for conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the

variation in aperture delay from sample to sample. Aperture

jitter manifests itself as noise in the output.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02

and says that the converter is equivalent to a perfect ADC of

this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation of the last code transition

(111...110) to (111...111) from the ideal (VREF - 1.5 LSB for

ADCS7476 and ADCS7477, VREF - 1 LSB for ADCS7478),

after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the either the two

second order or all four third order intermodulation products

to the sum of the power in both of the original frequencies.

IMD is usually expressed in dBFS.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADCS7476/77/78 is guaranteed

not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition

(000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB

for the ADCS7476 and ADCS7477, and GND + 1 LSB for the

ADCS7478).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or DC.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding DC.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not present

at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dBc, of the rms total of the first five harmonic levels

at the output to the level of the fundamental at the output. THD

is calculated as

where f1 is the RMS power of the fundamental (output) fre-

quency and f2 through f6 are the RMS power in the first 5

harmonic frequencies.

TOTAL UNADJUSTED ERROR is the worst deviation found

from the ideal transfer function. As such, it is a comprehensive

specification which includes full scale error, linearity error,

and offset error.

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ADCS7476/ADCS7477/ADCS7478

Timing Diagrams

20057702

FIGURE 1. ADCS7476 Serial Interface Timing Diagram

20057703

FIGURE 2. ADCS7477 Serial Interface Timing Diagram

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ADCS7476/ADCS7477/ADCS7478

20057704

FIGURE 3. ADCS7478 Serial Interface Timing Diagram

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ADCS7476/ADCS7477/ADCS7478

Typical Performance Characteristics TA = +25°C, VDD = 3V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, fIN =

100 kHz unless otherwise stated.

ADCS7476

ADCS7476 DNL

20057706

ADCS7476 INL

20057705

ADCS7476 Spectral Response @ 100kHz Input

20057707

ADCS7476 THD vs. Source Impedance

20057750

ADCS7476 THD vs. Input Frequency, 600 kSPS

20057751

ADCS7476 THD vs. Input Frequency, 1 MSPS

20057752

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ADCS7476/ADCS7477/ADCS7478

ADCS7476 SINAD vs. Input Frequency, 600 kSPS

20057753

ADCS7476 SINAD vs. Input Frequency, 1 MSPS

20057754

ADCS7476 SNR vs. fSCLK

20057756

ADCS7476 SINAD vs. fSCLK

20057757

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ADCS7476/ADCS7477/ADCS7478

ADCS7477 DNL

20057770

ADCS7477 INL

20057771

ADCS7477 Spectral Response @ 100kHz Input

20057772

ADCS7477 SNR vs. fSCLK

20057773

ADCS7477 SINAD vs. fSCLK

20057774

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ADCS7476/ADCS7477/ADCS7478

ADCS7478 DNL

20057760

ADCS7478 INL

20057761

ADCS7478 Spectral Response @ 100kHz Input

20057762

ADCS7478 SNR vs. fSCLK

20057763

ADCS7478 SINAD vs. fSCLK

20057764

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ADCS7476/ADCS7477/ADCS7478

Applications Information

1.0 ADCS7476/77/78 OPERATION

The ADCS7476/77/78 are successive-approximation analog-

to-digital converters designed around a charge-redistribution

digital-to-analog converter. Simplified schematics of the

ADCS7476/77/78 in both track and hold operation are shown

in Figure 4 and Figure 5, respectively. In Figure 4 the device

is in track mode: switch SW1 connects the sampling capacitor

to the input, and SW2 balances the comparator inputs. The

device is in this state until CS is brought low, at which point

the device moves to hold mode.

Figure 5 shows the device in hold mode: switch SW1 con-

nects the sampling capacitor to ground, maintaining the sam-

pled voltage, and switch SW2 unbalances the comparator.

The control logic then instructs the charge-redistribution DAC

to add or subtract fixed amounts of charge from the sampling

capacitor until the comparator is balanced. When the com-

parator is balanced, the digital word supplied to the DAC is

the digital representation of the analog input voltage. The de-

vice moves from hold mode to track mode on the 13th rising

edge of SCLK.

20057709

FIGURE 4. ADCS7476/77/78 in Track Mode

20057710

FIGURE 5. ADCS7476/77/78 in Hold Mode

2.0 USING THE ADCS7476/77/78

Serial interface timing diagrams for the ADCS7476/77/78 are

shown in Figure 1, , and Figure 3. CS is chip select, which

initiates conversions and frames the serial data transfers.

SCLK (serial clock) controls both the conversion process and

the timing of serial data. SDATA is the serial data out pin,

where a conversion result is found.

Basic operation of the ADCS7476/77/78 begins with CS going

low, which initiates a conversion process and data transfer.

Subsequent rising and falling edges of SCLK will be labelled

with reference to the falling edge of CS; for example, "the third

falling edge of SCLK" shall refer to the third falling edge of

SCLK after CS goes low.

At the fall of CS, the SDATA pin comes out of TRI-STATE,

and the converter moves from track mode to hold mode. The

input signal is sampled and held for conversion at the falling

edge of CS. The converter moves from hold mode to track

mode on the 13th rising edge of SCLK (see Figure 1,

Figure 2, or Figure 3). The SDATA pin will be placed back into

TRI-STATE after the 16th falling edge of SCLK, or at the rising

edge of CS, whichever occurs first. After a conversion is com-

pleted, the quiet time tQUIET must be satisfied before bringing

CS low again to begin another conversion.

Sixteen SCLK cycles are required to read a complete sample

from the ADCS7476/77/78. The sample bits (including any

leading or trailing zeroes) are clocked out on falling edges of

SCLK, and are intended to be clocked in by a receiver on

subsequent falling edges of SCLK. The ADCS7476/77/78 will

produce four leading zeroes on SDATA, followed by twelve,

ten, or eight data bits, most significant first. After the data bits,

the ADCS7477 will clock out two trailing zeros, and the

ADCS7478 will clock out four trailing zeros. The ADCS7476

will not clock out any trailing zeros; the least significant data

bit will be valid on the 16th falling edge of SCLK.

Depending upon the application, the first edge on SCLK after

CS goes low may be either a falling edge or a rising edge. If

the first SCLK edge after CS goes low is a rising edge, all four

leading zeroes will be valid on the first four falling edges of

17 www.national.com

ADCS7476/ADCS7477/ADCS7478

SCLK. If instead the first SCLK edge after CS goes low is a

falling edge, the first leading zero may not be set up in time

for a microprocessor or DSP to read it correctly. The remain-

ing data bits are still clocked out on the falling edges of SCLK.

3.0 ADCS7476/77/78 TRANSFER FUNCTION

The output format of the ADCS7476/77/78 is straight binary.

Code transitions occur midway between successive integer

LSB values. The LSB widths for the ADCS7476 is VDD / 4096;

for the ADCS7477 the LSB width is VDD / 1024; for the

ADCS7478, the LSB width is VDD / 256. The ideal transfer

characteristic for the ADCS7476 and ADCS7477 is shown in

Figure 6, while the ideal transfer characteristic for the

ADCS7478 is shown in Figure 7.

20057711

FIGURE 6. ADCS7476/77 Ideal Transfer Characteristic

20057712

FIGURE 7. ADCS7478 Ideal Transfer Characteristic

www.national.com 18

ADCS7476/ADCS7477/ADCS7478

4.0 TYPICAL APPLICATION CIRCUIT

A typical application of the ADCS7476/77/78 is shown in

Figure 8. The combined analog and digital supplies are pro-

vided in this example by the National LP2950 low-dropout

voltage regulator, available in a variety of fixed and adjustable

output voltages. The supply is bypassed with a capacitor net-

work located close to the device. The three-wire interface is

also shown connected to a microprocessor or DSP.

20057713

FIGURE 8. Typical Application Circuit

5.0 ANALOG INPUTS

An equivalent circuit for the ADCS7476/77/78 input channel

is shown in Figure 9. The diodes D1 and D2 provide ESD

protection for the analog inputs. At no time should an analog

input exceed VDD + 300 mV or GND - 300 mV, as these ESD

diodes will begin conducting current into the substrate or sup-

ply line and affect ADC operation.

The capacitor C1 in Figure 9 typically has a value of 4 pF, and

is mainly due to pin capacitance. The resistor R1 represents

the on resistance of the multiplexer and track / hold switch,

and is typically 100 ohms. The capacitor C2 is the

ADCS7476/77/78 sampling capacitor, and is typically 26 pF.

The sampling nature of the analog input causes input current

pulses that result in voltage spikes at the input. The

ADCS7476/77/78 will deliver best performance when driven

by a low-impedance source to eliminate distortion caused by

the charging of the sampling capacitance. In applications

where dynamic performance is critical, the input might need

to be driven with a low output-impedance amplifier. In addi-

tion, when using the ADCS7476/77/78 to sample AC signals,

a band-pass or low-pass filter will reduce harmonics and

noise and thus improve THD and SNR.

20057714

FIGURE 9. Equivalent Input Circuit

6.0 DIGITAL INPUTS AND OUTPUTS

The ADCS7476/77/78 digital inputs (SCLK and CS) are not

limited by the same absolute maximum ratings as the analog

inputs. The digital input pins are instead limited to +6.5V with

respect to GND, regardless of VDD, the supply voltage. This

allows the ADCS7476/77/78 to be interfaced with a wide

range of logic levels, independent of the supply voltage.

Note that, even though the digital inputs are tolerant of up to

+6.5V above GND, the digital outputs are only capable of

driving VDD out. In addition, the digital input pins are not prone

to latch-up; SCLK and CS may be asserted before VDD with-

out any risk.

7.0 MODES OF OPERATION

The ADCS7476/77/78 has two possible modes of operation:

normal mode, and shutdown mode. The ADCS7476/77/78

enters normal mode (and a conversion process is begun)

when CS is pulled low. The device will enter shutdown mode

if CS is pulled high before the tenth falling edge of SCLK after

CS is pulled low, or will stay in normal mode if CS remains

low. Once in shutdown mode, the device will stay there until

CS is brought low again. By varying the ratio of time spent in

the normal and shutdown modes, a system may trade-off

throughput for power consumption.

8.0 NORMAL MODE

The best possible throughput is obtained by leaving the

ADCS7476/77/78 in normal mode at all times, so there are no

power-up delays. To keep the device in normal mode contin-

uously, CS must be kept low until after the 10th falling edge

of SCLK after the start of a conversion (remember that a con-

version is initiated by bringing CS low).

If CS is brought high after the 10th falling edge, but before the

16th falling edge, the device will remain in normal mode, but

the current conversion will be aborted, and SDATA will return

to TRI-STATE (truncating the output word).

Sixteen SCLK cycles are required to read all of a conversion

word from the device. After sixteen SCLK cycles have

elapsed, CS may be idled either high or low until the next

conversion. If CS is idled low, it must be brought high again

before the start of the next conversion, which begins when

CS is again brought low.

After sixteen SCLK cycles, SDATA returns to TRI-STATE.

Another conversion may be started, after tQUIET has elapsed,

by bringing CS low again.

9.0 SHUTDOWN MODE

Shutdown mode is appropriate for applications that either do

not sample continuously, or are willing to trade throughput for

power consumption. When the ADCS7476/77/78 is in shut-

down mode, all of the analog circuitry is turned off.

To enter shutdown mode, a conversion must be interrupted

by bringing CS back high anytime between the second and

tenth falling edges of SCLK, as shown in Figure 10. Once

CS has been brought high in this manner, the device will enter

shutdown mode; the current conversion will be aborted and

SDATA will enter TRI-STATE. If CS is brought high before the

second falling edge of SCLK, the device will not change

mode; this is to avoid accidentally changing mode as a result

of noise on the CS line.

19 www.national.com

ADCS7476/ADCS7477/ADCS7478

20057716

FIGURE 10. Entering Shutdown Mode

10.0 EXITING SHUTDOWN MODE

20057717

FIGURE 11. Entering Normal Mode

To exit shutdown mode, bring CS back low. Upon bringing

CS low, the ADCS7476/77/78 will begin powering up. Power

up typically takes 1 µs. This microsecond of power-up delay

results in the first conversion result being unusable. The sec-

ond conversion performed after power-up, however, is valid,

as shown in Figure 11.

If CS is brought back high before the 10th falling edge of

SCLK, the device will return to shutdown mode. This is done

to avoid accidentally entering normal mode as a result of

noise on the CS line. To exit shutdown mode and remain in

normal mode, CS must be kept low until after the 10th falling

edge of SCLK. The ADCS7476/77/78 will be fully powered-

up after 16 SCLK cycles.

11.0 POWER-UP TIMING

The ADCS7476/77/78 typically requires 1 µs to power up, ei-

ther after first applying VDD, or after returning to normal mode

from shutdown mode. This corresponds to one "dummy" con-

version for any SCLK frequency within the specifications in

this document. After this first dummy conversion, the AD-

CS7476/77/78 will perform conversions properly. Note that

the tQUIET time must still be included between the first dummy

conversion and the second valid conversion.

12.0 STARTUP MODE

When the VDD supply is first applied, the ADCS7476/77/78

may power up in either of the two modes: normal or shutdown.

As such, one dummy conversion should be performed after

start-up, exactly as described in Section 11.0 POWER-UP

TIMING. The part may then be placed into either normal mode

or the shutdown mode, as described in Section 8.0 NORMAL

MODE and Section 9.0 SHUTDOWN MODE.

13.0 POWER CONSIDERATIONS

There are three concerns relating to the power supply of these

products: the effects of power supply noise upon the conver-

sion process, the digital output loading effects upon the con-

version process and managing total power consumption of

the product.

13.1 Power Supply Noise

Since the reference voltage of the ADCS7476/77/78 is the

reference voltage, any noise greater than 1/2 LSB in ampli-

tude will have some effect upon the converter noise perfor-

mance. This effect is proportional to the input voltage level.

The power supply should receive all the considerations of a

reference voltage as far as stability and noise is concerned.

Using the same supply voltage for these devices as is used

for digital components will lead to degraded noise perfor-

mance.

13.2 Digital Output Effect Upon Noise

The charging of any output load capacitance requires current

from the digital supply, VDD. The current pulses required from

the supply to charge the output capacitance will cause voltage

variations at the ADC supply line. If these variations are large

enough, they could degrade SNR and SINAD performance of

the ADC. Similarly, discharging the output capacitance when

the digital output goes from a logic high to a logic low will dump

current into the die substrate, causing "ground bounce" noise

in the substrate that will degrade noise performance if that

current is large enough. The larger the output capacitance,

the more current flows through the device power supply line

and die substrate and the greater is the noise coupled into the

analog path.

The first solution to keeping digital noise out of the power

supply is to decouple the supply from any other components

or use a separate supply for the ADC. To keep noise out of

the supply, keep the output load capacitance as small as

practical. If the load capacitance is greater than 50 pF, use a

100 Ω series resistor at the ADC output, located as close to

the ADC output pin as practical. This will limit the charge and

discharge current of the output capacitance and improve

noise performance. Since the series resistor and the load ca-

www.national.com 20

ADCS7476/ADCS7477/ADCS7478

pacitance form a low frequency pole, verify signal integrity

once the series resistor has been added.

13.3 Power Management

When the ADCS7476/77/78 is operated continuously in nor-

mal mode, throughput up to 1 MSPS can be achieved. The

user may trade throughput for power consumption by simply

performing fewer conversions per unit time, and putting the

ADCS7476/77/78 into shutdown mode between conversions.

This method is not advantageous beyond 350 kSPS through-

put.

A plot of maximum power consumption versus throughput is

shown in Figure 12. To calculate the power consumption for

a given throughput, remember that each time the part exits

shutdown mode and enters normal mode, one dummy con-

version is required. Generally, the user will put the part into

normal mode, execute one dummy conversion followed by

one valid conversion, and then put the part back into shut-

down mode. When this is done, the fraction of time spent in

normal mode may be calculated by multiplying the throughput

(in samples per second) by 2 µs, the time taken to perform

one dummy and one valid conversion. The power consump-

tion can then be found by multiplying the fraction of time spent

in normal mode by the normal mode power consumption fig-

ure. The power dissipated while the part is in shutdown mode

is negligible.

For example, to calculate the power consumption at 300

kSPS with VDD = 5V, begin by calculating the fraction of time

spent in normal mode: 300,000 samples/second x 2 µs = 0.6,

or 60%. The power consumption at 300 kSPS is then 60% of

17.5 mW (the maximum power consumption at VDD = 5V) or

10.5 mW.

20057755

FIGURE 12. Maximum Power Consumption vs. Throughput

14.0 LAYOUT AND GROUNDING

Capacitive coupling between noisy digital circuitry and sensi-

tive analog circuitry can lead to poor performance. The solu-

tion is to keep the analog and digital circuitry separated from

each other and the clock line as short as possible.

Digital circuits create substantial supply and ground current

transients. This digital noise could have significant impact up-

on system noise performance. To avoid performance degra-

dation of the ADCS7476/77/78 due to supply noise, do not

use the same supply for the ADCS7476/77/78 that is used for

digital logic.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. However, to maximize accuracy in high

resolution systems, avoid crossing analog and digital lines al-

together. It is important to keep clock lines as short as possi-

ble and isolated from ALL other lines, including other digital

lines. In addition, the clock line should also be treated as a

transmission line and be properly terminated.

The analog input should be isolated from noisy signal lines to

avoid coupling of spurious signals into the input. Any external

component (e.g., a filter capacitor) connected between the

converter’s input pins and ground or to the reference input pin

and ground should be connected to a very clean point in the

ground plane.

We recommend the use of a single, uniform ground plane and

the use of split power planes. The power planes should be

located within the same board layer. All analog circuitry (input

amplifiers, filters, reference components, etc.) should be

placed over the analog power plane. All digital circuitry and I/

O lines should be placed over the digital power plane. Fur-

thermore, all components in the reference circuitry and the

input signal chain that are connected to ground should be

connected together with short traces and enter the analog

ground plane at a single, quiet point.

21 www.national.com

ADCS7476/ADCS7477/ADCS7478

Physical Dimensions inches (millimeters) unless otherwise noted

6-Lead SOT-23

Order Number ADCS7476AIMF, ADCS7476AIMFX, ADCS7477AIMF, ADCS7477AIMFX, ADCS7478AIMF or

ADCS7478AIMFX

NS Package Number MF06A

6-Lead LLP

Order Number ADCS4746AISD, ADCS7476AISDX, ADCS7477AISD, ADCS4747AISDX, ADCS7478AISD, ADCS7478AISDX

NS Package Number SDB06A

www.national.com 22

ADCS7476/ADCS7477/ADCS7478

Notes

23 www.national.com

ADCS7476/ADCS7477/ADCS7478

Notes

ADCS7476/ADCS7477/ADCS7478 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP

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