ADC16061
Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter
General Description
The ADC16061 is a self-calibrating 16-bit, 2.5 Megasample
per second analog to digital converter. It operates on a single
+5V supply, consuming just 390mW (typical).
The ADC16061 provides an easy and affordable upgrade
from 12 bit and 14 bit converters. The ADC16061 may also
be used to replace many hybrid converters with a resultant
saving of space, power and cost.
The ADC16061 operates with excellent dynamic perfor-
mance at input frequencies up to
1
⁄
2
the clock frequency. The
calibration feature of theADC16061 can be used to get more
consistent and repeatable results over the entire operating
temperature range. On-command self-calibration reduces
many of the effects of temperature-induced drift, resulting in
more repeatable conversions.
The Power Down feature reduces power consumption to
less than 2mW.
TheADC16061 comes in aTQFPand is designed to operate
over the commercial temperature range of 0˚C to +70˚C.
Features
nSingle +5V Operation
nSelf Calibration
nPower Down Mode
Key Specifications
nResolution 16 Bits
nConversion Rate 2.5 Msps (min)
nDNL 1.0 LSB (typ)
nSNR (f
IN
= 500 kHz) 80 dB (typ)
nSupply Voltage +5V ±5%
nPower Consumption 390mW (typ)
Applications
nPC-Based Data Acquisition
nDocument Scanners
nDigital Copiers
nFilm Scanners
nBlood Analyzers
nSonar/Radar
Connection Diagram
Ordering Information
Commercial
(0˚C ≤TA ≤+70˚C) Package
ADC16061CCVT VEG52A 52 Pin Thin Quad Flat Pack
DS100889-1
January 2000
ADC16061 Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter
© 2000 National Semiconductor Corporation DS100889 www.national.com
Block Diagram
DS100889-2
ADC16061
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Pin Descriptions and Equivalent Circuits
Pin
No. Symbol Equivalent Circuit Description
Analog I/O
1V
IN
+Non-Inverting analog signal Input. With a 2.0V reference voltage
and a 2.0V common mode voltage, V
CM
, the input signal voltage
range is from 1.0 volt to 3.0 Volts.
4V
IN
−
Inverting analog signal Input. With a 2.0V reference voltage and a
2.0V common mode voltage, V
CM
, the input signal voltage range is
from 1.0 Volt to 3.0 Volts. The input signal should be balanced for
best performance.
48 V
REF
+
IN
Positive reference input. This pin should be bypassed to AGND
with a 0.1 µF monolithic capacitor.
V
REF
+ minus V
REF− IN
should be a minimum of 1.8V and a
maximum of 2.2V. The full-scale input voltage is equal to V
REF
+
IN
minus V
REF
−
IN
.
47 V
REF
−
IN
Negative reference input. In most applications this pin should be
connected to AGND and the full reference voltage applied to
V
REF
+
IN
. If the application requires that V
REF
−
IN
be offset from
AGND, this pin should be bypassed to AGND with a 0.1 µF
monolithic capacitor. V
REF
+
IN
minus V
REF− IN
should be a
minimum of 1.8V and a maximum of 2.2V. The full-scale input
voltage is equal to V
REF
+
IN
minus V
REF
−
IN
.
50 V
REF
+
OUT
Output of the high impedance positive reference buffer. With a
2.0V reference input, and with a V
CM
of 2.0V, this pin will have a
3.0V output voltage. This pin should be bypassed to AGND with a
0.1 µF monolithic capacitor in parallel with a 10 µF capacitor.
49 V
REF
−
OUT
The output of the negative reference buffer. With a 2.0V reference
andaV
CM
of 2.0V, this pin will have a 1.0V output voltage. This
pin should be bypassed to AGND with a 0.1 µF monolithic
capacitor in parallel with a 10 µF capacitor.
52 V
REF (MID)
Output of the reference mid-point, nominally equal to 0.4 V
A
(2.0V). This pin should be bypassed to AGND with a 0.1 µF
monolithic capacitor. This voltage is derived from V
CM
.
51 V
CM
Input to the common mode buffer, nominally equal to 40%of the
supply voltage (2.0V). This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. Best performance is obtained if this
pin is driven with a low impedance source of 2.0V.
ADC16061
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Pin Descriptions and Equivalent Circuits (Continued)
Digital I/O
10 CLOCK
Digital clock input. The input voltage is captured t
AD
after the fall of
the clock signal. The range of frequencies for this input is 300 kHz
to 2.5 MHz. The clock frequency should not be changed or
interrupted during conversion or while reading data output.
11 CAL
CAL is a level-sensitive digital input that, when pulsed high for at
least two clock cycles, puts the ADC into the CALIBRATE mode.
Calibration should be performed upon ADC power-up (after
asserting a reset) and each time the temperature changes by more
than 50˚C since the ADC16061 was last calibrated. See Section
2.3 for more information.
40 RESET
RESET is a level-sensitive digital input that, when pulsed high for
at least 2 CLOCK cycles, results in the resetting of the ADC. This
reset pulse must be applied after ADC power-up, before
calibration.
18 RD RD is the (READ) digital input that, when low, enables the output
data buffers. When this input pin is high, the output data bus is in
a high impedance state.
44 PD PD is the Power Down input that, when low, puts the converter
into the power down mode. When this pin is high, the converter is
in the active mode.
17 EOC EOC is a digital output that, when low, indicates the availability of
new conversion results at the data output pins.
21-32
35-38 D00-15 Digital data outputs that make up the 16-bit TRI-STATE conversion
results. D00 is the LSB, while D15 is the MSB (SIGN bit) of the
two’s complement output word.
Analog Power
6, 7,
45 V
A
Positive analog supply pins. These pins should be connected to a
clean, quiet +5V source and bypassed to AGND with 0.1 µF
monolithic capacitors in parallel with 10 µF capacitors, both located
within 1 cm of these power pins.
5, 8,
46 AGND The ground return for the analog supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and grounding) for more details).
ADC16061
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Pin Descriptions and Equivalent Circuits (Continued)
Digital Power
20 V
D
Positive digital supply pin. This pin should be connected to the
same clean, quiet +5V source as is V
A
and bypassed to DGND
with a 0.1 µF monolithic capacitor in parallel with a 10µF capacitor,
both located within 1 cm of the power pin.
12,
13,
14,
19,
41,
42, 43
DGND
The ground return for the digital supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and Grounding) for more details.
34 V
D
I/O
Positive digital supply pin for the ADC16061’s output drivers. This
pin should be connected to a +3V to +5V source and bypassed to
DGND I/O with a 0.1 µF monolithic capacitor. If the supply for this
pin is different from the supply used for V
A
and V
D
, it should also
be bypassed with a 10 µF capacitor. All bypass capacitors should
be located within 1 cm of the supply pin.
33 DGND I/O
The ground return for the digital supply for the ADC16061’s output
drivers. This pin should be connected to the system digital ground,
but not be connected in close proximity to the ADC16061’s DGND
or AGND pins. See Section 5.0 (Layout and Grounding) for more
details.
NC
2, 3,
9, 15,
16, 39 NC
All pins marked NC (no connect) should be left floating. Do not
connect the NC pins to ground, power supplies, or any other
potential or signal. These pins are used for test in the
manufacturing process.
ADC16061
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
A
,V
D
,V
D
I/O) 6.5V
Voltage on Any I/O Pin −0.3V to V
+
+0.3V
Input Current at Any Pin (Note 3) ±25mA
Package Input Current (Note 3) ±50mA
Power Dissipation at T
A
=25˚C (Note 4)
ESD Susceptibility (Note 5)
Human Body Model 1500V
Machine Model 200V
Soldering Temp., Infrared, 10 sec. (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings(Notes 1, 2)
Operating Temperature
Range 0˚C ≤T
A
≤+70˚C
V
A,
V
D
+4.75V to +5.25V
V
D
I/O 2.7V to V
D
V
REF
− IN 1.0V to 3.0V
V
REF
− IN AGND to 0.1V
Digital Inputs −0.05V to V
D
+ 0.05V
|V
A
−V
D
|≤100 mV
|AGND - DGND | 0V to 100 mV
Converter Electrical Characteristics
The following specifications apply for AGND =DGND =DGND I/O =0V, V
+
=V
A
=V
D
=+5.0V, V
D
I/O =3.0V or 5.0V,
PD =+5V, V
REF+ IN
=+2.0V, V
REF− IN
=AGND, f
CLK
=2.5 MHz, C
L
=50 pF/pin. After Auto-Cal. Boldface limits apply for
T
A
=T
J
=T
MIN
to T
MAX
:all other limits T
A
=T
J
=25˚C(Notes 7, 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
Static Converter Characteristics
Resolution with No
Missing Codes 15 Bits(min)
INL Integral Non Linearity At 16 Bits ±3±9LSB(max)
DNL Differential Non Linearity At 16 Bits ±1+3 LSB(max)
−2 LSB(min)
Full-Scale Error ±0.6 3.0 %FS(max)
Zero Offset Error +0.1 ±0.7 %FS(max)
Reference and Analog Input Characteristics
V
IN
Input Voltage Range
(V
IN+
−V
IN−
)2.0 1.8
2.2 V(min)
V(max)
C
IN
Input Capacitance V
IN
=1.0V + 0.7Vrms
(CLK
LOW) 12 pF
(CLK
HIGH) 28 pF
V
REF
Reference Voltage
Range [( V
REF
+
IN
)−
(V
REF
−
IN
)] (Note 14) 2.00 1.8 V(min)
2.2 V(max)
Reference Input
Resistance 3.5 KΩ
Dynamic Converter Characteristics
BW Full Power Bandwidth 8 MHz
SNR Signal-to-Noise Ratio f
IN
=500 kHz 80 dB
SINAD Signal-to-Noise &
Distortion f
IN
=500 kHz 79 dB
THD Total Harmonic
Distortion f
IN
=500 kHz −88 dB
SFDR Spurious Free Dynamic
Range f
IN
=500 kHz 91 dB
IMD Intermodulation
Distortion f
IN1
=95 kHz
f
IN2
=105 kHz −97 dB
ADC16061
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DC and Logic Electrical Characteristics
The following specifications apply for AGND =DGND =DGND I/O =0V, V
+
=V
A
=V
D
=+5.0V, V
D
I/O =3.0V or 5.0V,
PD =+5V, V
REF+
=+2.0V, V
REF IN
=AGND, f
CLK
=2.5 MHz, RS =25Ω,C
L
=50 pF/pin. After Auto-Cal. Boldface limits
apply for T
A
=T
J
=T
MIN
to T
MAX
:all other limits T
A
=T
J
=25˚C(Notes 7, 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
CLOCK, RD, PD Digital Input Characteristics
V
IN(1)
Logical ″1″Input Voltage V
+
=5.25V 2.0 V(min)
V
IN(0)
Logical ″0″Input Voltage V
+
=4.75V 0.8 V(max)
I
IN(1)
Logical ″1″Input Current V
IN
=5.0V 5 µA
I
IN(0)
Logical ″0″Input Current V
IN
=0V −5 µA
C
IN
V
IN
Input Capacitance 5 pF
CAL, RESET Digital Input Characteristics
V
IN(1)
Logical ″1″Input Voltage V
+
=5.25V 3.5 V(min)
V
IN(0)
Logical ″0″Input Voltage V
+
=4.75V 1.0 V(max)
I
IN(1)
Logical ″1″Input Current V
IN
=5.0V 5 µA
I
IN(0)
Logical ″0″Input Current V
IN
=0V −5 µA
C
IN
Input Capacitance 5 pF
D00 - D13 Digital Output Characteristics
V
OUT(1)
Logical ″1″Output
Voltage V
D
I/O =4.75V, I
OUT
=−360 µA 4.5 V(min)
V
OUT(1)
Logical ″1″Output
Voltage V
D
I/O =2.7V, I
OUT
=−360 µA 2.5 V(min)
V
OUT(0)
Logical ″0″Output
Voltage V
D
I/O =5.25V, I
OUT
=1.6 mA 0.4 V(max)
V
D
I/O =3.3V, I
OUT
=1.6 mA 0.4 V(max)
I
OZ
TRI-STATE Output
Current V
OUT
=3V or 5V 100 nA
V
OUT
=0V −100 nA
+I
SC
Output Short Circuit
Source Current V
OUT
=0V, V
D
I/O =3V −10 mA
−I
SC
Output Short Circuit Sink
Current V
OUT
=V
D
I/O =3V 12 mA
Power Supply Characteristics
I
A
Analog Supply Current PD =V
D
I/O 70 85 mA(max)
I
D
Digital Supply Current PD =V
D
I/O 7 8mA(max)
I
D
I/O Output Bus Supply
Current PD =V
D
I/O 1 2mA(max)
Total Power
Consumption PD =V
D
I/O 390 475 mW(max)
PD =DGND <2mW
PSRR Power Supply Rejection
Ratio
Change in Full Scale as V
A
goes from
4.25V to 5.25V 68 dB
100 mV
PP
100 kHz riding on V
A
54 dB
AC Electrical Characteristics
The following specifications apply for AGND =DGND =DGND I/O =0V, V
+
=V
A
=V
D
=+5.0V, V
D
I/O =3.0V or 5.0V,
PD =+5V, V
REF
+=+2.0V, V
REF IN
=AGND, f
CLK
=2.5 MHz, RS =25Ω,C
L
=50 pF/pin. After Auto-Cal. Boldface limits
apply for T
A
=T
J
=T
MIN
to T
MAX
:all other limits T
A
=T
J
=25˚C(Notes 7, 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
(Limits)
f
CLK
Conversion Clock (CLOCK)
Frequency 300 kHz(min)
32.5 MHz(max)
Conversion Clock Duty Cycle 45
55 %(min)
%(max)
t
CONV
Conversion Latency 13 Clock Cycles
t
AD
Aperture Delay 9 ns
ADC16061
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AC Electrical Characteristics (Continued)
The following specifications apply for AGND =DGND =DGND I/O =0V, V
+
=V
A
=V
D
=+5.0V, V
D
I/O =3.0V or 5.0V,
PD =+5V, V
REF
+=+2.0V, V
REF IN
=AGND, f
CLK
=2.5 MHz, RS =25Ω,C
L
=50 pF/pin. After Auto-Cal. Boldface limits
apply for T
A
=T
J
=T
MIN
to T
MAX
:all other limits T
A
=T
J
=25˚C(Notes 7, 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
(Limits)
t
OD
Falling edge of CLK to Data
Valid 50 ns
t
EOCL
Falling edge of CLK to falling
edge of EOC 1/(4f
CLK
)90
130 ns(min)
ns(max)
t
DATA_VALID
Falling edge of CLOCK to Data
Valid 1/(8f
CLK
)38
95 ns(min)
ns(max)
t
AD
Aperture Delay 9 ns
t
ON
RD low to data valid on D00
-D15 23 33 ns(max)
t
OFF
RD high to D00 -D15 in
TRI-STATE 25 33 ns(max)
t
CAL
Calibration Time 110 ms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND =AGND =DGND I/O =0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN <AGND or VIN >VAor VD), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(T
J
max - TA)/θJA. In the 52-pin
TQFP, θJA is 70˚C/W, so PDMAX = 1,785 mW at 25˚C and 1,142 mW at the maximum operating ambient temperature of 70˚C. Note that the power dissipation of this
device under normal operation will typically be about 416 mW (390 mW quiescent power + 26 mW due to 1 TTL load on each digital output. The values for maximum
power dissipation listed above will be reached only when the ADC16061 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩresistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: See AN450, ″Surface Mounting Methods and Their Effect on Product Reliability″, or the section entitled ″Surface Mount″found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltages above VAor below GND will not damage this device, provided current is limited per Note 3. How-
ever, errors in the A/D conversion can occur if the input goes above VAor below GND by more than 100 mV. As an example, if VAis 4.75 VDC, the full-scale input
voltage must be ≤4.85VDC to ensure accurate conversions
Note 8: To guarantee accuracy, it is required that VAand VDbe connected together and to the same power supply with separate bypass capacitors at each V+pin.
Note 9: With the test condition for VREF =(VREF+)−(V
REF−) given as +2.0V, the 16-bit LSB is 30 µV.
Note 10: Typical figures are at TA=TJ=25˚C, and represent most likely parametric norms.
Note 11: Tested limits are guaranteed to Nationsl’s AOQL (Average Outgoing Quality Level) with 50%duty cycle clock.
Note 12: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13: Timing specifications are tested at the TTL logic levels, VIL =0.4V for a falling edge and VIH =2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 14: Optimum SNR performance will be obtained by keeping the reference voltage in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), or the
LM4041CIZ-ADJ (TO-92 package), bandgap voltage reference is recommended for this application.
DS100889-11
ESD Protection Scheme for Digital Input pins
DS100889-12
ESD Protection Scheme for Analog Input and Digital
Output pins
ADC16061
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Electrical Characteristics (continued)
DS100889-13
FIGURE 1. Transfer Characteristics
DS100889-14
FIGURE 2. Errors removed by Auto-Cal cycle
ADC16061
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Typical Performance Characteristics
INL vs Temperature
DS100889-25
DNL vs Temperature
DS100889-26
SNR vs Temperature
DS100889-27
INL vs V
REF
and Temperature
DS100889-35
DNL vs V
REF
DS100889-34
THD vs Temperaure
DS100889-28
SINAD & ENOB vs Temperature
DS100889-29
SINAD & ENOB vs Clock Duty
Cycle
DS100889-30
SFDR vs Temperature
DS100889-31
IMD
DS100889-32
Spectral Response
DS100889-33
ADC16061
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Specification Definitions
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY is the time required after the falling
edge of the clock for the sampling switch to open. In other
words, for the Track/Hold circuit to go from ’track’ mode into
the ’hold’ mode. The Track/Hold circuit affectively stops cap-
turing the input signal and goes into the ’hold’ mode t
AD
after
the fall of the clock.
OFFSET ERROR is the difference between the ideal LSB
transition to the actual transition point. The LSB transition
should occur when V
IN
+=V
IN
−.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD
−1.76) / 6.02.
FULL SCALE ERROR is the difference between the input
voltage [(V
IN
+)−(V
IN
−)] just causing a transition to positive
full scale and V
REF
− 1.5 LSB, where V
REF
is(V
REF
+
IN
)−
(V
REF
−
IN
).
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with f
IN
equal to 100 kHz plus integral multiples
of f
CLK
. The input frequency at which the output is −3 dB
relative to the low frequency input signal is the full power
bandwidth.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to theADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from nega-
tive full scale (
1
⁄
2
LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output stage. Data for any given sample is
available the Pipeline Delay plus the Output Delay after that
sample is taken. New data is available at every clock cycle,
but the data lags the conversion by the pipeline delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SI-
NAD)) is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral com-
ponents below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first six harmonic
components, to the rms value of the input signal.
Timing Diagrams
DS100889-15
TIMING DIAGRAM 1. Output Timing
ADC16061
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Timing Diagrams (Continued)
DS100889-16
TIMING DIAGRAM 2. Reset and Calibration Timing
ADC16061
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Functional Description
Operating on a single +5V supply, the ADC16061 uses a
pipelined architecture and has error correction circuitry and a
calibration mode to help ensure maximum performance at all
times.
Balanced analog signals with a peak-to-peak voltage equal
to the input reference voltage, V
REF
, and centered around
the common mode input voltage, V
CM
, are digitized to 16 bits
(15 bits plus sign). Neglecting offsets, positive input signal
voltages (V
IN
+−V
IN
−≥0) produce positive digital output
data and negative input signal voltages (V
IN
+−V
IN
−<0)
produce negative output data. The input signal can be digi-
tized at any clock rate between 300 Ksps and 2.5 Msps.
Input voltages below the negative full scale value will cause
the output word to take on the negative full scale value of
1000,0000,0000,0000. Input voltage above the positive full
scale value will cause the output word to take on the positive
full scale value of 0111,1111,1111,1111.
The output word rate is the same as the clock frequency. The
analog input voltage is acquired at the falling edge of the
clock and the digital data for that sample is delayed by the
pipeline for 13 clock cycles plus t
DATA_VALID
. The digital out-
put is undefined if the chip is being reset or is in the calibra-
tion mode. The output signal may be inhibited by the RD pin
while the converter is in one of these modes.
The RD pin must be low to enable the digital outputs. A logic
low on the power down (PD) pin reduces the converter
power consumption to less than two milliwatts.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC16061:
4.75V ≤V
A
≤5.25V
5.25V ≤V
D
≤5.25V
3.0V ≤V
D
I/O ≤V
D
0.3MHz ≤f
CLK
≤2.5 MHz
V
CM
=2.0V (forced)
V
REF IN
+=2.0V
V
REF IN
−=AGND
1.1 The Analog Inputs
TheADC16061 has two analog signal inputs, V
IN
+ and V
IN
−.
These two pins form a balanced input. There are two refer-
ence pins, V
REF
+
IN
and V
REF
−
IN
. These pins form a differ-
ential input reference.
1.2 Reference Inputs
V
REF
+
IN
should always be more positive than V
REF
−
IN
. The
effective reference voltage, V
REF
, is the difference between
these two voltages:
V
REF
=(V
REF
+
IN
)−(V
REF
−
IN
).
The operational voltage range of V
REF
+
IN
is +1.8 Volts to
+3.0 Volts. The operational voltage range of V
REF
−
IN
is
ground to 1.0V. For best performance, the difference be-
tween V
REF
+
IN
and V
REF
−
IN
should remain within the range
of 1.8V to 2.2V. Reducing the reference voltage below 1.8V
will decrease the signal-to-noise ratio (SNR) of the
ADC16061. Increasing the reference voltage (and, conse-
quently, the input signal swing) above 2.2V will increase
THD.
V
REF (MID)
is the reference mid-point and is derived from
V
CM
. This point is brought out only to be by passed. Bypass
this pin with 0.1µF capacitor to ground. Do not load this pin.
It is very important that all grounds associated with the refer-
ence voltage make connection to the analog ground plane at
a single point to minimize the effects of noise currents in the
ground path.
1.3 Signal Inputs
The signal inputs are V
IN
+ and V
IN
−. The signal input, V
IN
,
is defined as V
IN
=(V
IN
+)−(V
IN
−).
Figure 3
indicates the relationship between the input voltage
and the reference voltages.
Figure 4
shows the expected in-
put signal range.
The ADC16061 performs best with a balanced input cen-
tered around V
CM
. The peak-to-peak voltage swing at either
V
IN
+orV
IN
− should be less than the reference voltage and
each signal input pin should be centered on the V
CM
voltage.
The two V
CM
-centered input signals should be exactly 180˚
out of phase from each other. As a simple check to ensure
this, be certain that the average voltage at the ADC input
pins is equal to V
CM
. Drive the analog inputs with a source
impedance less than 100 Ohms.
DS100889-17
FIGURE 3. Typical Input to Reference Relationship.
DS100889-18
FIGURE 4. Expected Input Signal Range.
ADC16061
www.national.com13
Applications Information (Continued)
The sign bit of the output word will be a logic low when V
IN
+
is greater than V
IN
− . When V
IN
+ is less than V
IN
−, the sign
bit of the output word will be a logic high.
For single ended operation, one of the analog inputs should
be connected to V
CM
. However, SNR and SINAD are re-
duced by about 12dB with a single ended input as compared
with differential inputs.
An input voltage of V
IN
=(V
IN
+)−(V
IN
−) =0 will be inter-
preted as mid-scale and will thus be converted to
0000,0000,0000,0000, plus any offset error.
The V
IN
+ and the V
IN
− inputs of the ADC16061 consist of an
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 12 pF when the clock is low,
and 28 pF when the clock is high. It is recommended that the
ADC16061 be driven with a low impedance source of 100
Ohms or less.
Since a dynamic capacitance is more difficult to drive than is
a fixed capacitance, choose driving amplifiers carefully. The
CLC440, LM6152, LM6154, LM6172, LM6181 and LM6182
are good amplifiers for driving the ADC16061.
Asimple application circuit is shown in
Figure 6
and
Figure 7
.
Here we use two LM6172 dual amplifiers to provide a bal-
anced input to the ADC16061. Note that better noise perfor-
mance is achieved when V
REF
+
IN
voltage is forced with a
well-bypassed resistive divider. The resulting offset and off-
set drift is minimal.
1.4 V
CM
Analog Inputs
The V
CM
input of the ADC16061 is internally biased to 40%
of the V
A
supply with on-chip resistors, as shown in
Figure 5
.
The V
CM
pin must be bypassed to prevent any power supply
noise from modulating this voltage. Modulation of the V
CM
potential will result in the introduction of noise into the input
signal. The advantage of simply bypassing V
CM
(without
driving it) is the circuit simplicity. On the other hand, if the V
A
supply can vary for any reason, V
CM
will also vary at a rate
and amplitude related to the RC filter created by the bypass
capacitor and the internal divider resistors. However, perfor-
mance of this approach will be adequate for many
applications.
By forcing V
CM
to a fixed potential, you can avoid the prob-
lems mentioned above. One such approach is to buffer the
2.0 Volt reference voltage to drive the V
CM
input, holding it at
a constant potential as shown in
Figure 6
and
Figure 8
.Ifthe
reference voltage is different from the desired V
CM
, that de-
sired V
CM
voltage may be derived from the reference or from
another stable source.
Note that the buffer used for this purpose should be a slow,
low noise amplifier. The LMC660, LMC662, LMC272 and
LMC7101 are good choices for driving the V
CM
pin of the
ADC16061.
If it is desired to use a multiplexer at the analog input, that
multiplexer should be switched at the rising edge of the clock
signal.
2.0 DIGITAL INPUTS
Digital Inputs consist of CLOCK, RESET, CAL, RD and PD.
All digital input pins should remain stable from the fall of the
clock until 30ns after the fall of the clock to minimize digital
noise corruption of the input signal on the die.
2.1 The CLOCK signal drives an internal phase delay loop to
create timing for theADC. Drive the clock input with a stable,
low phase jitter clock signal in the range of 300 kHz to 2.5
MHz. The trace carrying the clock signal should be as short
as possible. This trace should not cross any other signal line,
analog or digital, not even at 90˚.
The CLOCK signal also drives the internal state machine. If
the clock is interrupted, the data within the pipeline could be-
come corrupted.
A 100 Ohm damping resistor should be placed in series with
the CLOCK pin to prevent signal undershoot at that input.
2.2 The RESET input is level sensitive and must be pulsed
high for at least two clock cycles to reset the ADC after
power-up and before calibration (See Timing Diagram 2).
2.3 The CAL input is level sensitive and must be pulsed high
for at least two clock cycles to begin ADC calibration (See
Timing Diagram 2). Reset the ADC16061 before calibrating.
Re-calibrate after the temperature has changed by more
than 50˚C since the last calibration was performed and after
return from power down.
During calibration, use the same clock frequency that will be
used for conversions to avoid excessive offset errors.
Calibration takes 272,800 clock cycles. Irrelevant data may
appear at the data outputs during RESET or CAL and for 13
clock cycles thereafter. Calibration should not be started until
the reference outputs have settled (100ms with 1µF capaci-
tors on these outputs) after power up or coming out of the
power down mode.
2.4 RD pin is used to READ the conversion data. When the
RD pin is low, the output buffers go into the active state.
When the RD input is high, the output buffers are in the high
impedance state.
2.5 The PD pin, when low, holds the ADC16061 in a
power-down mode where power consumption is typically
less than 2mW to conserve power when the converter is not
being used. Power consumption during shut-down is not af-
fected by the clock frequency, or by whether there is a clock
signal present. The data in the pipeline is corrupted while in
the power down mode. The ADC16061 should be reset and
calibrated upon returning to normal operation after a power
down.
3.0 OUTPUTS
The ADC16061 has four analog outputs: V
REF
+
OUT
,
V
REF
−
OUT
,V
REF (MID)
and V
CM
. There are 17 digital out-
puts: EOC (End of Conversion) and 16 Data Output pins.
3.1 The reference output voltages are made available only
for the purpose of bypassing with capacitors. These pins
should not be loaded with more than 10 µADC. These output
voltages are described as
V
REF
+
OUT
=V
CM
+
1
⁄
2
V
REF
DS100889-21
FIGURE 5. V
CM
input to the ADC16061 V
CM
is set to
40%of V
A
with on-chip resistors. Performance is
improved when V
CM
is driven with a stable, low
impedance source
ADC16061
www.national.com 14
Applications Information (Continued)
V
REF
−
OUT
=V
CM
−
1
⁄
2
V
REF
where V
REF
=(V
REF
+
IN
)−(V
REF
+ IN)
V
REF (MID)
=(V
REF
+
OUT
+V
REF
−
OUT
)/2.
To avoid signal clipping and distortion, V
REF
+
OUT
should not
exceed 3.3V, V
REF
−
OUT
should not be below 750 mV and
V
CM
should be held in the range of 1.8V to 2.2V.
3.2 The EOC output goes low to indicate the presence of
valid data at the output data lines. Valid data is present the
entire time that this signal is low, except during reset. Corrupt
or irrelevant data may appear at the data outputs when the
RESET pin or the CAL pin is high.
3.3 The Data Outputs are TTL/CMOS compatible. The out-
put data format is two’s complement. Valid data is present at
these outputs while the EOC pin is low. While the t
EOCL
time
and the t
DATA_VALID
time provide information about output
timing, a simple way to capture a valid output is to latch the
data on the rising edge of the CLOCK (pin 10).
Also helpful in minimizing noise due to output switching is to
minimize the load currents at the digital outputs. This can be
done by connecting buffers between the ADC outputs and
any other circuitry. Only one input should be connected to
each output pin. Additionally, inserting series resistors of 47
or 56 Ohms at the digital outputs, close to the ADC pins, will
isolate the outputs from other circuitry and limit output cur-
rents. (See
Figure 6
).
4.0 POWER SUPPLY CONSIDERATIONS
Each power supply pin should be bypassed with a parallel
combination of a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. The chip capacitors should be within
1
⁄
2
centimeter
of the power pins. Leadless chip capacitors are preferred be-
cause they provide low lead inductance.
While a single 5V source is used for the analog and digital
supplies of the ADC16061, these supply pins should be well
isolated from each other to prevent any digital noise from be-
ing coupled to the analog power pins. Supply isolation with
ferrite beads is shown in
Figure 6
and
Figure 8
.
As is the case with all high-speed converters, theADC16061
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 15 mV
P-P
.
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even during power up or power
down.
The V
D
I/O provides power for the output drivers and may be
operated from a supply in the range of 2.7V to the V
D
supply
(nominal 5V). This can simplify interfacing to 3.0 Volt devices
and systems. Powering V
D
I/O from 3 Volts will also reduce
power consumption and noise generation due to output
switching. DO NOT operate the V
D
I/O at a voltage higher
than V
D
or V
A
.
DS100889-19
FIGURE 6. Simple application circuit with single-ended to differential buffer.
ADC16061
www.national.com15
Applications Information (Continued)
DS100889-20
FIGURE 7. Differential drive circuit of
Figure 6
. All 5k resistors are 0.1%. Tolerance of the other resistors is not
critical.
DS100889-22
FIGURE 8. Driving the signal inputs with a transformer.
ADC16061
www.national.com 16
Applications Information (Continued)
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
ADC16061 are required to achieve specified performance.
The analog and digital grounds may be in the same layer, but
should be separated from each other and should never over-
lap each other. Separation should be at least
1
⁄
8
inch, where
possible.
The ground return for the digital supply (DGND I/O ) carries
the ground current for the output drivers. This output current
can exhibit high transients that could add noise to the con-
version process. To prevent this from happening, the DGND
I/O pin should NOT be connected in close proximity to any of
the ADC16061’s other ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuitry sepa-
rated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signifi-
cant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or sig-
nal edges, like the 74F and the 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow compared with the
rest of the ground plane. A typical width is 3/16 inch (4 to 5
mm).This narrowing beneath the converter provides a fairly
high impedance to the high frequency components of the
digital switching currents, directing them away from the ana-
log pins. The relatively lower frequency analog ground cur-
rents see a relatively low impedance across this narrow
ground connection.
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
To maximize accuracy in high speed, high resolution sys-
tems, however, avoid crossing analog and digital lines alto-
gether. It is important to keep any clock lines isolated from
ALL other lines, including other digital lines. Even the gener-
ally accepted 90 degree crossing should be avoided as even
a little coupling can cause problems at high frequencies.
This is because other lines can introduce phase noise (jitter)
into the clock line, which can lead to degradation of SNR.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, not even with just a small part of their bodies beside
each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 9
gives an example of a suitable layout.All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
All ground connections should have a low inductance path to
ground.
ADC16061
www.national.com17
Applications Information (Continued)
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance with the
ADC16061, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolate the ADC clock
from any digital circuitry with buffers, as with the clock tree
shown in
Figure 10
.
As mentioned in section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce phase
noise (jitter) into the clock signal, which can lead to in-
creased distortion. Even lines with 90˚ crossings have ca-
pacitive coupling, so try to avoid even these 90˚ crossings of
the clock line.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than 100
mV below the ground pins or 100 mV above the supply pins).
Exceeding these limits on even a transient basis may cause
faulty or erratic operation. It is not uncommon for high speed
digital circuits (e.g., 74F and 74AC devices) to exhibit under-
shoot that goes more than a volt below ground. A resistor of
about 50 to 100Ωin series with the offending digital input will
eliminate the problem.
Do not allow input voltages to exceed the supply voltage dur-
ing power up.
Be careful not to overdrive the inputs of the ADC16061 with
a device that is powered from supplies outside the range of
theADC16061 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
D
I/O and DGND I/O. These large charging
current spikes can couple into the analog circuitry of the
ADC16061, degrading dynamic performance. Adequate by-
passing and maintaining separate analog and digital ground
planes will reduce this problem. The digital data outputs
should be buffered (with 74ACQ541, for example). Dynamic
performance can also be improved by adding series resis-
tors at each digital output, close to the ADC16061, which re-
duces the energy coupled back into the converter output
pins by limiting the output current. A reasonable value for
these resistors is 47Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the in-
put alternates between 12 pF and 28 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
DS100889-23
FIGURE 9. Example at a suitable layout.
DS100889-24
FIGURE 10. Isolating the ADC clock from other
circuitry with a clock tree.
ADC16061
www.national.com 18
Applications Information (Continued)
mance. Amplifiers that have been used successfully to drive
the analog inputs of the ADC16061 include the CLC427,
CLC440, LM6152, LM6154, LM6181 and the LM6182. A
small series reistor at each amplifier output and a capacitor
across the analog inputs (as shown in
Figure 7
) will often im-
prove performance.
Operating with the reference pins outside of the speci-
fied range. As mentioned in section 1.2, V
REF
should be in
the range of 1.8V ≤V
REF
≤2.2V
with V
REF
−
IN
≤1.0V. Operating outside of these limits could
lead to excessive distortion or noise.
Using a clock source with excessive jitter, using an ex-
cessively long clock signal trace, or having other sig-
nals coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR performance.
Connecting pins marked ″NC″to any potential. Some of
these pins are used for factory testing. They should all be left
floating. Connecting them to ground, power supply, or some
other voltage could result in a non-functional device.
ADC16061
www.national.com19
Physical Dimensions inches (millimeters) unless otherwise noted
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www.national.com
52-Lead Thin Quad Flat Pack
Ordering Number ADC16061CCVT
NS Package Number VEG52A
ADC16061 Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
