GENERAL DESCRIPTION
The DS1339 serial real-time clock (RTC) is a low-
power clock/date device with two programmable time-
of-day alarms and a programmable square-wave
output. Address and data are transferred serially
through an I2C bus. The clock/date provides seconds,
minutes, hours, day, date, month, and year
information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1339 has a built-in power-
sense circuit that detects power failures and
automatically switches to the backup supply,
maintaining time, date, and alarm operation.
APPLICATIONS
Handhelds (GPS, POS Terminals)
Consumer Electronics (Set-Top Box, Digital
Recording, Network Appliance)
Office Equipment (Fax/Printers, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Routers, Switches, Servers)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
Pin Configurat ion s appe ar at end of data sheet.
BENEFITS AND FEATURES
Completely Manages All Timekeeping
Functions
o Real-Time Clock Counts Seconds,
Minutes, Hours, Date of the Month,
Month, Day of the Week, and Year
with Leap-Year Compensation Valid
Up to 2100
o Two Time -of-Day Alarms
o Progr amm able Square -Wave Output
o Oscillator Stop Flag
Interfaces to Most Microcontrollers
o I2C Serial Interface
Low-Power Operation Extends Battery
Backup Run Ti me
o Automatic Power-Fai l Detec t and
Switch Circuitry
o Trickle-Charge Capability
Underwriters Laboratories® (UL)
Recognized
Surface-Mount Package with an
Integrated Crystal (DS1339C Saves
Additional Space and Simplifies Design
ORDERING INFORMATION
PART
TEMP RANGE
VOLTAGE (V)
PIN-PACKAGE
TOP MARK†
DS1339C-2#
-40°C to +85°C
2.0
16 SO (300 mils)
DS1339C-2
DS1339C-3#
-40°C to +85°C
3.0
16 SO (300 mils)
DS1339C-3
DS1339C-33#
-40°C to +85°C
3.3
16 SO (300 mils)
DS1339C-33
DS1339U-2+
-40°C to +85°C
2.0
8 µSOP
1339 rr-2
DS1339U-3+
-40°C to +85°C
3.0
8 µSOP
1339 rr-3
DS1339U-33+
-40°C to +85°C
3.3
8 µSOP
1339 rr-33
+Denotes a lead(Pb)-free/RoHS-compliant package.
#Denotes a RoHS-compliant device that may incl ude lead that is exempt under the RoHS requirements. The lead finis h is JESD97 category
e3, and is compatible with both lead-based and lead-free soldering processes.
†A “+” anywhere on the top mark indicates a lead(Pb)-free device. A “#” denotes a RoHS-compli ant devic e. rr = second li ne, revis i on code
DS1339
I
2
C Serial Real-Time Clock
19-5770; Rev 3/15
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DS1339 I2C Serial Real-Time Clock
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground………………………………………………………………-0.3V to +6.0V
Operating Temperature Range (Noncondensing)………………………………………………………….-40°C to +85°C
Storage Temperature Range………………………………………………………………………………..-55°C to +125°C
Lead Temperature (soldering, 10s)...…………………………………………………………………………………+260°C
Soldering Temperature (reflow).……………………………………………………………………………………….+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functi onal operation of the device at t hese or any other conditions bey ond t hose i ndi cated in the operational secti ons of the specifications is
not implied. Exposure to the absolute maximum rating condit i ons for extended periods may aff ect device reliabi l i ty.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
µSOP
Junction-to-Ambient Thermal Resistance (θJA).…………………...……………………………………….206.3°C/W
Junction-to-Case Thermal Resistance (θJC)……………………………………………………………………42°C/W
SO
Junction-to-Ambient Thermal Resistance (θJA).……………………………………………………………….73°C/W
Junction-to-Case Thermal Resistance (θJC)……………………………………………………………………23°C/W
Note 1: Package thermal resist ances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed inf ormati on on package thermal considerat i ons , refer to
www.maxim-ic.com/thermal-tutorial
.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Suppl y Voltage VCC
DS1339-2
1.8
2.0
5.5
V
DS1339-3 2.7 3.0 5.5
DS1339-33 2.97 3.3 5.5
Backup Supply Voltage VBACKUP 1.3 3.0 3.7 V
Logic 1 VIH 0.7 x
VCC VCC +
0.3 V
Logic 0 VIL -0.3 +0.3 x
V
CC
V
Power-Fail Voltage VPF
DS1339-2 1.58 1.70 1.80
V DS1339-3 2.45 2.59 2.70
DS1339-33 2.70 2.85 2.97
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DS1339 I2C Serial Real-Time Clock
DC ELECTRICAL CHARACTERISTICS
(VCC = MIN to MAX, TA = -40°C to +85°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage ILI (Note 3) 1 µA
I/O Leakage ILO (Note 4) 1 µA
Logic 0 Out
VOL = 0.4V; VCC > VCC MIN (-3, -33);
VCC ≥ 2.0V (-2) IOL (Note 4) 3 mA
Logic 0 Out
VOL = 0.2 (VCC);
1.8V < VCC < 2.0V (DS1339-2) IOL (Note 4) 3 mA
Logic 0 Out
VOL = 0.2 (VCC);
1.3V < VCC < 1.8V (DS1339-2) IOL (Note 4) 250 µA
VCC Active Current ICCA (Note 5) 450 µA
VCC Standby Current (Not e 6) ICCS
-2: VCC = 2.2V 60 100
µA
-3: VCC = 3.3 V 80 150
-33: VCC = 5.5V 200
Trickle-Charger Resistor Register
10h = A5h, VCC = Typ, VBACKUP = 0V R1 (Note 7) 250 Ω
Trickle-Charger Resistor Register
10h = A6h, VCC = Typ, VBACKUP = 0V R2 2000 Ω
Trickle-Charger Resistor Register
10h = A7h, VCC = Typ, VBACKUP = 0V R3 4000 Ω
VBACKUP Leakage Current IBKLKG 25 100 nA
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VBACKUP Current EOSC = 0, SQW Off IBKOSC (Note 8) 400 700 nA
VBACKUP Current EOSC = 0, SQW On IBKSQW (Note 8) 600 1000 nA
VBACKUP Current EOSC = 1 IBKDR 10 100 nA
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DS1339 I2C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(VCC = MIN to MAX, TA = -40°C to +85°C.) (Note 9)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
SCL Clock Frequency fSCL Fast mode 100 400 kHz
Standard mode 100
Bus Free Time Between a STOP
and START Condition tBUF Fast mode 1.3 µs
Standard mode 4.7
Hold Time (Repeated) START
Condition (Note 10) tHD:STA Fast mode 0.6 µs
Standard mode 4.0
LOW Period of SCL Clock tLOW Fast mode 1.3 µs
Standard mode 4.7
HIGH Period of SCL Clock tHIGH Fast mode 0.6 µs
Standard mode 4.0
Setup Time for a Repeated
START Condition tSU:STA Fast mode 0.6 µs
Standard mode 4.7
Data Hold Time (Notes 11, 12) tHD:DAT Fast mode 0 0.9 µs
Standard mode 0
Data Setup Time (Note 13) tSU:DAT Fast mode 100 ns
Standard mode 250
Rise Time of Both SDA and SCL
Signals (Note 14) tR Fast mode 20 + 0.1CB 300 ns
Standard mode 20 + 0.1CB 1000
Fall Time of Both SDA and SCL
Signals (Note 14) tF Fast mode 20 + 0.1CB 300 ns
Standard mode 20 + 0.1CB 300
Setup Time for STOP Condition tSU:STO Fast mode 0.6 µs
Standard mode 4.0
Capacitive Load for Each Bus
Line (Note 14) CB 400 pF
I/O Capacitance (SDA, SCL) CI/O (Note 9) 10 pF
Oscillator Stop Flag (OSF) Delay tOSF (Note 15) 100 ms
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DS1339 I2C Serial Real-Time Clock
POWER-UP/DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 2, Figure 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Recovery at Power-Up tREC (Note 16) 2 ms
VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs
VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 µs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-b ackup mode.
Note 2:
Limi ts at -40°C are guaranteed by design and are not production tested.
Note 3:
SCL only.
Note 4: SDA and SQW/INT.
Note 5:
ICCA—SCL at fSC max, VIL = 0 .0 V, VIH = VCC, trickle charger disabled.
Note 6:
Specified with the I
2
C bus inactive, VIL = 0 .0 V, VIH = VCC, trickle charger disabled.
Note 7:
VCC must be less than 3.63V if the 250
Ω
resistor is selected.
Note 8:
Using recommended crystal on X1 and X2.
Note 9:
Guaranteed by design; not production t ested.
Note 10:
After this period, t he first clock puls e is generat ed.
Note 11: A device must internall y provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
Note 12:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatical l y the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line
is released.
Note 14:
CB—total capacitance of one bus line in pF.
Note 15: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤
VCC
≤
VCCMAX and 1.3V
≤
VBACKUP
≤
3.7V.
Note 16:
This delay applies only if the oscillator is running. If the oscil l ator is disabl ed or stopped, no power-up delay occ urs.
Figure 1. Power-Up/Dow n Timing
OUTPUTS
VCC
V
PF(MAX)
V
PF(MIN)
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZED
RECOGNIZED
VALID
t
VCCF
t
VCCR
t
REC
5 of 20
DS1339 I2C Serial Real-Time Clock
Figure 2. Timing Diagram
Figure 3. Block Diagram
ALARM, TRICKLE
CHARGE, AND
CONTROL
REGISTERS
SERIAL BUS
INTERFACE AND
ADDRESS REGISTER
CONTROL LOGIC
1Hz
1Hz/4.096kHz/8.192kHz/32.768kHz MUX/
BUFFER
USER BUFFER (7
BYTES)
CLOCK AND
CALENDAR
REGISTERS
Power Control
X1
C
L
C
L
X2
DS1339
SQW/INT
VCC
VBACKUP
SCL
SDA
GND
Oscillator
and divider
"C" version only
N
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DS1339 I2C Serial Real-Time Clock
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3v, TA = +25°C, unless otherwise noted.)
I
BACKUP
vs. V
BACKUP
300
350
400
450
500
550
600
650
700
750
800
850
900
1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
BACKUP
(V)
SUPPLY CURRENT (nA
VCC=0V
RS1=RS0=1
IBATOSC2
(SQWE = 1)
IBATOSC1
(SQWE = 0)
I
BACKUP
vs. Temper at ur e
V
BACKUP
= 3.0V
300
350
400
450
500
550
600
650
-40 -20 020 40 60 80
TEMPERATURE (°C)
SUPPLY CURRENT (nA
VCC=0V
INTCN = 0
RS2 = RS1 = 1
INTCN = 0
I
CC
vs. V
CC
50
100
150
200
250
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
CC
(V)
SUPPLY CURRENT (uA
SCL=400kHz
ICCA
SCL=SDA=0Hz
ICCS
Oscill ator Frequency vs. Suppl y Volt age
32768.0
32768.1
32768.2
32768.3
32768.4
32768.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Oscillator Supply Voltage (V)
FREQUENCY (Hz)
7 of 20
DS1339 I2C Serial Real-Time Clock
PIN DESCRIPTION
PIN
NAME FUNCTION
µSOP
SO
1 — X1
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
circuitry is designed for operation with a crystal having a specified load
capacitance (CL) of 6pF. An external 32.768kHz oscillator can also drive the
DS1339. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is left unconnected.
For more information about crystal selection and crystal layout considerations,
refer to Application Note 58: Crystal Considerations with Dallas Real-Time
Clocks.
2 — X2
3 14 VBACKUP
Secondary Power Suppl y. Supply voltage must be held between 1.3V and 3.7V
for proper operation. This pin can be connected to a primary cell, such as a
lithium button cell. Additionally, this pin can be connected to a rechargeable cell
or a super cap when used in conjunction with the trickle-charge feature. Diodes
should not be placed in series between the backup source and the VBACKUP input,
or improper operation will result. If a backup supply is not required, VBACKUP must
be grounded. UL recognized to ensure against reverse charging current when
used with a lithium cell. For more information, visit www.maxim-ic.com/qa/info/ul.
4 15 GND Ground. DC power is provided to the device on these pins.
5 16 SDA
Serial Data Input/Output. SDA is the input/output pin for the I2C serial interface.
The SDA pin is an open-drain output and requires an external pullup resistor.
The pull up voltage may be up to 5.5V regardless of the voltage on VCC.
6 1 SCL
Serial Clock Input. SCL is used to synchronize data movement on the I2C serial
interface. The pull up voltage may be up to 5.5V regardless of the voltage on
VCC.
7 2 SQW/INT
Square-Wave/Interrupt Output. Programmable square-wave or interrupt output
signal. The SQW/INT pin is an open-drain output and requires an external pullup
resistor. The pull up voltage may be up to 5.5V regardless of the voltage on VCC.
If not used, this pin ma y be left unconnected.
8 3 VCC
Primary Power Supply. When voltage is applied within normal limits, the device
is fully accessible and data can be written and read. When a backup supply is
connected and VCC is bel o w VPF, reads and writes are inhibited. The timekeeping
and alarm functions operate when the device is powered by VCC or VBACKUP.
— 4–13 N.C. No Connection. These pins are unused and must be connected to ground.
TYPICAL OPERATING CIRCUIT
DS1339
4
CPU
VCC
VCC
VCC
5
6
8
1 2
SDA
SCL
GND
X2X1
VCC
RPU RPU CRYSTAL
SQW/INT
V
BACKUP
3
7
i
8 of 20
DS1339 I2C Serial Real-Time Clock
DETAILED DESCRIPTION
The DS1339 serial real-time clock (RTC) is a low-power clock/date device with two programmable time-of-day
alarms and a programmable square-wave output. Address and data are transferred serially through an I2C bus.
The clock/date provides seconds, m inutes, hours, da y, date, month, and year information. The date at the end of
the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1339 has a built-in power-
sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date,
and alarm operation.
OPERATION
The DS133 9 oper ates as a slave de vice on t he ser ial bus . Acces s is obta ined b y im plem enting a ST ART c onditio n
and providing a device identification code followed by data. Subsequent registers can be accessed sequentially
until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is
greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If
VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is
greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The
registers are maintained from the VBACKUP source until VCC is returned to nominal levels. The block diagram in
Figure 3 shows the main elements of the serial real-time clock.
POWER CONTROL
The power-control function is provided by a precise, temperature-compensated voltage reference and a
comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read
when VCC is great er th an V PF. Ho we ver , when V CC falls be low VPF, th e interna l cl o ck registers are blocked from any
access. If VPF is less than VBACKUP, the d evice po wer is s witched from VCC to VBACKUP whe n VCC drops belo w VPF. If
VPF is greater th an VBACKUP, the device po wer is switched fr om VCC to VBACKUP when VCC drops below VBACKUP. The
registers are m aintained f rom the VBACKUP sourc e until VCC is returne d to nom inal l evels ( Table 1). After VCC returns
above VPF, r ead and write acc ess is allo wed after tREC (Figure 1) . On the f irst applicat ion of po wer to the dev ice the
time and date registers are reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS).
Table 1. Power Control
SUPPLY CONDITION READ/WRITE
ACCESS POWERED
BY
VCC < VPF, VCC < VBACKUP
No
VBACKUP
VCC < VPF, VCC > VBACKUP
No
VCC
VCC > VPF, VCC < VBACKUP
Yes
VCC
VCC > VPF, VCC > VBACKUP
Yes
VCC
OSCILLATOR CIRCUIT
The DS1339 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a
functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal
with the specified characteristics.
9 of 20
DS1339 I2C Serial Real-Time Clock
Table 2. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency fO 32.768 kHz
Series Resistance ESR 50 kΩ
Load Capacitance CL 6 pF
*The crystal, t races, and crystal input pins should be isolated from RF generating signals. Refer to
Applic ation Note 58: Crystal Considerati ons for Dallas Real-Time C locks for additional specifications.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the m atch between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional
error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the
oscillator circuit may result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time
Clocks for detailed information
DS1339C ONLY
The DS133 9C integra tes a standar d 32,768H z crysta l in the pack age. Typical ac curac y at nominal VCC and +25°C
is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
Figure 4. Typical PC Board Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
NOTE: AVOID ROUTING SIGNALS IN
THE CROSSHATCHED AREA (UPPER
LEFT-HAND QUADRANT) OF THE
PACKAGE UNLESS THERE IS A
GROUND PLANE BETWEEN THE
SIGNAL LIN E AND TH E PAC KA GE.
10 of 20
DS1339 I2C Serial Real-Time Clock
ADDRESS MAP
Table 3 shows the address map for the DS1339 registers. During a multibyte access, when the address pointer
reaches th e end of the regi ster space (10 h), i t wra ps a round to locat ion 0 0h. O n an I 2C ST ART , ST O P, or ad dres s
pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need
to re-read the registers in case of an update of the main registers during a read.
Table 3. Timekeep er R eg ist ers
ADDRESS BIT 7 BIT 6 B IT 5 BIT 4 BI T 3 BIT 2 B IT 1 BIT 0 FUNCTION RANGE
00h 0 10 Seconds Seconds Seconds 00–59
01h 0 10 Minutes Minutes Minutes 00–59
02h 0 12/24 AM/PM 10 Hour Hour Hours
1–12
+AM/PM
00–23
20 Hour
03h
0
0
0
0
0
Day
Day
1–7
04h
0
0
10 Date
Date
Date
01–31
05h Century 0 0
10
Month
Month
Month/
Century
01–12 +
Century
06h 10 Year Year Year 00–99
07h A1M1 10 Seconds Seconds
Alarm 1
Seconds
00–59
08h A1M2 10 Minutes Minutes
Alarm 1
Minutes
00–59
09h A1M3 12/24 AM/PM 10 Hour Hour Alarm 1
Hours
1–12 +
AM/PM
00–23
20 Hour
0Ah A1M4 DY/DT 10 Date Day, Date
Alarm 1
Day,
Alarm 1
Date
1-7, 1-31
0Bh A2M2 10 Minutes Minutes
Alarm 2
Minutes
00–59
0Ch A2M3 12/24 AM/PM 10 Hour Hour Alarm 2
Hours
1–12 +
AM/PM
00–23
20 Hour
0Dh A2M4 DY/DT 10 Date Day, Date
Alarm 2
Day,
Alarm 2
Date
1–7, 1–31
0Eh EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE Control —
0Fh
OSF
0
0
0
0
0
A2F
A1F
Status
—
10h TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
Trickle
Charger
—
Note: Unless ot herwise spec ifi ed, the stat e of the registers are not defined when power is first appli ed or when VCC and VBACKUP falls below the
VBACKUP(MIN).
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DS1339 I2C Serial Real-Time Clock
TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Table 3 shows the RTC
registers . The tim e and d ate ar e set or initi alized by wr iting the a ppropr iate r egist er b ytes. The c ontents of the tim e
and date registers are in the BCD format. The DS1339 can be run in either 12-hour or 24-hour m ode. Bit 6 of the
hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the
12-hour m ode, bit 5 is the AM/PM b it with logic high b eing PM. In the 24-hour m ode, bit 5 is the 20-hour bit (20 to
23 hours). All hours values, including the alarms, must be re-entered whenever the 12/24-hour mode bit is
changed. The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00.
The da y-of-week r egister increm ents at midnight. Val ues that corres pond to the da y of week are user -defined, but
must be s equent ial (i. e., if 1 equals Sunday, then 2 equ als Mon day and so on). Illo gical t ime and date entries r esult
in undefined operation.
W hen reading or wr iting th e time and date regis ters, sec ondary (user ) buff ers are used t o prevent er rors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any START or STOP, and when the address pointer rolls over to zero. The countdown chain
is reset whenever the seconds register is written. Write transfers occurs on the acknowledge pulse from the
device. T o avoid rol lover is sues , once the coun tdow n chain is res et, the r em aining tim e and date reg isters must be
written within one second. If enabled, the 1Hz square-wave output transitions high 500ms after the seconds data
transfer, provided the oscillator is already running.
ALARMS
The DS13 39 contains t wo tim e of day/date alarm s. Alarm 1 can be set by writ ing to register s 07h to 0Ah. Alarm 2
can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the Alarm Enable and INTCN
bits of the C ontrol Re gister) to activate the SQW/INT outp ut on an alarm m atch condition. B it 7 of each of the time
of day/date alarm registers are mask bits (Table 4). When all the mask bits for each alarm are logic 0, an alarm
only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of
day/date al arm registers. The alar ms can als o be progr ammed to r epeat ever y second, m inute, hour, da y, or date.
Table 4 shows the possible settings. Configurations not listed in the table result in illogical operation.
The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that
register reflects the day of t he week or the d ate of the m onth. If D Y/DT is wr itt en t o a lo gic 0, the alar m is the res ult
of a m atch with dat e of the m onth. If DY/DT is written t o a logic 1, th e alarm is the r esult of a m atch with d ay of the
week.
The device checks for an alarm match once per second. When the RTC register values match alarm register
settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the
SQW/INT) signal. If the BBSQI b it is set to 1, the INT output activates while the part is being powered b y VBACKUP.
The alarm output remains active until the alarm flag is cleared by the user.
12 of 20
DS1339 I2C Serial Real-Time Clock
Table 4. Alarm Mask Bits
DY/
DT
ALARM 1 REGISTER MASK BITS
(Bit 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once per second
X
1
1
1
0
Alarm when seconds match
X
1
1
0
0
Alarm when minutes and seconds match
X
1
0
0
0
Alarm when hours, minutes, and seconds match
0 0 0 0 0
Alarm when date, hours, minutes, and seconds
match
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match
DY/
DT
ALARM 2 REGISTER MASK BITS
(Bit 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 sec. of every min.)
X
1
1
0
Alarm when minutes match
X
1
0
0
Alarm when hours and minutes match
0
0
0
0
Alarm when date, hours, and minutes match
1
0
0
0
Alarm when day, hours, and minutes match
SPECIAL-PURPOSE REGISTERS
The DS1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave
output.
CONTROL REGISTER (0Eh)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE
Bit 7: Enable Oscillato r
(EOSC).
This bi t when set to log ic 0 starts the oscillato r. W hen this bit is set t o a logic 1,
the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to a logic 1 enables the
square wave or interrupt output when VCC is absent and the DS1339 is being powered by the VBACKUP pin. When
BBSQI is a log ic 0, the SQ W/INT pin goes high im pedanc e when VCC falls below the po wer-f a il tr ip p o int. T hi s bit is
disabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the squar e-wave output when the
square wave has be en en abled. Table 5 shows the s q uar e-wave f requencies that c an be selec ted with th e R S bits.
These bits are both set to logic 1 (32kHz) when power is first applied.
Table 5. SQW/
INT
Output
INTCN RS2 RS1
SQW/INT
OUTPUT
A2IE A1IE
0
0
0
1Hz
X
X
0
0
1
4.096kHz
X
X
0
1
0
8.192kHz
X
X
0
1
1
32.768kHz
X
X
1
X
X
A1F
0
1
1
X
X
A2F
1
0
1
X
X
A2F + A1F
1
1
13 of 20
DS1339 I2C Serial Real-Time Clock
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. W hen the INTCN bit is set to logic 1, a m atch between the t imekeeping re gisters and the alarm 1 or alar m 2
registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the
status regis ter to ass ert SQ W /INT (when INT CN = 1). When the A2IE bit is set to logic 0 or I NTC N is set to logic 0,
the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the
status regis ter to ass ert SQ W /INT (when INT CN = 1). When the A1IE bit is s et to logic 0 or INTC N is set to logic 0,
the A1F bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
STATUS REGISTER (0Fh)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OSF 0 0 0 0 0 A2F A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in th is bi t i ndicates that the oscill ator eith er is st o ppe d or was sto pped
for s ome period of tim e an d m a y be used to j udge the va lidit y of t he cloc k and d a te data. This bit is e dge tr ig gered
and is set to logic 1 whe n the osci llator s t ops . T he f ol l o wing ar e ex amples of c ondit ions t hat can c aus e the O SF b it
to be set:
1) The first time power is applied.
2) The voltage on both VCC and VBACKUP are insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in th e A larm 2 Flag bit indic ates t hat the time matched the al ar m 2 registers . If
the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared
when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value
unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in th e A larm 1 Flag bit indic ates t hat th e time m atc hed the al arm 1 regist ers . If
the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared
when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value
unchanged.
14 of 20
DS1339 I2C Serial Real-Time Clock
TRICKLE CHARGER REGISTER (10h)
The sim plified schematic in Figure 5 shows the basic components of the trick le charger. The trickle-charge select
(TC S) bits (bits 4 to 7) contr ol the selec tion of the trick le charger . T o prevent ac cidenta l enabl ing, on ly a patt ern on
1010 enables the tr ick le charger. A ll other pat terns disabl e the trick le c harger. T he trick le c harger is disabl ed wh en
power is f irst app lied. T he dio de-selec t (DS) bi ts (bits 2 and 3) selec t wheth er or not a d iode is connecte d b etween
VCC and VBACKUP. The R OU T bits (bits 0 and 1) s elec t the valu e of the resistor connec ted b etween VCC and V BACKUP.
Table 6 shows the bit values.
Table 6. Trickle Charger Register (10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
TCS3
TCS2
TCS1
TCS0
DS1
DS0
ROUT1
ROUT0
X
X
X
X
0
0
X
X
Disabled
X
X
X
X
1
1
X
X
Disabled
X
X
X
X
X
X
0
0
Disabled
1
0
1
0
0
1
0
1
No diode, 250Ω resistor
1
0
1
0
1
0
0
1
One diode, 250Ω resistor
1
0
1
0
0
1
1
0
No diode, 2kΩ resistor
1
0
1
0
1
0
1
0
One diode, 2kΩ resistor
1
0
1
0
0
1
1
1
No diode, 4kΩ resistor
1
0
1
0
1
0
1
1
One diode, 4kΩ resistor
0
0
0
0
0
0
0
0
Initial power-up values
Warning: The ROUT value of 250
Ω
must not be selected whenever VCC is greater than 3.63V.
The user determines diode and resistor selection according to the maximum current desired for battery or super
cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume
that a 3.3 V sys tem power supply is applie d to VCC and a super c ap is connected to VBACKUP. Als o assume that the
trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX
would therefore be calculated as follows:
IMAX = (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) / 2kΩ ≈ 1.3mA
As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and therefore the
charge current decreases.
15 of 20
DS1339 I2C Serial Real-Time Clock
Figure 5. Programmable Trickle Charger
I2C SERIAL DATA BUS
The DS13 39 s u pports the I2C bus prot oco l. A de vice that sends d ata onto the b u s is def in ed as a transm itter and a
device rec eiving data as a receiver . The devic e that controls the m essage is call ed a mas ter. The devices that are
controlled by the m aster are referred to as slaves. The bus must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1339
operates as a sl ave on t he I2C bus. W ithin the bus spec ifications, a stand ard m ode (100k Hz cycle rat e) and a fast
mode (400kHz cycle rate) are defined. The DS1339 works in both modes. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 6):
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
START data transfer: A change in t he state of the d ata line, fr om HIG H to LOW, while the clock is HIGH ,
defines a START condition.
STOP data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid : T he state of the dat a lin e repres ents valid data whe n, aft er a ST ART condit ion, th e data line is
stable for the duration of the HIGH period of the c lock signal. T he data on the line m ust be changed dur ing
the LOW period of the clock signal. There is one clock pulse per bit of data.
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES CHARGER 1 OF 2
SELECT 1 OF 3
SELECT
TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
250Ω
2kΩ
4kΩ
R1
R3
R2
TRICKLE CHARGE REGISTER
TCS
0-3
= TRICKLE CHARGER SELECT
DS
0-1 = DIODE SELECT
ROUT
0-1 = RESISTOR SELECT
VCC
VBACKUP
16 of 20
DS1339 I2C Serial Real-Time Clock
Each data tr ansfer is initiat ed with a ST ART c ondition and ter minated with a STO P condition. T he n umber
of data bytes transferred between START and STOP conditions is not limited, and is determined by the
master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The m aster device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, s etup a nd hol d t im es must be taken into acc o unt. A master must s ignal an end of d ata to t he slave
by not gener ating an ack nowled ge bit on the last b yte that has bee n clocked out of the slav e. In this cas e,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Figure 6. Data Transfer on I2C Serial Bus
Depending upon the state of the R/W bit, two types of data transfer are possible:
1) Data tran sfer from a master tran smitter to a s lave receiv er. The firs t byte transm itted by the m aster is
the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each
received byte. Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave
transm itting a number of data bytes. The master returns an acknowledge bit after all received bytes other
than the last b yte. At the en d of the las t receiv ed b yte, a “not ack nowledg e” is retur ned. The m as ter devic e
generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a
STOP condition or with a repeated START condition. Since a repeated START condition is also the
beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit
(MSB) first.
The DS1339 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each
byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning a nd end of a serial tr ansfer . Address recogni tion is perf orm ed by hard ware af ter rec eption of the
slave address and direction bit (Figure 7). The slave address byte is the first byte received after the
START condition is generated b y the m aster. T he slave addr ess byte conta ins the 7-bit DS1339 address,
which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding
the slave address byte the slave outputs an acknowledge on the SDA line. After the DS1339
acknowledges the slave address + write bit, the m aster transmits a register address to the DS1339. This
17 of 20
DS1339 I2C Serial Real-Time Clock
sets the register pointer on the DS1339, with the DS1339 acknowledging the transfer. The master may
then transmit zero or more bytes of data, with the DS1339 acknowledging each byte received. The
address p ointer incr em ents af ter each data byte is trans fer red. T he mas ter genera tes a STO P cond ition to
terminate the data write.
2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver
mode. However, in this m ode, the direction bit indicates that the transf er direction is reversed . Serial data
is trans mitted on SDA b y the DS1339 while the ser ial cloc k is input o n SCL. START and STO P conditions
are recogni zed as the beginni ng and end of a serial transf er (Figure 8). The slave addr ess byte is the firs t
byte received after the START condition is generated by the master. The slave address byte contains the
7-bit DS1339 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After
receiving and decoding the slave address byte the slave outputs an acknowledge on the SDA line. The
DS1339 t hen begins to tr ansm it data starting with the r egister addres s pointed t o by the regist er pointer . If
the register pointer is not written to before the initiat ion of a read m ode the first address that is read is the
last one stored in the register pointer. The address pointer is incremented after each byte is transferred.
The DS1339 must receive a “not acknowledge” to end a read.
Figure 7. Data Wr ite—Slave Receiver Mode
Figure 8. Data Rea d (from Current Poi nter Location)—Slave Transmitter Mode
Figure 9. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit
...AXXXXXXXXAS 0 XXXXXXXX AXXXXXXXX AXXXXXXXX A P
S - Sta rt
A - Acknowledge (ACK)
P - Sto p
<R/W>
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
1101000
<Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>
Master to slave
Slave to master
...A
XXXXXXXXA
1101000S1XXXXXXXX AXXXXXXXX XXXXXXXX AP
<Data(n+2)> <Data(n+X)>
A
S - Sta rt
A - Acknowledge (ACK)
P - Sto p
A - Not Acknowledge (NACK)
<RW>
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
<Slave Address> <Data(n)> <Data(n+1)>
Master to slave
Slave to master
...
AXXXXXXXX XXXXXXXX AXXXXXXXX AXXXXXXXX AP
S - Sta rt
Sr - Repeated Start
A - Acknowledge (ACK)
P - Sto p
A - Not Acknowledge (NACK)
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
AXXXXXXXXA
1101000S 0
<RW>
<Word Address (n)>
A1101000Sr 1
<RW>
<Slave Address>
<Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
Master to slave
Slave to master
18 of 20
DS1339 I2C Serial Real-Time Clock
HANDLING, PCB LAYOUT, AND AS SEM BLY
The DS1339C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but
precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided
to prevent damage to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-pack ed. Handling instructions listed on the package
label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020B standard for
moisture-sensi tive device (MSD) classifications.
PIN CONFIGURATIONS
CHIP INFORMATION
PROCESS: CMOS
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “ +”, “#” , or “ -” in the pac kage code in dic at e s RoHS s ta tus o nly. Package dr a win gs may show a di ff erent
suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LA ND PATTERN NO.
8 µSOP U8+1 21-0036 90-0092
16 SO W16#H2 21-0042 90-0107
µSOP
SQW/INT
X1
X2
GND
VCC
SCL
SDA
V
BACKUP
DS1339
TOP VIEW
SQW/INT
SCL
SDA
GND
V
BACKUP
V
CC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DS1339C
SO (300 mils)
TOP VIEW
19 of 20
DS1339 I2C Serial Real-Time Clock
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
100108
Removed leaded part numbers from the Ordering Information table. 1
Removed the pullup resistor voltage spec from the Recommended DC
Operating Conditions table and added it to the pin descriptions.
2, 8
Removed Note 7 from the I
BKDR
specif icat ion in the DC Electrical Characteristics
table.
3
Updated the block diagram (Figure 3) to show that SQW/INT is open drain.
6
Added the UL link to the VBACKUP description in the Pin Des c ripti on table.
8
Removed the duplicate Oscillator Circuit section. 9
Added the initial POR state for time and date registers in the Power Control
section.
9
Changed the series resistance (ESR) value in Table 2 from 45k
Ω
to 50k
Ω
.
10
Added the overbar to the “A” legend for NACK in Figure 8. 18
4/11
Updated the soldering temperature and added lead temperature information to
the Absolute Maximum Ratings section; added the Package Thermal
Characteristics section and updated the µSOP θJA and θJC numbers; changed
the VCC max numbers from 2.2V to 5.5V for DS1339-2 and 3.3V to 5.5V for
DS1339-3 in the Recommended DC Operating Conditions table.
2
Updated the ICCS parameter in the DC Electrical Characteristics table.
3
Changed the 10 Hour bit to 20 Hour bit for 02h, 09h, and 0Ch in Table 1 and the
Time and Date Operation section.
11, 12
Updated the Handling, PCB Layout, and Assembly section; removed the
transistor count from the Chip Information section; added the land pattern
numbers to the Package Information table.
19
3/15
Updated Benefits and Features section
1
20 of 20
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reserves the right to change the circuitr y and spec ifications wi th out noti c e at a ny ti me.
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