CY7C1061DV33
16-Mbit (1 M × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05476 Rev. *H Revised October 19, 2011
16-Mbit (1 M × 16) Static RAM
Features
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 175 mA at 100 MHz
■Low CMOS standby power
❐ISB2 = 25 mA
■Operating voltages of 3.3 ± 0.3 V
■2.0 V data retention
■Automatic power down when deselected
■TTL compatible inputs and outputs
■Easy memory expansion with CE1 and CE2 features
■Available in Pb-free 54-pin TSOP II and 48-ball VFBGA
packages
■Offered in single CE and dual CE options
Functional Description
The CY7C1061DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A19). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 11
for a complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and 48-ball
VFBGA packages.
15
16
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
1M x 16
ARRAY
A0
A12
A14
A13
A
A
A17
A18
A10
A11
I/O0 – I/O7
OE
I/O8 – I/O15
CE1
WE
BLE
BHE
A9
A19
CE2
Logic Block Diagram
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 2 of 17
Contents
Selection Guide ................................................................3
Pin Configurations ...........................................................3
Maximum Ratings .............................................................5
Operating Range ............................................................... 5
DC Electrical Characteristics ..........................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
AC Switching Characteristics .........................................7
Data Retention Characteristics ....................................... 8
Over the Operating Range ...............................................8
Data Retention Waveform ................................................ 8
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 3 of 17
Selection Guide
Description -10 Unit
Maximum access time 10 ns
Maximum operating current 175 mA
Maximum CMOS standby current 25 mA
Pin Configurations
Figure 1. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVXI) (Top View) [1, 2]
Figure 2. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVJXI) (Top View) [1, 2]
WE
A
11
A
10
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
18
A
19
326
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
WE
A11
A10
A6
A0
A3CE1
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
A7
I/O0
BHE
CE2
A17
A2
A1
BLE
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
A19
A18 NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
Notes
1. NC pins are not connected on the die.
2. In BVXI package, ball H6 is MSB address A19 and ball G2 is NC; in BVJXI package, ball H6 is NC and ball G2 is MSB address A19.
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 4 of 17
Figure 3. 48-ball VFBGA (8 × 9.5 × 1 mm) Single Chip Enable (-BV1XI) (Top View) [3, 4]
Figure 4. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) (Top View) [3]
Pin Configurations (continued)
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
NC
A
17
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
I/O
11
18
17
20
19
23
28
25
24
22
21
27
26
V
SS
I/O
10
I/O
12
V
CC
I/O
13
I/O
14
V
SS
A
16
A
17
A
11
A
12
A
13
A
14
I/O
0
A
15
I/O
7
I/O
9
V
CC
I/O
8
I/O
15
A
19
A
4
A
3
A
2
A
1
CE
1
V
CC
WE
CE
2
BLE
NC
V
SS
OE
A
8
A
7
A
6
A
5
A
0
NC
A
9
BHE
A
10
10
A
18
46
45
47
50
49
48
51
54
53
52
I/O
2
I/O
1
I/O
3
V
SS
V
CC
V
SS
I/O
6
I/O
5
V
CC
I/O
4
Notes
3. NC pins are not connected on the die.
4. In BV1XI package, ball A6 is NC, ball H6 is NC and ball G2 is MSB address A19. BV1XI package has only single Chip Enable (CE).
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 5 of 17
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on VCC
relative to GND [5] ........................................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [5] ................................ –0.5 V to VCC + 0.5 V
DC Input Voltage [5] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................. >2001 V
Latch Up Current .................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85 C 3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
-10
Unit
Min Max
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 8.0 mA – 0.4 V
VIH Input HIGH voltage – 2.0 VCC + 0.3 V
VIL Input LOW voltage [5] – –0.3 0.8 V
IIX Input leakage current GND < VI < VCC –1 +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 +1 A
ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA,
CMOS levels
–175mA
ISB1 Automatic CE power down
current – TTL inputs
Max VCC, CE1 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX
–30mA
ISB2 Automatic CE power down
current – CMOS inputs
Max VCC, CE1 > VCC – 0.3 V, CE2 < 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–25mA
Note
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 6 of 17
Capacitance
Parameter [6] Description Test Conditions 54-pin TSOP II 48-ball VFBGA Unit
CIN Input Capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 6 8 pF
COUT I/O Capacitance 8 10 pF
Thermal Resistance
Parameter [6] Description Test Conditions 54-pin TSOP II 48-ball VFBGA Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
24.18 28.37 C/W
JC Thermal resistance
(junction to case)
5.40 5.79 C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms [7]
90%
10%
3.0 V
GND
90%
10%
All Input Pulses
3.3 V
Output
5 pF*
Including
JIG and
Scope (b)
R1 317
R2
351
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
= 1.5 V
30 pF*
* Capacitive Load Consists
of all Components of the
Test Environment
High-Z Characteristics:
(a)
> 1 V/ns
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 7 of 17
AC Switching Characteristics
Over the Operating Range
Parameter [8] Description -10 Unit
Min Max
Read Cycle
tpower VCC(typical) to the first access [9] 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE1 LOW/CE2 HIGH to data valid – 10 ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z [10] 1–ns
tHZOE OE HIGH to high Z [10] –5ns
tLZCE CE1 LOW/CE2 HIGH to low Z [10] 3–ns
tHZCE CE1 HIGH/CE2 LOW to high Z [10] –5ns
tPU CE1 LOW/CE2 HIGH to power-up [11] 0–ns
tPD CE1 HIGH/CE2 LOW to power-down [11] –10ns
tDBE Byte enable to data valid – 5 ns
tLZBE Byte enable to low Z 1 – ns
tHZBE Byte disable to high Z – 5 ns
Write Cycle [12, 13]
tWC Write cycle time 10 – ns
tSCE CE1 LOW/CE2 HIGH to write end 7 – ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7–ns
tSD Data setup to write end 5.5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z [10] 3–ns
tHZWE WE LOW to high Z [10] –5ns
tBW Byte Enable to End of Write 7 – ns
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part (a) of Figure 5 on page 6, unless specified otherwise.
9. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
10. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 6. Transition is measured 200 mV from steady state
voltage.
11. These parameters are guaranteed by design and are not tested.
12. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW
to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that
terminates the write.
13. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Document Number: 38-05476 Rev. *H Page 8 of 17
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Max Unit
VDR VCC for data retention – 2 – V
ICCDR Data retention current VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–25mA
tCDR [14] Chip deselect to data retention
time
–0–ns
tR[15] Operation recovery time – tRC –ns
Data Retention Waveform
Figure 6. Data Retention Waveform [16]
3.0 V3.0 V
tCDR
VDR > 2 V
Data Retention Mode
tR
CE
VCC
Switching Waveforms
Figure 7. Read Cycle No. 1 (Address Transition Controlled) [17, 18]
Previous Data Valid Data Valid
RC
tAA
tOHA
tRC
Address
Data Out
Notes
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
16. For all packages except -BV1XI, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH. For -BV1XI package, CE refers to CE.
17. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL.
18. WE is HIGH for read cycle.
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Document Number: 38-05476 Rev. *H Page 9 of 17
Figure 8. Read Cycle No. 2 (OE Controlled) [19, 20, 21]
Figure 9. Write Cycle No. 1 (CE Controlled) [19, 22, 23]
Switching Waveforms (continued)
50%
50%
Data Valid
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
High Impedance
t
HZOE
t
HZBE
t
PD
High
OE
CE
ICC
ISB
Impedance
Address
Data Out
V
CC
Supply
t
DBE
t
LZBE
t
HZCE
BHE,BLE
Current
I
CC
I
SB
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
Data I/O
Address
CE
WE
BHE, BLE
Notes
19. For all packages except -BV1XI, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH. For -BV1XI package, CE refers to CE.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE transition LOW.
22. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
23. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 10 of 17
Figure 10. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26]
Figure 11. Write Cycle No. 3 (BLE or BHE Controlled) [24]
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
Data I/O
Address
CE
WE
BHE,BLE
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
Data I/O
Address
BHE,BLE
CE
WE
Notes
24. For all packages except -BV1XI, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH. For -BV1XI package, CE refers to CE.
25. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
26. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
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Document Number: 38-05476 Rev. *H Page 11 of 17
Truth Table
For all packages except -BV1XI
CE1CE2OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X X High Z High Z Power down Standby (ISB)
X L X X X X High Z High Z Power down Standby (ISB)
L H L H L L Data out Data out Read all bits Active (ICC)
L H L H L H Data out High Z Read lower bits only Active (ICC)
L H L H H L High Z Data out Read upper bits only Active (ICC)
L H X L L L Data in Data in Write all bits Active (ICC)
L H X L L H Data in High Z Write lower bits only Active (ICC)
L H X L H L High Z Data in Write upper bits only Active (ICC)
L H H H X X High Z High Z Selected, outputs disabled Active (ICC)
Truth Table
For -BV1XI package only
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High Z High Z Power down Standby (ISB)
L L H L L Data out Data out Read all bits Active (ICC)
L L H L H Data out High Z Read lower bits only Active (ICC)
L L H H L High Z Data out Read upper bits only Active (ICC)
L X L L L Data in Data in Write all bits Active (ICC)
L X L L H Data in High Z Write lower bits only Active (ICC)
L X L H L High Z Data in Write upper bits only Active (ICC)
L H H X X High Z High Z Selected, outputs disabled Active (ICC)
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 12 of 17
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1061DV33-10ZSXI 51-85160 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) (Pb-free) Industrial
CY7C1061DV33-10BVXI 51-85178 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Dual Chip Enable)
CY7C1061DV33-10BVJXI 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Dual Chip Enable -
JEDEC compatible)
CY7C1061DV33-10BV1XI 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Single Chip Enable)
Ordering Code Definitions
Temperature Range:
I = Industrial
Pb-free
Package Type: XXX = ZS or BV or BVJ
ZS = 54-pin TSOP II
BV = 48-ball VFBGA (Dual Chip Enable)
BVJ = 48-ball VFBGA (Dual Chip Enable - JEDEC compatible)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
Data width: 1 = × 16-bits
06 = 16-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 - 10 X706 D IV331XXX
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 13 of 17
Package Diagrams
Figure 12. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *C
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 14 of 17
Figure 13. 48-ball VFBGA (8 × 9.5 × 1.0 mm) BV48B Package Outline, 51-85178
Package Diagrams (continued)
51-85178 *A
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 15 of 17
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
VFBGA very fine-pitch ball gird array
WE write enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
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CY7C1061DV33
Document Number: 38-05476 Rev. *H Page 16 of 17
Document History Page
Document Title: CY7C1061DV33, 16-Mbit (1 M × 16) Static RAM
Document Number: 38-05476
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 201560 SWI See ECN Advance data sheet for C9 IPP
*A 233748 RKF See ECN AC, DC parameters are modified as per EROS
(Specification number 01-2165)
Added Pb-free devices in the Ordering Information
*B 469420 NXR See ECN Converted from Advance Information to Preliminary
Corrected typo in the Document Title
Removed –8 and –12 speed bins from product offering
Removed Commercial Operating Range
Changed 2G-Ball of FBGA and pin 40 of TSOPII from DNU to NC
Included the Maximum ratings for Static Discharge Voltage and Latch Up
Current on page 3
Changed ICC(Max) from 220 mA to 125 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot specification in footnote 1.
Updated the Ordering Information Table
*C 499604 NXR See ECN Added note 1 for NC pins
Updated Test Condition for ICC in DC Electrical Characteristics table
Updated the 48-Ball FBGA Package
*D 1462583 VKN /
AESA
See ECN Converted from preliminary to final
Changed ICC specification from 125 mA to 175 mA
Updated thermal specs
*E 2704415 VKN /
PYRS
05/11/09 Included 48 FBGA -BVJXI package
Added footnote #2
*F 3109102 AJU 12/13/2010 Added Ordering Code Definitions.
Updated Package Diagrams.
*G 3126531 PRAS 01/03/2011 Added 48-ball VFBGA Single Chip Enable package.
Updated Ordering Information.
Added Acronyms.
*H 3414708 TAVA 10/19/2011 Updated Features.
Updated DC Electrical Characteristics.
Updated Switching Waveforms.
Updated Package Diagrams.
Added Units of Measure.
Updated in new template.
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Document Number: 38-05476 Rev. *H Revised October 19, 2011 Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1061DV33
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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