Series PWM Controlled Step-Up DC/DC Controllers Input Voltage Range : 2.5V ~ 20V Output Voltage Range : 2.5V ~ 16V (Fixed Voltage Type) : 30V + (Adjustable Type) Oscillation Frequency Range : 100kHz ~ 600kHz Output Current : up to 1.5A Ceramic Capacitor Compatible MSOP-8A Package Applications General Description Features The XC9101 series are step-up multiple current and voltage feedback DC/DC controller ICs. Current sense, clock frequencies and amp feedback gain can all be externally regulated. A stable power supply is possible with output currents of up to 1.5A. With output voltage fixed internally, VOUT is selectable in 0.1V steps within a 2.5V - 16.0V range ( 2.5%). For output voltages outside this range, we recommend the FB version which has a 0.9V internal reference voltage. Using this version, the required output voltage can be set-up using 2 external resistors. Switching frequencies can also be set-up externally within a range of 100~600 kHz and therefore frequencies suited to your particular application can be selected. With the current sense function, peak currents (which flow through the driver transistor and the coil) can be controlled. Soft-start time can be adjusted using external resistor and capacitor. Stable Operations via Current & Voltage Multiple Feedback Mobile, Cordless phones Palm top computers, PDAs Portable games Cameras, Digital cameras Laptops 4 Unlimited Options for Peripheral Selection Current Protection Circuit Ceramic Capacitor Compatible During shutdown (CE pin =L), consumption current can be reduced to as little as 0.5A (TYP.) or less. Typical Application Circuit Typical Performance Characteristic U3FWJ44N 22H VOUT:5.0V FOSC:180kHz XP161A1355PR 1 EXT Vss 8 2 Isen VOUT 7 3 VIN GAIN 6 150k 220F 0.1F +10F 94F 4 CE/SS CLK 5 1F 22K 470pF 180pF Efficiency : EFFI (%) 50m 100 80 4.2V 3.3V 60 VIN=2.5V 40 1 10 100 1000 Output Current : IOUT (mA) 387 XC9101Series Pin Configuration EXT 1 8 VSS Isen 2 7 VOUTFB VIN 3 6 CCGAIN CESS 4 5 CLK Pin Assignment MSOP-8A (TOP VIEW) 4 PIN NUMBER PIN NAME FUNCTION 1 EXT Driver 2 Isen Current Sense 3 VIN Power Input 4 CESS CE/Soft Start 5 CLK Clock Input 6 CCGAIN Phase Compensation 7 VOUTFB Voltage Sense 8 VSS Ground Product Classification Ordering Information qwerty DISIGNATOR SYMBOL C q D VOUT/FB VOUT (Fixed Voltage Type) FB Soft-start Soft-start externally set-up Soft-start externally set-up Output Voltage : For voltages above 10V, see below : we Number 10=A, 11=B, 12=C, 13=D, 14=E, 15=F, 16=H e.g. VOUT=2.3Vw=2, e=3 VOUT=13.5Vw=D, e=5 FB productsw=0, e=9 fixed r t y A K R L Adjustable Frequency MSOP-8A Embossed tape. Standard Feed Embossed tape. Reverse Feed The standard output voltages of the XC9101C series are 2.5V, 3.3V, and 5.0V. Voltages other than those listed are semi-custom. MSOP-8A 4.900.10 3.000.10 0.15 +0.08 -0.02 3.000.10 0.86 -0.10 +0.20 1.02 -0.21 +0.11 0 (0.65) 388 0.000.20 +0.08 0.30 -0.02 0.530.13 Packaging Information 6 XC9101 Series Marking MSOP-8A q Represents the product series DESIGNATOR PRODUCT NAME 4 XC9101***AK* w Represents product type, DC/DC converter DESIGNATOR TYPE PRODUCT NAME C VOUT, CE PIN D FB, CE PIN XC9101C**AK* XC9101D09AK* e Represents integral number of output voltage, or FB type DESIGNATOR VOLTAGEV 2 PRODUCT NAME 2. X 3 3. X 4 4. X 5 5. X 6 6. X 7 7. X 8 8. X 9 9. X 0 FB products DESIGNATOR VOLTAGEV PRODUCT NAME XC9101C2*AK* XC9101C3*AK* A 10. X B 11. X XC9101C4*AK* XC9101C5*AK* C 12. X D 13. X XC9101C6*AK* XC9101C7*AK* XC9101C8*AK* E 14. X F 15. X XC9101CE*AK* XC9101CF*AK* H 16. X XC9101CH*AK* 4 XC9101CA*AK* XC9101CB*AK* XC9101CC*AK* XC9101CD*AK* XC9101C9*AK* XC9101D09AK* r Represents decimal number of output voltage DESIGNATOR VOLTAGEV 0 X. 0 3 X. 3 9 FB products PRODUCT NAME XC9101C*0AK* XC9101C*3AK* XC9101D09AK* t Represents oscillation frequency's control type DESIGNATOR TYPE PRODUCT NAME A Adjustable Frequency XC9101***AK* 389 XC9101Series Block Diagram EXT timming controll logic EXT Current Limit Protection VSS VOUT R1 Verr ISEN Limitter comp. PWM VIN Internal Voltage Regulator 4 CC/GAIN Ierr 2.0V to internal circuit Ramp Wave, Internal CLK generator Sampling CE/SS Chip Enable, Soft Start up, U.V.L.O. CE,UVLO to internal circuit CLK Vref generator 0.9V Absolute Maximum Ratings 390 R2 MIX Ta=25 PARAMETER SYMBOL RATINGS UNITS EXT Pin Voltage VEXT -0.3VDD0.3 Isen Pin Voltage VIsen -0.322 VIN Pin Voltage VIN -0.322 CE/SS Pin Voltage VCE -0.322 CLK Pin Voltage VCLK -0.3VDD0.3 CC/GAIN Pin Voltage VCC -0.3VDD0.3 VOUT/FB Pin Voltage VOUT/FB -0.322 EXT Pin Current IEXT 100 mA Continuous Total Power Dissipation Pd 150 mW Operating Ambient Temperature Topr -4085 Storage Temperature Tstg -55125 XC9101 Series Electrical Characteristics XC9101C33AKR Ta=25 PARAMETER SYMBOL Output Voltage VOUT Maximum Operating Voltage Minimum Operating Voltage MIN. TYP. MAX. 3.218 3.300 3.382 V q VINmax 20 - - V q VINmin - - 2.5 V q 150 255 A w 90 176 A w Supply Current 1 IDD1 Supply Current 2 IDD2 CONDITIONS IOUT=300mA VIN=2.5V VOUT=CE=Set Output Voltagex0.95V VIN=2.5V, CE=VIN VOUT=Set Output Voltagex1.05V Stand-by Current ISTB VIN=2.5V, CE=VOUT=VSS CLK Oscillation Frequency FOSC RT=10.0k, CT=220pF Frequency Input Stability FOSC VINFOSC 280 VIN=2.5V20V VIN=2.5V Frequency Temperature FOSC Fluctuation ToprFOSC Maximum Duty Cycle MAXDTY VOUT=Set Voltagex0.95V Minimum Duty Cycle MINDTY VOUT=Set Voltagex1.05V Current Limiter Voltage ILIM Topr=-40+85 UNITS CIRCUITS 0.5 2.0 A w 330 380 kHz e 5 % e 5 % e % r 79 85 89 0 % r VIN pin voltage-ISEN pin voltage 90 150 220 mV y 4.5 A y ISEN Current IISEN VIN=2.5V, ISEN=2.5V 7 13 CE "High" Current ICEH CE=VIN=2.5V, VOUT=0V -0.1 0 0.1 A t CE "Low" Current ICEL CE=0V, VIN=2.5V, VOUT=0V -0.1 0 0.1 A t CE "High" Voltage VCEH V t 0.2 V t 31 58 r 27 45 r % q 20 ms q k u Existence of CLK Oscillation, 0.6 4 VOUT=0V, CE : Voltage applied CE "Low" Voltage VCEL Disappearance of CLK Oscillation, VOUT=0V, CE : Voltage applied EXT "High" ON Resistance EXT "Low" ON Resistance REXTH REXTL Efficiency *1 EFFI Soft-Start Time TSS CC/GAIN Pin Output Impedance EXT=VIN-0.4V, CE=VIN=2.5V VOUT=Set voltagex0.95V EXT=0.4V, CE=VIN=2.5V VOUT=Set voltagex1.05 88 Connect CSS and RSS, CE : 0V2.5V RCCGAIN 5 10 400 VIN = 2.5V unless specified *1 : EFFI = {[(Output Voltage) x (Output Current)] / [(Input Voltage) x (Input Current)]} x 100 *2 : The capacity range of the capacitor used to set the external CLK frequency is 150 ~ 220pF 391 XC9101Series XC9101C50AKR SYMBOL Output Voltage VOUT Maximum Operating Voltage VINmax Minimum Operating Voltage VINmin Supply Current 1 IDD1 Supply Current 2 IDD2 CONDITIONS IOUT=300mA 5.000 5.125 V q 20 - - V q - - 2.5 V q 160 270 A w 90 176 A w VIN=3.0V, CE=VIN VOUT=Set Output Voltagex1.05V ISTB VIN=3.0V, CE=VOUT=VSS FOSC RT=10.0k, CT=220pF VINFOSC TYP. 4.875 VOUT=CE=Set Output Voltagex0.95V Stand-by Current FOSC MIN. MAX. VIN=3.0V CLK Oscillation Frequency Frequency Input Stability 4 Ta=25 PARAMETER 280 VIN=2.5V20V VIN=3.0V Frequency Temperature FOSC Fluctuation ToprFOSC Maximum Duty Cycle MAXDTY VOUT=Set Voltagex0.95V Minimum Duty Cycle MINDTY VOUT=Set Voltagex1.05V Topr=-40+85 79 UNITS CIRCUITS 0.5 2.0 A w 330 380 kHz e 5 % e 5 % e 89 % r 0 % r 85 ILIM VIN pin voltage-ISEN pin voltage 90 150 220 mV y ISEN Current IISEN VIN=3.0V, ISEN=3.0V 4.5 7 13 A y CE "High" Current ICEH CE=VIN=3.0V, VOUT=0V -0.1 0 0.1 A t CE "Low" Current ICEL CE=0V, VIN=3.0V, VOUT=0V -0.1 0 0.1 A t V t 0.2 V t 27 51 r 25 37 r 87 % q 5 ms q 400 k u Current Limiter Voltage CE "High" Voltage VCEH Existence of CLK Oscillation, 0.6 VOUT=0V, CE : Voltage applied CE "Low" Voltage VCEL Disappearance of CLK Oscillation, VOUT=0V, CE : Voltage applied EXT "High" ON REXTH Resistance EXT "Low" ON REXTL EXT=0.4V, CE=VIN=3.0V VOUT=Set voltagex1.05V Resistance Efficiency *1 EFFI Soft-Start Time TSS CC/GAIN Pin EXT=VIN-0.4V, CE=VIN=3.0V VOUT=Set voltagex0.95V Connect CSS and RSS, CE : 0V3.0V RCCGAIN Output Impedance VIN = 3.0V unless specified *1 : EFFI = {[(Output Voltage) x (Output Current)] / [(Input Voltage) x (Input Current)]} x 100 *2 : The capacity range of the capacitor used to set the external CLK frequency is 150 ~ 220pF 392 XC9101 Series XC9101D09AKR PARAMETER Ta=25 SYMBOL CONDITIONS IOUT=300mA UNITS CIRCUITS MIN. TYP. MAX. 0.8775 0.9 0.9225 V q 20 - - V q Output Voltage VOUT Maximum Operating Voltage VINmax Minimum Operating Voltage VINmin - 2.5 V q Supply Current 1 IDD1 VIN=2.5V, VIN=CE, FB=0.9x0.95V 150 255 A w Supply Current 2 IDD2 VIN=2.5V, CE=VIN, VOUT=0.9x1.05V 90 176 A w Stand-by Current ISTB VIN=2.5V, CE=FB=VSS CLK Oscillation Frequency FOSC RT=10.0k, CT=220pF Frequency Input Stability FOSC VINFOSC - 280 VIN=2.5V20V Frequency Temperature FOSC Fluctuation ToprFOSC Maximum Duty Cycle MAXDTY VOUT=0.9x0.95V Minimum Duty Cycle MINDTY VOUT=0.9x1.05V VIN=2.5V Topr=-40+85 79 0.5 2.0 A w 330 380 kHz e 5 % e 5 % e 89 % r 0 % r 85 Current Limiter Voltage ILIM VIN pin voltage-ISEN pin voltage 90 150 220 mV y ISEN Current IISEN VIN=2.5V, ISEN=2.5V 4.5 7 13 A y CE "High" Current ICEH CE=VIN=2.5V, FB=0V -0.1 0 0.1 A t CE "Low" Current ICEL CE=0V, VIN=2.5V, FB=0V -0.1 0 0.1 A t V t 0.2 V t 31 58 r 27 45 r % q 20 ms q k u CE "High" Voltage VCEH Existence of CLK Oscillation, VOUT=0V, CE : Voltage applied CE "Low" Voltage VCEL 0.6 Disappearance of CLK Oscillation, 4 VOUT=0V, CE : Voltage applied EXT "High" ON Resistance REXTH EXT "Low" ON Resistance REXTL Efficiency *1 EFFI Soft-Start Time TSS CC/GAIN Pin EXT=VIN-0.4V, CE=VIN VOUT=Set voltagex0.95V EXT=0.4V, CE=VIN VOUT=Set voltagex1.05V 88 Connect CSS and RSS, CE : 0V2.5V RCCGAIN Output Impedance 5 10 400 VIN = 2.5V unless specified External Components : RFB1=200k, RFB2=100k, CFB=82pF *1 : EFFI = {[(Output Voltage) x (Output Current)] / [(Input Voltage) x (Input Current)]} x 100 *2 : The capacity range of the capacitor used to set the external CLK frequency is 150 ~ 220pF 393 XC9101Series Typical Application Circuits XC9101C33AKR 22H SD 3.3V NMOS 20m 1 EXT VSS 8 2 Isen VOUT 7 3 VIN 4 CE/SS CC/GAIN 6 470pF 100k 220F 2.5V CLK 5 180pF 1F 47F(OS) +220F(any) 33k 0.1F 4 NMOS Coil : XP161A1355PR : 22H(CR105 SUMIDA) Resistor : 20m for Isen (NPR1 KOA), 33k(trimmer) for CLK, 100k for SS Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1F(ceramic) for SS,1F(ceramic) for Bypass 47F(OS)+220F(any) for CL, 220F(any) for CIN SD : U3FWJ44N (TOSHIBA) XC9101C50AKR 22H SD 5.0V NMOS 20m 1 EXT VSS 8 2 Isen VOUT 7 3 VIN 4 CE/SS CC/GAIN 6 470pF 100k 3.0V 220F CLK 5 1F 180pF 47F(OS) +220F(any) 33k 0.1F NMOS Coil : XP161A1355PR : 22H(CR105 SUMIDA) Resistor : 20m for Isen (NPR1 KOA), 33k(trimmer) for CLK, 100k for SS Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1F(ceramic) for SS,1F(ceramic) for Bypass 47F(OS)+220F(any) for CL, 220F(any) for CIN SD 394 : U3FWJ44N (TOSHIBA) XC9101 Series XC9101D09AKR 22H SD NMOS CFB 1 EXT VSS 8 2 Isen FB 7 RFB1 10m 3 VIN CC/GAIN 6 RFB2 150k 4 CE/SS 220F 0.1F 1F 470pF CLK 5 180pF 33k NMOS Coil : XP161A11A1PR : 22H(CDRH127 SUMIDA) Resistor : 10m for Isen (NPR1 KOA), 33k(trimmer) for CLK, 150k for SS 47F(OS) +220F(any) 4 Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1F(ceramic) for SS,1F(ceramic) for Bypass 47F(OS)+220F(any) for CL, 220F(any) for CIN SD VOUT RFB1 : U5FWJ44N (TOSHIBA) : 16V : 560k RFB2 : 33k CFB : 27pF VOUT RFB1 : 20V : 470k RFB2 : 22k CFB : 33pF 395 XC9101Series Operational Explanation Step-up DC/DC converter controllers of the XC9101 series carry out pulse width modulation (PWM) according to the multiple feedback signals of the output voltage and coil current. The internal circuits consist of different blocks that operate at VIN or the stabilized power (2.0 V) of the internal regulator. The output setting voltage of the type C controller and the FB pin voltage (Vref = 0.9 V) of type D controller have been adjusted and set by laser-trimming. <Clock> With regard to clock pulses, a capacitor and resistor connected to the CLK pin generate ramp waveforms whose top and bottom are 0.7V and 0.15V, respectively. The frequency can be set within a range of 100 to 600 kHz externally (refer to the "Functional Settings" section for further information). The clock pulses are processed to generate a signal used for synchronizing internal sequence circuits. <Verr amplifier> 4 The Verr amplifier is designed to monitor the output voltage. A fraction of the voltage applied to internal resistors R1, R2 in the case of a type C controller, and the voltage at the FB pin in the case of a type D controller, are fed back and compared with the reference voltage. In response to feedback of a voltage lower than the reference voltage, the output voltage of the Verr amplifier increases. The output of the Verr amplifier enters the mixer via resistor (RVerr). This signal works as a pulse width control signal during PWM operations. By connecting an external capacitor and resistor through the CE/GAIN pin, it is possible to set the gain and frequency characteristics of Verr amplifier signals (refer to the "Functional Settings" section for further information). <Ierr amplifier> The Ierr amplifier monitors the coil current. The potential difference between the VIN and Isen pins is sampled at each switching operation. Then the potential difference is amplified or held, as necessary, and input to the mixer. The Ierr amplifier outputs a signal ensuring that the greater the potential difference between the VIN and Isen pins, the smaller the switching current. The gain and frequency characteristics of this amplifier are fixed internally. <Mixer and PWM> The mixer modulates the signal sent from Verr by the signal from Ierr. The modulated signal enters the PWM comparator for comparison with the sawtooth pulses generated at the CLK pin. If the signal is greater than the sawtooth waveforms, a signal is sent to the output circuit to turn on the external switch. <Current Limiter> The current flowing through the coil is monitored by the limiter comparator via the VIN and Isen pins. The limiter comparator outputs a signal when the potential difference between the VIN and Isen pins reaches about 150 mV or more. This signal is converted to a logic signal and handled as a DFF reset signal for the internal limiter circuit. When a reset signal is input, a signal is output immediately at the EXT pin to turn off the MOS switch. When the limiter comparator sends a signal to enable data acceptance, a signal to turn on the MOS switch is output at the next clock pulse. If at this time the potential difference between the VIN and Isen pins is large, operation is repeated to turn off the MOS switch again. DFF operates in synchronization with the clock signal of the CLK pin. Limiter signal /RESET PWM/PFM switching signal CLK sync signal D CLK Q Output signal to EXT pin PWM/PFM switching signal <Soft Start> The soft start function is made available by attaching a capacitor and resistor to the CE/SS pin. The Vref voltage applied to the Verr amplifier is restricted by the start-up voltage of the CE/SS pin. This ensures that the Verr amplifier operates with its two inputs in balance, thereby preventing the ON-TIME signal from becoming stronger than necessary. Consequently, soft start time needs to be set sufficiently longer than the time set to CLK. The start-up time of the CE/SS pin equals the time set for soft start (refer to the "Functional Settings" section for further information). The soft start function operates when the voltage at the CE/SS pin is between 0V to 1.55V. If the voltage at the CE/SS pin doesn't start from 0V but from a mid level voltage when the power is switched on, the soft start function will become ineffective and the possibilities of large rush currents and ripple voltages occuring will be increased. 396 XC9101 Series Functional Settings 1. Soft Start CE and soft start (SS) functions are commonly assigned to the CE/SS pin. The soft start function is effective until the voltage at the CE pin reaches approximately 1.55 V rising from 0 V. Soft start time is approximated by the equation below according to values of Vcont, Rss, and Css. T = -Css x Rss x ln((Vcont - 1.55)/Vcont) Example: When CSS = 0.1 F, RSS = 470 k, and Vcont = 5 V, T = -0.1 e-6 x 470 e3 x ln ((5 - 1.55)/5) = 17.44 ms. CE/SS pin [Inside the IC] Rss Vcont CE, UVLO Css Vref circuit Set the soft start time to a value sufficiently longer than the period of a clock pulse. To Verr amplifier 4 > Circuit example 1: N-ch open drain Vcont [Inside the IC] Rss CE/SS pin ON/OFF signal Css > Circuit example 2: CMOS logic (low current dissipation) Vcont [Inside the IC] Rss ON/OFF signal CE/SS pin Css > Circuit example 3: CMOS logic (low current dissipation), quick off Vcont [Inside the IC] Rss ON/OFF signal CE/SS pin Css 397 XC9101Series 2. Oscillation Frequency The oscillation frequency of the internal clock generator is approximated by the following equation according to the values of the capacitor and resistor attached to the CLK pin. To stablize the IC's operation, set the oscillation frequency within a range of 100kHz to 600kHz. Select a value for Cclk within a range of 150pF to 220pF and fix the frequency based on the value for Rclk. f = 1/(-Cclk x Rclk x ln0.26) Example: When Cclk = 220 pF and Rclk = 10 k, f = 1/(-220e-12 x 10e3 x ln(0.26)) = 337.43 kHz. [Inside the IC] CLK pin Rclk 4 Cclk CLK Generater 3. Gain and Frequency Characteristics of the Verr Amplifier The gain at output and frequency characteristics of the Verr amplifier are adjusted by the values of the capacitor and resistor attached to the CC/GAIN pin. It is generally recommended to attach a CC of 220 to 1,000 pF without RGAIN. The greater the CC value, the more stable the phase and the slower the transient response. When using the IC with RGAIN connected, it should be noted that if the RGAIN resistance value is too high, abnormal oscillation may occur during transient response time. The size of RGAIN should be carefully evaluated before connection. [Inside the IC] CC/GAIN pin VOUT/FB Verr CC RGAIN Vref RVerr 4. Current Limit The current limit value is approximated by the following equation according to resistor RSEN inserted between the VIN and Isen pins. Double function, current FB input and current limiting, is assigned to the Isen pin. The current limiting value is approximated by the following equation according to the value for RSEN. Ilpeak_limit = 0.15/Rsen Example: When RSEN = 100 m, Ilpeak_limit = 0.15/0.1 = 1.5 A [Inside the IC] Isen pin Rsen Limiter signal VIN pin Comparator with 150V offset The inside error ampliphier sends feedback signal when the voltage occurs at RSEN resisitors because of the flow of coil current in order to phase compensate. The more the RSEN value becomes larger, the more the error signal becomes bigger, and it could lead to an intermittent oscillation. Please be careful if there is a problem with the application. When the regular operation, the voltage which occurs between RSEN resistors because of coil peak should be set lower than the current limit voltage of 90mV (min.). For more details, please refer the notes on the external components. 398 XC9101 Series 5. FB Voltage and Cfb With regard to the XC9101D series, the output voltage is set by attaching externally divided resistors. The output voltage is determined by the equation shown below according to the values of Rfb1 and Rfb2. In general, the sum of Rfb1 and Rfb2 should be 1 MEG or less. VOUT = 0.9 x (Rfb1 + Rfb2)/Rfb2 The value of Cfb (phase compensation capacitor) is approximated by the following equation according to the values of Rfb1 and fzfb. The value of fzfb should be 10 kHz, as a general rule. Cfb = 1/(2 x x Rfb1 x fzfb) Example: When Rfb1 = 455 k and Rfb2 = 100 k : VOUT = 0.9 x (455 k + 100 k)/100 k = 4.995 V : Cfb = 1/(2 x x 455 k x 10 k) = 34.98 pF [Inside the IC] Output voltage Cfb Rfb1 FB pin Verr Rfb2 0.9V 4 Verr amplifier Directions for use Application Notes 1. The XC9101 series are designed for use with an output ceramic capacitor. If, however, the potential difference between input and output is too large, a ceramic capacitor may fail to absorb the resulting high switching energy and oscillation could occur on the output side. If the input-output potential difference is large, connect an electrolytic capacitor in parallel to compensate for insufficient capacitance. 2. The EXT pin of the XC9101 series is designed to minimize the through current that occurs in the internal circuitry. However, the gate drive of external PMOS has a low impedance for the sake of speed. Therefore, if the input voltage is high and the bypass capacitor is attached away from the IC, the charge/discharge current to the external PMOS may lead to unstable operations due to switching operation of the EXT pin. As a solution to this problem, place the bypass capacitor as close to the IC as possible, so that voltage variations at the VIN and VSS pins caused by switching are minimized. If this is not effective, insert a resistor of several to several tens of ohms between the EXT pin and PMOS gate. Remember that the insertion of a resistor slows down the switching speed and may result in reduced efficiency. 3. A PNP transistor can be used in place of PMOS. If using a PNP transistor, insert a resistor (Rb) and capacitor (Cb) between the EXT pin and the base of the PNP transistor in order to limit the base current without slowing the switching speed. Adjust Rb in a range of 500 to 1 k according to the load and hFE of the transistor. Use a ceramic capacitor for Cb, complying with Cb 1/(2 x x Rb x Fosc x 0.7), as a rule. [Inside the IC] EXT pin Rb VIN Cb 4. Although the C_CLK connection capacitance range is from 150 ~ 220pF, the most suitable value for maximum stability is around 180pF. 399 XC9101Series Recommended Pattern Layout q In order to stablize VDD's voltage level, we recommend that a by-pass capacitor (CDD) be connected as close as possible to the VIN & VSS pins. w In order to stablize the GND voltage level which can fluctuate as a result of switching, we suggest that C_CLK's, R_CLK's & C_GAIN's GND be separated from Power GND and connected as close as possible to the VSS pin (by-pass capacitor, CDD). Please use a multi layer board and check the wiring carefully. Pattern Layout Examples XC9101D Series 2 Layer Evaluation Board L SD CDD 4 CFB N-MOS RFB1 1 5 2 6 3 7 4 8 VDD Line CL IC GND RSEN RSS VIN CIN CGAIN RFB2 RCLK CSS CCLK Through Hole 1 5 2 6 3 7 4 8 RCLK, CCLK, CGAIN, RFB2 GND Through Hole 400 Power GND XC9101 Series 1 Layer Evaluation Board L SD CDD CFB N-MOS RFB1 1 5 2 6 3 7 4 8 VDD Line CL IC GND RSEN RSS VIN CIN Power GND CGAIN RFB2 RCLK CSS CCLK 4 Notes Ensure that the absolute maximum ratings of the external components and the XC9101 DC/DC IC itself are not exceeded. We recommend that sufficient counter measures are put in place to eliminate the heat that may be generated by the external N-MOSFET as a result of switching losses. Try to use a N-MOSFET with as small a gate capacitance as possible in order to avoid overly large output spike voltages that may occur (such spikes occur in proportion to gate capacitance). The performance of the XC9101 DC/DC converter is greatly influenced by not only its own characteristics, but also by those of the external components it is used with. We recommend that you refer to the specifications of each component to be used and take sufficient care when selecting components. Wire external components as close to the IC as possible and use thick, short connecting wires to reduce wiring impedance. In particular, minimize the distance between the by-pass capacitor and the IC. Make sure that the GND wiring is as strong as possible as variations in ground potential caused by ground current at the time of switching may result in unstable operation of the IC. Specifically, strengthen the ground wiring in the proximity of the VSS pin. 401 XC9101Series Test Circuits Fig. q (FB Type) Fig. q (VOUT Type) SD 22H 22H NMOS SD NMOS 1 EXT 100m RSS CFB Vss 8 2 Isen VOUT 7 3 VIN GAIN 6 1 EXT RL V 100m 2 Isen RSS 3 VIN 4 CE/SS CLK 5 220F 0.1F 470pF 10K 1F 20F FB 7 RFB2 GAIN 6 RL 4 CE/SS CLK 5 220F 0.1F 10K 220pF RFB1 Vss 8 1F 220pF 20F 470pF XC9101C33A RSS104k C-SS0.1F XC9101C50A RSS138k C-SS0.1F 4 Fig. w Fig. e 1 EXT 1 EXT Vss 8 2 IsenVOUT/FB 7 3 VIN A Vss 8 VOUT/FB 7 2 Isen 3 VIN GAIN 6 GAIN 6 4 CE/SS CLK 5 4 CE/SS CLK 5 220pF 0.1F OSC 10K 220pF 10K 0.1F Fig. t Fig. r 1 EXT 1 EXT Vss 8 2 IsenVOUT/FB 7 OSC 3 VIN 3 VIN GAIN 6 0.1F A 4 CE/SS CLK 5 Vss 8 2 IsenVOUT/FB 7 V GAIN 6 4 CE/SS CLK 5 10K 220pF 10K 0.1F 220pF Fig. y Fig. u 1 EXT Vss 8 1 EXT 2 IsenVOUT/FB 7 V 3 VIN A GAIN 6 3 VIN 4 CE/SS CLK 5 0.1F 402 10K Vss 8 2 IsenVOUT/FB 7 GAIN 6 4 CE/SS CLK 5 0.1F 220pF 1M V V V XC9101 Series Typical Performance Characteristics VOUT = 3.3V, FOSC : 180kHz VOUT = 5.0V, FOSC : 180kHz L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1355PR L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1355PR 3.6 5.3 3.5 5.2 Output Voltage : VOUT (V) Output Voltage : VOUT (V) XC9101D09AKR (1) OUTPUT VOLTAGE vs. OUTPUT CURRENT 3.4 3.3 3.2 3.1 VIN=2.5V 3.0V 3.0 5.1 5.0 4.9 VIN=2.5V 3.3V 4.2V 4.8 4.7 1 10 100 1000 1 Output Current : IOUTmA 10 100 1000 Output Current : IOUTmA VOUT = 8.0V, FOSC : 330kHz VOUT = 12.0V, FOSC : 330kHz L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1355PR L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1265PR 8.3 13.0 8.2 Output Voltage : VOUT (V) Output Voltage : VOUT (V) 4 8.1 8.0 7.9 7.8 12.5 12.0 11.5 VIN=5.0V 8.0V VIN=3.3V 5.0V 11.0 7.7 1 10 100 Output Current : IOUTmA 1000 1 10 100 1000 Output Current : IOUTmA 403 XC9101Series (2) EFFICIENCY vs. OUTPUT CURRENT VOUT = 3.3V, FOSC : 180kHz VOUT = 5.0V, FOSC : 180kHz L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1355PR L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1355PR 4 100 Efficiency : EFFI (%) Efficiency : EFFI (%) 100 80 3.0V VIN=2.5 60 40 80 4.2V 3.3V 60 VIN=2.5V 40 1 10 100 1000 1 Output Current : IOUTmA 1000 VOUT = 12.0V, FOSC : 180kHz L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1355PR L=22H, CIN=220FElectrolytic+10FCeramic CL=40FCeramic, RSEN=50m, CDD=1FCeramic SDU3FWJ44N, CGAIN=470pFCeramic, TrXP161A1265PR 100 Efficiency : EFFI (%) Efficiency : EFFI (%) 100 VOUT = 8.0V, FOSC : 180kHz 100 80 5.0V VIN=3.3 60 40 80 8.0V VIN=5.0V 60 40 1 10 100 Output Current : IOUTmA 404 10 Output Current : IOUTmA 1000 1 10 100 Output Current : IOUTmA 1000 XC9101 Series VOUT = 3.3V, FOSC : 180kHz VOUT = 5.0V, FOSC : 180kHz L=22H,CIN=220F(Electrolytic)+10F(Ceramic) CL=40F(Ceramic),RSEN=50m,CDD=1F(Ceramic) SD:U3FWJ44N,CGAIN=470pF(Ceramic),Tr:XP161A1355PR L=22H,CIN=220F(Electrolytic)+10F(Ceramic) CL=40F(Ceramic),RSEN=50m,CDD=1F(Ceramic) SD:U3FWJ44N,CGAIN=470pF(Ceramic),Tr:XP161A1355PR 100 100 80 80 Ripple Voltage : Vr (mVp-p) Ripple Voltage : Vr (mVp-p) (3) RIPPLE VOLTAGE vs. OUTPUT CURRENT 60 3.0V 40 VIN=2.5V 20 4.2V 60 3.3V VIN=2.5V 40 20 0 0 1 10 100 1000 1 Output Current : IOUT (mA) 1000 VOUT = 12.0V, FOSC : 330kHz L=22H,CIN=220F(Electrolytic)+10F(Ceramic) CL=40F(Ceramic),RSEN=50m,CDD=1F(Ceramic) SD:U3FWJ44N,CGAIN=470pF(Ceramic),Tr:XP161A1355PR L=22H,CIN=220F(Electrolytic)+10F(Ceramic) CL=40F(Ceramic),RSEN=50m,CDD=1F(Ceramic) SD:U3FWJ44N,CGAIN=470pF(Ceramic),Tr:XP161A1265PR 4 100 Ripple Voltage : Vr (mVp-p) Ripple Voltage : Vr (mVp-p) 100 VOUT = 8.0V, FOSC : 330kHz 100 80 60 5.0V 40 VIN=3.3V 20 0 80 8.0V 60 VIN=5.0V 40 20 0 1 10 100 1000 1 Output Current : IOUT (mA) 10 100 1000 Output Current : IOUT (mA) VOUT = 3.3V, FOSC : 180kHz VOUT = 5.0V, FOSC : 180kHz L=22H,CL=94F(Tantalum),CIN=94F(Tantalum) RSEN=50m,CDD=1F(Ceramic) SD:U3FWJ44N,CGAIN=470pF(Ceramic),Tr:XP161A1355PR L=22H,CL=94F(Tantalum),CIN=94F(Tantalum) RSEN=50m,CDD=1F(Ceramic) SD:U3FWJ44N,CGAIN=470pF(Ceramic),Tr:XP161A1355PR 200 Ripple Voltage : Vr (mVp-p) 200 Ripple Voltage : Vr (mVp-p) 10 Output Current : IOUT (mA) 160 3.0V 120 VIN=2.5V 80 40 160 4.2V VIN=3.3V 120 80 40 0 0 1 10 100 Output Current : IOUT (mA) 1000 1 10 100 1000 Output Current : IOUT (mA) Note : If the difference between the input and output voltage is large or small, switching ON / OFF time will be shortened. As such, the external components used and their values ( inductance value of the coil, resistor connected to CLK, capacitor etc. ) may have a critical influence on the actual operation of the IC. 405