This is information on a product in full production.
March 2017 DocID028196 Rev 4 1/217
STM32F469xx
ARM
®
Cortex
®
-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG
HS/FS, Ethernet, FMC, dual Quad-SPI, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI
Datasheet - production data
Features
•Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
•Memories
– Up to 2 MB of Flash memory organized into two
banks allowing read-while-write
– Up to 384+4 KB of SRAM including 64 KB of
CCM (core coupled memory) data RAM
– Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR, SDRAM, Flash NOR/NAND
memories
– Dual-flash mode Quad-SPI interface
•Graphics:
– Chrom-ART Accelerator™ (DMA2D), graphical
hardware accelerator enabling enhanced
graphical user interface with minimum CPU load
– LCD parallel interface, 8080/6800 modes
– LCD TFT controller supporting up to XGA
resolution
–MIPI
® DSI host controller supporting up to 720p
30Hz resolution
•Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
•Low power
– Sleep, Stop and Standby modes
–V
BAT supply for RTC, 20×32 bit backup registers
+ optional 4 KB backup SRAM
•3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
•2×12-bit D/A converters
•General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
•Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. 2x watchdogs and
SysTick timer
•Debug mode
– SWD & JTAG interfaces
–Cortex
®-M4 Trace Macrocell™
•Up to 161 I/O ports with interrupt capability
– Up to 157 fast I/Os up to 90 MHz
– Up to 159 5 V-tolerant I/Os
•Up to 21 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs and 4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem control)
– Up to 6 SPIs (45 Mbits/s), 2 with muxed full-
duplex I2S for audio class accuracy via internal
audio PLL or external clock
– 1 x SAI (serial audio interface)
– 2 × CAN (2.0B Active)
– SDIO interface
•Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller
with on-chip PHY
– USB 2.0 high-speed/full-speed device/host/OTG
controller with dedicated DMA, on-chip full-
speed PHY and ULPI
– Dedicated USB power rail enabling on-chip
PHYs operation throughout the entire MCU
power supply range
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
•8- to 14-bit parallel camera interface up to
54 Mbytes/s
•True random number generator
•CRC calculation unit
•RTC: subsecond accuracy, hardware calendar
•96-bit unique ID
Table 1. Device summary
Reference Part numbers
STM32F469xx
STM32F469AE, STM32F469AG, STM32F469AI
STM32F469BE, STM32F469BG, STM32F469BI
STM32F469IE, STM32F469IG, STM32F469II
STM32F469NE, STM32F469NG, STM32F469NI
STM32F469VE, STM32469VG, STM32469VI
STM32F469ZE, STM32469ZG, STM32469ZI
&"'!
WLCSP168
UFBGA176 (10 x 10 mm)
TFBGA216 (13 x 13 mm)
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
LQFP208 (28 × 28 mm)
UFBGA169 (7 × 7 mm)
www.st.com
Contents STM32F469xx
2/217 DocID028196 Rev 4
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.1 LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.2 LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1.3 UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1.4 TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 21
2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21
2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22
2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.9 Flexible Memory Controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.10 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.11 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.12 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.13 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 27
2.15 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.16 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.17 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.18 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.19 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.19.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.19.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.20 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.20.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.20.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID028196 Rev 4 3/217
STM32F469xx Contents
5
2.20.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35
2.21 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35
2.22 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.23 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.24.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.24.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.24.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.25 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.26 Universal synchronous/asynchronous receiver transmitters (USART) . . 39
2.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.28 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.29 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.31 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.32 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 42
2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 42
2.34 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.35 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 43
2.36 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 43
2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.38 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.39 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.40 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.41 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.42 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.43 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.44 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Contents STM32F469xx
4/217 DocID028196 Rev 4
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 95
5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 95
5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 95
5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 122
5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 131
5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.23 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
DocID028196 Rev 4 5/217
STM32F469xx Contents
5
5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.29 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.3.30 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.3.31 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 185
5.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 186
5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 188
5.3.34 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.3 WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.6 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.7 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 215
A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
List of tables STM32F469xx
6/217 DocID028196 Rev 4
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F469xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 10. STM32F469xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 11. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 12. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 13. STM32F469xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 94
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 95
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 95
Table 22. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . 100
Table 26. Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 27. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 102
Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 103
Table 29. Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 30. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 105
Table 31. Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 106
Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 34. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 37. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 39. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 41. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 42. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
DocID028196 Rev 4 7/217
STM32F469xx List of tables
8
Table 44. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 45. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 125
Table 47. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 48. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 49. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 50. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 51. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 56. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 57. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 58. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 59. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 60. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 61. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 62. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 63. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 64. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 65. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 66. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 67. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 68. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 69. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 70. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 71. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 72. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 73. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 74. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 75. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 77. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 78. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 79. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 80. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
Table 81. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
Table 82. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 83. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 84. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 85. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 86. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 87. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 166
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 166
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 167
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 168
Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 169
Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 171
List of tables STM32F469xx
8/217 DocID028196 Rev 4
Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 97. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 106. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 107. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 108. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 189
Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 190
Table 112. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 113. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 114. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 115. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 116. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 117. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 118. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 206
Table 120. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 121. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 122. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 123. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 124. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 215
Table 125. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
DocID028196 Rev 4 9/217
STM32F469xx List of figures
11
List of figures
Figure 1. Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2. Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. STM32F469xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. STM32F469xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30
Figure 9. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. STM32F46x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14. STM32F46x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 15. STM32F46x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16. STM32F46x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. STM32F46x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 18. STM32F46x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19. STM32F46x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 20. STM32F46x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 21. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 22. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 24. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 25. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 26. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 27. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . . 106
Figure 28. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . . 107
Figure 29. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 30. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 31. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 33. ACCHSI vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 39. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 40. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 41. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 42. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 43. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 44. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
List of figures STM32F469xx
10/217 DocID028196 Rev 4
Figure 45. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 46. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 47. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 48. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 49. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 150
Figure 50. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 51. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 52. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 53. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 54. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 55. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 56. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 160
Figure 57. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 160
Figure 58. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 165
Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 167
Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 63. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 64. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 66. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 67. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 68. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 69. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 179
Figure 70. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 180
Figure 71. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 72. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 73. Quad-SPI SDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 74. Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 80. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 191
Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 82. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 83. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 194
Figure 84. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 85. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 86. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 87. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 88. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 89. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 201
Figure 90. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 91. LQFP176 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 92. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,
DocID028196 Rev 4 11/217
STM32F469xx List of figures
11
ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 93. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 94. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 207
Figure 95. LQFP208 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 96. LQFP208 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 97. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm, package outline . . . . . . . . . 211
Figure 98. TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Description STM32F469xx
12/217 DocID028196 Rev 4
1 Description
The STM32F469xx devices are based on the high-performance ARM® Cortex®-M4 32-bit
RISC core operating at a frequency of up to 180 MHz. The Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all ARM® single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F469xx devices incorporate high-speed embedded memories (Flash memory
up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
and a true random number generator (RNG). They also feature standard and advanced
communication interfaces:
•Up to three I2Cs
•Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
•Four USARTs plus four UARTs
•An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
•Two CANs
•One SAI serial audio interface
•An SDMMC host interface
•Ethernet and camera interface
•LCD-TFT display controller
•Chrom-ART Accelerator™
•DSI Host.
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory, and camera interface for CMOS sensors. Refer to
Table 2 for the list of peripherals available on each part number.
The STM32F469xx devices operate in the –40 to +105 °C temperature range from a 1.7 to
3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full
speed mode, is available on all packages.
The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of
power-saving mode allows the design of low-power applications.
The STM32F469xx devices are offered in eight packages, ranging from 100 to 216 pins.
The set of included peripherals changes with the device chosen, according to Table 2.
DocID028196 Rev 4 13/217
STM32F469xx Description
46
These features make the STM32F469xx microcontrollers suitable for a wide range of
applications:
•Motor drive and application control
•Medical equipment
•Industrial applications: PLC, inverters, circuit breakers
•Printers, and scanners
•Alarm systems, video intercom, and HVAC
•Home audio appliances
Figure 5 shows the general block diagram of the device family.
Table 2. STM32F469xx features and periphe ral counts
Peripherals
STM32F469Vx
STM32F469Zx
STM32F469Ax
STM32F469Ix
STM32F469Bx
STM32F469Nx
Flash memory in Kbytes
512
1024
2048
512
1024
2048
512
1024
2048
512
1024
2048
512
1024
2048
512
1024
2048
SRAM in
Kbytes
System 384 (160+32+128+64)
Backup 4
FMC memory controller Yes
Quad-SPI Yes
Ethernet No Yes
Timers
General-
purpose 10
Advanced-
control 2
Basic 2
Random number generator Yes
Communication
interfaces
SPI / I2S 4/2(full duplex)(1) 6/2(full duplex)(1)
I2C3
USART/UART 4/3 4/4
USB OTG FS Yes
USB OTG HS Yes
CAN 2
SAI 1
SDIO Yes
Camera interface Yes
Description STM32F469xx
14/217 DocID028196 Rev 4
MIPI-DSI Host Yes
LCD-TFT Yes
Chrom-ART Accelerator™
(DMA2D) Yes
GPIOs 71 106 114 131 161 161
12-bit ADC
Number of channels
3
14 20 24 16 24 24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency 180 MHz
Operating voltage 1.7 to 3.6V(2)
Operating temperatures Ambient operating temperature: −40 to 85 °C / −40 to 105 °C
Junction temperature: −40 to 105 °C / −40 to 125 °C
Package LQFP100 LQPF144 UFBGA169
WLCSP168
LQFP176
UFBGA176 LQFP208 TFBGA216
1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).
Table 2. STM32F469xx features and peripheral counts (continued)
Peripherals
STM32F469Vx
STM32F469Zx
STM32F469Ax
STM32F469Ix
STM32F469Bx
STM32F469Nx
DocID028196 Rev 4 15/217
STM32F469xx Description
46
1.1 Compatibility throughout the family
STM32F469xx devices are not compatible with other STM32F4xx devices.
Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and
LQFP208 packages (highlighted pins).
The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices,
only few IO port pins are substituted, as shown in Figure 3 and Figure 4.
The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other
STM32F4xx devices.
Description STM32F469xx
16/217 DocID028196 Rev 4
1.1.1 LQFP176 package
Figure 1. Incompatible board design for LQFP176 package
1. Pins from 85 to 133 are not compatible.
069
966
3,
3,
3,
9''
966
9&$3
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
9''86%
966
3*
3*
3*
3*
3*
3*
3*
966'6,
'6,+267B'1
'6,+267B'3
9'''6,
'6,+267B&.1
'6,+267B&.3
966'6,
'6,+267B'1
'6,+267B'3
9&$3'6,
9''6,
3'
3'
9''
966
3'
3'
3'
3'
3'
3'
670)[[[[
/4)3
3+
3%
3%
3%
3%
966
3,
3,
3,
3,
3+
3+
3+
9''
966
9&$3
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
9''
966
3*
3*
3*
3*
3*
3*
3*
3'
3'
9''
966
3'
3'
3'
3'
3'
3'
3%
3%
3%
3%
9''
966
3+
3+
3+
3+
3+
670)[[
/4)3
3+
DocID028196 Rev 4 17/217
STM32F469xx Description
46
1.1.2 LQFP208 package
Figure 2. Incompatible board design for LQFP208 package
1. Pins from 118 to 128 and pin 137 are not compatible
069
3& 3&
9''86% 9''
966 966
3* 3*
3* 3*
3* 3*
3* 3*
3* 3*
3* 3*
3* 3*
966'6, 3.
'6,+267B'1 3.
'6,+267B'3 3.
9'''6, 966
'6,+267B&.1 9''
'6,+267B&.3 3-
966'6, 3-
'6,+267B'1 3-
'6,+267B'3 3-
9&$3'6, 3-
9'''6, 3-
3' 3'
3' 3'
670)[670)[
/4)3
670)[[[[
/4)3
Description STM32F469xx
18/217 DocID028196 Rev 4
1.1.3 UFBGA176 package
Figure 3. UFBGA176 port-to-te rminal assignment differences
1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
'6,
+267B
'3
'6,
+267B
'1
'6,
+267B
&.1
'6,
+267B
&.3
9&$3
'6,
9''
'6,
9''B
86%
966
'6,
'6,
+267B
'3
'6,
+267B
'1
9''
'6,
1&
069
$3(3(
3( 3( 3% 3% 3* 3* 3% 3 % 3 ' 3& 3 $ 3 $ 3 $
%3(3(
3( 3% 3% 3% 3* 3* 3* 3* 3' 3' 3& 3& 3$
&9%$7 3, 3, 3, 3'5
B21
9'' 3* 3' 3' 3, 3$
'3& 3, 3, 3, %227 966 966 966 3' 3' 3' 3, 3$
(3& 3) 3, 3, 3, 3$
)3&
966 9'' 3+ 966 9&$3 3& 3$
*3+ 966 9'' 3+ 966 9'' 3& 3&
+3+ 3) 3) 3+ 3* 3&
-15 67 3) 3+ 3* 3*
.3) 3)
3)
9'' 966 3* 3* 3*
/3) %<3$66
B5(* 3' 3*
0966$3&
3)
3& 3& 3& 3% 3* 9&$3
B 3+ 3' 3'
195() 3$ 3$ 3& 3) 3* 9'' 9'' 9'' 3( 3+ 3' 3' 3'
33$ 3$ 3$ 3& 3) 3) 3( 3( 3( 3( 3% 3% 3' 3'
53$ 3% 3) 3( 3( 3( 3% 3 % 3 % 3%
966
3$
9''
9'' 9'' 9''
95()
9''$ 3$ 3% 3) 3)
966 966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966 966
3)
3)
3' 3, 3,
3' 3,
3+ 3,
966 9&$3 3&
966 9'' 3&
966 9'' 3*
3*
3* 3*
3'
3'
3+
3+
9''
3+
3+
3+ 3+
3+
9''
3' 3, 1&
3' 3,
'6,
+267B
'3
3,
966 9&$3 3&
966 9'' 3&
966
'6,
9''B
86% 3*
3*
3* 3*
3'
3'
9''
'6,
'6,
+267B
'1
9''
'6,
9&$3
'6,
'6,
+267B
&.3
'6,
+267B
'3
'6,
+267B
'1
'6,
+267B
&.1
9''
^dDϯϮ&ϰϮdždžϯdždž
^dDϯϮ&ϰϬdždžϰϭdždž
^dDϯϮ&ϰϲϵdždž
^dDϯϮ&ϰϳϵdždž
DocID028196 Rev 4 19/217
STM32F469xx Description
46
1.1.4 TFBGA216 package
Figure 4. TFBGA216 port-to-terminal assignment differences
1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
06Y9
$3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$
%3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$
&9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3, 3, 3$
'3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$
(3& 3) 3, 3, %227 9'' 9'' 9'' 9'' 9&$3 3+ 3+ 3, 3$
)3& 966 3, 9'' 3& 3$
*3+ 3) 3, 3, 9'' 3& 3&
+3+ 3, 3+ 966 3* 3&
-1567 3) 3+ 3+ 966 9'' 3* 3*
.3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3' 3% 3'
/3) 3& %<3$66
5(* 3% 3' 3'
0966$ 3* 3' 3' 3* 3* 3- 3+
195() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+
95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+
3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3%
3)
3
59''$
3'5
21
3( 3( 3(
9''
9''
966
966
966
966 966 966 966 966
966
9''
3-3)
9'' 9'' 9'' 9&$3 3'
9''
3)
3)
3& 3& 3& 3% 3)
9''
966
3'
^dDϯϮ&ϰϮdždžϯdždž
^dDϯϮ&ϰϬdždžϰϭdždž
^dDϯϮ&ϰϲϵdždž
^dDϯϮ&ϰϳϵdždž
9''
9'' 3'
9''
9''
9'' 3'
9''
9''
'6,
'6,
+267B
&.3
9'''
86%
966
'6,
9''
'6,
'6,
+267B
&.1
'6,
+267B
'3
9&$3
'6,
'6,
+267B
'1
'6,
+267B
'3
'6,
+267B
'1
3-
9'' 3- 3.
3-
3-
3-
3-
3. 3/
9''
Description STM32F469xx
20/217 DocID028196 Rev 4
Figure 5. STM32F469xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
4XDG63,
069
86$570%SV*3,23257$
$+%$3%
86$570%SV
(;7,7:.83
$)
3$>@
86$570%SV
*3,23257%
3%>@
86$570%SV
7,0(53:0
FRPSOFKDQ7,0B&+>@1
FKDQ7,0B&+>@(75
%.,1DV$)
86$570%SV7,0(53:0
86$570%SV
*3,23257&
3&>@
86$570%SV
86$57
5;7;6&.
&76576DV$)
86$570%SV*3,23257'
3'>@
86$570%SV*3,23257(
3(>@
86$570%SV
*3,23257)
3)>@
86$570%SV*3,23257*
3*>@
86$570%SV
63,,6
$3% 0 + ]
DQDORJLQSXWVFRPPRQ
WRWKH$'&V
DQDORJLQSXWVFRPPRQ
WRWKH$'&
9''5()B$'&
DQDORJLQSXWVWR$'&
&KDQQHOV(75DV$)
7,0
7,0
7,0
&KDQQHOV
7,0
5;7;6&.
86$57
5;7;6&.
86$57
5;7;DV$)
8$57
5;7;DV$)
8$57
026,0,626&.
166:60&.DV$)
63,,6
026,0,626&.
63,,6 166:60&.DV$)
6&/6'$60%$DV$)
,&60%86
6&/6'$60%$DV$)
,&60%86
7;5;
E[&$1
7;5;
E[&$1
'$&DV$)
'$&
'$&DV$)
'$&
,7)
7,0(5
7,0(5
::'*
.%%.35$0
57&B7$03
57&B7$03
57&B287
57&B5(),1
57&B76
26&B,1
26&B287
26&,1
26&287
9''$966$
1567
86$570%SV86$57
5;7;6&.
&76576DV$)
VPFDUG
LU'$
VPFDUG
LU'$
VPFDUG
LU'$
VPFDUG
LU'$
E
E
E
E
E
E
E
E
&76576DV$)
&76576DV$)
6',200&
'>@
&0'&.DV$)
9%$7 WR9
'0$
$+%$3%
'0$
6&/6'$60%$DV$)
,&60%86
86$570%SV*3,23257+
3+>@
-7$*6:
$50
&RUWH[0
0+] ,%86
6%86
'%86
19,&(70
038)38
-7567-7',
-7&.6:&/.
-7'26:'-7'2
75$&(&.
75$&('
86% '0$
),)2
27*+6
''
9''86% WR9
8/3,&/.'
',56731;7
6&/6'$,17,'9%86 *3'0$ 6WUHDPV
),)2
*3'0$ 6WUHDPV
),)2
)ODVK0%
$&&(/
&$&+(
65$0.%
65$0.%
(;70(0&75/)0&
65$0365$0125)ODVK
1$1')ODVK6'5$0
&/.1(>@$>@'>@
12(1:(11%/>@
6'&/.(>@6'1(>@
15$61&$61$'9
1:$,7,175
&$0(5$ +6<1&96<1&
3,;&.'
,7)
86%
3+<
27*)6 ''
9''86% WR9
6&/6'$,17,'9%86
),)2
3+<
),)2
86$570%SV
7(036(1625
$'&
$'&
$'&
,)
,)
#9''$
#9''$
3253'5
6833/<
683(59,6,21
39'
5HVHW
,QW
325
;7$/26&
0+]
;7$/N+]
0$1$*7
57&
5&+6
5&/6
6WDQGE\LQWHUIDFH
,:'*
#9%$7
#9''$
$:8
5(6(7
&/2&.
&75/
3//
#9''$#9''
%DFNXS5HJLVWHU
$+%0+]
/6
/6
&KDQQHOVDV$)
7,0
&KDQQHOVDV$)
7,0
&+DV$)
7,0
E
E
E
86$570%SV7,0(5
FKDQQHOVDV$)
86$570%SV
7,0(5
FKDQQHODV$)
E
E
86$570%SV
7,0(5
FKDQQHODV$) E
%25
),)2
8$57
8$57
86$570%SV63,
6'6&.)6
0&/.DV$)
&5&
86$570%SV
6$,
'LJ)LOWHU
),)2
&/.
%.B1&6%.B1&6
'>@
86$570%SV
63,
),)2
)ODVK0%
65$0.%
51*
$+%0+]
&KDQQHOV(75DV$)
&KDQQHOV(75DV$)
86$570%SV*3,23257,
3,>@
86$570%SV*3,23257-
3->@
86$570%SV*3,23257.
3.>@
$+%0+]
+&/.[
3&/.[
86$570%SV
63,
026,0,626&.
166DV$)
026,0,626&.
166DV$)
026,0,626&.
166DV$)
026,0,626&.
166DV$)
&&0GDWD5$0.%
/&'7)7 ),)2
'0$' ),)2
'6,+RVW
'6,
3+,
'6,+267B'31
'6,+267B'31
'6,+267B&.31
9'''6,9''6,966'6,
9&$3'6,
'6,+267B7(
FRPSOFKDQ7,0B&+>@1
FKDQ7,0B&+>@(75
%.,1DV$)
5;7;DV$)
5;7;DV$)
$+%%860$75,;
$3%0+]
$3%0+]
DocID028196 Rev 4 21/217
STM32F469xx Functional overview
46
2 Functional overview
2.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM
The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an ARM core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F46x line is compatible with all ARM tools and software.
Figure 5 shows the general block diagram of the STM32F46x line.
Note: Cortex®-M4 with FPU core is binary compatible with the Cortex®-M3 core.
2.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
ARM® Cortex®-M4 with FPU processors. It balances the inherent performance advantage
of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which normally require
the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
2.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32F469xx
22/217 DocID028196 Rev 4
2.4 Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
2.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
2.6 Embedded SRAM
All devices embed:
•Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
•4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.7 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB
and APB peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
DocID028196 Rev 4 23/217
STM32F469xx Functional overview
46
Figure 6. STM32F469xx Multi-AHB matrix
2.8 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
ZD
ŽƌƚĞdžͲDϰ
'W
Dϭ
'W
DϮ
D
ƚŚĞƌŶĞƚ
h^Kd'
,^
ƵƐŵĂƚƌŝdžͲ^
/K
K
>
&ůĂƐŚ
ŵĞŵŽƌLJ
^ZDϭ
ϭϲϬ<ďLJƚĞ
^ZDϮ
ϯϮ<ďLJƚĞ
,Ϯ
ƉĞƌŝƉŚĞƌĂůƐ
,ϭ
ƉĞƌŝƉŚĞƌĂůƐ
&DĞdžƚĞƌŶĂů
DĞŵƚů
/ͲďƵƐ
ͲďƵƐ
^ͲďƵƐ
DͺW/
DͺDDϭ
DͺDDϮ
DͺWϮ
d,ZEdͺD
h^ͺ,^ͺD
D^ϯϯϴϲϮsϭ
DĚĂƚĂZD
ϲϰͲ<ďLJƚĞ
Wϭ
WϮ
^ZDϯ
ϭϮϴ<ďLJƚĞ
>Ͳd&d ŚƌŽŵZd
ĐĐĞůĞƌĂƚŽƌ;DϮͿ
>Ͳd&dͺD
DϮ
YƵĂĚ^W/
Functional overview STM32F469xx
24/217 DocID028196 Rev 4
The DMA can be used with the main peripherals:
•SPI and I2S
•I2C
•USART
•General-purpose, basic and advanced-control timers TIMx
•DAC
•SDIO
•Camera interface (DCMI)
•ADC
•SAI1
•QUADSPI.
2.9 Flexible Memory Controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
•The NOR/PSRAM memory controller
•The NAND/memory controller
•The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
•Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•8-,16-,32-bit data bus width
•Independent Chip Select control for each memory bank
•Independent configuration for each memory bank
•Write FIFO
•Read FIFO for SDRAM controller
•The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
DocID028196 Rev 4 25/217
STM32F469xx Functional overview
46
2.10 Quad-SPI memory interface (QUADSPI)
All STM32F469xx devices embeds a Quad-SPI memory interface, which is a specialized
communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can
work in direct mode through registers, external flash status register polling mode and
memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting
8, 16 and 32-bit access. Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.11 LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
•2 displays layers with dedicated FIFO (64x32-bit)
•Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•Up to 8 Input color formats selectable per layer
•Flexible blending between two layers using alpha value (per pixel or constant)
•Flexible programmable parameters for each layer
•Color keying (transparency color)
•Up to 4 programmable interrupt events.
2.12 DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
•LTDC interface:
– Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
– Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command Mode (DBI).
•APB slave interface:
– Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
– Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode.
•Video mode pattern generator:
– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
Functional overview STM32F469xx
26/217 DocID028196 Rev 4
The DSI Host main features:
•Compliant with MIPI® Alliance standards
•Interface with MIPI® D-PHY
•Supports all commands defined in the MIPI® Alliance specification for DCS:
– Transmission of all Command mode packets through the APB interface
– Transmission of commands in low-power and high-speed during Video Mode
•Supports up to two D-PHY data lanes
•Bidirectional communication and escape mode support through data lane 0
•Supports non-continuous clock in D-PHY clock lane for additional power saving
•Supports Ultra Low-Power mode with PLL disabled
•ECC and Checksum capabilities
•Support for End of Transmission Packet (EoTp)
•Fault recovery schemes
•3D transmission support
•Configurable selection of system interfaces:
– AMBA APB for control and optional support for Generic and DCS commands
– Video Mode interface through LTDC
– Adapted Command Mode interface through LTDC
•Independently programmable Virtual Channel ID in
– Video Mode
– Adapted Command Mode
– APB Slave
Video Mode interfaces features:
•LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
•Programmable polarity of all LTDC interface signals
•Extended resolutions beyond the DPI standard maximum resolution of 800x480 pixels:
maximum resolution is limited by available DSI physical link bandwidth:
– Number of lanes: 2
– Maximum speed per lane: 500Mbps
Adapted interface features:
•Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
•LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
DocID028196 Rev 4 27/217
STM32F469xx Functional overview
46
Video mode pattern generator:
•Vertical and horizontal color bar generation without LTDC stimuli
•BER pattern without LTDC stimuli
2.13 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•Rectangle filling with a fixed color
•Rectangle copy
•Rectangle copy with pixel format conversion
•Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
2.14 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4 with FPU core.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.15 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected
to the 16 external interrupt lines.
Functional overview STM32F469xx
28/217 DocID028196 Rev 4
2.16 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
2.17 Boot modes
At startup, boot pins are used to select one out of three boot options:
•Boot from user Flash
•Boot from system memory
•Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
2.18 Power supply schemes
•VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (re fer to
Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
•VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers.
For example, when device is powered at 1.8V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
DocID028196 Rev 4 29/217
STM32F469xx Functional overview
46
The following conditions must be respected:
– During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
– During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–V
DDUSB rising and falling time rate specifications must be respected.
– In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB
supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
– If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by VDDUSB.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by VDDUSB are operating between VDD_MIN and VDD_MAX.
Figure 7. VDDUSB connected to an external independent power supply
The DSI (Display Serial Interface) sub-system uses several power supply pins which are
independent from the other supply pins:
•VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-
PHY. This supply must be connected to global VDD.
•VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally
to VDD12DSI.
•VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.
•VSSDSI pin is an isolated supply ground used for DSI sub-system.
•If DSI functionality is not used at all, then:
– VDDDSI pin must be connected to global VDD.
– VCAPDSI pin must be connected externally to VDD12DSI but the external
capacitor is no more needed.
– VSSDSI pin must be grounded.
069
9
''86%B0,1
9
''B0,1
WLPH
9
''86%B0$;
86% IXQFWLRQDODUHD
9
''
9
''$
86% QRQ
IXQFWLRQDO
DUHD
9
''86%
3RZHURQ 3RZHUGRZQ
2SHUDWLQJPRGH
86%QRQ
IXQFWLRQDO
DUHD
Functional overview STM32F469xx
30/217 DocID028196 Rev 4
2.19 Power supply supervisor
2.19.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.19.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON must be
connected to VSS, as shown in Figure 8.
Figure 8. Power supply supervisor interconnection with internal reset OFF
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 9).
A comprehensive set of power-saving mode allows to design low-power applications.
3'5B21
670)[[
966
3'5QRWDFWLYH99''9
9%$7
9''
$SSOLFDWLRQUHVHW
VLJQDORSWLRQDO
069
DocID028196 Rev 4 31/217
STM32F469xx Functional overview
46
When the internal reset is OFF, the following integrated features are no more supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•The brownout reset (BOR) circuitry must be disabled
•The embedded programmable voltage detector (PVD) is disabled
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages allow to disable the internal reset through the PDR_ON signal when connected
to VSS.
Figure 9. PDR_ON co n trol with internal reset OFF
1. PDR_ON signal to be kept always low.
2.20 Voltage regulator
The regulator has four operating modes:
•Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
•Regulator OFF
2.20.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
069
9''
WLPH
3'5 9
WLPH
1567
3'5B21 3'5B21
5HVHWE\RWKHUVRXUFHWKDQ
SRZHUVXSSO\VXSHUYLVRU
Functional overview STM32F469xx
32/217 DocID028196 Rev 4
There are three power modes configured by software when the regulator is ON:
•MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in under-drive mode (reduced leakage mode).
•Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Section 2.18 and Table 124.
All packages have the regulator ON feature.
2.20.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Table 3. Voltage regulator configuratio n mode versus device operating mode(1)
1. ‘-’ means that the corresponding configuration is not available.
V oltage regulator
configuration Run mode Sleep mode Stop mode Standby mode
Normal mode MR MR MR or LPR -
Over-drive
mode(2)
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
MR MR - -
Under-drive mode - - MR or LPR -
Power-down
mode ---Yes
DocID028196 Rev 4 33/217
STM32F469xx Functional overview
46
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Operating conditions.The two
2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer
to Section 2.18.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•The over-drive and under-drive modes are not available.
•The Standby mode is not available.
Figure 10. Regulator OFF
The following conditions must be respected:
•VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
•If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 11).
•Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 12).
•If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application
(see Operating conditions).
DL9
%<3$66B5(*
9&$3B
9&$3B
3$
9
9'' 1567
9''
$SSOLFDWLRQUHVHW
VLJQDORSWLRQDO
([WHUQDO9&$3BSRZHU
VXSSO\VXSHUYLVRU
([WUHVHWFRQWUROOHUDFWLYH
ZKHQ9&$3B0LQ9
9
Functional overview STM32F469xx
34/217 DocID028196 Rev 4
Figure 11. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
DLJ
9''
WLPH
0LQ9
3'5 RU9 9&$3B9&$3B
9
1567
WLPH
3$
9''
WLPH
0LQ9
9&$3B9&$3B
9
3$
1567
WLPH DLI
3'5 RU9
DocID028196 Rev 4 35/217
STM32F469xx Functional overview
46
2.20.3 Regulator ON/OFF and internal reset ON/OFF availability
2.21 Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
•The real-time clock (RTC)
•4 Kbytes of backup SRAM
•20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.22). It can be enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.22).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF
WLCSP168
UFBGA169
LQFP144
LQFP208
Yes No
Yes
PDR_ON set to VDD
Yes
PDR_ON set to VSS
LQFP176
UFBGA176
TFBGA216
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
LQFP100 Yes No Yes No
Functional overview STM32F469xx
36/217 DocID028196 Rev 4
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
2.22 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•Stop mo de
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5):
– Normal mode (default mode when MR or LPR is enabled)
– Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
•Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
2.23 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
Table 5. Voltage regulator modes in stop mode
Voltage regulator
configuration Main regulator (MR) Low-power regulator (LPR)
Normal mode MR ON LPR ON
Under-drive mode MR in under-drive mode LPR in under-drive mode
DocID028196 Rev 4 37/217
STM32F469xx Functional overview
46
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is conne cte d to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.24 Ti mers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
Table 6. Timer featu re comparison
Timer
type Timer Counter
resolution Counter
type Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)(1)
Advanced
control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 Yes 90 180
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 No 45 90/180
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any integer
between 1
and 65536
Yes 4 No 45 90/180
TIM9 16-bit Up
Any integer
between 1
and 65536
No 2 No 90 180
TIM10
,
TIM11
16-bit Up
Any integer
between 1
and 65536
No 1 No 90 180
TIM12 16-bit Up
Any integer
between 1
and 65536
No 2 No 45 90/180
TIM13
,
TIM14
16-bit Up
Any integer
between 1
and 65536
No 1 No 45 90/180
Basic TIM6,
TIM7 16-bit Up
Any integer
between 1
and 65536
Yes 0 No 45 90/180
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the
RCC_DCKCFGR register.
Functional overview STM32F469xx
38/217 DocID028196 Rev 4
2.24.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•Input capture
•Output compare
•PWM generation (edge- or center-aligned modes)
•One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
2.24.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F46x devices
(see Table 6 for differences).
•TIM2, TIM3, TIM4, TIM5
The STM32F46x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down
counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-
reload up/down counter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
2.24.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
DocID028196 Rev 4 39/217
STM32F469xx Functional overview
46
2.24.4 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
2.24.5 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.24.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•A 24-bit downcounter
•Autoreload capability
•Maskable system interrupt generation when the counter reaches 0
•Programmable clock source.
2.25 Inter-integrated circuit interface (I2C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).
2.26 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
Table 7. Comparison of I2C analog and digital filters
Filter Analog Digital
Pulse width of suppressed spikes ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks
Functional overview STM32F469xx
40/217 DocID028196 Rev 4
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
2.27 Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
Table 8. USART feature comparison(1)
Name Standard
features Modem
(RTS/CTS) LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud rate in Mbit/s APB
mapping
Oversampling
by 16 Oversampling
by 8
USART1 X X X X X X 5.62 11.25
APB2
(max.
90 MHz)
USART2 X X X X X X 2.81 5.62
APB1
(max.
45 MHz)
USART3 X X X X X X 2.81 5.62
APB1
(max.
45 MHz)
UART4 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
UART5 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
USART6 X X X X X X 5.62 11.25
APB2
(max.
90 MHz)
UART7 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
UART8 X - X - X - 2.81 5.62
APB1
(max.
45 MHz)
1. X = feature supported.
DocID028196 Rev 4 41/217
STM32F469xx Functional overview
46
2.28 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note: For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
2.29 Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
2.30 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
2.31 Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
Functional overview STM32F469xx
42/217 DocID028196 Rev 4
2.32 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
•Supports 10 and 100 Mbit/s rates
•Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F4xx reference manual for details)
•Tagged MAC frame support (VLAN support)
•Half-duplex (CSMA/CD) and full-duplex operation
•MAC control sublayer (control frames) support
•32-bit CRC generation and removal
•Several address filtering modes for physical and multicast address (multicast and
group addresses)
•32-bit status code for each transmitted or received frame
•Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•Triggers interrupt when system time becomes greater than target time
2.34 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
DocID028196 Rev 4 43/217
STM32F469xx Functional overview
46
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
2.35 Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing
•Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
•12 host channels with periodic OUT support
•Software configurable to OTG1.3 and OTG2.0 modes of operation
•USB 2.0 LPM (Link Power Management) support
•Internal FS OTG PHY support
•HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.36 Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
Functional overview STM32F469xx
44/217 DocID028196 Rev 4
The major features are:
•Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing
•Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•8 bidirectional endpoints
•16 host channels with periodic OUT support
•Software configurable to OTG1.3 and OTG2.0 modes of operation
•USB 2.0 LPM (Link Power Management) support
•Internal FS OTG PHY support
•External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•Internal USB DMA
•HNP/SNP/IP inside (no need for any external resistor)
•for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.37 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
•Programmable polarity for the input pixel clock and synchronization signals
•Parallel data communication can be 8-, 10-, 12- or 14-bit
•Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•Supports continuous mode or snapshot (a single frame) mode
•Capability to automatically crop the image black & white.
2.38 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
2.39 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
DocID028196 Rev 4 45/217
STM32F469xx Functional overview
46
2.40 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•Simultaneous sample and hold
•Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
2.41 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT
, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.42 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•two DAC converters: one for each output channel
•8-bit or 10-bit monotonic output
•left or right data alignment in 12-bit mode
•synchronized update capability
•noise-wave generation
•triangular-wave generation
•dual DAC channel independent or simultaneous conversions
•DMA capability for each channel
•external triggers for conversion
•input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
Functional overview STM32F469xx
46/217 DocID028196 Rev 4
2.43 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.44 Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F46x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID028196 Rev 4 47/217
STM32F469xx Pinouts and pin description
82
3 Pinouts and pin description
Figure 13. STM32F46x LQFP100 pinout
1. The above figure shows the package top view.
069
/4)3
3+
3&
3&
3&
3&
966$
95()
9''$
3$
3$
3$
3$
966
9''
3$
3+
1567
3&
3&
9''
3(
966
9%$7
3&
966
3$
3$
3%
3(
3(
3$
3%
3(
3(
3%
3%
3(
3(
9&$3
3%
3(
3(
966
3%
3%
3(
3%
9''
3%
3'
3&
'6,+267B'1
'6,+267B'3
9'''6,
'6,+267B&.1
'6,+267B&.3
966'6,
'6,+267B'1
'6,+267B'3
9&$3'6,
9'''6,
3'
3'
3'
3'
3&
9''86%
3$
3$
3&
3$
3$
3$
3$
3&
9''
3%
3%
3%
3'
3%
%227
3%
3'
3'
3%
3%
3'
3&
3$
3'
3'
3&
3$
9''
3'
3'
3&
966
9&$3
Pinouts and pin description STM32F469xx
48/217 DocID028196 Rev 4
Figure 14. STM32F46x LQFP144 pinout
1. The above figure shows the package top view.
069
/4)3
3&
3&
3&
9''
966$
95()
9''$
3$
3$
3$
3$
966
9''
3$
3$
1567
3&
966
3)
3+
3)
3)
9''
3+
3$
3&
3%
3)
3)
3&
3%
9''
3*
3(
3%
3)
3(
966
3(
3)
3)
9''
3(
3(
3*
3(
3(
3(
3'
'6,+267B'3
'6,+267B&.1
'6,+267B&.3
966'6,
'6,+267B'1
'6,+267B'3
9&$3'6,
9'''6,
3'
3'
9''
966
3'
3'
3'
'6,+267B'1
9'''6,
3*
3*
3*
9''86%
3*
3*
3*
3*
3(
9''
3(
%227
3%
3'5B21
3(
3%
3*
3*
3%
3%
9''
3*
3'
3%
3%
3*
9''
3'
3%
966
3*
966
3'
3'
3'
3'
3'
3&
3&
3&
3$
3$
9''
966
9&$3
3$
3$
3$
3$
3$
3&
3&
3&
3&
3$
3%
3%
3'
3%
3%
9&$3
3%
9''
3(
3%
3$
3)
3)
3&
3&
3)
3(
9%$7
3&
3)
3(
3(
3(
DocID028196 Rev 4 49/217
STM32F469xx Pinouts and pin description
82
Figure 15. STM32F46x WLCSP168 pinout
1. The above figure shows the package bottom view.
06Y9
3, 9'' 3( 3% 3% 9'' 3* 3' 966 3' 3$ 3,
3(
$
%
&
'
(
)
*
+
-
.
/
0
1
3
3, 966 3% 3% 966 3* 9'' 3' 3& 3, 3+
9%$7 3( 3, 3( 3% 3* 3' 3' 3& 3, 9'' 966
3& 3( 3, 3'5B
21 3* 3* 3' 3& 3$ 3+ 9&$3 3$
3& 3& 3( 3% 3* 3' 3' 3, 3+ 3$ 3$ 3$
966 3, 3, 3( %227 3$ 3$ 3& 3& 3& 966 9''
86%
3) 9'' 3) 3, 3% 3& 3* 3* 3* 3* 3* 3*
3) 3) 3) 1567 3) 966 3* 3% 3'
'6,
+267
B'3
'6,
+267
B'1
966
'6,
9'' 966 3) 3& 3$ 3) 3* 3( 3'
'6,
+267
B'1
'6,
+267
B&.1
'6,
+267
B&.3
3+ 3+ 3) 3$ 3+ 3) 3( 3% 3%
'6,
+267
B'3
9''
'6,
9&$3
'6,
3& 966$ 3$ 3$ 3$ 3) 3( 3+ 3' 3' 3' 9''
'6,
9''$ 3+ 3+ 3$ 3) 3( 3( 3+ 3+ 3' 3' 966
3+ 966 3$ 3% 966 3( 3( 9&$3 3+ 3% 3'
3%
9'' 3$ 3% 3% 9'' 3* 3( 3( 966 9'' 3+ 3%
Pinouts and pin description STM32F469xx
50/217 DocID028196 Rev 4
Figure 16. STM32F46x UFBGA16 9 ballout
1. The above figure shows the package top view.
06Y9
3, 3$
$3, %227 3* 3&3* 3' 3$3( 3( 3$ 3$
3, 3,
%3( 3% 3' 3&3* 3' 3$,3, 3% 3$ 3,
3( 3+
&3( 3% 3' 3'3' 3' 3&
3'5B
21 3% 3, 3+
3( 3*
'3( 3% 3' 3+3% 3$ 9''9'' 3% 966 9&$3
3& 3*
(3, 9%$7 3* 3$3* 3$ 3&966 3, 3* 3*
3& 3*
)3, 966 9'' 3&3* 966 3&3) 9'' 3* 3*
3+
'6,
+267B
'1
*3+ 3) 966 9663( 9'' 3&3) 3& 9''
86%
'6,
+267B
'3
'6,B
+267
&.1
+1567 3) 3( 3+3( 3+ 3+
3) 3) 966'6,
'6,
+267B
&.3
3)
966
'6,
+267B
'1
966$ 3$ 966 3+966 3( 9669''$ 9'' 9''
'6,
'6,
+267B
'3
3$ 9''
'6,
.3$ 3% 3( 3+9'' 3( 9''3$ 3$ 966'6, 9&$3
'6,
3+ 3'
/3+ 3% 3( 9''9'' 3( 3'3+ 3) 3' 3'
3& 3%
13$ 3) 3( 9&$33* 3% 3%3$ 3% 3% 3%
3& 3'
03+ 3) 3* 9663) 3% 3'3$ 3) 3' 3'
-
DocID028196 Rev 4 51/217
STM32F469xx Pinouts and pin description
82
Figure 17. STM32F46x UFBGA176 ballout
1. The above figure shows the package top view.
069
$3(3(
3( 3 ( 3 % 3% 3* 3* 3% 3% 3' 3& 3$ 3$ 3$
%3(3(
3( 3% 3% 3% 3* 3* 3* 3* 3' 3' 3& 3& 3$
&9%$7 3, 3, 3, 3'5
B21 3* 3' 3' 3, 1&
'3& 3, 3, 3, %227 966 966 966 3' 3' 3' 3, 3$
(3& 3 ) 3, 3,
'6,
+267B
'3
3, 3$
)3&
966 9'' 3+ 9 66 9&$3 3 & 3$
*3+ 966 9'' 3+ 966 9'' 3& 3&
+3+ 3) 3) 3+ 966
'6,
9''B
86% 3* 3&
-1567 3) 3+ 3* 3*
.3) 3)
3)
9'' 966 3* 3* 3*
/3) %<3$66
B5(* 3*
0966$3&
3)
3& 3 & 3 & 3% 3* 9&$3
B 3+ 3'
195() 3$ 3$ 3& 3) 3 * 9 '' 9 '' 9 '' 3 + 3 ' 3 ' 3 '
33 $ 3$ 3 $ 3& 3) 3) 3( 3( 3( 3% 3% 3' 3'
53$ 3% 3) 3( 3( 3 % 3 % 3 %
966
3$
9''
'6,
'6,
+267B
'1
9''
'6,
9&$3
'6,
'6,
+267B
&.3
'6,
+267B
'3
'6,
+267B
'1
'6,
+267B
&.1
9''
9'' 9'' 9''
95()
9''$ 3$ 3% 3) 3(
966 966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966966966 966 966
966 966
3)
3)
3'
3'
9'' 3$
3(
3(
3( 3%
Pinouts and pin description STM32F469xx
52/217 DocID028196 Rev 4
Figure 18. STM32F46x LQFP176 pinout
1. The above figure shows the package top view.
069
3'5B21
9''
3(
3(
3%
3%
%227
3%
3%
3%
3%
3%
3*
9''
966
3*
3*
3*
3*
3*
3*
3'
3'
9''
966
3'
3'
3'
3'
3'
3'
3&
3&
3&
3,
3,
3(
3$
3(
3$
3(
3(
3$
3(
3$
9%$7
3&
3,
3&
3&
3&
3&
3&
3)
9''86%
3)
966
3)
3*
3)
3*
3)
3*
3)
3*
3*
3*
3)
3*
3)
966'6,
3)
'6,+267B'1
3)
'6,+267B'3
3)
9'''6,
3+
'6,+267B&.1
3+
'6,+267B&.3
1567
966'6,
3&
'6,+267B'1
3&
'6,+267B'3
3&
9&$3'6,
3&
9'''6,
3'
3'
95()
9''
966
3$
3'
3$
3'
3$
3'
3$
%<3$66B5(*
9''
3$
3$
3$
3$
3&
3&
3%
3%
3%
3)
3)
966
3)
3)
3)
3*
3*
3(
3(
3(
3(
3(
3(
3(
3(
3(
3%
3%
9&$3B
/4)3
3$
3,
3$
3$
9''
966
3,
3,
3,
3+
3+
3+
3+
3%
3%
3%
3%
3,
9''
966
9&$3
3$
3'
3'
3'
3&
3,
3,
3,
966
3+
3+
9''
966
9''
9''
966$
9''$
9''
966
9''
9''
DocID028196 Rev 4 53/217
STM32F469xx Pinouts and pin description
82
Figure 19. STM32F46x LQFP208 pinout
1. The above figure shows the package top view.
06Y9
/4)3
3,
3,
3,
3,
9''
3'5B21
966
3(
3(
3%
3%
%227
3%
3%
3%
3%
3%
3*
3.
3.
3.
3.
3.
9''
966
3*
3*
3*
3*
3*
3*
3-
3-
3-
3-
3'
3'
9''
966
3'
3'
3'
3'
3'
3'
3&
3&
3&
3$
3$
9''
3,
3( 3,
3( 3,
3( 3,
3( 3+
3( 3+
9%$7 3+
3, 9''
3& 966
3& 9&$3
3& 3$
3, 3$
3, 3$
3, 3$
966 3$
9'' 3$
3) 3&
3) 3&
3) 3&
3, 3&
3, 9''86%
3, 966
3) 3*
3) 3*
3) 3*
966 3*
9'' 3*
3) 3*
3) 3*
3) 966'6,
3) '6,+267B'1
3) '6,+267B'3
3+ 9'''6,
3+ '6,+267B&.1
1567 '6,+267B&.3
3& 966'6,
3& '6,+267B'1
3& '6,+267B'3
3& 9&$3'6,
9'' 9'''6,
966$ 3'
95() 3'
9''$ 9''
3$ 966
3$ 3'
3$ 3'
3+ 3'
3+ 3'
3+ 3'
3+ 3'
3$ 3%
966 3%
9'' 3%
3$
3$
3$
3$
3&
3&
9''
966
3%
3%
3%
3,
3-
3-
3-
3-
3-
3)
3)
966
9''
3)
3)
3)
3*
3*
3(
3(
3(
966
9''
3(
3(
3(
3(
3(
3(
3%
3%
9&$3
966
9''
3-
3+
3+
3+
3+
3+
3+
3+
9''
3%
Pinouts and pin description STM32F469xx
54/217 DocID028196 Rev 4
Figure 20. STM32F46x TFBGA216 ballout
1. The above figure shows the package top view.
06Y9
$3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$
%3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$
&9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3, 3, 3$
'3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$
(3& 3) 3, 3, %227 9'' 9'' 9'' 9'' 9&$3 3+ 3+ 3, 3$
)3& 966 3, 9'' 3& 3$
*3+ 3) 3, 3, 9'' 3& 3&
+3+ 3, 3+ 966 3* 3&
-1567 3) 3+ 3+ 966 9'' 3* 3*
.3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3' 3% 3'
/3) 3& %<3$66
5(* 3% 3' 3'
0966$ 3* 3' 3' 3* 3* 3- 3+
195() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+
95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+
3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3%
3)
3
59''$
9''
'6,
'6,
+267B
&.3
9'''
86%
966
'6,
9''
'6,
'6,
+267B
&.1
'6,
+267B
'3
3'5
21
9&$3
'6,
'6,
+267B
'1
'6,
+267B
'3
'6,
+267B
'1
3( 3( 3(
9''
9''
966
966
966
966 966 966 966 966
966
9''
3-3)
9'' 9'' 9'' 9&$3 3'
9''
3)
3)
3& 3& 3& 3% 3)
9''
966
3'
DocID028196 Rev 4 55/217
STM32F469xx Pinouts and pin description
82
Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to analog parts
B Dedicated BOOT0 pin
RST Bidirectional reset pin with weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Pinouts and pin description STM32F469xx
56/217 DocID028196 Rev 4
Table 10. STM32F469xx pin and ball definitions
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
1 144 B2 F9 A2 1 1 A3 PE2 I/O FT -
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
ETH_MII_TXD3, FMC_A23,
EVENTOUT
-
NC
(2) 1 C1 E10 A1 2 2 A2 PE3 I/O FT - TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT -
NC
(2) 2 C2 C11 B1 3 3 A1 PE4 I/O FT -
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
-
NC
(2) 3 D1 B12 B2 4 4 B1 PE5 I/O FT -
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
NC
(2) 4 D2 D11 B3 5 5 B2 PE6 I/O FT -
TRACED3, TIM9_CH2,
SPI4_MOSI, SAI1_SD_A,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
-
2------G6 VSS S-- - -
-------F5 VDD S-- - -
3 5 E5 C12 C1 6 6 C1 VBAT S - - - -
- - - - D2 7 7 C2 PI8 I/O FT
(3)
(4) EVENTOUT
RTC_TAMP1/
RTC_TAMP2/
RTC_TS
4 6G4D12D18 8D1 PC13 I/OFT
(3)
(4) EVENTOUT
RTC_TAMP1/
RTC_TS/
RTC_OUT
5 7 E1 E11 E1 9 9 E1 PC14-OSC32_IN
(PC14) I/O FT
(3)
(4) EVENTOUT OSC32_IN
68F1E12F11010F1
PC15-
OSC32_OUT
(PC15)
I/O FT
(3)
(4) EVENTOUT OSC32_OUT
-------G5 VDD S-- - -
- - E2 G9 D3 11 11 E4 PI9 I/O FT CAN1_RX, FMC_D30,
LCD_VSYNC, EVENTOUT -
- - E4 F10 E3 12 12 D5 PI10 I/O FT
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
- - F2 F11 E4 13 13 F3 PI11 I/O FT
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
-
- - F5 F12 F2 14 14 F2 VSS S - - - -
--F4G11F31515F4 VDD S-- - -
DocID028196 Rev 4 57/217
STM32F469xx Pinouts and pin description
82
- 9 F3 G10 E2 16 16 D2 PF0 I/O FT I2C2_SDA, FMC_A0,
EVENTOUT -
- 10 G3 H10 H3 17 17 E2 PF1 I/O FT I2C2_SCL, FMC_A1,
EVENTOUT -
- 11 G5 G12 H2 18 18 G2 PF2 I/O FT I2C2_SMBA, FMC_A2,
EVENTOUT -
- - - - - - 19 E3 PI12 I/O FT LCD_HSYNC, EVENTOUT -
- - - - - - 20 G3 PI13 I/O FT LCD_VSYNC, EVENTOUT -
- - - - - - 21 H3 PI14 I/O FT LCD_CLK, EVENTOUT -
- 12 H4 H11 J2 19 22 H2 PF3 I/O FT (5) FMC_A3, EVENTOUT ADC3_IN9
- 13 L4 J10 J3 20 23 J2 PF4 I/O FT (5) FMC_A4, EVENTOUT ADC3_IN14
- 14 H3 H12 K3 21 24 K3 PF5 I/O FT (5) FMC_A5, EVENTOUT ADC3_IN15
7 15 G7 J11 G2 22 25 H6 VSS S - - - -
8 16 G8 J12 G3 23 26 H5 VDD S - - - -
- - - - K2 24 27 K2 PF6 I/O FT (5)
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_Rx,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
- - - - K1 25 28 K1 PF7 I/O FT (5)
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_Tx,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_IN5
- - - - L3 26 29 L3 PF8 I/O FT (5)
SPI5_MISO, SAI1_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_IN6
- - - - L2 27 30 L2 PF9 I/O FT (5)
SPI5_MOSI, SAI1_FS_B,
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_IN7
- 17 H1 K10 L1 28 31 L1 PF10 I/O FT (5)
QUADSPI_CLK,
DCMI_D11, LCD_DE,
EVENTOUT
ADC3_IN8
9 18 G2 K11 G1 29 32 G1 PH0-OSC_IN
(PH0) I/O FT - EVENTOUT OSC_IN
10 19 G1 K12 H1 30 33 H1 PH1-OSC_OUT
(PH1) I/O FT - EVENTOUT OSC_OUT
11 20 H2 H9 J1 31 34 J1 NRST I/O RST -
12 21 M1 J9 M2 32 35 M2 PC0 I/O FT (5)
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
IN10
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
58/217 DocID028196 Rev 4
13 22 N1 L12 M3 33 36 M3 PC1 I/O FT (5)
TRACED0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, ETH_MDC,
EVENTOUT
ADC123_
IN11
14 23 - - M4 34 37 M4 PC2 I/O FT (5)
SPI2_MISO, I2S2ext_SD,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT
ADC123_
IN12
15 24 - - M5 35 38 L4 PC3 I/O FT (5)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC123_
IN13
- 25 - - - 36 39 J5 VDD S - - - -
-------J6 VSS S-- - -
16 26 J2 L11 M1 37 40 M1 VSSA S - - - -
----N1--N1 VREF- S-- - -
17 27 - - P1 38 41 P1 VREF+ S - - - -
18 28 J3 M12 R1 39 42 R1 VDDA S - - - -
19 29 J5 L10 N3 40 43 N3 PA0-WKUP(PA0) I/O FT (6)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS, UART4_TX,
ETH_MII_CRS,
EVENTOUT
ADC123_IN0,
WKUP
20 30 K1 K9 N2 41 44 N2 PA1 I/O FT (5)
TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
QUADSPI_BK1_IO3,
ETH_MII_RX_CLK/ETH_R
MII_REF_CLK, LCD_R2,
EVENTOUT
ADC123_IN1
21 31 K2 L9 P2 42 45 P2 PA2 I/O FT (5)
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
ETH_MDIO, LCD_R1,
EVENTOUT
ADC123_IN2
- - L2 M11 F4 43 46 K4 PH2 I/O FT -
QUADSPI_BK2_IO0,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
- - L1 N12 G4 44 47 J4 PH3 I/O FT -
QUADSPI_BK2_IO1,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
-
- - M2 M10 H4 45 48 H4 PH4 I/O FT -
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID028196 Rev 4 59/217
STM32F469xx Pinouts and pin description
82
- - L3 K8 J4 46 49 J3 PH5 I/O FT - I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT -
22 32 K3 N10 R2 47 50 R2 PA3 I/O FT (5)
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC123_IN3
23 33 J1 N11 - - 51 K6 VSS S - - - -
- - - - L4 48 - L5 BYPASS_REG I FT - - -
24 34 J4 P12 K4 49 52 K5 VDD S - - - -
25 35 N2 M9 N4 50 53 N4 PA4 I/O TTa -
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
ADC12_IN4,
DAC_OUT1
26 36 M3 L8 P4 51 54 P4 PA5 I/O TTa -
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SPI1_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_IN5,
DAC_OUT2
27 37 N3 P11 P3 52 55 P3 PA6 I/O FT (5)
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM13_CH1,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_IN6
28 38 K4 J8 R3 53 56 R3 PA7 I/O FT (5)
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SPI1_MOSI,
TIM14_CH1,
QUADSPI_CLK,
ETH_MII_RX_DV/ETH_RMI
I_CRS_DV, FMC_SDNWE,
EVENTOUT
ADC12_IN7
NC
(2) 39 - - N5 54 57 N5 PC4 I/O FT (5)
ETH_MII_RXD0/ETH_RMII
_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_IN14
NC
(2) 40 - - P5 55 58 P5 PC5 I/O FT (5)
ETH_MII_RXD1/ETH_RMII
_RXD1, FMC_SDCKE0,
EVENTOUT
ADC12_IN15
------59L7 VDD S-- - -
------60L6 VSS S-- - -
29 41 N4 P10 R5 56 61 R5 PB0 I/O FT (5)
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT
ADC12_IN8
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
60/217 DocID028196 Rev 4
30 42 K5 N9 R4 57 62 R4 PB1 I/O FT (5)
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
ADC12_IN9
31 43 L5 P9 M6 58 63 M5 PB2-
BOOT1(PB2) I/O FT - EVENTOUT -
- - - - - - 64 G4 PI15 I/O FT - LCD_G2, LCD_R0,
EVENTOUT -
------65R6 PJ0 I/OFT- LCD_R7, LCD_R1,
EVENTOUT -
- - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -
------67P7 PJ2 I/OFT-
DSIHOST_TE, LCD_R3,
EVENTOUT -
- - - - - - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT -
- 44M5K7R65970P8 PF11 I/OFT -
SPI5_MOSI,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
- 45 N5 M8 P6 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT -
- - J6 N8 M8 61 72 K7 VSS S - - - -
- 46K6P8N86273L8 VDD S - - - -
- 47M4J7N66374N6 PF13 I/OFT - FMC_A7, EVENTOUT -
- 48H5L7R76475P6 PF14 I/OFT - FMC_A8, EVENTOUT -
- 49M6H8P76576M8 PF15 I/OFT - FMC_A9, EVENTOUT -
- 50N6J6N76677N7 PG0 I/OFT - FMC_A10, EVENTOUT -
- 51M7P7M76778M7 PG1 I/OFT - FMC_A11, EVENTOUT -
32 52 N7 N7 R8 68 79 R8 PE7 I/O FT -
TIM1_ETR, UART7_Rx,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
33 53 G6 M7 P8 69 80 N9 PE8 I/O FT -
TIM1_CH1N, UART7_Tx,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
-
34 54 H6 K6 P9 70 81 P9 PE9 I/O FT -
TIM1_CH1,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
-
- 55 J7 - M9 71 82 K8 VSS S - - - -
- 56 L6 - N9 72 83 L9 VDD S - - - -
35 57 H7 P6 R9 73 84 R9 PE10 I/O FT -
TIM1_CH2N,
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID028196 Rev 4 61/217
STM32F469xx Pinouts and pin description
82
36 58 K7 N6 P10 74 85 P10 PE11 I/O FT -
TIM1_CH2, SPI4_NSS,
FMC_D8, LCD_G3,
EVENTOUT
-
37 59 L7 M6 R10 75 86 R10 PE12 I/O FT -
TIM1_CH3N, SPI4_SCK,
FMC_D9, LCD_B4,
EVENTOUT
-
38 60 J8 L6 N11 76 87 R12 PE13 I/O FT -
TIM1_CH3, SPI4_MISO,
FMC_D10, LCD_DE,
EVENTOUT
-
39 61 K8 J5 P11 77 88 P11 PE14 I/O FT -
TIM1_CH4, SPI4_MOSI,
FMC_D11, LCD_CLK,
EVENTOUT
-
40 62 L8 P5 R11 78 89 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT -
41 63 M8 N5 R12 79 90 P12 PB10 I/O FT -
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT
-
42 64 N8 K5 R13 80 91 R13 PB11 I/O FT -
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RMI
I_TX_EN, DSIHOST_TE,
LCD_G5, EVENTOUT
-
43 65 N9 N4 M10 81 92 L11 VCAP1 S - - - -
44 - M9 P4 - - 93 K9 VSS S - - - -
45 66 L9 P3 N10 82 94 L10 VDD S - - - -
- - - - - - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT -
- - - - M11 83 96 P13 PH6 I/O FT -
I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
- - - - N12 84 97 N13 PH7 I/O FT -
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1, DCMI_D9,
EVENTOUT
-
- - H8 M5 - - 98 P14 PH8 I/O FT -
I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
- - H9 L5 - - 99 N14 PH9 I/O FT -
I2C3_SMBA, TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
62/217 DocID028196 Rev 4
- - J9 M4 - - 100 P15 PH10 I/O FT -
TIM5_CH1, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
-
- - K9 N3 - - 101 N15 PH11 I/O FT -
TIM5_CH2, FMC_D19,
DCMI_D2, LCD_R5,
EVENTOUT
-
- - H10 P2 - - 102 M15 PH12 I/O FT -
TIM5_CH3, FMC_D20,
DCMI_D3, LCD_R6,
EVENTOUT
-
---H7---K10 VSS S-- - -
-66----103K11 VDD S-- - -
46 67 N10 H5 P12 85 104 L13 PB12 I/O FT -
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII
_TXD0, OTG_HS_ID,
EVENTOUT
-
47 68 N11 K4 P13 86 105 K14 PB13 I/O FT -
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS, CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII
_TXD1, EVENTOUT
OTG_HS_
VBUS
48 69 N12 P1 R14 87 106 R14 PB14 I/O FT -
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO, I2S2ext_SD,
USART3_RTS,
TIM12_CH1, OTG_HS_DM,
EVENTOUT
-
49 70 N13 N2 R15 88 107 R15 PB15 I/O FT -
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2, OTG_HS_DP,
EVENTOUT
-
50 71 L10 L4 P15 89 108 L15 PD8 I/O FT - USART3_TX, FMC_D13,
EVENTOUT -
51 72 M10 N1 P14 90 109 L14 PD9 I/O FT - USART3_RX, FMC_D14,
EVENTOUT -
52 73 L11 M3 N15 91 110 K15 PD10 I/O FT - USART3_CK, FMC_D15,
LCD_B3, EVENTOUT -
- 74 M11 J4 N14 92 111 N10 PD11 I/O FT -
USART3_CTS,
QUADSPI_BK1_IO0,
FMC_A16/FMC_CLE,
EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID028196 Rev 4 63/217
STM32F469xx Pinouts and pin description
82
- 75 M13 M2 N13 93 112 M10 PD12 I/O FT -
TIM4_CH1, USART3_RTS,
QUADSPI_BK1_IO1,
FMC_A17/FMC_ALE,
EVENTOUT
-
- - M12 H4 M15 94 113 M11 PD13 I/O FT -
TIM4_CH2,
QUADSPI_BK1_IO3,
FMC_A18, EVENTOUT
-
- 76 J10 M1 - 95 114 J10 VSS S - - - -
- 77 K10 - J13 96 115 J11 VDD S - - - -
53 78 L12 L3 M14 97 116 L12 PD14 I/O FT - TIM4_CH3, FMC_D0,
EVENTOUT -
54 79 L13 L2 L14 98 117 K13 PD15 I/O FT - TIM4_CH4, FMC_D1,
EVENTOUT -
55 80 K13 L1 J12 99 118 H11 VDDDSI S - - - -
-------H10 VSS S-- - -
56 81 K12 K1 K12 100 119 K12 VCAPDSI S - - - -
- - - K2 D13 - - G13 VDD12DSI S - - - -
57 82 J12 K3 M12 101 120 J12 DSIHOST_D0P I/O - - - -
58 83 J13 J3 M13 102 121 J13 DSIHOST_D0N I/O - - - -
59 84 K11 H1 H12 103 122 G12 VSSDSI S - - - -
60 85 H12 J1 L12 104 123 H12 DSIHOST_CKP I/O - - - -
61 86 H13 J2 L13 105 124 H13 DSIHOST_CKN I/O - - - -
62 87 J11 - D13 106 125 - VDD12DSI S - - - -
63 88 G12 H3 E12 107 126 F12 DSIHOST_D1P I/O - - - -
64 89 G13 H2 E13 108 127 F13 DSIHOST_D1N I/O - - - -
- - H11 - H12 109 128 - VSSDSI S - - - -
- 90 F13 G5 L15 110 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT -
- 91 F12 G4 K15 111 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT -
- 92 E13 G2 K14 112 131 N12 PG4 I/O FT - FMC_A14/FMC_BA0,
EVENTOUT -
- 93 E12 G1 K13 113 132 N11 PG5 I/O FT - FMC_A15/FMC_BA1,
EVENTOUT -
- 94 F11 G3 J15 114 133 J15 PG6 I/O FT - DCMI_D12, LCD_R7,
EVENTOUT -
- 95 E11 H6 J14 115 134 J14 PG7 I/O FT -
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
64/217 DocID028196 Rev 4
- 96 D13 G6 H14 116 135 H14 PG8 I/O FT -
SPI6_NSS, USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
- - G9 F2 G12 117 136 G10 VSS S - - - -
65 97 G11 F1 H13 118 137 G11 VDDUSB S - - - -
66 98 F9 F3 H15 119 138 H15 PC6 I/O FT -
TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
SDIO_D6, DCMI_D0,
LCD_HSYNC, EVENTOUT
-
67 99 F10 G7 G15 120 139 G15 PC7 I/O FT -
TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
SDIO_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
68 100 E10 F4 G14 121 140 G14 PC8 I/O FT -
TRACED1, TIM3_CH3,
TIM8_CH3, USART6_CK,
SDIO_D0, DCMI_D2,
EVENTOUT
-
69 101 G10 F5 F14 122 141 F14 PC9 I/O FT -
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN,
QUADSPI_BK1_IO0,
SDIO_D1, DCMI_D3,
EVENTOUT
-
70 102 D8 E1 F15 123 142 F15 PA8 I/O FT -
MCO1, TIM1_CH1,
I2C3_SCL, USART1_CK,
OTG_FS_SOF, LCD_R6,
EVENTOUT
-
71 103 E8 E2 E15 124 143 E15 PA9 I/O FT -
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, DCMI_D0,
EVENTOUT
OTG_FS_
VBUS
72 104 E9 E3 D15 125 144 D15 PA10 I/O FT -
TIM1_CH3, USART1_RX,
OTG_FS_ID, DCMI_D1,
EVENTOUT
-
73 105 A13 F7 C15 126 145 C15 PA11 I/O FT -
TIM1_CH4, USART1_CTS,
CAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT
-
74 106 A12 F6 B15 127 146 B15 PA12 I/O FT -
TIM1_ETR, USART1_RTS,
CAN1_TX, OTG_FS_DP,
LCD_R5, EVENTOUT
-
75 107 A11 D1 A15 128 147 A15 PA13(JTMS-
SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT -
76 108 D12 D2 F13 129 148 E11 VCAP2 S - - - -
- 109 D11 C1 F12 130 149 F10 VSS S - - - -
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID028196 Rev 4 65/217
STM32F469xx Pinouts and pin description
82
77 110 D10 C2 G13 131 150 F11 VDD S - - - -
- - D9 B1 - - 151 E12 PH13 I/O FT -
TIM8_CH1N, CAN1_TX,
FMC_D21, LCD_G2,
EVENTOUT
-
- - C13 D3 - - 152 E13 PH14 I/O FT -
TIM8_CH2N, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
- - C12 E4 - - 153 D13 PH15 I/O FT -
TIM8_CH3N, FMC_D23,
DCMI_D11, LCD_G4,
EVENTOUT
-
- - B13 E5 E14 132 154 E14 PI0 I/O FT -
TIM5_CH4,
SPI2_NSS/I2S2_WS(7),
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
- - C11 C3 D14 133 155 D14 PI1 I/O FT -
SPI2_SCK/I2S2_CK(7),
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
--B12A1-
NC
(2) 156 C14 PI2 I/O FT -
TIM8_CH4, SPI2_MISO,
I2S2ext_SD, FMC_D26,
DCMI_D9, LCD_G7,
EVENTOUT
-
- - B10 B2 C13 134 157 C13 PI3 I/O FT -
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
-
78 - - - D9 135 - F9 VSS S - - - -
- - - B5 C9 136 158 E10 VDD S - - - -
79 111 A10 D4 A14 137 159 A14 PA14(JTCK-
SWCLK) I/O FT - JTCK-SWCLK, EVENTOUT -
80 112 B11 A2 A13 138 160 A13 PA15(JTDI) I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
EVENTOUT
-
81 113 C10 D5 B14 139 161 B14 PC10 I/O FT -
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDIO_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
82 114 B9 B3 B13 140 162 B13 PC11 I/O FT -
I2S3ext_SD, SPI3_MISO,
USART3_RX, UART4_RX,
QUADSPI_BK2_NCS,
SDIO_D3, DCMI_D4,
EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
66/217 DocID028196 Rev 4
83 115 A9 C4 A12 141 163 A12 PC12 I/O FT -
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDIO_CK, DCMI_D9,
EVENTOUT
-
84 116 C9 E6 B12 142 164 B12 PD0 I/O FT - CAN1_RX, FMC_D2,
EVENTOUT -
85 117 C7 A3 C12 143 165 C12 PD1 I/O FT - CAN1_TX, FMC_D3,
EVENTOUT -
86 118 B8 C5 D12 144 166 D12 PD2 I/O FT -
TRACED2, TIM3_ETR,
UART5_RX, SDIO_CMD,
DCMI_D11, EVENTOUT
-
87 119 C8 D6 D11 145 167 C11 PD3 I/O FT -
SPI2_SCK/I2S2_CK,
USART2_CTS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
-
88 120 C6 B4 D10 146 168 D11 PD4 I/O FT - USART2_RTS, FMC_NOE,
EVENTOUT -
89 121 B7 C6 C11 147 169 C10 PD5 I/O FT - USART2_TX, FMC_NWE,
EVENTOUT -
- 122 F8 A4 D8 148 170 F8 VSS S - - - -
- 123 F7 - C8 149 171 E9 VDD S - - - -
90 124 D7 E7 B11 150 172 B11 PD6 I/O FT -
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
-
91 - A8 A5 A11 151 173 A11 PD7 I/O FT - USART2_CK, FMC_NE1,
EVENTOUT -
------174B10 PJ12 I/OFT- LCD_G3, LCD_B0,
EVENTOUT -
- - - - - - 175 B9 PJ13 I/O FT - LCD_G4, LCD_B1,
EVENTOUT -
- - - - - - 176 C9 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - - - 177 D10 PJ15 I/O FT - LCD_B3, EVENTOUT -
- 125 E6 D7 C10 152 178 D9 PG9 I/O FT -
USART6_RX,
QUADSPI_BK2_IO2,
FMC_NE2/FMC_NCE,
DCMI_VSYNC, EVENTOUT
-
- 126 E7 C7 B10 153 179 C8 PG10 I/O FT -
LCD_G3, FMC_NE3,
DCMI_D2, LCD_B2,
EVENTOUT
-
- 127 B6 B6 B9 154 180 B8 PG11 I/O FT -
ETH_MII_TX_EN/ETH_RMI
I_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID028196 Rev 4 67/217
STM32F469xx Pinouts and pin description
82
- 128 A7 A6 B8 155 181 C7 PG12 I/O FT -
SPI6_MISO,
USART6_RTS, LCD_B4,
FMC_NE4, LCD_B1,
EVENTOUT
-
- - A6 E8 A8 156 182 B3 PG13 I/O FT -
TRACED0, SPI6_SCK,
USART6_CTS,
ETH_MII_TXD0/ETH_RMII
_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
- - - - A7 157 183 A4 PG14 I/O FT -
TRACED1, SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RMII
_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
- 129 - B7 D7 158 184 F7 VSS S - - - -
- 130 - A7 C7 159 185 E8 VDD S - - - -
- - - - - - 186 D8 PK3 I/O FT - LCD_B4, EVENTOUT -
- - - - - - 187 D7 PK4 I/O FT - LCD_B5, EVENTOUT -
- - - - - - 188 C6 PK5 I/O FT - LCD_B6, EVENTOUT -
- - - - - - 189 C5 PK6 I/O FT - LCD_B7, EVENTOUT -
- - - - - - 190 C4 PK7 I/O FT - LCD_DE, EVENTOUT -
- 131 F6 D8 B7 160 191 B7 PG15 I/O FT -
USART6_CTS,
FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
92 132 B5 A8 A10 161 192 A10 PB3(JTDO/TRA
CESWO) I/O FT -
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK/I2S3_CK,
EVENTOUT
-
93 133 D6 C8 A9 162 193 A9 PB4(NJTRST) I/O FT -
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
I2S3ext_SD, EVENTOUT
-
94 134 D5 B8 A6 163 194 A8 PB5 I/O FT -
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1, DCMI_D10,
LCD_G7, EVENTOUT
-
95 135 C5 G8 B6 164 195 B6 PB6 I/O FT -
TIM4_CH1, I2C1_SCL,
USART1_TX, CAN2_TX,
QUADSPI_BK1_NCS,
FMC_SDNE1, DCMI_D5,
EVENTOUT
-
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pinouts and pin description STM32F469xx
68/217 DocID028196 Rev 4
96 136 B4 A9 B5 165 196 B5 PB7 I/O FT -
TIM4_CH2, I2C1_SDA,
USART1_RX, FMC_NL,
DCMI_VSYNC, EVENTOUT
-
97 137 A5 F8 D6 166 197 E6 BOOT0 I B - - VPP
98 138 D4 B9 A5 167 198 A7 PB8 I/O FT -
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
ETH_MII_TXD3, SDIO_D4,
DCMI_D6, LCD_B6,
EVENTOUT
-
99 139 C4 E9 B4 168 199 B4 PB9 I/O FT -
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
CAN1_TX, SDIO_D5,
DCMI_D7, LCD_B7,
EVENTOUT
-
NC
(2) 140 A4 A10 A4 169 200 A6 PE0 I/O FT -
TIM4_ETR, UART8_Rx,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
NC
(2) 141 A3 C9 A3 170 201 A5 PE1 I/O FT - UART8_Tx, FMC_NBL1,
DCMI_D3, EVENTOUT -
- - E3 B10 D5 - 202 F6 VSS S - - - -
- 142 C3 D9 C6 171 203 E5 PDR_ON S - - - -
100 143 D3 A11 C5 172 204 E7 VDD S - - - -
- - B3 D10 D4 173 205 C3 PI4 I/O FT -
TIM8_BKIN, FMC_NBL2,
DCMI_D5, LCD_B4,
EVENTOUT
-
- - A2 C10 C4 174 206 D3 PI5 I/O FT -
TIM8_CH1, FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
-
- - A1 B11 C3 175 207 D6 PI6 I/O FT -
TIM8_CH2, FMC_D28,
DCMI_D6, LCD_B6,
EVENTOUT
-
- - B1 A12 C2 176 208 D4 PI7 I/O FT -
TIM8_CH3, FMC_D29,
DCMI_D7, LCD_B7,
EVENTOUT
-
1. Function availability depends on the chosen device.
2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to “0” in the
output data register to avoid extra current consumption in low power modes.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:
www.st.com.
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
Table 10. STM32F469xx pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions Additional
functions
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
DocID028196 Rev 4 69/217
STM32F469xx Pinouts and pin description
82
6. If the device is delivered in an WLCSP168, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active
low).
7. PI0 and PI1 cannot be used for I2S2 full-duplex mode.
Pinouts and pin description STM32F469xx
70/217 DocID028196 Rev 4
Table 11. FMC pin de fi n iti on
Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16 SDRAM
PF0 A0 - - A0
PF1 A1 - - A1
PF2 A2 - - A2
PF3 A3 - - A3
PF4 A4 - - A4
PF5 A5 - - A5
PF12 A6 - - A6
PF13 A7 - - A7
PF14 A8 - - A8
PF15 A9 - - A9
PG0 A10 - - A10
PG1 A11 - - A11
PG2 A12 - - A12
PG3 A13 - -
PG4 A14 - - BA0
PG5 A15 - - BA1
PD11 A16 A16 CLE -
PD12 A17 A17 ALE -
PD13 A18 A18 - -
PE3 A19 A19 - -
PE4 A20 A20 - -
PE5 A21 A21 - -
PE6 A22 A22 - -
PE2 A23 A23 - -
PG13 A24 A24 - -
PG14 A25 A25 - -
PD14 D0 DA0 D0 D0
PD15 D1 DA1 D1 D1
PD0 D2 DA2 D2 D2
PD1 D3 DA3 D3 D3
PE7 D4 DA4 D4 D4
PE8 D5 DA5 D5 D5
PE9 D6 DA6 D6 D6
PE10 D7 DA7 D7 D7
PE11 D8 DA8 D8 D8
DocID028196 Rev 4 71/217
STM32F469xx Pinouts and pin description
82
PE12 D9 DA9 D9 D9
PE13 D10 DA10 D10 D10
PE14 D11 DA11 D11 D11
PE15 D12 DA12 D12 D12
PD8 D13 DA13 D13 D13
PD9 D14 DA14 D14 D14
PD10 D15 DA15 D15 D15
PH8 D16 - - D16
PH9 D17 - - D17
PH10 D18 - - D18
PH11 D19 - - D19
PH12 D20 - - D20
PH13 D21 - - D21
PH14 D22 - - D22
PH15 D23 - - D23
PI0 D24 - - D24
PI1 D25 - - D25
PI2 D26 - - D26
PI3 D27 - - D27
PI6 D28 - - D28
PI7 D29 - - D29
PI9 D30 - - D30
PI10 D31 - - D31
PD7 NE1 NE1 - -
PG9 NE2 NE2 NCE -
PG10 NE3 NE3 - -
PG11 - - - -
PG12 NE4 NE4 - -
PD3 CLK CLK - -
PD4 NOE NOE NOE -
PD5 NWE NWE NWE -
PD6 NWAIT NWAIT NWAIT -
PB7 NADV NADV - -
PF6 - - - -
PF7 - - - -
Table 11. FMC pin definition (continued)
Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16 SDRAM
Pinouts and pin description STM32F469xx
72/217 DocID028196 Rev 4
PF8 - - - -
PF9 - - - -
PF10 - - - -
PG6 - - - -
PG7 - - INT -
PE0 NBL0 NBL0 - NBL0
PE1 NBL1 NBL1 - NBL1
PI4 NBL2 - - NBL2
PI5 NBL3 - - NBL3
PG8 - - - SDCLK
PC0 - - - SDNWE
PF11 - - - SDNRAS
PG15 - - - SDNCAS
PH2 - - - SDCKE0
PH3 - - - SDNE0
PH6 - - - SDNE1
PH7 - - - SDCKE1
PH5 - - - SDNWE
PC2 - - - SDNE0
PC3 - - - SDCKE0
PB5 - - - SDCKE1
PB6 - - - SDNE1
Table 11. FMC pin definition (continued)
Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16 SDRAM
STM32F469xx Pinouts and pin description
DocID028196 Rev 4 73/217
Table 12. Alternate function
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
Port
A
PA0 - TIM2_CH1/
TIM2_ETR TIM5_CH1 TIM8_ETR - - - USART2_
CTS
UART4_
TX - - ETH_MII_CRS - - - EVENT
OUT
PA1 -TIM2_CH2 TIM5_CH2 -- --
USART2_
RTS
UART4_
RX
QUADSPI_
BK1_IO3 -ETH_MII_RX_
CLK/ETH_RMI
I_REF_CLK
--
LCD_R2 EVENT
OUT
PA2 -TIM2_CH3 TIM5_CH3 TIM9_CH1 ---
USART2_T
X-- -
ETH_MDIO --
LCD_R1 EVENT
OUT
PA3 -TIM2_CH4 TIM5_CH4 TIM9_CH2 ---
USART2_
RX -LCD_B2 OTG_HS
_ULPI_D0 ETH_MII_COL --
LCD_B5 EVENT
OUT
PA4 -- - - -
SPI1_NSS SPI3_NSS/
I2S3_WS
USART2_
CK -- --OTG_HS_S
OF
DCMI_HS
YNC
LCD_VSY
NC
EVENT
OUT
PA5 -TIM2_CH1/
TIM2_ETR -TIM8_CH1
N-SPI1_SCK ----
OTG_HS
_ULPI_C
K
---LCD_R4
EVENT
OUT
PA6 -TIM1_BKIN TIM3_CH1 TIM8_BKI
N-SPI1_
MISO ---
TIM13_CH1 - --DCMI_PIX
CLK LCD_G2 EVENT
OUT
PA7 -TIM1_
CH1N TIM3_CH2 TIM8_CH1
N-SPI1_
MOSI ---
TIM14_CH1 QUADSPI
_CLK
ETH_MII_RX_
DV/ETH_RMII
_CRS_DV
FMC_SDN
WE --
EVENT
OUT
PA8 MCO1 TIM1_CH1 --
I2C3_SCL - -USART1_
CK --
OTG_FS_
SOF ---
LCD_R6 EVENT
OUT
PA9 -TIM1_CH2 --
I2C3_SMBA SPI2_SCK/I
2S2_CK -USART1_T
X-- - - -
DCMI_D0 -EVENT
OUT
PA10 -TIM1_CH3 -- - --
USART1_
RX --
OTG_FS_
ID --
DCMI_D1 -EVENT
OUT
PA11 -TIM1_CH4 -- - --
USART1_
CTS -CAN1_RX OTG_FS_
DM --
-LCD_R4
EVENT
OUT
PA12 -TIM1_ETR -- - --
USART1_
RTS -CAN1_TX OTG_FS_
DP --
-LCD_R5
EVENT
OUT
PA13 JTMS-
SWDIO ---------- - ---
EVENT
OUT
PA14 JTCK-
SWCLK ---------- - ---
EVENT
OUT
PA15 JTDI TIM2_CH1/
TIM2_ETR -- -SPI1_NSS
SPI3_NSS/
I2S3_WS -- - - - - - -
EVENT
‘OUT
Pinouts and pin description STM32F469xx
74/217 DocID028196 Rev 4
Port
B
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2
N- - - - - LCD_R3 OTG_HS
_ULPI_D1
ETH_MII_
RXD2 --LCD_G1
EVENT
OUT
PB1 -TIM1_CH3N TIM3_CH4 TIM8_CH3
N-----
LCD_R6 OTG_HS
_ULPI_D2
ETH_MII_
RXD3 --
LCD_G0 EVENT
OUT
PB2 -- - - - - - --- - - - --
EVENT
OUT
PB3
JTDO /
TRACES
WO
TIM2_CH2 --
SPI1_SCK SPI3_SCK/
I2S3_CK -- - - - - - -
EVENT
OUT
PB4 NJTRST -TIM3_CH1 --
SPI1_MISO SPI3_MIS
O
I2S3ext
_SD -- - - - - -
EVENT
OUT
PB5 --
TIM3_CH2 -I2C1_SMBA SPI1_MOSI SPI3_MOS
I/I2S3_SD -CAN2_RX OTG_HS
_ULPI_D7
ETH_PPS
OUT
FMC_
SDCKE1 DCMI_D10 LCD_G7 EVENT
OUT
PB6 --
TIM4_CH1 -I2C1_SCL --
USART1
_TX -CAN2_TX
QUADSPI
_BK1_NC
S
-FMC_
SDNE1 DCMI_D5 EVENT
OUT
PB7 --
TIM4_CH2 -I2C1_SDA --
USART1_
RX ----
FMC_NL DCMI_VS
YNC
EVENT
OUT
PB8 --
TIM4_CH3 TIM10_CH
1I2C1_SCL ----
CAN1_RX -ETH_MII_
TXD3 SDIO_D4 DCMI_D6 LCD_B6 EVENT
OUT
PB9 --
TIM4_CH4 TIM11_CH
1I2C1_SDA SPI2_NSS/I
2S2_WS ---
CAN1_TX --
SDIO_D5 DCMI_D7 LCD_B7 EVENT
OUT
PB10 -TIM2_CH3 --
I2C2_SCL SPI2_SCK/I
2S2_CK -USART3
_TX -QUADSPI_
BK1_NCS
OTG_HS
_ULPI_D3
ETH_MII_RX_
ER --LCD_G4
EVENT
OUT
PB11 -TIM2_CH4 --
I2C2_SDA -USART3
_RX -OTG_HS
_ULPI_D4
ETH_MII_TX_
EN/ETH_RMII
_TX_EN
-DSIHOST_
TE LCD_G5 EVENT
OUT
PB12 -TIM1_BKIN --
I2C2_SMBA SPI2_NSS/I
2S2_WS -USART3
_CK -CAN2_RX OTG_HS
_ULPI_D5
ETH_MII_TXD
0/ETH_RMII_T
XD0
OTG_HS_
ID --
EVENT
OUT
PB13 -TIM1_CH1N -- -
SPI2_SCK/I
2S2_CK -USART3
_CTS -CAN2_TX OTG_HS
_ULPI_D6
ETH_MII_TXD
1/ETH_RMII_T
XD1
---
EVENT
OUT
PB14 -TIM1_CH2N -TIM8_CH2
N-SPI2_MISO I2S2ext_S
D
USART3
_RTS -TIM12_CH1 --
OTG_HS_
‘DM --
EVENT
OUT
PB15 RTC
_REFIN TIM1_CH3N -TIM8_CH3
N-SPI2_MOSI
/I2S2_SD ---
TIM12_CH2 --
OTG_HS_
DP --
EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
STM32F469xx Pinouts and pin description
DocID028196 Rev 4 75/217
Port
C
PC0 - - - - - - - - - -
OTG_HS
_ULPI_ST
P
-FMC_SDN
WE -LCD_R5
EVENT
OUT
PC1 TRACE
D0 ----
SPI2_MOSI
/I2S2_SD
SAI1_SD_
A-- - ETH_MDC ---
EVENT
OUT
PC2 -- - - -
SPI2_MISO I2S2ext_S
D-- -
OTG_HS
_ULPI_DI
R
ETH_MII_TXD
2
FMC_SDN
E0 --
EVENT
OUT
PC3 -- - - -
SPI2_MOSI
/I2S2_SD ----
OTG_HS
_ULPI_N
XT
ETH_MII_TX_
CLK
FMC_SDC
KE0 --
EVENT
OUT
PC4 -- - - - - - --- -
ETH_MII_RXD
0/ETH_RMII_R
XD0
FMC_SDN
E0 --
EVENT
OUT
PC5 -- - - - - - --- -
ETH_MII_RXD
1/ETH_RMII_R
XD1
FMC_SDC
KE0 --
EVENT
OUT
PC6 --
TIM3_CH1 TIM8_CH1 - I2S2_MCK --
USART6
_TX -- -
SDIO_D6 DCMI_D0 LCD_HSY
NC
EVENT
OUT
PC7 --
TIM3_CH2 TIM8_CH2 --
I2S3_MCK -USART6
_RX -- -
SDIO_D7 DCMI_D1 LCD_G6 EVENT
OUT
PC8 TRACE
D1 -TIM3_CH3 TIM8_CH3 ----
USART6
_CK -- -
SDIO_D0 DCMI_D2 -EVENT
OUT
PC9 MCO2 -TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN ---
QUADSPI_
BK1_IO0 --
SDIO_D1 DCMI_D3 -EVENT
OUT
PC10 - -----
SPI3_SCK/
I2S3_CK
USART3_
TX
UART4_
TX
QUADSPI_
BK1_IO1 --
SDIO_D2 DCMI_D8 LCD_R2 EVENT
OUT
PC11 - ----
I2S3ext_SD SPI3_MIS
O
USART3_
RX
UART4_
RX
QUADSPI_
BK2_NCS --
SDIO_D3 DCMI_D4 -EVENT
OUT
PC12 TRACE
D3 ---- -SPI3_MOS
I/I2S3_SD
USART3_
CK
UART5_
TX -- -
SDIO_CK DCMI_D9 -EVENT
OUT
PC13 -- - - - - ---- - - - --
EVENT
OUT
PC14 -- - - - - ---- - - - --
EVENT
OUT
PC15 -- - - - - ---- - - - --
EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
Pinouts and pin description STM32F469xx
76/217 DocID028196 Rev 4
Port
D
PD0 - - - - - - - - - CAN1_RX - - FMC_D2 - - EVENT
OUT
PD1 -- - - - - ---
CAN1_TX --
FMC_D3 --
EVENT
OUT
PD2 TRACE
D2 -TIM3_ETR -- ---
UART5_
RX -- -
SDIO_CMD DCMI_D11 - EVENT
OUT
PD3 -- - - -
SPI2_SCK/I
2S2_CK -USART2_
CTS -- - -
FMC_CLK DCMI_D5 LCD_G7 EVENT
OUT
PD4 -- - - - - -
USART2_
RTS -- - -
FMC_NOE --
EVENT
OUT
PD5 -- - - - - -
USART2_T
X-- - -
FMC_NWE --
EVENT
OUT
PD6 -- - - -
SPI3_MOSI
/I2S3_SD
SAI1_SD_
A
USART2_
RX -- - -
FMC_NWAI
TDCMI_D10 LCD_B2 EVENT
OUT
PD7 -- - - - - -
USART2_
CK -- - -
FMC_NE1 --
EVENT
OUT
PD8 -- - - - - -
USART3_T
X-- - -
FMC_D13 --
EVENT
OUT
PD9 -- - - - - -
USART3_
RX -- - -
FMC_D14 --
EVENT
OUT
PD10 -- - - - - -
USART3_
CK -- - -
FMC_D15 -LCD_B3 EVENT
OUT
PD11 -- - - - - -
USART3_
CTS -QUADSPI_
BK1_IO0 --
FMC_A16/F
MC_CLE --
EVENT
OUT
PD12 --
TIM4_CH1 -- --
USART3_
RTS -QUADSPI_
BK1_IO1 --
FMC_A17/F
MC_ALE --
EVENT
OUT
PD13 --
TIM4_CH2 -- ----
QUADSPI_
BK1_IO3 --
FMC_A18 --
EVENT
OUT
PD14 --
TIM4_CH3 -- ----
---
FMC_D0 --
EVENT
OUT
PD15 --
TIM4_CH4 -- ----
---
FMC_D1 --
EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
STM32F469xx Pinouts and pin description
DocID028196 Rev 4 77/217
Port
E
PE0 - - TIM4_ETR - - - - - UART8_
Rx -- -FMC_NBL0DCMI_D2-
EVENT
OUT
PE1 -- - - - - --
UART8_
Tx -- -
FMC_NBL1 DCMI_D3 -EVENT
OUT
PE2 TRACE
CLK ----
SPI4_SCK SAI1_
MCLK_A --
QUADSPI_
BK1_IO2 -ETH_MII_TXD
3FMC_A23 --
EVENT
OUT
PE3 TRACE
D0 ---- -SAI1
_SD_B -- - - -
FMC_A19 --
EVENT
OUT
PE4 TRACE
D1 ----
SPI4_NSS SAI1
_FS_A -- - - -
FMC_A20 DCMI_D4 LCD_B0 EVENT
OUT
PE5 TRACE
D2 --
TIM9_CH1 -SPI4_MISO SAI1
_SCK_A -- - - -
FMC_A21 DCMI_D6 LCD_G0 EVENT
OUT
PE6 TRACE
D3 --
TIM9_CH2 -SPI4_MOSI SAI1
_SD_A -- - - -
FMC_A22 DCMI_D7 LCD_G1 EVENT
OUT
PE7 -TIM1_ETR -- - ---
UART7_
Rx -QUADSPI
_BK2_IO0 -FMC_D4 --
EVENT
OUT
PE8 -TIM1_CH1N -- - ---
UART7_
Tx -QUADSPI
_BK2_IO1 -FMC_D5 --
EVENT
OUT
PE9 -TIM1_CH1 -- - -----
QUADSPI
_BK2_IO2 -FMC_D6 --
EVENT
OUT
PE10 -TIM1_CH2N -- - -----
QUADSPI
_BK2_IO3 -FMC_D7 --
EVENT
OUT
PE11 -TIM1_CH2 -- -
SPI4_NSS ----- -
FMC_D8 -LCD_G3 EVENT
OUT
PE12 -TIM1_CH3N -- -
SPI4_SCK ----- -
FMC_D9 -LCD_B4 EVENT
OUT
PE13 -TIM1_CH3 -- -
SPI4_MISO ----- -
FMC_D10 -LCD_DE EVENT
OUT
PE14 -TIM1_CH4 -- -
SPI4_MOSI ----- -
FMC_D11 -LCD_CLK EVENT
OUT
PE15 -TIM1_BKIN -- - ------ -
FMC_D12 -LCD_R7 EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
Pinouts and pin description STM32F469xx
78/217 DocID028196 Rev 4
Port
F
PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 - - EVENT
OUT
PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 - - EVENT
OUT
PF2 - - - - I2C2_SMBA - - - - - - - FMC_A2 - - EVENT
OUT
PF3 - - - - - - - - - - - - FMC_A3 - - EVENT
OUT
PF4 - - - - - - - - - - - - FMC_A4 - - EVENT
OUT
PF5 - - - - - - - - - - - - FMC_A5 - - EVENT
OUT
PF6 - - - TIM10_CH
1-SPI5_NSS
SAI1_
SD_B -UART7_
Rx
QUADSPI_
BK1_IO3 -- ---
EVENT
OUT
PF7 - - - TIM11_CH
1-SPI5_SCK
SAI1_
MCLK_B -UART7_
Tx
QUADSPI_
BK1_IO2 -- ---
EVENT
OUT
PF8 - - - - - SPI5_MISO SAI1_
SCK_B - - TIM13_CH1 QUADSPI
_BK1_IO0 ----
EVENT
OUT
PF9 - - - - - SPI5_MOSI SAI1_
FS_B - - TIM14_CH1 QUADSPI
_BK1_IO1 ----
EVENT
OUT
PF10 - - - - - - - - - QUADSPI_
CLK - - DCMI_D11 LCD_DE EVENT
OUT
PF11 - - - - - SPI5_MOSI - - - - - - FMC_SDN
RAS DCMI_D12 - EVENT
OUT
PF12-- -- - - ----- -FMC_A6--
EVENT
OUT
PF13-- -- - - ----- -FMC_A7--
EVENT
OUT
PF14-- -- - - ----- -FMC_A8--
EVENT
OUT
PF15-- -- - - ----- -FMC_A9--
EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
STM32F469xx Pinouts and pin description
DocID028196 Rev 4 79/217
Port
G
PG0 - - - - - - - - - - - - FMC_A10 - - EVENT
OUT
PG1 - - - - - - - - - - - - FMC_A11 --
EVENT
OUT
PG2 - - - - - - - - - - - - FMC_A12 --
EVENT
OUT
PG3 - - - - - - - - - - - - FMC_A13 --
EVENT
OUT
PG4 - - - - - - - - - - - - FMC_A14/F
MC_BA0 --
EVENT
OUT
PG5 - - - - - - - - - - - - FMC_A15/F
MC_BA1 --
EVENT
OUT
PG6 - - - - - - - - - - - - DCMI_D12 LCD_R7 EVENT
OUT
PG7 - - - - - SAI1
_MCLK_A
USART6
_CK - - - FMC_INT DCMI_D13 LCD_CLK EVENT
OUT
PG8 - - - - - SPI6_NSS - - USART6
_RTS --
ETH_PPS_OU
T
FMC_SDCL
KLCD_G7 EVENT
OUT
PG9 - - - - - - - - USART6
_RX
QUADSPI_
BK2_IO2 --
FMC_NE2/
FMC_NCE
DCMI_VS
YNC
EVENT
OUT
PG10 - - - - - - - - LCD_G3 - - FMC_NE3 DCMI_D2 LCD_B2 EVENT
OUT
PG11 - - - - - - - - - - -
ETH_MII
_TX_EN /
ETH_RMII
_TX_EN
- DCMI_D3 LCD_B3 EVENT
OUT
PG12 - - - - - SPI6_MISO - - USART6
_RTS LCD_B4 - - FMC_NE4 - LCD_B1 EVENT
OUT
PG13 TRACE
D0 ----SPI6_SCK--
USART6
_CTS --
ETH_MII
_TXD0 /
ETH_RMII
_TXD0
FMC_A24 - LCD_R0 EVENT
OUT
PG14 TRACE
D1 ----SPI6_MOSI--
USART6
_TX
QUADSPI_
BK2_IO3 -
ETH_MII
_TXD1 /
ETH_RMII
_TXD1
FMC_A25 - LCD_B0 EVENT
OUT
PG15 - - - - - - - - USART6
_CTS -- -
FMC_
SDNCAS DCMI_D13 - EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
Pinouts and pin description STM32F469xx
80/217 DocID028196 Rev 4
Port
H
PH0 - - - - - - - - - - - - - - - EVENT
OUT
PH1 - - - - - - - - - - - - - - EVENT
OUT
PH2 - - - - - - - - - QUADSPI_
BK2_IO0 - ETH_MII_CRS FMC_SDC
KE0 -LCD_R0
EVENT
OUT
PH3 - - - - - - - - - QUADSPI_
BK2_IO1 - ETH_MII_COL FMC_SDN
E0 -LCD_R1
EVENT
OUT
PH4 - - - - I2C2_SCL - - - - LCD_G5
OTG_HS
_ULPI_N
XT
---LCD_G4
EVENT
OUT
PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_SDN
WE --
EVENT
OUT
PH6 - - - - I2C2_SMBA SPI5_SCK - - - TIM12_CH1 - ETH_MII_RXD
2
FMC_SDN
E1 --
EVENT
OUT
PH7 - - - - I2C3_SCL SPI5_MISO - - - - - ETH_MII_RXD
3
FMC_SDC
KE1 DCMI_D9 - EVENT
OUT
PH8 - - - - I2C3_SDA - - - - - - - FMC_D16 DCMI_HS
YNC LCD_R2 EVENT
OUT
PH9 - - - - I2C3_SMBA - - - - TIM12_CH2 - - FMC_D17 DCMI_D0 LCD_R3 EVENT
OUT
PH10 - - TIM5_CH1 - - - - - - - - - FMC_D18 DCMI_D1 LCD_R4 EVENT
OUT
PH11 - - TIM5_CH2 - - - - - - - - - FMC_D19 DCMI_D2 LCD_R5 EVENT
OUT
PH12 - - TIM5_CH3 - - - - - - - - - FMC_D20 DCMI_D3 LCD_R6 EVENT
OUT
PH13 - - - TIM8_CH1
N- - - - - CAN1_TX - - FMC_D21 - LCD_G2 EVENT
OUT
PH14 - - - TIM8_CH2
N- - - - - - - - FMC_D22 DCMI_D4 LCD_G3 EVENT
OUT
PH15 - - - TIM8_CH3
N- - - - - - - - FMC_D23 DCMI_D11 LCD_G4 EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
STM32F469xx Pinouts and pin description
DocID028196 Rev 4 81/217
Port I
PI0 - - TIM5_CH4 - - SPI2_NSS/I
2S2_WS - - - - - - FMC_D24 DCMI_D13 LCD_G5 EVENT
OUT
PI1 - - - - - SPI2_SCK/I
2S2_CK - - - - - - FMC_D25 DCMI_D8 LCD_G6 EVENT
OUT
PI2 - - - TIM8_CH4 - SPI2_MISO I2S2ext_S
D- - - - - FMC_D26 DCMI_D9 LCD_G7 EVENT
OUT
PI3 - - - TIM8_ETR - SPI2_MOSI
/I2S2_SD - - - - - - FMC_D27 DCMI_D10 EVENT
OUT
PI4 - - - TIM8_BKI
N- - - - - - - - FMC_NBL2 DCMI_D5 LCD_B4 EVENT
OUT
PI5 - - - TIM8_CH1 - - - - - - - - FMC_NBL3 DCMI_VS
YNC LCD_B5 EVENT
OUT
PI6 - - - TIM8_CH2 - - - - - - - - FMC_D28 DCMI_D6 LCD_B6 EVENT
OUT
PI7 - - - TIM8_CH3 - - - - - - - - FMC_D29 DCMI_D7 LCD_B7 EVENT
OUT
PI8 - - - - - - - - - - - - - - EVENT
OUT
PI9 - - - - - - - - - CAN1_RX - - FMC_D30 - LCD_VSY
NC
EVENT
OUT
PI10 - - - - - - - - - - - ETH_MII_RX_
ER FMC_D31 - LCD_HSY
NC
EVENT
OUT
PI11 - - - - - - - - - LCD_G6
OTG_HS
_ULPI
_DIR
----
EVENT
OUT
PI12 - - - - - - - - - - - - - - LCD_HSY
NC
EVENT
OUT
PI13 - - - - - - - - - - - - - - LCD_VSY
NC
EVENT
OUT
PI14 - - - - - - - - - - - - - - LCD_CLK EVENT
OUT
PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0 EVENT
‘OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
Pinouts and pin description STM32F469xx
82/217 DocID028196 Rev 4
Port
J
PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1 EVENT
OUT
PJ1 - - - - - - - - - - - - - - LCD_R2 EVENT
OUT
PJ2 - - - - - - - - - - - - - DSIHOST
_TE LCD_R3 EVENT
OUT
PJ3 - - - - - - - - - - - - - - LCD_R4 EVENT
OUT
PJ4 - - - - - - - - - - - - - - LCD_R5 EVENT
OUT
PJ5 - - - - - - - - - - - - - - LCD_R6 EVENT
OUT
PJ12 - - - - - - - - - LCD_G3 - - - - LCD_B0 EVENT
OUT
PJ13 - - - - - - - - - LCD_G4 - - - - LCD_B1 EVENT
OUT
PJ14 - - - - - - - - - - - - - - LCD_B2 EVENT
OUT
PJ15 - - - - - - - - - - - - - - LCD_B3 EVENT
OUT
Port
K
PK3 - - - - - - - - - - - - - - LCD_B4 EVENT
OUT
PK4 - - - - - - - - - - - - - - LCD_B5 EVENT
OUT
PK5 - - - - - - - - - - - - - - LCD_B6 EVENT
OUT
PK6 - - - - - - - - - - - - - - LCD_B7 EVENT
OUT
PK7 - - - - - - - - - - - - - - LCD_DE EVENT
OUT
Table 12. Alternate functio n (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS TIM1/2 TIM3/4/
5TIM8/9/
10/11 I2C1/2/3 SPI1/2/3
/4/5/6 SPI2/3/
SAI1
SPI2/3/
USART
1/2/3
USAR
T6/
UART
4/5/7/
8
CAN1/2/
TIM12/
13/14/
QUAD
SPI/LCD
QUAD
SPI/OT
G2_HS
/OTG1
_FS
ETH
FMC/
SDIO/
OTG2_
FS
DCMI/
DSI
HOST LCD SYS
DocID028196 Rev 4 83/217
STM32F469xx Memory mapping
87
4 Memory mapping
The memory map is shown in Figure 21.
Figure 21. Memory map
06Y9
0E\WH
%ORFN
&RUWH[
,QWHUQDO
SHULSKHUDOV
0E\WH
%ORFN
)0&
[
[)))))))
[
[)))))))
[
[)))))))
[
[)))))))
[
[)))))))
[$
[&)))))))
['
[')))))))
[(
[))))))))
5HVHUYHG
[[)))
[[))))
[[)))))))
[
5HVHUYHG
[)))
[[))))
[
5HVHUYHG [&[)))))))
$+% [[')))))))
$+%
[%))
[
65$0
.%DOLDVHGE\ELWEDQGLQJ [[))))
$3%
$3%
[))
[[))))
5HVHUYHG
[[)))))))
[))))
$+%
5HVHUYHG
)ODVKPHPRU\
[[)))))))
[)))[)))$)
[)))&[)))& )
[[)))))
[[))))))
[[)))))
6\VWHPPHPRU\
5HVHUYHG
5HVHUYHG
$OLDVHGWR)ODVKV\VWHP
PHPRU\RU65$0GHSHQGLQJ
RQWKH%227SLQV
[)))&[)))))))
[)))$[))))))
&&0GDWD5$0
.%GDWD65$0 [[))))
[[))(%)))
[))(&[))(& )
2SWLRQE\WHV
5HVHUYHG [))(&[))())))
[
&RUWH[0
LQWHUQDOSHULSKHUDO [([()))))
5HVHUYHG [([))))))))
0E\WH
%ORFN
)0&DQG
48$'63,
0E\WH
%ORFN
)0&EDQNDQG
48$'63,EDQN
0E\WH
%ORFN
)0&EDQNWR
48$'63,EDQN
0E\WH
%ORFN
3HULSKHUDOV
0E\WH
%ORFN
65$0
0E\WH
%ORFN
65$0
65$0
.%DOLDVHGE\ELWEDQGLQJ
65$0
.%DOLDVHGE\ELWEDQGLQJ
5HVHUYHG
2SWLRQ%\WHV
5HVHUYHG
5HVHUYHG
Memory mapping STM32F469xx
84/217 DocID028196 Rev 4
Table 13. STM32F469xx register boundary addresses(1)
Bus Boundary address Peripheral
-0xE00F FFFF - 0xFFFF FFFF Reserved
Cortex®-M4 0xE000 0000 - 0xE00F FFFF Cortex®-M4 internal peripherals
AHB3
0xD000 0000 - 0xDFFF FFFF FMC bank 6
0xC000 0000 - 0xCFFF FFFF FMC bank 5
0xA000 1000 - 0xA0001FFF Quad-SPI control register
0xA000 2000 - 0xBFFF FFFF Reserved
0xA000 0000- 0xA000 0FFF FMC control register
0x9000 0000 - 0x9FFF FFFF Quad-SPI bank
0x8000 0000 - 0x8FFF FFFF FMC bank 3
0x7000 0000 - 0x7FFF FFFF FMC bank 2 (reserved)
0x6000 0000 - 0x6FFF FFFF FMC bank 1
-0x5006 0C00- 0x5FFF FFFF Reserved
AHB2
0x5006 0800 - 0x5006 0BFF RNG
0x5005 0400 - 0x5006 07FF Reserved
0x5005 0000 - 0x5005 03FF DCMI
0x5004 0000- 0x5004 FFFF Reserved
0x5000 0000 - 0x5003 FFFF USB OTG FS
DocID028196 Rev 4 85/217
STM32F469xx Memory mapping
87
-0x4008 0000- 0x4FFF FFFF Reserved
AHB1
0x4004 0000 - 0x4007 FFFF USB OTG HS
0x4002 BC00- 0x4003 FFFF Reserved
0x4002 B000 - 0x4002 BBFF Chrom (DMA2D)
0x4002 9400 - 0x4002 AFFF Reserved
0x4002 9000 - 0x4002 93FF
ETHERNET MAC
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF Reserved
0x4002 6400 - 0x4002 67FF DMA2
0x4002 6000 - 0x4002 63FF DMA1
0x4002 5000 - 0x4002 5FFF Reserved
0x4002 4000 - 0x4002 4FFF BKPSRAM
0x4002 3C00 - 0x4002 3FFF Flash interface register
0x4002 3800 - 0x4002 3BFF RCC
0x4002 3400 - 0x4002 37FF Reserved
0x4002 3000 - 0x4002 33FF CRC
0x4002 2C00 - 0x4002 2FFF Reserved
0x4002 2800 - 0x4002 2BFF GPIOK
0x4002 2400 - 0x4002 27FF GPIOJ
0x4002 2000 - 0x4002 23FF GPIOI
0x4002 1C00 - 0x4002 1FFF GPIOH
0x4002 1800 - 0x4002 1BFF GPIOG
0x4002 1400 - 0x4002 17FF GPIOF
0x4002 1000 - 0x4002 13FF GPIOE
0x4002 0C00 - 0x4002 0FFF GPIOD
0x4002 0800 - 0x4002 0BFF GPIOC
0x4002 0400 - 0x4002 07FF GPIOB
0x4002 0000 - 0x4002 03FF GPIOA
Table 13. STM32F469xx register boundary addresses(1) (continued)
Bus Boundary address Peripheral
Memory mapping STM32F469xx
86/217 DocID028196 Rev 4
APB2
0x4001 7400 - 0x4001 FFFF Reserved
0x4001 6C00 - 0x4001 73FF DSI Host
0x4001 6800 - 0x4001 6BFF LCD-TFT
0x4001 5C00 - 0x4001 67FF Reserved
0x4001 5800 - 0x4001 5BFF SAI1
0x4001 5400 - 0x4001 57FF SPI6
0x4001 5000 - 0x4001 53FF SPI5
0x4001 4C00 - 0x4001 4FFF Reserved
0x4001 4800 - 0x4001 4BFF TIM11
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
0x4001 3C00 - 0x4001 3FFF EXTI
0x4001 3800 - 0x4001 3BFF SYSCFG
0x4001 3400 - 0x4001 37FF SPI4
0x4001 3000 - 0x4001 33FF SPI1
0x4001 2C00 - 0x4001 2FFF SDIO
0x4001 2400 - 0x4001 2BFF Reserved
0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3
0x4001 1800 - 0x4001 1FFF Reserved
0x4001 1400 - 0x4001 17FF USART6
0x4001 1000 - 0x4001 13FF USART1
0x4001 0800 - 0x4001 0FFF Reserved
0x4001 0400 - 0x4001 07FF TIM8
0x4001 0000 - 0x4001 03FF TIM1
Table 13. STM32F469xx register boundary addresses(1) (continued)
Bus Boundary address Peripheral
DocID028196 Rev 4 87/217
STM32F469xx Memory mapping
87
-0x4000 8000- 0x4000 FFFF Reserved
APB1
0x4000 7C00 - 0x4000 7FFF UART8
0x4000 7800 - 0x4000 7BFF UART7
0x4000 7400 - 0x4000 77FF DAC
0x4000 7000 - 0x4000 73FF PWR
0x4000 6C00 - 0x4000 6FFF Reserved
0x4000 6800 - 0x4000 6BFF CAN2
0x4000 6400 - 0x4000 67FF CAN1
0x4000 6000 - 0x4000 63FF Reserved
0x4000 5C00 - 0x4000 5FFF I2C3
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF I2C1
0x4000 5000 - 0x4000 53FF UART5
0x4000 4C00 - 0x4000 4FFF UART4
0x4000 4800 - 0x4000 4BFF USART3
0x4000 4400 - 0x4000 47FF USART2
0x4000 4000 - 0x4000 43FF I2S3ext
0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF SPI2 / I2S2
0x4000 3400 - 0x4000 37FF I2S2ext
0x4000 3000 - 0x4000 33FF IWDG
0x4000 2C00 - 0x4000 2FFF WWDG
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
0x4000 2400 - 0x4000 27FF Reserved
0x4000 2000 - 0x4000 23FF TIM14
0x4000 1C00 - 0x4000 1FFF TIM13
0x4000 1800 - 0x4000 1BFF TIM12
0x4000 1400 - 0x4000 17FF TIM7
0x4000 1000 - 0x4000 13FF TIM6
0x4000 0C00 - 0x4000 0FFF TIM5
0x4000 0800 - 0x4000 0BFF TIM4
0x4000 0400 - 0x4000 07FF TIM3
0x4000 0000 - 0x4000 03FF TIM2
1. The reserved boundary address are shown in grayed cells
Table 13. STM32F469xx register boundary addresses(1) (continued)
Bus Boundary address Peripheral
Electrical characteristics STM32F469xx
88/217 DocID028196 Rev 4
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 22.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 23.
Figure 22. Pin loading conditions Figure 23. Pin input voltage
-36
#P&
-#5PIN
-36
-#5PIN
6).
DocID028196 Rev 4 89/217
STM32F469xx Electrical characteristics
190
5.1.6 Power supply scheme
Figure 24. Power supply scheme
1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19 and Section 2.20.
2. The two 2.2 µF ceramic capacitors on VCAP_1 and VCAP_2 should be replaced by two 100 nF decoupling
capacitors when the voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA and VSSA must be connected to VDD and VSS, respectively.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
069
%DFNXSFLUFXLWU\
26&.57&
:DNHXSORJLF
%DFNXSUHJLVWHUV
EDFNXS5$0
.HUQHOORJLF
&38GLJLWDO
5$0
$QDORJ
5&V3//
3RZHU
VZLWFK
9%$7
*3,2V
287
,1
îQ)
î)
9%$7 WR9
9ROWDJH
UHJXODWRU
9''$
$'&
/HYHOVKLIWHU
,2
/RJLF
9''
Q)
)
)ODVKPHPRU\
9&$3B
9&$3B
î)
%<3$66B5(*
3'5B21 5HVHW
FRQWUROOHU
9''
966
9''
95()
95()
966$
95()
Q)
)
27*)6
3+<
9''86%
Q)
9''86%
'6,
3+<
'6,
9ROWDJH
UHJXODWRU
9'''6,
9&$3'6,
9'''6,
966'6,
)
Electrical characteristics STM32F469xx
90/217 DocID028196 Rev 4
5.1.7 Current consumption measurement
Figure 25. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14, Table 15, and Table 16
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
DL
9%$7
9''
9''$
,''B9%$7
,''
Table 14. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS
External main supply voltage
(including VDDA, VDD, VDDUSB, VDDDSI and VBAT)(1)
1. All main power (VDD, VDDA, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
−0.3 4.0
V
VIN
Input voltage on FT pins(2)
2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
VSS −0.3 VDD+4.0
Input voltage on TTa pins VSS −0.3 4.0
Input voltage on any other pin VSS −0.3 4.0
Input voltage on BOOT pin VSS 9.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX −VSS| Variations between all the different ground pins(3)
3. Including VREF- pin
-50
VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.18
DocID028196 Rev 4 91/217
STM32F469xx Electrical characteristics
190
Table 15. Current characteristics
Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD_x power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
290
mA
Σ IVSS Total current out of sum of all VSS_x ground lines (sink)(1) −290
Σ IVDDUSB Total current into VDDUSB power line (source) 25
IVDD Maximum current into each VDD_x power line (source)(1) 100
IVSS Maximum current out of each VSS_x ground line (sink)(1) −100
IIO
Output current sunk by any I/O and control pin 25
Output current sourced by any I/Os and control pin −25
ΣIIO
Total output current sunk by sum of all I/O and control pins (2)
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
120
Total output current sunk by sum of all USB I/Os 25
Total output current sourced by sum of all I/Os and control pins(2) −120
IINJ(PIN) (3)
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.24.
Injected current on FT pins (4)
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
−5/+0
Injected current on NRST and BOOT0 pins (4)
Injected current on TTa pins(5)
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.
±5
ΣIINJ(PIN)(5) Total injected current (sum of all I/O and control pins)(6)
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
±25
Tabl e 16 . Th e rma l ch a r ac te ris tic s
Symbol Ratings Value Unit
TSTG Storage temperature range −65 to +150 °C
TJMaximum junction temperature 125 °C
Electrical characteristics STM32F469xx
92/217 DocID028196 Rev 4
5.3 Operating conditions
5.3.1 General operating conditions
Table 17. General operating conditions
Symbol Parameter Conditions(1) Min Typ Max Unit
fHCLK Internal AHB clock frequency
Power Scale 3 (VOS[1:0] bits in PWR_CR
register = 0x01),
Regulator ON, over-drive OFF
0-120
MHz
Power Scale 2 (VOS[1:0] bits
in PWR_CR register = 0x10),
Regulator ON
Over-drive
OFF
0
-144
Over-drive
ON -168
Power Scale 1 (VOS[1:0] bits
in PWR_CR register= 0x11),
Regulator ON
Over-drive
OFF
0
-168
Over-drive
ON -180
fPCLK1 Internal APB1 clock frequency
Over-drive OFF 0 - 42
Over-drive ON 0 - 45
fPCLK2 Internal APB2 clock frequency
Over-drive OFF 0 - 84
Over-drive ON 0 - 90
VDD Standard operating voltage - 1.7(2) -3.6
V
VDDA(3)(4)
Analog operating voltage
(ADC limited to 1.2 M samples)
Must be the same potential as VDD(5)
1.7(2) -2.4
Analog operating voltage
(ADC limited to 2.4 M samples) 2.4 - 3.6
VDDUSB
USB supply voltage
(supply voltage for PA11, PA12,
PB14 and PB15 pins)
USB not used 1.7 3.3 3.6
USB used 3.0 - 3.6
VDDDSI DSI system operating voltage - 1.7(2) -3.6
VBAT Backup operating voltage - 1.65 - 3.6
DocID028196 Rev 4 93/217
STM32F469xx Electrical characteristics
190
V12
Regulator ON: 1.2 V internal
voltage on VCAP_1/VCAP_2 pins
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 120 MHz
HCLK max frequency
1.08 1.14 1.20
V
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 144 MHz
HCLK max frequency with over-drive OFF
or 168 MHz with over-drive ON
1.20 1.26 1.32
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 168 MHz
HCLK max frequency with over-drive OFF
or 180 MHz with over-drive ON
1.26 1.32 1.40
Regulator OFF: 1.2 V external
voltage must be supplied from
external regulator on
VCAP_1/VCAP_2 pins(6)
Max frequency 120 MHz 1.10 1.14 1.20
Max frequency 144 MHz 1.20 1.26 1.32
Max frequency 168 MHz 1.26 1.32 1.38
VIN
Input voltage on RST and FT
pins(7)
2V ≤ VDD ≤ 3.6 V −0.3 - 5.5
V
VDD ≤ 2V −0.3 - 5.2
Input voltage on TTa pins - −0.3 - VDDA
+0.3
Input voltage on BOOT0 pin - 0 - 9
PD
Power dissipation
at TA = 85 °C for suffix 6
or TA = 105 °C for suffix 7(8)
LQFP100 - - 465
mW
LQFP144 - - 500
WLCSP168 - - 645
UFBGA169 - - 385
LQFP176 - - 526
UFBGA176 - - 513
LQFP208 - - 1053
TFBGA216 - - 690
TA
Ambient temperature for 6
suffix version
Maximum power dissipation −40 - 85
°C
Low power dissipation(9) −40 - 105
Ambient temperature for 7
suffix version
Maximum power dissipation −40 - 105
Low power dissipation(9) −40 - 125
TJJunction temperature range 6 suffix version −40 - 105
7 suffix version −40 - 125
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
3. When the ADC is used, refer to Table 76.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
6. The over-drive mode is not supported when the internal regulator is OFF.
Table 17. General operating conditions (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit
Electrical characteristics STM32F469xx
94/217 DocID028196 Rev 4
5.3.2 VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Table 19.
Figure 26. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 18. Limitations depending on the operating power supply range
Operating
power
supply range
ADC
operation
Maximum Flash
memory access
frequency with
no wait states
(fFlashmax)
Maximum HCLK
frequency
vs.
Flash memory wait
states (1)(2)
I/O operation Possible Flash
memory
operations
VDD =
1.7 to 2.1 V(3)
Conversion time
up to 1.2 Msps
20 MHz(4)
168 MHz
with 8 wait states
and over-drive OFF No I/O
compensation
8-bit erase
and program
operations only
VDD =
2.1 to 2.4 V 22 MHz
180 MHz
with 8 wait states
and over-drive ON
16-bit erase
and program
operations
VDD =
2.4 to 2.7 V
Conversion time
up to 2.4 Msps
24 MHz
180 MHz
with 7 wait states
and over-drive ON I/O compensation
works
16-bit erase
and program
operations
VDD =
2.7 to 3.6 V(5) 30 MHz
180 MHz
with 5 wait states
and over-drive ON
32-bit erase
and program
operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
4. Prefetch is not available.
5. When VDDUSB is connected to VDD, the voltage range for USB full speed PHYs can drop down to 2.7 V. However the
electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.
069
(65
5
/HDN
&
DocID028196 Rev 4 95/217
STM32F469xx Electrical characteristics
190
5.3.3 Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up / power-down (regulator ON)
5.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
5.3.5 Reset and power cont rol block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
Table 19. VCAP1/VCAP2 operating conditions(1)
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF
ESR ESR of external capacitor < 2 Ω
Symbol Parameter Min Max Unit
tVDD
VDD rise time rate 20 ∞
µs/V
VDD fall time rate 20 ∞
Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate Power-up 20 ∞
µs/V
VDD fall time rate Power-down 20 ∞
tVCAP
VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞
VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞
Electrical characteristics STM32F469xx
96/217 DocID028196 Rev 4
Table 22. Reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.09 2.14 2.19
V
PLS[2:0]=000 (falling edge) 1.98 2.04 2.08
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37
PLS[2:0]=001 (falling edge) 2.13 2.19 2.25
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51
PLS[2:0]=010 (falling edge) 2.29 2.35 2.39
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65
PLS[2:0]=011 (falling edge) 2.44 2.51 2.56
PLS[2:0]=100 (rising edge) 2.70 2.76 2.82
PLS[2:0]=100 (falling edge) 2.59 2.66 2.71
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99
PLS[2:0]=101 (falling edge) 2.65 2.84 2.92
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10
PLS[2:0]=110 (falling edge) 2.85 2.93 2.99
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21
PLS[2:0]=111 (falling edge) 2.95 3.03 3.09
VPVDhyst(1) PVD hysteresis - - 100 - mV
VPOR/PDR
Power-on/power-down
reset threshold
Falling edge 1.60 1.68 1.76
V
Rising edge 1.64 1.72 1.80
VPDRhyst(1) PDR hysteresis - - 40 - mV
VBOR1 Brownout level 1 threshold
Falling edge 2.13 2.19 2.24
V
Rising edge 2.23 2.29 2.33
VBOR2 Brownout level 2 threshold
Falling edge 2.44 2.50 2.56
Rising edge 2.53 2.59 2.63
VBOR3 Brownout level 3 threshold
Falling edge 2.75 2.83 2.88
Rising edge 2.85 2.92 2.97
VBORhyst(1) BOR hysteresis - - 100 - mV
TRSTTEMPO(1)(2) POR reset temporization - 0.5 1.5 3.0 ms
IRUSH(1)
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
- - 160 200 mA
ERUSH(1)
InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)
VDD = 1.7 V, TA = 105 °C,
IRUSH = 171 mA for 31 µs --5.4µC
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first
instruction is read by the user application code.
DocID028196 Rev 4 97/217
STM32F469xx Electrical characteristics
190
5.3.6 Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are subject to general
operating conditions for TA.
5.3.7 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 25.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark® code.
Table 23. Over-drive switching char acteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
Tod_swen
Over_drive switch
enable time
HSI -45 -
µs
HSE max for 4 MHz
and min for 26 MHz 45 -100
External HSE
50 MHz -40 -
Tod_swdis
Over_drive switch
disable time
HSI -20 -
HSE max for 4 MHz
and min for 26 MHz. 20 -80
External HSE
50 MHz -15 -
Electrical characteristics STM32F469xx
98/217 DocID028196 Rev 4
Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in input mode with a static value at VDD or VSS (no load).
•All peripherals are disabled except if it is explicitly mentioned.
•The Flash memory access time is adjusted both to fHCLK frequency and VDD range
(see Table 18: Limitations depending on the operating power supply range).
•When the regulator is OFF, the V12 is provided externally, as described in Table 17:
General operating condition s.
•The voltage scaling and over-drive mode are adjusted to fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 120 MHz
– Scale 2 for 120 MHz < fHCLK ≤ 144 MHz
– Scale 1 for 144 MHz < fHCLK ≤ 180 MHz. The over-drive is only ON at 180 MHz.
•The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
•External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
•The typical current consumption values are obtained for 1.7 V ≤
VDD ≤ 3.6 V voltage
range and for ambient temperature TA= 25 °C unless otherwise specified.
•The maximum values are obtained for 1.7 V ≤
VDD ≤ 3.6 V voltage range and a
maximum ambient temperature (TA), unless otherwise specified.
•For the voltage range 1.7 V ≤
VDD ≤ 2.1 V the maximum frequency is 168 MHz.
DocID028196 Rev 4 99/217
STM32F469xx Electrical characteristics
190
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulat o r ON
Symbol Parameter Conditions fHCLK (MHz) Typ
Max(1)
Unit
TA =
25 °C TA =
85 °C TA =
105 °C
IDD
Supply
current in
RUN mode
All
Peripherals
enabled(2)(3)
180 103 109(4) 142 175(4)
mA
168 94 99 124 149
150 84 89 114 140
144 77 81 104 127
120 57 60 79 98
90 43 46 64 84
60 30 33 51 70
30 16 19 37 57
25 14 16 34 54
16 7 10 28 48
8472646
4362444
2352343
All
Peripherals
disabled(2)
180 50 56(4) 89 124(4)
168 45 51 75 102
150 41 46 70 97
144 37 42 63 88
120 28 31 49 69
90 21 24 42 63
60 15 17 36 56
30 9 11 29 49
25 7 10 28 48
16 4 7 25 45
8362244
4352343
2252343
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
4. Guaranteed by test in production.
Electrical characteristics STM32F469xx
100/217 DocID028196 Rev 4
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
TA =
25 °C TA =
85 °C TA =
105 °C
IDD
Supply current in
RUN mode
All Peripherals
enabled(2)(3)
168 97 102 128 154
mA
150 87 92 118 143
144 80 84 108 131
120 65 68 88 108
90 51 54 73 93
60 37 41 59 79
30 21 23 42 62
25 18 20 39 59
All Peripherals
disabled
168 49 55 79 105
150 44 49 44 100
144 40 45 68 92
120 36 39 58 78
90 29 32 51 71
60 22 25 44 64
30 13 15 34 54
25 11 13 32 52
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
DocID028196 Rev 4 101/217
STM32F469xx Electrical characteristics
190
Table 26. Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF
Symbol Parameter Conditions fHCLK
(MHz)
Typ Max(1)
Unit
IDD12 IDD
TA = 25 °C TA = 85 °C TA = 105 °C
IDD12 IDD IDD12 IDD IDD12 IDD
IDD12 / IDD
Supply current
in RUN mode
from V12 and
VDD supply
All Peripherals
enabled(2) (3)
168 93 1 98 1 123 1 148 1
mA
150 83 1 88 1 113 1 138 1
144 76 1 80 1 103 1 126 1
120561591781971
90431451641831
60291321501701
30151181361561
25131151341531
All Peripherals
disabled
168441501721941
150401451681901
144361401621821
120271301481661
90201231411601
60141161351531
30 8 1101281471
25 7 1 9 1271461
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, DSI regulator, an additional power
consumption should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
Electrical characteristics STM32F469xx
102/217 DocID028196 Rev 4
Table 27. Typical and maximum current consumption in Sleep mode, regulator ON
Symbol Parameter Conditions fHCLK (MHz) Typ Max(1)(2)(3)
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
IDD
Supply
current in
Sleep mode
All
Peripherals
enabled
180 78 88(4) 118 151(4)
mA
168 71 76 101 127
150 64 71 94 119
144 58 62 85 109
120 43 46 65 85
90 33 37 54 74
60 23 25 44 63
30 13 15 34 53
25 11 13 32 52
16 5 8 27 47
847 2545
435 2444
225 2343
All
Peripherals
disabled
180 23 29(4) 63 96(4)
168 21 25 50 76
150 19 23 48 74
144 17 31 43 67
120 13 16 34 54
90 10 13 31 51
60 7 10 28 48
30 5 7 25 45
25 4 7 25 45
16 2 5 23 43
825 2343
425 2343
224 2342
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
4. Guaranteed by test in production.
DocID028196 Rev 4 103/217
STM32F469xx Electrical characteristics
190
Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF
Symbol Parameter Conditions fHCLK
(MHz)
Typ Max(1)
Unit
IDD12 IDD
TA = 25 °C TA = 85 °C TA = 105 °C
IDD12 IDD IDD12 IDD IDD12 IDD
IDD12 / IDD
Supply current
in RUN mode
from V12 and
VDD supply
All
Peripherals
enabled
168 70 1 75 1 100 1 126 1
mA
150 63 1 70 1 93 1 118 1
144 57 1 61 1 84 1 108 1
120421451641841
90321361531731
60221241431631
30121141331531
25101121311511
All
Peripherals
disabled
168201241491751
150181221471731
144161191421661
120121141331531
90101121301501
60 7 1 9 1271471
30 4 1 6 1241441
25 4 1 6 1241441
1. Guaranteed based on test during characterization.
Electrical characteristics STM32F469xx
104/217 DocID028196 Rev 4
Table 29. Typical and maximum current consumption in Stop mode
Symbol Parameter Conditions Typ
Max(1)
Unit
TA =
25 °C TA =
85 °C TA =
105 °C
IDD_STOP_NM
(normal mode)
Supply current in Stop
mode with voltage
regulator in main
regulator mode
Flash memory in Stop mode, all
oscillators OFF, no independent
watchdog
0.63 317 33
mA
Flash memory in Deep power
down mode, all oscillators OFF,
no independent watchdog
0.58 317 33
Supply current in Stop
mode with voltage
regulator in Low Power
regulator mode
Flash memory in Stop mode, all
oscillators OFF, no independent
watchdog
0.50 215 28
Flash memory in Deep power
down mode, all oscillators OFF,
no independent watchdog
0.44 2 15 28
IDD_STOP_UDM
(under-drive
mode)
Supply current in Stop
mode with voltage
regulator in main
regulator and under-
drive mode
Flash memory in Deep power
down mode, main regulator in
under-drive mode, all oscillators
OFF, no independent watchdog
0.21 1 6 12
Supply current in Stop
mode with voltage
regulator in Low Power
regulator and under-
drive mode
Flash memory in Deep power
down mode, Low Power regulator
in under-drive mode, all
oscillators OFF, no independent
watchdog
0.14 1 6 13
1. Data based on characterization, tested in production.
DocID028196 Rev 4 105/217
STM32F469xx Electrical characteristics
190
Table 30. Typical and maximum current consumption in Standby mode
Symbol Parameter Conditions
Typ(1) Max(2)
Unit
TA = 25 °C TA =
25 °C TA =
85 °C TA =
105 °C
VDD =
1.7 V VDD=
2.4 V VDD =
3.3 V VDD = 3.3 V
IDD_STBY
Supply current
in Standby
mode
Backup SRAM ON, RTC and
LSE oscillator OFF 1.7 2.5 2.9 6(3) 18 35(3)
µA
Backup SRAM OFF, RTC and
LSE oscillator OFF 1.0 1.8 2.20 5(3) 15 30(3)
Backup SRAM OFF, RTC ON
and LSE oscillator in Power
Drive mode
1.7 2.7 3.2 720 39
Backup SRAM ON, RTC ON
and LSE oscillator in Power
Drive mode
2.4 3.4 4.0 825 48
Backup SRAM ON, RTC ON
and LSE oscillator in High
Drive mode
3.2 4.2 4.8 10 29 57
Backup SRAM OFF, RTC ON
and LSE oscillator in High
Drive mode
2.5 3.5 4.1 825 48
1. PDR is off for VDD=1.7 V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by
additional 1.2 μA
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.
Electrical characteristics STM32F469xx
106/217 DocID028196 Rev 4
Figure 27 . Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in Low drive mode)
Table 31. Typical and maximum current consumption in VBAT mode
Symbol Parameter Conditions(1)
Typ Max(2)
Unit
TA = 25 °C TA =
25 °C TA =
85 °C TA =
105 °C
VBAT =
1.7 V VBAT=
2.4 V VBAT =
3.3 V VBAT = 3.3 V
IDD_VBAT
Backup
domain supply
current
Backup SRAM ON, RTC ON
and LSE oscillator in Low
Power mode
1.431 1.577 1.825 1.9 12.0 24.0
µA
Backup SRAM OFF, RTC ON
and LSE oscillator in Low
Power mode
0.720 0.849 1.060 1.1 7.0 13.9
Backup SRAM ON, RTC ON
and LSE oscillator in High
Drive mode
2.212 2.368 2.630 2.80 17.3 34.6
Backup SRAM OFF, RTC ON
and LSE oscillator in High
Drive mode
1.499 1.637 1.862 2.0 12.3 24.5
Backup SRAM ON, RTC and
LSE OFF 0.710 0.720 0.760 0.8(3) 5.0 10.0(3)
Backup SRAM OFF, RTC and
LSE OFF 0.018 0.020 0.024 0.2(3) 2.0 4.0(3)
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Based on characterization, tested in production.
3. Based on test during characterization.
0
1
2
3
4
5
6
0 20406080100
I
DD_VBAT
(μA)
Temperature (°C)
1.65V
1.70V
1.80V
2.00V
2.40V
2.70V
3.00V
3.30V
3.60V
DocID028196 Rev 4 107/217
STM32F469xx Electrical characteristics
190
Figure 28 . Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in High drive mode)
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 58: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 33), the I/Os used by
an application also contribute to the current consumption. When an I/O pin switches, it uses
0
1
2
3
4
5
6
7
0 20406080100
IDD_VBAT (μA)
Temperature (°C)
1.65V
1.70V
1.80V
2.00V
2.40V
2.70V
3.00V
3.30V
3.60V
Electrical characteristics STM32F469xx
108/217 DocID028196 Rev 4
the current from the MCU supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load (internal or external) connected to the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 32. Switching output I/O current consumption(1)
Symbol Parameter Conditions I/O toggling
frequency
(fsw) Typ Unit
IDDIO
I/O switching
Current
VDD = 3.3 V
C= CINT(2)
2 MHz 0.0
mA
8 MHz 0.2
25 MHz 0.6
50 MHz 1.1
60 MHz 1.3
84 MHz 1.8
90 MHz 1.9
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT + CS
2 MHz 0.1
8 MHz 0.4
25 MHz 1.23
50 MHz 2.43
60 MHz 2.93
84 MHz 3.86
90 MHz 4.07
ISW VDD fSW C××=
DocID028196 Rev 4 109/217
STM32F469xx Electrical characteristics
190
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•At startup, all I/O pins are in analog input configuration.
•All peripherals are disabled unless otherwise mentioned.
•I/O compensation cell enabled.
•The ART accelerator is ON.
•Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
•HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
–f
HCLK = 180 MHz (Scale1 + over-drive ON), fHCLK = 144 MHz (Scale 2),
fHCLK = 120 MHz (Scale 3)
•Ambient operating temperature is 25 °C and VDD=3.3 V.
IDDIO
I/O switching
Current
VDD = 3.3 V
CEXT = 10 pF
C = CINT + CEXT + CS
2 MHz 0.18
mA
8 MHz 0.67
25 MHz 2.09
50 MHz 3.6
60 MHz 4.5
84 MHz 7.8
90 MHz 9.8
VDD = 3.3 V
CEXT = 22 pF
C = CINT + CEXT + CS
2 MHz 0.26
8 MHz 1.01
25 MHz 3.14
50 MHz 6.39
60 MHz 10.68
VDD = 3.3 V
CEXT = 33 pF
C = CINT + Cext + CS
2 MHz 0.33
8 MHz 1.29
25 MHz 4.23
50 MHz 11.02
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
2. This test is performed by cutting the LQFP176 package pin (pad removal).
Table 32. Switching output I/O current consumption(1) (continued)
Symbol Parameter Conditions I/O toggling
frequency
(fsw) Typ Unit
Electrical characteristics STM32F469xx
110/217 DocID028196 Rev 4
Table 33. Peripheral current consumption
Peripheral IDD(Typ)(1)
Unit
Scale 1 Scale 2 Scale 3
AHB1
(up to
180 MHz)
GPIOA 3.16 3.00 2.58
µA/MHz
GPIOB 2.67 2.62 2.25
GPIOC 2.42 2.31 2.10
GPIOD 2.22 2.10 1.79
GPIOE 2.60 2.48 2.23
GPIOF 2.39 2.27 2.08
GPIOG 2.27 2.13 1.98
GPIOH 2.34 2.20 2.02
GPIOI 2.52 2.37 2.17
GPIOJ 2.16 2.03 1.86
GPIOK 2.20 2.06 1.89
OTG_HS+ULPI 36.49 33.89 29.90
CRC 0.62 0.55 0.50
BKPSRAM 0.83 0.74 0.63
DMA1(2) 3.3 x N + 6.8 3 x N + 6.3 2.7 x N + 5.5
DMA2(2) 3.4 x N + 5.7 3.1 x N + 5.3 2.8 x N + 4.6
DMA2D 33.33 30.66 26.98
ETH_MAC
ETH_MAC_TX
ETH_MAC_RX
ETH_MAC_PTP
22.30 20.69 18.19
AHB2
(up to
180 MHz)
USB_OTG_FS 34.33 31.96 28.35
µA/MHz
DVCMI 3.61 3.35 2.98
RNG 1.94 1.82 1.61
AHB3
(up to
180 MHz)
QUADSPI 16.83 15.57 13.83
µA/MHz
FMC 17.22 15.92 14.00
Bus matrix(3) 12.17 11.19 9.97 µA/MHz
DocID028196 Rev 4 111/217
STM32F469xx Electrical characteristics
190
APB1
(up to
45 MHz)
TIM2 19.11 17.56 15.33
µA/MHz
TIM3 15.62 14.22 12.17
TIM4 16.22 14.64 12.83
TIM5 18.44 16.72 14.00
TIM6 3.18 2.69 2.17
TIM7 3.11 2.56 2.00
TIM12 8.67 7.56 6.50
TIM13 6.11 5.33 4.43
TIM14 6.44 5.61 4.67
PWR 17.44 15.61 13.53
USART2 5.44 4.64 3.93
USART3 5.51 4.72 4.00
UART4 5.22 4.64 3.83
UART5 5.33 4.64 3.83
UART7 5.56 4.78 4.10
UART8 5.24 4.64 3.93
I2C1 4.78 4.08 3.43
I2C2 5.11 4.50 3.73
I2C3 4.78 4.08 3.43
SPI2/I2S2(4) 4.11 3.53 3.00
SPI3/I2S3(4) 4.33 3.67 3.17
CAN1 8.89 7.83 6.87
CAN2 7.22 6.44 5.50
DAC(5) 2.89 2.69 2.40
WWDG 1.73 1.44 1.00
Table 33. Peripheral current consumption (continued)
Peripheral IDD(Typ)(1)
Unit
Scale 1 Scale 2 Scale 3
Electrical characteristics STM32F469xx
112/217 DocID028196 Rev 4
APB2
(up to
90 MHz)
SDIO 7.94 7.18 6.37
µA/MHz
TIM1 19.44 17.81 15.80
TIM8 19.44 17.81 15.80
TIM9 8.44 7.60 6.77
TIM10 5.67 5.03 4.50
TIM11 5.72 5.10 4.55
ADC1(6) 5.06 4.54 4.05
ADC2(6) 5.00 4.47 3.97
ADC3(6) 5.26 4.75 4.17
USART1 4.83 4.33 3.83
USART6 4.83 4.33 3.83
SPI1 2.11 1.76 1.60
SPI4 2.11 1.69 1.60
SPI5 2.11 1.76 1.60
SPI6 2.11 1.76 1.60
SYSCFG 1.72 1.35 1.22
LTDC 37.61 34.53 30.60
SAI1 3.44 3.01 2.72
DSI 32.98 30.32 26.87
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. DMA1/DMA2 current consumption is calculated by the equation. N: is the number of streams enabled,
N= [1..8]
3. The BusMatrix is automatically active when at least one master is ON.
4. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
5. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.8 mA per DAC channel for the analog part.
6. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.6 mA per ADC for the analog part.
Table 33. Peripheral current consumption (continued)
Peripheral IDD(Typ)(1)
Unit
Scale 1 Scale 2 Scale 3
DocID028196 Rev 4 113/217
STM32F469xx Electrical characteristics
190
5.3.8 Wakeup time from low-power modes
The wakeup times given in Table 34 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•For Stop or Sleep modes: the wakeup event is WFE.
•WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 34. Low-power mode wakeup timings
Symbol Parameter Conditions Typ(1) Max(1) Unit
tWUSLEEP(2) Wakeup from Sleep - 5 6 CPU clock
cycles
tWUSTOP(2)
Wakeup from Stop mode
with MR/LP regulator in
normal mode
Main regulator is ON 12.9 15.0
µs
Main regulator is ON and Flash
memory in Deep power down mode 105 120
Low power regulator is ON 22 28
Low power regulator is ON and Flash
memory in Deep power down mode 114 130
tWUSTOP(2)
Wakeup from Stop mode
with MR/LP regulator in
Under-drive mode
Main regulator in under-drive mode
(Flash memory in Deep power-down
mode)
107 114
Low power regulator in under-drive
mode (Flash memory in Deep
power-down mode)
115 121
tWUSTDBY (2)(3) Wakeup from Standby mode - 318 371
1. Based on test during characterization.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
3. tWUSTDBY maximum value is given at –40 °C.
Electrical characteristics STM32F469xx
114/217 DocID028196 Rev 4
5.3.9 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 58. However, the recommended clock input
waveform is shown in Figure 29.
The characteristics given in Table 35 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 58: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 30.
The characteristics given in Table 36 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Table 35. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
External user clock source
frequency(1)
-
1-50MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
1. Guaranteed by design.
5--
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) --10
Cin(HSE) OSC_IN input capacitance(1) --5-pF
DuCy(HSE) Duty cycle - 45 - 55 %
ILOSC_IN Input leakage current VSS ≤VIN ≤VDD --±1µA
Table 36. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User External clock source frequency(1)
-
- 32.768 1000 kHz
VLSEH OSC32_IN input pin high level voltage 0.7VDD -V
DD V
VLSEL OSC32_IN input pin low level voltage VSS -0.3V
DD
tw(LSE)
tf(LSE)
OSC32_IN high or low time(1) 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) --50
DocID028196 Rev 4 115/217
STM32F469xx Electrical characteristics
190
Figure 29. High-speed external clock source AC timing diagram
Figure 30. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 37. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
Cin(LSE) OSC32_IN input capacitance(1) --5-pF
DuCy(LSE) Duty cycle - 30 - 70 %
ILOSC32_IN Input leakage current VSS ≤VIN ≤VDD --±1µA
1. Guaranteed by design.
Table 36. Low-speed external user clock characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
AI
/3# ?) .
%XTERNAL
34-&
CLOCKSOURCE
6(3%(
TF(3% T7(3%
),
4(3%
T
TR(3% T7(3%
F(3%?EXT
6(3%,
DL
26&B,1
([WHUQDO
670)
FORFNVRXUFH
9/6(+
WI/6( W:/6(
,/
7/6(
W
WU/6( W:/6(
I/6(BH[W
9/6(/
Electrical characteristics STM32F469xx
116/217 DocID028196 Rev 4
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 31). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the applic ation note AN2867 “Oscillator
design guide for ST microcontrollers” available from www.st.com.
Figure 31. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Table 37. HSE 4-26 MHz oscillator characteristics (1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency - 4 - 26 MHz
RFFeedback resistor - - 200 - kΩ
IDD HSE current consumption
VDD=3.3 V,
ESR= 30 Ω,
CL=5 pF@25 MHz
- 450 -
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF@25 MHz
- 530 -
ACCHSE(2)
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
HSE accuracy - −500 - 500 ppm
Gm_crit_max Maximum critical crystal gmStartup - - 1 mA/V
tSU(HSE)(3)
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is based on characterization and not tested in production. It is measured
for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Startup time VDD is stabilized - 2 - ms
DL
26&B28 7
26&B,1 I+6(
&/
5)
670)
0+]
UHVRQDWRU
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
%LDV
FRQWUROOHG
JDLQ
5(;7
&/
DocID028196 Rev 4 117/217
STM32F469xx Electrical characteristics
190
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the informations given in this paragraph are based on
characterization results obtained with typical external components specified in Table 38.
In the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Note: For information on selecting the crystal, refer to the applic ation note AN2867 “Oscillator
design guide for ST microcontrollers” available from www.st.com.
Figure 32. Typical application with a 32.768 kHz crystal
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
RFFeedback resistor - - 18.4 - MΩ
IDD LSE current consumption
Low power mode(2)
2. LSE mode cannot be changed “on the fly” otherwise, a glitch can be generated on OSCIN pin.
--1
µA
High drive mode(2) --3
ACCLSE(3)
3. This parameter depends on the crystal used in the application. Refer to application note AN2867.
LSE accuracy - −500 - 500 ppm
Gm_crit_max Maximum critical crystal gm
Low power mode(2) - - 0.56
µA/V
High drive mode(2) --1.5
tSU(LSE)(4)
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is
measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Startup time VDD is stabilized - 2 - s
DL
26&B28 7
26&B,1 I/6(
&/
5)
670)
N+]
UHVRQDWRU
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
%LDV
FRQWUROOHG
JDLQ
&/
Electrical characteristics STM32F469xx
118/217 DocID028196 Rev 4
5.3.10 Internal clock source characteristics
The parameters given in Table 39 and Table 40 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 17.
High-speed internal (HSI) RC oscillator
Figure 33. ACCHSI vs. temperature
1. Based on test during characterization.
Table 39. HSI oscillator characteristics (1)
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - - 16 - MHz
ACCHSI
HSI user trimming step(2)
2. Guaranteed by design
---1%
HSI oscillator accuracy
TA = –40 to 105 °C(3)
3. Based on test during characterization.
−8-4.5%
TA = –10 to 85 °C(3) −4- 4 %
TA = 25 °C(4)
4. Factory calibrated, parts not soldered.
−1- 1 %
tsu(HSI)(2) HSI oscillator startup time - - 2.2 4 µs
IDD(HSI)(2) HSI oscillator power consumption - - 60 80 µA
06Y9
Ͳϴ
Ͳϲ
Ͳϰ
ͲϮ
Ϭ
Ϯ
ϰ
ϲ
ͲϰϬ Ϭ Ϯϱ ϱϱ ϴϱ ϭϬϱ ϭϮϱ
,^/;йͿ
d; Σ
Ϳ
DŝŶ DĂdž dLJƉŝĐĂů
DocID028196 Rev 4 119/217
STM32F469xx Electrical characteristics
190
Low-speed internal (LSI) RC oscillator
Figure 34. ACCLSI versus temperature
5.3.11 PLL characteristics
The parameters given in Table 41 and Table 42 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.
Table 40. LSI oscillator characteristics (1)
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI(2)
2. Based on test during characterization.
Frequency 17 32 47 kHz
tsu(LSI)(3)
3. Guaranteed by design.
Startup time - 15 40 µs
IDD(LSI)(3) Power consumption - 0.4 0.6 µA
-36
.ORMALIZEDDEVIATI ON
4EMPERAT UR E#
MAX
AVG
MIN
Table 41 . Ma in PLL ch ara cteri st ic s
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN PLL input clock(1) -0.95
(2) 12.10
MHz
fPLL_OUT PLL multiplier output clock - 24 - 180
fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75
fVCO_OUT PLL VCO output - 192 - 432
Electrical characteristics STM32F469xx
120/217 DocID028196 Rev 4
tLOCK PLL lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Cycle-to-cycle jitter
System clock
120 MHz
RMS - 25 -
ps
peak to peak - ±150 -
Period Jitter
RMS - 15 -
peak to peak - ±200 -
Main clock output (MCO) for RMII
Ethernet
Cycle to cycle at 50 MHz on
1000 samples -32-
Main clock output (MCO) for MII
Ethernet
Cycle to cycle at 25 MHz on
1000 samples -40-
Bit Time CAN jitter Cycle to cycle at 1 MHz on
1000 samples - 330 -
IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75
mA
IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel can degrade the Jitter up to +30%.
4. Based on test during characterization.
Table 41. Main PLL characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 42. PLLI2S (audio PLL) characteristics
Symbol Parameter Conditions Min Typ Max Unit
fPLLI2S_IN PLLI2S input clock(1) -0.95
(2) 12.10
MHzfPLLI2S_OUT
PLLI2S multiplier output
clock ---216
fVCO_OUT PLLI2S VCO output - 192 - 432
tLOCK PLLI2S lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Master I2S clock jitter
Cycle to cycle at
12.288 MHz on 48KHz
period, N=432, R=5
RMS - 90 - -
peak to peak - ±280 - ps
Average frequency of 12.288 MHz,
N=432, R=5
on 1000 samples
-90-ps
WS I2S clock jitter Cycle to cycle at 48 KHz
on 1000 samples - 400 - ps
DocID028196 Rev 4 121/217
STM32F469xx Electrical characteristics
190
IDD(PLLI2S)(4) PLLI2S power consumption
on VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75
mA
IDDA(PLLI2S)(4) PLLI2S power consumption
on VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Based on test during characterization.
Table 42. PLLI2S (audio PLL) characte ristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 43. PLLSAI (audio and LCD-TFT PLL) character istics
Symbol Parameter Conditions Min Typ Max Unit
fPLLSAI_IN PLLSAI input clock(1) -0.95
(2) 12.10
MHzfPLLSAI_OUT PLLSAI multiplier output clock - - - 216
fVCO_OUT PLLSAI VCO output - 192 - 432
tLOCK PLLSAI lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Main SAI clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS - 90 -
peak
to
peak
- ±280 - ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -ps
FS clock jitter Cycle to cycle at 48 KHz
on 1000 samples -400 - ps
IDD(PLLSAI)(4) PLLSAI power consumption on
VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75
mA
IDDA(PLLSAI)(4) PLLSAI power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Based on test during characterization.
Electrical characteristics STM32F469xx
122/217 DocID028196 Rev 4
5.3.12 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 54). It is available only on the main PLL.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
fPLL_IN and fMod must be expressed in Hz.
As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
fVCO_OUT must be expressed in MHz.
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
As a result:
Table 44. SSCG parameters constraint
Symbol Parameter Min Typ Max(1)
1. Guaranteed by design.
Unit
fMod Modulation frequency - - 10 KHz
md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - - 215 −1-
MODEPER round fPLL_IN 4f
Mod
×()⁄[]=
MODEPER round 106410
3
×()⁄[]250==
INCSTEP round 215 1–()md PLLN××()100 5×MODEPER×()⁄[]=
INCSTEP round 215 1–()2240××()100 5×250×()⁄[]126md(quantitazed)%==
mdquantized% MODEPER INCSTEP×100×5×()215 1–()PLLN×()⁄=
mdquantized% 250 126×100×5×()215 1–()240×()⁄2.002%(peak)==
DocID028196 Rev 4 123/217
STM32F469xx Electrical characteristics
190
Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 35. PLL output clock waveforms in center spread mode
Figure 36. PLL output clock waveforms in down spread mode
5.3.13 MIPI D-PHY characteristics
The parameters given in Table 45 and Table 46 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.
069
)UHTXHQF\
3//B287
7LPH
)
WPRGH
PG
[WPRGH
PG
069
)UHTXHQF\
3//B287
7LPH
)
WPRGH
[PG
[WPRGH
Table 45. MIPI D-PHY characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
Hi-Speed Input/Output Characteristics
UINST UI instantaneous - 2 - 12.5 ns
Electrical characteristics STM32F469xx
124/217 DocID028196 Rev 4
VCMTX
HS transmit common mode
voltage - 150 200 250
mV
|∆VCMTX|VCMTX mismatch when output
is Differential-1 or Differential-0 ---5
|VOD| HS transmit differential voltage - 140 200 270
|∆VOD|VOD mismatch when output is
Differential-1 or Differential-0 ---14
VOHHS HS output high voltage - - - 360
ZOS
Single ended output
impedance -405062.5Ω
∆ZOS
Single ended output
impedance mismatch ---10%
tHSr & tHSf 20%-80% rise and fall time - 100 - 0.35*UI ps
LP Receiver Input Characteristics
VIL
Logic 0 input voltage (not in
ULP State) ---550
mV
VIL-ULPS
Logic 0 input voltage in ULP
State ---300
VIH Input high level voltage - 880 - -
Vhys Voltage hysteresis - 25 - -
LP Emitter Output Characteristics
VIL Output low level voltage - 1.1 1.2 1.2 V
VIL-ULPS Output high level voltage - -50 - 50 mV
VIH
Output impedance of LP
transmitter -110--Ω
Vhys 15%-85% rise and fall time - - - 25 ns
LP Contention Detector Characteristics
VILCD Logic 0 contention threshold - - - 200
mV
VIHCD Logic 0 contention threshold - 450 - -
1. Guaranteed based on test during characterization.
Table 45. MIPI D-PHY characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DocID028196 Rev 4 125/217
STM32F469xx Electrical characteristics
190
Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Conditions Min Typ Max Unit
TLPX
Transmitted length of any Low-
Power state period -50--
ns
TCLK-PREPARE
Time that the transmitter drives
the Clock Lane LP-00 Line
state immediately before the
HS-0 Line state starting the HS
transmission.
-38-95
TCLK-PREPARE
+
TCLK-ZERO
Time that the transmitter drives
the HS-0 state prior to starting
the clock.
- 300 - -
TCLK-PRE
Time that the HS clock shall be
driven by the transmitter prior to
any associated Data Lane
beginning the transition from
LP to HS mode.
-8--UI
TCLK-POST
Time that the transmitter
continues to send HS clock
after the last associated Data
Lane has transitioned to LP
Mode.
-62+52*UI--
ns
TCLK-TRAIL
Time that the transmitter drives
the HS-0 state after the last
payload clock bit of an HS
transmission burst.
-60--
THS-PREPARE
Time that the transmitter drives
the Data Lane LP-00 Line state
immediately before the HS-0
Line state starting the HS
transmission.
- 40+4*UI - 85+6*UI
THS-PREPARE
+
THS-ZERO
THS-PREPARE+ Time that the
transmitter drives the HS-0
state prior to transmitting the
Sync sequence.
- 145+10*UI - -
THS-TRAIL
Time that the transmitter drives
the flipped differential state
after last payload data bit of a
HS transmission burst.
-
Max
(n*8*UI,
60+n*4*UI)
--
THS-EXIT
Time that the transmitter drives
LP-11 following a HS burst. - 100 - -
TREOT 30%-85% rise time and fall time - - - 35
TEOT
Transmitted time interval from
the start of THS-TRAIL or
TCLK-TRAIL, to the start of the
LP-11 state following a HS
burst.
---
105+
n*12UI
Electrical characteristics STM32F469xx
126/217 DocID028196 Rev 4
Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram
Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram
5.3.14 MIPI D-PHY PLL characteristics
The parameters given in Table 47 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.
069
&ORFN
/DQH
'DWD
/DQH
7/3; 7+635(3$5(
7&/.35(
7&/.=(52
7&/.35(3$5(
7/3;
7+6(;,7
7&/.75$,/
7&/.3267
9,/
9,/
7(27
069
&ORFN
/DQH
7+635(3$5(
7/3;
7+675$,/ 7+6(;,7
/3 /3/3
'DWD
/DQH 9,/
75(27
7(27
7+6=(52
Table 47. DSI-PLL characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN PLL input clock - 4 - 100
MHz
fPLL_INFIN PFD input clock - 4 - 25
fPLL_OUT PLL multiplier output clock - 31.25 - 500
fVCO_OUT PLL VCO output - 500 - 1000
tLOCK PLL lock time - - - 200 µs
DocID028196 Rev 4 127/217
STM32F469xx Electrical characteristics
190
5.3.15 MIPI D-PHY regulator characteristics
The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.
IDD(PLL) PLL power consumption on VDD12
fVCO_OUT = 500 MHz - 0.55 0.70
mAfVCO_OUT = 600 MHz - 0.65 0.80
fVCO_OUT = 1000 MHz - 0.95 1.20
1. Based on test during characterization.
Table 47. DSI-PLL characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 48. DSI regulator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
VDD12DSI 1.2 V internal voltage on VDD12DSI - 1.15 1.20 1.30 V
CEXT External capacitor on VCAPDSI - 1.1 2.2 3.3 μF
ESR External Serial Resistor - 0 25 600 mΩ
IDDDSIREG Regulator power consumption - 100 120 125 µA
IDDDSI
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
Ultra Low Power Mode
(Reg. ON + PLL OFF) -290600
µA
Stop State
(Reg. ON + PLL OFF) -290600
IDDDSILP
DSI system current consumption on
VDDDSI in LP mode communication(2)
10 MHz escape clock
(Reg. ON + PLL OFF) -4.35.0
mA
20 MHz escape clock
(Reg. ON + PLL OFF) -4.35.0
IDDDSIHS
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode communication(3)
300 Mbps - 1 data lane
(Reg. ON + PLL ON) -8.08.8
mA
300 Mbps - 2data lane
(Reg. ON + PLL ON) - 11.4 12.5
500 Mbps - 1 data lane
(Reg. ON + PLL ON) -13.514.7
500 Mbps - 2data lane
(Reg. ON + PLL ON) -18.019.6
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode with CLK like payload
500 Mbps - 2data lane
(Reg. ON + PLL ON) -21.423.3
tWAKEUP Startup delay CEXT = 2.2 µF - 110 - µs
CEXT = 3.3 µF - - 160
IINRUSH Inrush current on VDDDSI External capacitor load at start - 60 200 mA
1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.
Electrical characteristics STM32F469xx
128/217 DocID028196 Rev 4
5.3.16 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 49. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max Unit
IDD Supply current
Write / Erase 8-bit mode, VDD = 1.7 V - 5 -
mAWrite / Erase 16-bit mode, VDD = 2.1 V - 8 -
Write / Erase 32-bit mode, VDD = 3.3 V - 12 -
Table 50. Flash memory programming
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog Word programming time Program/erase parallelism
(PSIZE) = x 8/16/32 -16100
(2) µs
tERASE16KB Sector (16 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 400 800
ms
Program/erase parallelism
(PSIZE) = x 16 - 300 600
Program/erase parallelism
(PSIZE) = x 32 - 250 500
tERASE64KB Sector (64 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 1200 2400
ms
Program/erase parallelism
(PSIZE) = x 16 - 700 1400
Program/erase parallelism
(PSIZE) = x 32 - 550 1100
tERASE128KB Sector (128 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 -24
s
Program/erase parallelism
(PSIZE) = x 16 -1.32.6
Program/erase parallelism
(PSIZE) = x 32 -12
DocID028196 Rev 4 129/217
STM32F469xx Electrical characteristics
190
tME Mass erase time
Program/erase parallelism
(PSIZE) = x 8 -1632
s
Program/erase parallelism
(PSIZE) = x 16 -1122
Program/erase parallelism
(PSIZE) = x 32 -816
tBE Bank erase time
Program/erase parallelism
(PSIZE) = x 8 -1632
Program/erase parallelism
(PSIZE) = x 16 -1122
Program/erase parallelism
(PSIZE) = x 32 -816
Vprog Programming voltage
32-bit program operation 2.7 - 3.6
V16-bit program operation 2.1 - 3.6
8-bit program operation 1.7 - 3.6
1. Based on test during characterization.
2. The maximum programming time is measured after 100K erase operations.
Table 51. Flash memory programming with VPP
Symbol Parameter Conditions Min(1) Typ Max(1)
1. Guaranteed by design.
Unit
tprog Double word programming
TA = 0 to +40 °C
VDD = 3.3 V
VPP = 8.5 V
-16100
(2)
2. The maximum programming time is measured after 100K erase operations.
µs
tERASE16KB Sector (16 KB) erase time - 230 -
mstERASE64KB Sector (64 KB) erase time - 490 -
tERASE128KB Sector (128 KB) erase time - 875 -
tME Mass erase time - 6.9 - s
tBE Bank erase time - - 6.9 - s
Vprog Programming voltage - 2.7 - 3.6
V
VPP VPP voltage range - 7 - 9
IPP
Minimum current sunk on
the VPP pin -10--mA
tVPP(3)
3. VPP should only be connected during programming/erasing.
Cumulative time during
which VPP is applied - - - 1 hour
Table 50. Flash memory programming (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Electrical characteristics STM32F469xx
130/217 DocID028196 Rev 4
Table 52. Flash memory endurance and data retention
5.3.17 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 53. They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Symbol Parameter Conditions Value Unit
Min(1)
1. Based on test during characterization.
NEND Endurance TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions) 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Years1 kcycle(2) at TA = 105 °C 10
10 kcycles(2) at TA = 55 °C 20
Table 53. EMS characteristics
Symbol Parameter Conditions Level/Class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD = 3.3 V, TFBGA216,
TA = +25 °C, fHCLK = 168 MHz,
conforming to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TFBGA216,
TA = +25 °C, fHCLK = 168 MHz,
conforming to IEC 61000-4-2
4A
DocID028196 Rev 4 131/217
STM32F469xx Electrical characteristics
190
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•Corrupted program counter
•Unexpected reset
•Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
5.3.18 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards.
Table 54. EMI characteristics
Symbol Parameter Conditions Monitored
frequency ba nd
Max vs. [fHSE/fCPU]Unit
8/168 MHz 8/180 MHz
SEMI Peak level
VDD = 3.3 V, TA = 25 °C, TFBGA216
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks
enabled, clock dithering disabled.
0.1 to 30 MHz 2 2
dBµV30 to 130 MHz 4 1
130 MHz to 1GHz 10 10
SAE EMI Level 3 3 -
VDD = 3.3 V, TA = 25 °C, TFBGA216
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks
enabled, clock dithering enabled
0.1 to 30 MHz 5 -10
dBµV30 to 130 MHz 3 -15
130 MHz to 1GHz 8 0
SAE EMI level 2 2 -
Electrical characteristics STM32F469xx
132/217 DocID028196 Rev 4
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•A supply overvoltage is applied to each power supply pin
•A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
5.3.19 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 57.
Table 55. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge
voltage
(human body model)
TA = +25 °C
conforming to ANSI/ESDA/JEDEC JS-001 2 2000
V
VESD(CDM)
Electrostatic discharge
voltage
(charge device model)
TA = +25 °C conforming to ANSI/ESD S5.3.1,
LQFP100, LQFP144, LQFP176, LQFP208,
UFBGA169, UFBGA176, TFBGA216 and
WLCSP148 packages
C3 250
1. Guaranteed based on test during characterization.
Table 56. Electrical sensitivities(1)
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
1. MSV on PA4 and PA5 is 5 V, versus 5.4 V on all IOs.
DocID028196 Rev 4 133/217
STM32F469xx Electrical characteristics
190
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
5.3.20 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL
compliant.
Table 57. I/O current injection susceptibility(1)
1. NA = not applicable.
Symbol Description
Functional susceptibility
Unit
Negative
injection Positive
injection
IINJ
Injected current on BOOT0 and NRST pins −0NA
mA
Injected current on DSIHOST_D0P,
DSIHOST_D0N, DSIHOST_D1P, DSIHOST_D0N,
DSIHOST_CKP, DSIHOST_CKN pins
−00
Injected current on PA0 and PC0 pins −0NA
Injected current on any other FT pin −5NA
Injected current on any other pin −5+ 5
Table 58. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL
FT, TTa and NRST I/O input low
level voltage 1.7 V≤VDD≤ 3.6 V - -
0.35VDD −0.04(1)
V
0.3VDD(2)
BOOT0 I/O input low level
voltage
1.75 V≤VDD ≤ 3.6 V,
–40 °C≤TA≤ 105 °C --
0.1VDD+0.1(1)
1.7 V≤VDD ≤ 3.6 V,
0°C
≤TA≤ 105 °C --
VIH
FT, TTa and NRST I/O input
high level voltage(5) 1.7 V≤VDD≤ 3.6 V
0.45VDD+0.3(1)
--
0.7VDD(2)
BOOT0 I/O input high level
voltage
1.75 V≤VDD ≤ 3.6 V,
–40 °C≤TA≤ 105 °C
0.17VDD+0.7(1) --
1.7 V≤VDD ≤ 3.6 V,
0°C≤TA≤ 105 °C
Electrical characteristics STM32F469xx
134/217 DocID028196 Rev 4
VHYS
FT, TTa and NRST I/O input
hysteresis 1.7 V≤VDD≤ 3.6 V 10%VDD(3) --
V
BOOT0 I/O input hysteresis
1.75 V≤VDD ≤ 3.6 V, –
40 °C≤TA≤ 105 °C
0.1 - -
1.7 V≤VDD ≤ 3.6 V,
0°C≤TA≤ 105 °C
Ilkg
I/O input leakage current (4) VSS ≤VIN ≤ VDD --±1
µA
I/O FT input leakage current (5) VIN = 5V --3
RPU
Weak pull-up
equivalent
resistor(6)
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID) VIN = VSS
30 40 50
kΩ
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
71014
RPD
Weak pull-
down
equivalent
resistor(7)
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID) VIN = VDD
30 40 50
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
71014
CIO(8) I/O pin capacitance - - 5 - pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 57
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 57
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Based on test during characterization.
Table 58. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
DocID028196 Rev 4 135/217
STM32F469xx Electrical characteristics
190
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 39.
Figure 39. FT I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which
can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2. In particular:
•The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 15).
•The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 15).
069
9''9
9,/9,+9
7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,+PLQ 9''
7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9''
%DVHGRQ'HVLJQVLPXODWLRQV9,/PD[ 9''
77/UHTXLUHPHQW
9,+PLQ 9
77/UHTXLUHPHQW9,/PD[
9
$UHDQRW
GHWHUPLQHG
%DVHGRQ'HVLJQVLPXODWLRQV9,+PLQ 9''
Electrical characteristics STM32F469xx
136/217 DocID028196 Rev 4
Output voltage levels
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17. All I/Os are CMOS and TTL compliant.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 40 and
Table 60, respectively.
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
Table 59. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output low level voltage for an I/O pin CMOS port(2)
IIO = +8 mA
2.7 V ≤ VDD ≤ 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
-0.4
V
VOH(3)
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high level voltage for an I/O pin VDD −0.4 -
VOL (1) Output low level voltage for an I/O pin TTL port(2)
IIO =+ 8mA
2.7 V ≤ VDD ≤ 3.6 V
-0.4
VOH (3) Output high level voltage for an I/O pin 2.4 -
VOL(1) Output low level voltage for an I/O pin IIO = +20 mA
2.7 V ≤ VDD ≤ 3.6 V
-1.3
(4)
4. Based on characterization data.
VOH(3) Output high level voltage for an I/O pin VDD −1.3(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +6 mA
1.8 V ≤ VDD ≤ 3.6 V
-0.4
(4)
VOH(3) Output high level voltage for an I/O pin VDD −0.4(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +4 mA
1.7 V ≤ VDD ≤ 3.6V
-0.4
(5)
5. Guaranteed by design.
VOH(3) Output high level voltage for an I/O pin VDD −0.4(5) -
DocID028196 Rev 4 137/217
STM32F469xx Electrical characteristics
190
Table 60. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] bit
value(1) Symbol Parameter Conditions Min Typ Max Unit
00
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD ≥ 2.7 V - - 4
MHz
CL = 50 pF, VDD ≥ 1.7 V - - 2
CL = 10 pF, VDD ≥ 2.7 V - - 8
CL = 10 pF, VDD ≥ 1.8 V - - 4
CL = 10 pF, VDD ≥ 1.7 V - - 3
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 50 pF, VDD = 1.7 V to
3.6 V --100ns
01
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD≥ 2.7 V - - 25
MHz
CL = 50 pF, VDD≥ 1.8 V - - 12.5
CL = 50 pF, VDD≥ 1.7 V - - 10
CL = 10 pF, VDD ≥ 2.7 V - - 50
CL = 10 pF, VDD≥ 1.8 V - - 20
CL = 10 pF, VDD≥ 1.7 V - - 12.5
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 50 pF, VDD ≥ 2.7 V - - 10
ns
CL = 10 pF, VDD ≥ 2.7 V - - 6
CL = 50 pF, VDD ≥ 1.7 V - - 20
CL = 10 pF, VDD ≥ 1.7 V - - 10
10
fmax(IO)out Maximum frequency(3)
CL = 40 pF, VDD ≥ 2.7 V - - 50(4)
MHz
CL = 10 pF, VDD ≥ 2.7 V - - 100(4)
CL = 40 pF, VDD ≥ 1.7 V - - 25
CL = 10 pF, VDD ≥ 1.8 V - - 50
CL = 10 pF, VDD ≥ 1.7 V - - 42.5
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 40 pF, VDD ≥2.7 V - - 6
ns
CL = 10 pF, VDD ≥ 2.7 V - - 4
CL = 40 pF, VDD ≥ 1.7 V - - 10
CL = 10 pF, VDD ≥ 1.7 V - - 6
Electrical characteristics STM32F469xx
138/217 DocID028196 Rev 4
Figure 40. I/O AC characteristics de f i n iti on
11
fmax(IO)out Maximum frequency(3)
CL = 30 pF, VDD ≥ 2.7 V - - 100(4)
MHz
CL = 30 pF, VDD ≥ 1.8 V - - 50
CL = 30 pF, VDD ≥ 1.7 V - - 42.5
CL = 10 pF, VDD≥ 2.7 V - - 180(4)
CL = 10 pF, VDD ≥ 1.8 V - - 100
CL = 10 pF, VDD ≥ 1.7 V - - 72.5
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 30 pF, VDD ≥ 2.7 V - - 4
ns
CL = 30 pF, VDD ≥1.8 V - - 6
CL = 30 pF, VDD ≥1.7 V - - 7
CL = 10 pF, VDD ≥ 2.7 V - - 2.5
CL = 10 pF, VDD ≥1.8 V - - 3.5
CL = 10 pF, VDD ≥1.7 V - - 4
- tEXTIpw
Pulse width of external signals
detected by the EXTI
controller
-10--ns
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 40.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Table 60. I/O AC characteristics(1)(2) (continued)
OSPEEDRy
[1:0] bit
value(1) Symbol Parameter Conditions Min Typ Max Unit
DLG
WU,2RXW
287387
(;7(51$/
21&/
0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI7DQGLIWKHGXW\F\FOHLV
ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´
7
WI,2RXW
DocID028196 Rev 4 139/217
STM32F469xx Electrical characteristics
190
5.3.21 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 58).
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
Figure 41. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 61. Otherwise the reset is not taken into account by the device.
Table 61. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ
VF(NRST)(2) NRST Input filtered pulse - - - 100
ns
VNF(NRST)(2) NRST Input not filtered pulse VDD > 2.7 V 300 - -
TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
DLF
670)
538
1567
9''
)LOWHU
,QWHUQDO5HVHW
)
([WHUQDO
UHVHWFLUFXLW
Electrical characteristics STM32F469xx
140/217 DocID028196 Rev 4
5.3.22 TIM timer characteristics
The parameters given in Table 62 are guaranteed by design. Refer to Section 5.3.20 for
details on the input/output alternate function characteristics (output compare, input capture,
external clock, PWM output).
5.3.23 Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•Standard-mode (Sm): with a bit rate up to 100 kbit/s
•Fast-mode (Fm): with a bit rate up to 400 kbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0386 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Refer to
Section 5.3.20 for more details on the I2C I/O characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 62. TIMx characteristics(1)(2)
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
Symbol Parameter Conditions(3)
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =
4x PCLKx.
Min Max Unit
tres(TIM) Timer resolution time
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
180 MHz 1-
tTIMxCLK
AHB/APBx prescaler>4,
fTIMxCLK = 90 MHz 1-
tTIMxCLK
fEXT Timer external clock
frequency on CH1 to CH4 fTIMxCLK = 180 MHz
0fTIMxCLK/2 MHz
ResTIM Timer resolution - 16/32 bit
tMAX_COUNT Maximum possible count
with 32-bit counter -65536 ×
65536 tTIMxCLK
Table 63. I2C analog filter characteristics(1)
Symbol Parameter Min Max Unit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2) 150(3) ns
DocID028196 Rev 4 141/217
STM32F469xx Electrical characteristics
190
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 64 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).
1. Guaranteed based on test during characterization.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
Table 64. SPI dynamic characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode, 2.7 V≤VDD≤3.6 V,
SPI1,4,5,6, --45
MHz
Master mode, 1.71 V≤VDD≤3.6 V,
SPI1,4,5,6 - - 22.5(2)
Master transmitter mode,
1.7 V≤VDD≤3.6 V, SPI1,4,5,6 --45
Slave full duplex mode,
2.7 V≤VDD≤3.6 V, SPI1,4,5,6 - - 22.5
Slave transmitter mode,
1.71 V≤VDD≤3.6 V, SPI1,4,5,6 --33
Slave transmitter mode,
2.7 V≤VDD≤3.6 V, SPI1,4,5,6 --45
Slave mode, 1.71 V≤VDD≤3.6 V,
SPI2,3 - - 22.5
Duty(SCK) Duty cycle of SPI clock
frequency Slave mode 30 50 70 %
Electrical characteristics STM32F469xx
142/217 DocID028196 Rev 4
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode, SPI presc = 2 TPCLK −1.5 TPCLK TPCLK+1.5
ns
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4TPCLK --
th(NSS) NSS hold time Slave mode, SPI presc = 2 2TPCLK
tsu(MI) Data input setup time
Master mode 2 - -
tsu(SI) Slave mode 3 - -
th(MI) Data input hold time
Master mode 4 - -
th(SI) Slave mode 2 - -
ta(SO) Data output access time Slave mode, SPI presc = 2 7 - 21
tdis(SO) Data output disable time Slave mode 5 - 12
tv(SO) Data output valid time
Slave mode (after enable edge),
2.7V ≤ VDD ≤ 3.6V -1115
Slave mode (after enable edge),
1.71 V≤VDD≤3.6 V -1111.5
th(SO) Data output hold time Slave mode (after enable edge) 6 - -
tv(MO) Data output valid time Master mode (after enable edge) - 4.5 5
th(MO) Data output hold time Master mode (after enable edge) 2 - -
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Table 64. SPI dynamic characteristics(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit
DocID028196 Rev 4 143/217
STM32F469xx Electrical characteristics
190
Figure 42. SPI timing diagram - slave mode and CPHA = 0
Figure 43. SPI timing diagram - slave mode and CPHA = 1(1)
ai14134c
SCK Input
CPHA=0
MOSI
INPUT
MISO
OUTPUT
CPHA=0
MSB O UT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS)
tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK) tdis(SO)
tsu(SI)
th(SI)
DLE
166LQSXW
W68166 WF6&. WK166
6&.LQSXW
&3+$
&32/
&3+$
&32/
WZ6&.+
WZ6&./
WD62 WY62 WK62 WU6&.
WI6&. WGLV62
0,62
287387
026,
,1387
WVX6, WK6,
06%287
06%,1
%,7287 /6%287
/6%,1
%,7,1
Electrical characteristics STM32F469xx
144/217 DocID028196 Rev 4
Figure 44. SPI timing diagram - master mode(1)
ai14136
SCK Input
CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BIT6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BIT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
th(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
DocID028196 Rev 4 145/217
STM32F469xx Electrical characteristics
190
I2S interface characteristics
Unless otherwise specified, the parameters given in Table 65 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CK, SD, WS).
Note: Refer to the I2S section o f RM0386 reference manual for more details on the sampling
frequency (F S).
fMCK, fCK, and DCK values reflect only the digit al perip heral behavior, source clock precision
might slightly change the values. The values of these parameters might be slightly impacted
by the source clock precision. DCK depends mainly on the value of ODD bit. The digital
Table 65 . I2S dynamic characteristics(1)
Symbol Parameter Conditions Min Max Unit
fMCK I2S Main clock output - 256x8K 256xFs(2)
MHz
fCK I2S clock frequency
Master data - 64xFs
Slave data - 64xFs
DCK I2S clock frequency duty cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode 0 5
ns
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time
Slave mode 3.5 -
Slave mode
PCM short pulse mode(3) 3.5 -
th(WS) WS hold time
Slave mode 0.5 -
Slave mode
PCM short pulse mode(3) 1-
tsu(SD_MR) Data input setup time
Master receiver 5 -
tsu(SD_SR) Slave receiver 1.5 -
th(SD_MR) Data input hold time
Master receiver 5 -
th(SD_SR) Slave receiver 1.5 -
tv(SD_ST) Data output valid time
Slave transmitter (after enable edge) - 19
tv(SD_MT) Master transmitter (after enable edge) - 2.50
th(SD_ST) Data output hold time
Slave transmitter (after enable edge) 5 -
th(SD_MT) Master transmitter (after enable edge) 0 -
1. Guaranteed based on test during characterization.
2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.
Electrical characteristics STM32F469xx
146/217 DocID028196 Rev 4
contribution leads to a minimu m value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of
(I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition.
Figure 45. I2S slave timing diagram (Philips protocol)(1)
1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 46. I2S master timing dia gram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CK Input
CPOL = 0
CPOL = 1
tc(CK)
WS input
SDtransmit
SDreceive
tw(CKH) tw(CKL)
tsu(WS) tv(SD_ST) th(SD_ST)
th(WS)
tsu(SD_SR) th(SD_SR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14881b
LSB receive(2)
LSB transmit(2)
CK output
CPOL = 0
CPOL = 1
tc(CK)
WS output
SDreceive
SDtransmit
tw(CKH)
tw(CKL)
tsu(SD_MR)
tv(SD_MT) th(SD_MT)
th(WS)
th(SD_MR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14884b
tf(CK) tr(CK)
tv(WS)
LSB receive
(2)
LSB transmit
(2)
DocID028196 Rev 4 147/217
STM32F469xx Electrical characteristics
190
SAI characteristics
Unless otherwise specified, the parameters given in Table 66 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C=30 pF
•Measurement points are performed at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function
characteristics (SCK,SD,WS).
Table 66. SAI characte ris tic s(1)
Symbol Parameter Conditions Min Max Unit
fMCKL SAI Main clock output - 256 x 8K 256xFs
MHz
fCK SAI clock frequency(2) Master data: 32 bits - 128xFs(3)
Slave data: 32 bits - 128xFs
tv(FS) FS valid time
Master mode,
2.7V ≤ VDD ≤ 3.6V -17
ns
Master mode,
1.71V ≤ VDD ≤ 3.6V -23
tsu(FS) FS setup time Slave mode 10 -
th(FS) FS hold time Slave mode 0 -
tsu(SD_MR) Data input setup time
Master receiver 1 -
tsu(SD_SR) Slave receiver 2 -
th(SD_MR) Data input hold time
Master receiver 6 -
th(SD_SR) Slave receiver 1 -
th(SD_B_ST) Data output valid time
Slave transmitter (after enable edge),
2.7V ≤ VDD ≤ 3.6V -14
Slave transmitter (after enable edge),
1.71V ≤ VDD ≤ 3.6V -23
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 9 -
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge),
2.7V ≤ VDD ≤ 3.6V -20
Master transmitter (after enable edge),
1.71V ≤ VDD ≤ 3.6V -26
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 -
1. Guaranteed based on test during characterization.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With Fs = 192 kHz.
Electrical characteristics STM32F469xx
148/217 DocID028196 Rev 4
Figure 47. SAI master timing waveform s
Figure 48. SAI slave timing wavef orms
-36
3!)?3#+?8
3!)?&3?8
OUTPUT
F3#+
3!)?3$?8
TRANSMIT
TV&3
3LOTN
3!)?3$?8
RECEIVE
TH&3
3LOTN
TV3$?-4 TH3$?-4
3LOTN
TSU3$?-2 TH3$?-2
-36
3!)?3#+?8
3!)?&3?8
INPUT
3!)?3$?8
TRANSMIT
TSU&3
3LOTN
3!)?3$?8
RECEIVE
TW#+(?8 TH&3
3LOTN
TV3$?34 TH3$?34
3LOTN
TSU3$?32
TW#+,?8
TH3$?32
F3#+
DocID028196 Rev 4 149/217
STM32F469xx Electrical characteristics
190
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 whe n the feat ur e is en ab led .
Table 67. USB OTG full speed startup time
Symbol Parameter Max Unit
tSTARTUP(1)
1. Guaranteed by design.
USB OTG full speed transceiver startup time 1 µs
Table 68. USB OTG full speed DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Typ. Max.(1) Unit
Input
levels
VDD
USB OTG full speed
transceiver operating
voltage
-3.0
(2)
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
-3.6
V
VDI(3)
3. Guaranteed by design.
Differential input sensitivity I(USB_FS_DP/DM,
USB_HS_DP/DM) 0.2 - -
VCM(3) Differential common mode
range Includes VDI range 0.8 - 2.5
VSE(3) Single ended receiver
threshold - 1.3 - 2.0
Output
levels
VOL Static output level low RL of 1.5 kΩ to 3.6 V(4)
4. RL is the load connected on the USB OTG full speed drivers.
--0.3
VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
RPD
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM)
VIN = VDD
17 21 24
kΩ
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
0.65 1.1 2.0
RPU
PA12, PB15 (USB_FS_DP,
USB_HS_DP) VIN = VSS 1.5 1.8 2.1
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS 0.25 0.37 0.55
Electrical characteristics STM32F469xx
150/217 DocID028196 Rev 4
Figure 49. USB OTG full speed timings: definition of data signal rise and fall time
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 72 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 71
and VDD supply voltage conditions summarized in Table 70, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
•Capacitive load C = 20 pF / 15 pF, unless otherwise specified
•Measurement points are done at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.
Table 69. USB OTG full speed electrical characteristics(1)
1. Guaranteed by design.
Driver characteristics
Symbol Parameter Conditions Min Max Unit
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420
ns
tfFall time(2) CL = 50 pF 4 20
trfm Rise/ fall time matching tr/tf90 110 %
VCRS Output signal crossover voltage - 1.3 2.0 V
ZDRV Output driver impedance(3)
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
Driving
high or low 28 44 Ω
Table 70. USB HS DC electrical characteristics
Symbol Parameter Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input level VDD USB OTG HS operating voltage 1.7 3.6 V
ai14137
tf
Differential
Data Lines
VSS
V
CRS
tr
Crossover
points
DocID028196 Rev 4 151/217
STM32F469xx Electrical characteristics
190
Figure 50. ULPI timing diagram
Table 71. USB HS clock timing parameters(1)
1. Guaranteed by design.
Symbol Parameter Min Typ Max Unit
-fHCLK value to guarantee proper operation of
USB HS interface 30 - -
MHz
FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66
FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03
DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60
%
DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025
tSTEADY
Time to reach the steady state frequency and
duty cycle after the first transition --1.4ms
tSTART_DEV Clock startup time after the
de-assertion of SuspendM
Peripheral - - 5.6
ms
tSTART_HOST Host - - -
tPREP
PHY preparation time after the first transition
of the input clock ---µs
#LOCK
#ONTROL)N
5,0)?$)2
5,0)?.84
DATA)N
BIT
#ONTROLOUT
5,0)?340
DATAOUT
BIT
T$$
T$#
T($
T3$
T(#
T3#
AIC
T$#
Electrical characteristics STM32F469xx
152/217 DocID028196 Rev 4
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 73, Table 74 and Table 75 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency and VDD supply voltage conditions summarized in Table 17, with the following
configuration:
•Output speed is set to OSPEEDRy[1:0] = 10
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.
Table 73 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 51 shows the corresponding timing diagram.
Figure 51. Ethernet SMI timing diagram
Table 72. Dynamic characteristics: USB ULPI(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Conditions Min. Typ. Max. Unit
tSC
Control in (ULPI_DIR, ULPI_NXT)
setup time -2.0--
ns
tHC
Control in (ULPI_DIR, ULPI_NXT)
hold time -1.5--
tSD Data in setup time - 1.0 - -
tHD Data in hold time - 1.0 - -
tDC/tDD Data/control output delay
2.7 V < VDD < 3.6 V,
CL = 20 pF -7.59.0
2.7 V < VDD < 3.6 V,
CL = 15 pF and
-40 < T < 125°C
- 7.5 12.0
1.7 V < VDD < 3.6 V,
CL = 15 pF and
-40 < T < 90°C
-7.511.5
069
(7+B0'&
(7+B0',22
(7+B0',2,
W0'&
WG0',2
WVX0',2 WK0',2
DocID028196 Rev 4 153/217
STM32F469xx Electrical characteristics
190
Table 74 gives the list of Ethernet MAC signals for the RMII and Figure 52 shows the
corresponding timing diagram.
Figure 52. Ethernet RMII timing diagram
Table 73. Dynamics characteristics: Ethernet MAC signals for SMI(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Min Typ Max Unit
tMDC MDC cycle time(2.38 MHz) 400 400 403
ns
Td(MDIO) Write data valid time THCLK - 1 THCLK THCLK + 1.5
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
RMII_REF_CLK
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
td(TXEN)
td(TXD)
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
ai1566
7
Electrical characteristics STM32F469xx
154/217 DocID028196 Rev 4
Table 75 gives the list of Ethernet MAC signals for MII and Figure 52 shows the
corresponding timing diagram.
Figure 53. Etherne t M II timing di ag ram
Table 74 . D yn a mic s ch a r ac te ris ti cs: Ethernet MAC signals for RMII(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Min Typ Max Unit
tsu(RXD) Receive data setup time 2.5 - -
ns
tih(RXD) Receive data hold time 2.0 - -
tsu(CRS) Carrier sense setup time 0.5 - -
tih(CRS) Carrier sense hold time 1.5 - -
td(TXEN) Transmit enable valid delay time 5.5 6.5 11
td(TXD) Transmit data valid delay time 6.0 6.5 11
Table 75. Dynamics characteristics: Ethernet MAC signals for MII(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Min Typ Max Unit
tsu(RXD) Receive data setup time 1 - -
ns
tih(RXD) Receive data hold time 3 - -
tsu(DV) Data valid setup time 0 - -
tih(DV) Data valid hold time 2.5 - -
tsu(ER) Error setup time 0 - -
tih(ER) Error hold time 2 - -
td(TXEN) Transmit enable valid delay time 0 7 13
td(TXD) Transmit data valid delay time 0 7 13
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
t
d(TXEN)
t
d(TXD)
t
su(RXD)
t
su(ER)
t
su(DV)
t
ih(RXD)
t
ih(ER)
t
ih(DV)
ai15668
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
DocID028196 Rev 4 155/217
STM32F469xx Electrical characteristics
190
CAN (controller area network) interface
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CANx_TX and CANx_RX).
5.3.24 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 76 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 17.
Table 76. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply
VDDA − VREF+ < 1.2 V
1.7(1) -3.6
VVREF+ Positive reference voltage 1.7(1) -V
DDA
VREF- Negative reference voltage - 0 -
fADC ADC clock frequency VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz
VDDA = 2.4 to 3.6 V 0.6 30 36
fTRIG(2) External trigger frequency
fADC = 30 MHz,
12-bit resolution - - 1764 kHz
---171/f
ADC
VAIN Conversion voltage range(3) -
0
(VSSA or VREF-
tied to ground)
-V
REF+ V
RAIN(2) External input impedance Details in Equation 1 --50kΩ
RADC(2)(4) Sampling switch resistance - - - 6 kΩ
CADC(2) Internal sample and hold
capacitor --47pF
tlat(2) Injection trigger conversion
latency
fADC = 30 MHz - - 0.100 µs
---3
(5) 1/fADC
tlatr(2) Regular trigger conversion
latency
fADC = 30 MHz - - 0.067 µs
--2
(5) 1/fADC
tS(2) Sampling time fADC = 30 MHz 0.100 - 16 µs
- 3 - 480 1/fADC
tSTAB(2) Power-up time - - 2 3 µs
Electrical characteristics STM32F469xx
156/217 DocID028196 Rev 4
Equation 1: RAIN max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
tCONV(2) Total conversion time
(including sampling time)
fADC = 30 MHz
12-bit resolution 0.50 - 16.40
µs
fADC = 30 MHz
10-bit resolution 0.43 - 16.34
fADC = 30 MHz
8-bit resolution 0.37 - 16.27
fADC = 30 MHz
6-bit resolution 0.30 - 16.20
9 to 492
(tS for sampling +n-bit resolution for successive approximation) 1/fADC
fS(2)
Sampling rate
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
Single ADC --2
Msps
12-bit resolution
Interleave Dual ADC
mode
--3.75
12-bit resolution
Interleave Triple ADC
mode
--6
IVREF+(2)
ADC VREF
DC current consumption in
conversion mode
- - 300 500 µA
IVDDA(2)
ADC VDDA
DC current consumption in
conversion mode
--1.61.8mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Based on test during characterization.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 76.
Table 76. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
RAIN k0.5–()
fADC CADC 2N2+
()ln××
---------------------------------------------------------------- RADC
–=
DocID028196 Rev 4 157/217
STM32F469xx Electrical characteristics
190
a
Table 77. ADC static accuracy at fADC = 18 MHz(1)
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
Symbol Parameter Test conditions Typ Max(2)
2. Based on test during characterization.
Unit
ET Total unadjusted error
fADC =18 MHz
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
±3 ±4
LSB
EO Offset error ±2 ±3
EG Gain error ±1 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±2 ±3
Table 78. ADC static accuracy at fADC = 30 MHz(1)
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
Symbol Parameter Test co nditions Typ Max(2)
2. Based on test during characterization.
Unit
ET Total unadjusted error
fADC = 30 MHz,
RAIN < 10 kΩ,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA − VREF < 1.2 V
±2 ±5
LSB
EO Offset error ±1.5 ±2.5
EG Gain error ±1.5 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±1.5 ±3
Table 79. ADC static accuracy at fADC = 36 MHz(1)
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
Symbol Parameter Test conditions Typ Max(2)
2. Based on test during characterization.
Unit
ET Total unadjusted error
fADC =36 MHz,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA − VREF < 1.2 V
±4 ±7
LSB
EO Offset error ±2 ±3
EG Gain error ±3 ±6
ED Differential linearity error ±2 ±3
EL Integral linearity error ±3 ±6
Electrical characteristics STM32F469xx
158/217 DocID028196 Rev 4
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 5.3.20 does not affect the ADC accuracy.
Table 80. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol Par ameter Test conditions Min Typ Max Unit
ENOB Effective number of bits fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
10.3 10.4 - bits
SINAD Signal-to-noise and distortion ratio 64 64.2 -
dBSNR Signal-to-noise ratio 64 65 -
THD Total harmonic distortion −67 −72 -
1. Guaranteed based on test during characterization.
Table 81. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit
ENOB Effective number of bits fADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
10.6 10.8 - bits
SINAD Signal-to noise and distortion ratio 66 67 -
dBSNR Signal-to noise ratio 64 68 -
THD Total harmonic distortion −70 −72 -
1. Guaranteed based on test during characterization.
DocID028196 Rev 4 159/217
STM32F469xx Electrical characteristics
190
Figure 54. ADC accuracy characteristics
1. See also Table 78.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 55. Typical connection diagram using the ADC
1. Refer to Table 76 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
AIC
%/
%'
, 3")$%!,
%4
%$
%,
6$$!
633!
62%&
ORDEPENDINGONPACKAGE=
6$$!
;,3" )$%!,
DL
670)
9''
$,1[
,/$
9
97
5$,1
&SDUDVLWLF
9$,1
9
97
5$'&
&$'&
ELW
FRQYHUWHU
6DPSOHDQGKROG$'&
FRQYHUWHU
Electrical characteristics STM32F469xx
160/217 DocID028196 Rev 4
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 56 or Figure 57,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 56. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ and VREF– inputs are both available on UFBGA176 and TFBGA216. VREF+ is also available on
LQFP100, LQFP144, LQFP176 and LQFP208. When VREF+ and VREF– are not available, they are
internally connected to VDDA and VSSA.
Figure 57. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ and VREF– inputs are both available on UFBGA176 and TFBGA216. VREF+ is also available on
LQFP100, LQFP144, LQFP176 and LQFP208. When VREF+ and VREF– are not available, they are
internally connected to VDDA and VSSA.
069
670)
)Q)
)Q)
95()
966$95()
9''$
069
670)
)Q)
95()9''$
95()9''$
DocID028196 Rev 4 161/217
STM32F469xx Electrical characteristics
190
5.3.25 Temperature sensor characteristics
5.3.26 VBAT monitoring characteristics
5.3.27 Reference voltage
The parameters given in Table 85 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
Table 82. Temperature sensor characteristics
Symbol Parameter Min Typ Max Unit
TL(1) VSENSE linearity with temperature - ±1±2°C
Avg_Slope(1) Average slope - 2.5 - mV/°C
V25(1) Voltage at 25 °C - 0.76 - V
tSTART(2) Startup time - 6 10
µs
TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - -
1. Based on test during characterization.
2. Guaranteed by design.
Table 83 . Temperatur e se n sor cal ib rat io n valu e s
Symbol Parameter Memory address
TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
Table 84. VBAT monitoring characteristics
Symbol Parameter Min Typ Max Unit
R Resistor bridge for VBAT -50-KΩ
QRatio on VBAT measurement - 4 -
Er(1) Error on Q –1 - +1 %
TS_vbat(2)(2) ADC sampling time when reading the VBAT
1 mV accuracy 5--µs
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
Table 85. internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V
TS_vrefint(1) ADC sampling time when reading the
internal reference voltage 10 - - µs
VRERINT_s(2) Internal reference voltage spread over the
temperature range VDD = 3V ± 10mV - 3 5 mV
Electrical characteristics STM32F469xx
162/217 DocID028196 Rev 4
5.3.28 DAC electrical characteristics
TCoeff(2) Temperature coefficient - 30 50 ppm/°C
tSTART(2) Startup time - 6 10 µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design
Table 85. internal reference voltage (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 86. Internal reference voltage calibration values
Symbol Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B
Table 87. DAC characteristics
Symbol Parameter Min Typ Max Unit Comments
VDDA Analog supply voltage 1.7(1) -3.6 V -
VREF+ Reference supply voltage 1.7(1) -3.6VV
REF+ ≤ VDDA
VSSA Ground 0- 0V -
RLOAD(2) Resistive load with buffer ON 5 - - kΩ-
RO(2) Impedance output with buffer
OFF --15kΩ
When the buffer is OFF, the Minimum
resistive load between DAC_OUT and
VSS to have a 1% accuracy is 1.5 MΩ
CLOAD(2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
DAC_OUT
min(2)
Lower DAC_OUT voltage
with buffer ON 0.2 - - V
It gives the maximum output excursion of
the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
(0x1C7) to (0xE38) at VREF+ = 1.7 V
DAC_OUT
max(2)
Higher DAC_OUT voltage
with buffer ON --
VDDA −
0.2 V
DAC_OUT
min(2)
Lower DAC_OUT voltage
with buffer OFF -0.5 - mV
It gives the maximum output excursion of
the DAC.
DAC_OUT
max(2)
Higher DAC_OUT voltage
with buffer OFF --
VREF+ −
1LSB V
IVREF+(4)
DAC DC VREF current
consumption in quiescent
mode (Standby mode)
-170240
µA
With no load, worst code (0x800) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
-5075
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
DocID028196 Rev 4 163/217
STM32F469xx Electrical characteristics
190
IDDA(4)
DAC DC VDDA current
consumption in quiescent
mode(3)
-280380µA
With no load, middle code (0x800) on the
inputs
-475625µA
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
DNL(4)
Differential non linearity
Difference between two
consecutive code-1LSB)
- - ±0.5 LSB Given for the DAC in 10-bit configuration.
- - ±2 LSB Given for the DAC in 12-bit configuration.
INL(4)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
- - ±1 LSB Given for the DAC in 10-bit configuration.
- - ±4 LSB Given for the DAC in 12-bit configuration.
Offset(4)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
- - ±10 mV Given for the DAC in 12-bit configuration
--±3LSB
Given for the DAC in 10-bit at VREF+ =
3.6 V
--±12LSB
Given for the DAC in 12-bit at VREF+ =
3.6 V
Gain
error(4) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration
tSETTLING(4)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±4LSB
-3 6µs
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(4) Total Harmonic Distortion
Buffer ON -- -dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Update
rate(2)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-- 1MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
tWAKEUP(4)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
-6.510µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and highest
possible ones.
PSRR+ (2)
Power supply rejection ratio
(to VDDA) (static DC
measurement)
- –67 –40 dB No RLOAD, CLOAD = 50 pF
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed based on test during characterization.
Table 87. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments
Electrical characteristics STM32F469xx
164/217 DocID028196 Rev 4
Figure 58. 12-bit buffered/non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
5.3.29 FMC characteristics
Unless otherwise specified, the parameters given in Tables 88 through 101 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 17, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output characteristics.
Asynchronous waveforms and timings
Figures 59 through 62 represent asynchronous waveforms, and Tables 88 through 95
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
•AddressSetupTime = 0x1
•AddressHoldTime = 0x1
•DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
•BusTurnAroundDuration = 0x0
•Capacitive load CL = 30 pF
5/
&/
%XIIHUHG1RQEXIIHUHG'$&
'$&B287[
%XIIHU
ELW
GLJLWDOWR
DQDORJ
FRQYHUWHU
DL9
DocID028196 Rev 4 165/217
STM32F469xx Electrical characteristics
190
Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
$ATA
&-#?.%
&-#?.",;=
&-#?$;=
T
V",?.%
TH$ATA?.%
&-#?./%
!DDRESS
&-#?!;=
T
V!?.%
&-#?.7%
TSU$ATA?.%
TW.%
-36
W./%
TTV./%?.% TH.%?./%
TH$ATA?./%
TH!?./%
TH",?./%
TSU$ATA?./%
&-#?.!$6
TV.!$6?.%
TW.!$6
&-#?.7!)4
TSU.7!)4?.%
TH.%?.7!)4
Electrical characteristics STM32F469xx
166/217 DocID028196 Rev 4
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 2THCLK − 0.5 2 THCLK+0.5
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1
tw(NOE) FMC_NOE low time 2THCLK 2THCLK+ 0.5
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time THCLK + 2.5 -
tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK +2 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - THCLK +1
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT
timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 7THCLK+0.5 7THCLK+1
ns
tw(NOE) FMC_NWE low time 5THCLK −1.5 5THCLK +2
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 -
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid 4THCLK+1 -
DocID028196 Rev 4 167/217
STM32F469xx Electrical characteristics
190
Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK 3THCLK+1
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK −0.5 THCLK+ 0.5
tw(NWE) FMC_NWE low time THCLK THCLK+ 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK +1.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high THCLK+0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 1.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK+0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK+ 2
th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - THCLK+ 0.5
.",
$ATA
&-#?.%X
&-#?.",;=
&-#?$;=
T
V",?.%
TH$ATA?.7%
&-#?./%
!DDRESS
&-#?!;=
T
V!?.%
TW.7%
&-#?.7%
TV.7%?.% TH.%?.7%
TH!?.7%
TH",?.7%
TV$ATA?.%
TW.%
-36
&-#?.!$6
TV.!$6?.%
TW.!$6
&-#?.7!)4
TSU.7!)4?.%
TH.%?.7!)4
Electrical characteristics STM32F469xx
168/217 DocID028196 Rev 4
Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR wr ite - NWAIT
timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8THCLK+1 8THCLK+2
ns
tw(NWE) FMC_NWE low time 6THCLK −16T
HCLK+2
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 -
.",
$ATA
&-#? .",;=
&-#? !$;=
T
V",?.%
TH$ATA?.%
!DDRESS
&-#? !;=
T
V!?.%
&-#?.7%
TV!?.%
-36
!DDRESS
&-#?.!$6
TV.!$6?.%
TW.!$6
TSU$ATA?.%
T
H!$?.!$6
&-#? .%
&-#?./%
TW.%
TW./%
TV./%?.% TH.%?./%
TH!?./%
TH",?./%
TSU$ATA?./% TH$ATA?./%
&-#?.7!)4
TSU.7!)4?.%
TH.%?.7!)4
DocID028196 Rev 4 169/217
STM32F469xx Electrical characteristics
190
Table 92. Asynchronous multiplexed PSRAM/NOR read timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK −13T
HCLK+0.5
ns
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK −0.5 2THCLK
ttw(NOE) FMC_NOE low time THCLK −1T
HCLK+1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 1 -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 2
tw(NADV) FMC_NADV low time THCLK −0.5 THCLK+0.5
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high) 0 -
th(A_NOE) Address hold time after FMC_NOE high THCLK −0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
tsu(Data_NE) Data to FMC_NEx high setup time THCLK+1.5 -
tsu(Data_NOE) Data to FMC_NOE high setup time THCLK+1 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 8THCLK+0.5 8THCLK+2
ns
tw(NOE) FMC_NWE low time 5THCLK −15T
HCLK +1.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK +1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 -
Electrical characteristics STM32F469xx
170/217 DocID028196 Rev 4
Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 94. Asynchronous multiplexed PSRAM/NOR write timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 4THCLK 4THCLK+0.5
ns
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK −1T
HCLK+0.5
tw(NWE) FMC_NWE low time 2THCLK 2THCLK+0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0.5 1
tw(NADV) FMC_NADV low time THCLK −0.5 THCLK+ 0.5
th(AD_NADV)
FMC_AD (address) valid hold time
after FMC_NADV high THCLK −2-
th(A_NWE) Address hold time after FMC_NWE high THCLK -
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK −2-
tv(BL_NE) FMC_NEx low to FMC_BL valid - 2
tv(Data_NADV) FMC_NADV high to Data valid - THCLK +1.5
th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 -
.",
$ATA
&-#? .%X
&-#? .",;=
&-#? !$;=
T
V",?.%
TH$ATA?.7%
&-#?./%
!DDRESS
&-#? !;=
T
V!?.%
TW.7%
&-#?.7%
TV.7%?.% TH.%?.7%
TH!?.7%
TH",?.7%
TV!?.%
TW.%
-36
!DDRESS
&-#?.!$6
TV.!$6?.%
TW.!$6
TV$ATA?.!$6
T
H!$?.!$6
&-#?.7!)4
TSU.7!)4?.%
TH.%?.7!)4
DocID028196 Rev 4 171/217
STM32F469xx Electrical characteristics
190
Synchronous waveforms and timings
Figures 63 through 66 represent synchronous waveforms and Table 96 through Table 99
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
•BurstAccessMode = FMC_BurstAccessMode_Enable;
•MemoryType = FMC_MemoryType_CRAM;
•WriteBurst = FMC_WriteBurst_Enable;
•CLKDivision = 1;
•DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
•CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period:
•For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 90 MHz at CL = 30 pF (on FMC_CLK).
•For 1.71 V≤ VDD<1.9 V, maximum FMC_CLK = 60 MHz at CL = 10 pF (on FMC_CLK).
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 9THCLK 9THCLK+0.5
ns
tw(NWE) FMC_NWE low time 7THCLK 7THCLK+2
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK–1 -
Electrical characteristics STM32F469xx
172/217 DocID028196 Rev 4
Figure 63. Synchronous multiplexed NOR/PSRAM read timings
&-#?#,+
&-#?.%X
&-#?.!$6
&-#?!;=
&-#?./%
&-#?!$;= !$;= $ $
&-#?.7!)4
7!)4#&'B
7!)40/,B
&-#?.7!)4
7!)4#&'B
7!)40/,B
TW#,+ TW#,+
$ATALATENCY
"53452.
TD#,+,.%X, TD#,+(.%X(
TD#,+,.!$6,
TD#,+,!6
TD#,+,.!$6(
TD#,+(!)6
TD#,+,./%, TD#,+(./%(
TD#,+,!$6
TD#,+,!$)6
TSU!$6#,+(
TH#,+(!$6
TSU!$6#,+( TH#,+(!$6
TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
-36
DocID028196 Rev 4 173/217
STM32F469xx Electrical characteristics
190
Table 96. Synchronous multiplexed NOR/PSRAM read timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK −1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 0
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+0.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK −0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 0.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 5 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
Electrical characteristics STM32F469xx
174/217 DocID028196 Rev 4
Figure 64. Synchronous multiplexed PSRAM write timings
&-#?#,+
&-#?.%X
&-#?.!$6
&-#?!;=
&-#?.7%
&-#?!$;= !$;= $ $
&-#?.7!)4
7!)4#&'B
7!)40/,B
TW#,+ TW#,+
$ATALATENCY
"53452.
TD#,+,.%X, TD#,+(.%X(
TD#,+,.!$6,
TD#,+,!6
TD#,+,.!$6(
TD#,+(!)6
TD#,+(.7%(
TD#,+,.7%,
TD#,+(.",(
TD#,+,!$6
TD#,+,!$)6 TD#,+,$ATA
TSU.7!)46#,+( TH#,+(.7!)46
-36
TD#,+,$ATA
&-#?.",
DocID028196 Rev 4 175/217
STM32F469xx Electrical characteristics
190
Table 97. Synchronous multiplexed PSRAM write timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period, VDD range= 2.7 to 3.6 V 2THCLK −1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 1.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK−0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK−0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
Electrical characteristics STM32F469xx
176/217 DocID028196 Rev 4
Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
tw(CLK) FMC_CLK period 2THCLK −1 -
ns
t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 0.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK −0.5 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK −0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 0 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
&-#?#,+
&-#?.%X
&-#?!;=
&-#?./%
&-#?$;= $ $
&-#?.7!)4
7!)4#&'B
7!)40/,B
&-#?.7!)4
7!)4#&'B
7!)40/,B
TW#,+ TW#,+
$ATALATENCY
TD#,+,.%X, TD#,+(.%X(
TD#,+,!6 TD#,+(!)6
TD#,+,./%, TD#,+(./%(
TSU$6#,+( TH#,+($6
TSU$6#,+( TH#,+($6
TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
-36
&-#?.!$6
TD#,+,.!$6, TD#,+,.!$6(
DocID028196 Rev 4 177/217
STM32F469xx Electrical characteristics
190
Figure 66. Synchronous non-multiplexed PSRAM write timings
Table 99. Synchronous non-multiplexed PSRAM write timings(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
t(CLK) FMC_CLK period 2THCLK −1 -
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 0.5
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK −0.5 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 2.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 -
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK−0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 -
-36
&-#?#,+
&-#?.%X
&-#?!;=
&-#?.7%
&-#?$;= $ $
&-#?.7!)4
7!)4#&'B7!)40/,B
TW#,+ TW#,+
$ATALATENCY
TD#,+,.%X, TD#,+(.%X(
TD#,+,!6 TD#,+(!)6
TD#,+(.7%(
TD#,+,.7%,
TD#,+,$ATA
TSU.7!)46#,+(
TH#,+(.7!)46
&-#?.!$6
TD#,+,.!$6, TD#,+,.!$6(
TD#,+,$ATA
&-#?.",
TD#,+(.",(
Electrical characteristics STM32F469xx
178/217 DocID028196 Rev 4
NAND controller waveforms and timings
Figures 67 through 70 represent synchronous waveforms, and Table 100 and Table 101
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•COM.FMC_SetupTime = 0x01;
•COM.FMC_WaitSetupTime = 0x03;
•COM.FMC_HoldSetupTime = 0x02;
•COM.FMC_HiZSetupTime = 0x01;
•ATT.FMC_SetupTime = 0x01;
•ATT.FMC_WaitSetupTime = 0x03;
•ATT.FMC_HoldSetupTime = 0x02;
•ATT.FMC_HiZSetupTime = 0x01;
•Bank = FMC_Bank_NAND;
•MemoryDataWidth = FMC_MemoryDataWidth_16b;
•ECC = FMC_ECC_Enable;
•ECCPageSize = FMC_ECCPageSize_512Bytes;
•TCLRSetupTime = 0;
•TARSetupTime = 0;
•Capacitive load CL = 30 pF.
In all timing tables, the THCLK is the HCLK clock period.
Figure 67. NAND controller waveforms for read access
&-#?.7%
&-#?./%.2%
&-#?$;=
TSU$./% TH./%$
-36
!,%&-#?!
#,%&-#?!
&-#?.#%X
TD!,%./% TH./%!,%
DocID028196 Rev 4 179/217
STM32F469xx Electrical characteristics
190
Figure 68. NAND controller waveforms for write access
Figure 69. NAND controller waveforms for common memory read access
-36
TH.7%$
TV.7%$
&-#?.7%
&-#?./%.2%
&-#?$;=
!,%&-#?!
#,%&-#?!
&-#?.#%X
TD!,%.7% TH.7%!,%
-36
&-#?.7%
&-#?./%
&-#?$;=
TW./%
TSU$./% TH./%$
!,%&-#?!
#,%&-#?!
&-#?.#%X
TD!,%./% TH./%!,%
Electrical characteristics STM32F469xx
180/217 DocID028196 Rev 4
Figure 70. NAND controller waveforms for common memory write access
SDRAM waveforms and timings
•CL = 30 pF on data and address lines.
•CL = 10 pF on FMC_SDCLK unless otherwise specified.
Table 100. Switching characteristics for NAND Flash read cycles
Symbol Parameter Min Max Unit
tw(N0E) FMC_NOE low width 4THCLK −0.5 4THCLK+0.5
ns
tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 9 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 -
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK −0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK −2-
Table 101. Switching characteristics for NAND Flash write cycles
Symbol Parameter Min Max Unit
tw(NWE) FMC_NWE low width 4THCLK 4THCLK+1
ns
tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK −1-
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK −3-
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3THCLK −0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK −1-
-36
TW.7%
TH.7%$
TV.7%$
&-#?.7%
&-#?.
/%
&-#?$;=
TD$.7%
!,%&-#?!
#,%&-#?!
&-#?.#%X
TD!,%./% TH./%!,%
DocID028196 Rev 4 181/217
STM32F469xx Electrical characteristics
190
In all timing tables, the THCLK is the HCLK clock period.
•For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_SDCLK = 90 MHz, at CL = 30 pF (on
FMC_SDCLK).
•For 1.71 V≤ VDD <1.9 V, maximum FMC_SDCLK = 75 MHz when CAS Latency = 3 and
60 MHz for CAS latency 1 or 2. CL = 10 pF (on FMC_SDCLK).
Figure 71. SDRAM read access waveforms (CL = 1)
Table 102. SDRAM read timings(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2THCLK −0.5 2THCLK+0.5
ns
tsu(SDCLKH _Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 0 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 0.5
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
-36
2OWN #OL
&-#?3$#,+
&-#?!>@
&-#?3$.2!3
&-#?3$.#!3
&-#?3$.7%
&-#?$;=
&-#?3$.%;=
TD3$#,+,?!DD2 TD3$#,+,?!DD#
TH3$#,+,?!DD2
TH3$#,+,?!DD#
TD3$#,+,?3.$%
TSU3$#,+(?$ATA TH3$#,+(?$ATA
#OL #OLI #OLN
$ATA $ATAI $ATAN$ATA
TH3$#,+,?3.$%
TD3$#,+,?.2!3
TD3$#,+,?.#!3 TH3$#,+,?.#!3
TH3$#,+,?.2!3
Electrical characteristics STM32F469xx
182/217 DocID028196 Rev 4
Figure 72. SDRAM write access waveforms
Table 103. LPSDR SDRAM read timings(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
tW(SDCLK) FMC_SDCLK period 2THCLK −0.5 2THCLK+0.5
ns
tsu(SDCLKH_Data) Data input setup time 2.5 -
th(SDCLKH_Data) Data input hold time 0 -
td(SDCLKL_Add) Address valid time - 1
td(SDCLKL_SDNE) Chip select valid time - 1
th(SDCLKL_SDNE) Chip select hold time 1 -
td(SDCLKL_SDNRAS SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 1 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
th(SDCLKL_SDNCAS) SDNCAS hold time 1 -
-36
2OWN #OL
&-#?3$#,+
&-#?!>@
&-#?3$.2!3
&-#?3$.#!3
&-#?3$.7%
&-#?$;=
&-#?3$.%;=
TD3$#,+,?!DD2 TD3$#,+,?!DD#
TH3$#,+,?!DD2
TH3$#,+,?!DD#
TD3$#,+,?3.$%
TD3$#,+,?$ATA
TH3$#,+,?$ATA
#OL #OLI #OLN
$ATA $ATAI $ATAN$ATA
TH3$#,+,?3.$%
TD3$#,+,?.2!3
TD3$#,+,?.#!3 TH3$#,+,?.#!3
TH3$#,+,?.2!3
TD3$#,+,?.7% TH3$#,+,?.7%
&-#?.",;=
TD3$#,+,?.",
DocID028196 Rev 4 183/217
STM32F469xx Electrical characteristics
190
Table 104. SDRAM write timings(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2THCLK −0.5 2THCLK+0.5
ns
td(SDCLKL _Data) Data output valid time - 2.5
th(SDCLKL _Data) Data output hold time 3.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNWE) SDNWE valid time - 1
th(SDCLKL_SDNWE) SDNWE hold time 0 -
td(SDCLKL_ SDNE) Chip select valid time - 0.5
th(SDCLKL-_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 2
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
td(SDCLKL_SDNCAS) SDNCAS hold time 0 -
td(SDCLKL_NBL) NBL valid time - 0.5
th(SDCLKL_NBL) NBL output time 0 -
Table 105. LPSDR SDRAM write timings(1)
1. Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
tw(SDCLK) FMC_SDCLK period 2THCLK −0.5 2THCLK+0.5
ns
td(SDCLKL _Data) Data output valid time - 5
th(SDCLKL _Data) Data output hold time 2 -
td(SDCLKL_Add) Address valid time - 2.8
td(SDCLKL-SDNWE) SDNWE valid time - 2
th(SDCLKL-SDNWE) SDNWE hold time 1 -
td(SDCLKL- SDNE) Chip select valid time - 1.5
th(SDCLKL- SDNE) Chip select hold time 1 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 1.5 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL-SDNCAS) SDNCAS hold time 1.5 -
td(SDCLKL_NBL) NBL valid time - 1.5
th(SDCLKL-NBL) NBL output time 1.5 -
Electrical characteristics STM32F469xx
184/217 DocID028196 Rev 4
5.3.30 Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 106 and Table 107 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table xx, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function
characteristics.
Figure 73. Quad-SPI SDR timing diagram
Table 106. Quad-SPI characteristics in SDR mode(1)
Symbol Parameter Test conditions Min Typ Max Unit
Fck
1/t(CK)
Quad-SPI clock frequency
2.7 V ≤VDD ≤3.6 V, CL= 20 pF - - 90
MHz
1.71 V ≤VDD ≤3.6 V, CL= 15 pF --84
tw(CKH) Quad-SPI clock high time ‐t(CK)/2-1 - t(CK)/2
ns
tw(CKL) Quad-SPI clock low time ‐t(CK)/2 - t(CK)/2+1
ts(IN) Data input set-up time ‐0.5 - -
th(IN) Data input hold time ‐3--
tv(OUT) Data output valid time ‐-34
th(OUT) Data output hold time ‐2.5 - -
1. Guaranteed based on test during characterization.
06Y9
'DWDRXWSXW ' ' '
&ORFN
'DWDLQSXW ' ' '
W&. WZ&.+ WZ&./
WU&. WI&.
WV,1 WK,1
WY287 WK287
DocID028196 Rev 4 185/217
STM32F469xx Electrical characteristics
190
Figure 74. Quad-SPI DDR timing diagram
5.3.31 Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 108 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
•DCMI_PIXCLK polarity: falling
•DCMI_VSYNC and DCMI_HSYNC polarity: high
•Data formats: 14 bits
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Table 107. Quad-SPI characteristics in DDR mode(1)
Symbol Parameter Test conditions Min Typ Max Unit
Fck
1/t(CK)
Quad-SPI clock frequency
2.7 V ≤VDD ≤3.6 V,
CL= 20 pF --80
MHz
1.71 V ≤VDD ≤3.6 V,
CL= 15 pF --70
tw(CKH) Quad-SPI clock high time ‐t(CK)/2-1 - t(CK)/2
ns
tw(CKL) Quad-SPI clock low time - t(CK)/2 - t(CK)/2+1
tsr(IN)
tsf(IN)
Data input set-up time
2.7 V ≤VDD ≤3.6 V 2 - -
1.71 V ≤VDD ≤3.6 V 0.5 - -
thr(IN)
thf(IN)
Data input hold time
2.7 V ≤VDD ≤3.6 V 3 - -
1.71 V ≤VDD ≤3.6 V 4.5 - -
tvr(OUT)
tvf(OUT)
Data output valid time
DHHC=0 - 8 10.5
DHHC=1
Pres=1,2… -T
hclk/2+2 Thclk/2+2.5
th(OUT)
tf(OUT)
Data output hold time
DHHC=0 7 - -
DHHC=1
Pres=1,2… Thclk/2+0.5 - -
1. Guaranteed based on test during characterization.
06Y9
'DWDRXWSXW ' ' '
&ORFN
'DWDLQSXW ' ' '
W&. WZ&.+ WZ&./
WU&. WI&.
WVI,1 WKI,1
WYI287 WKU287
' ' '
' ' '
WYU287 WKI287
WVU,1 WKU,1
Electrical characteristics STM32F469xx
186/217 DocID028196 Rev 4
Figure 75. DCMI timing diagram
5.3.32 LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 109 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
•LCD_CLK polarity: high
•LCD_DE polarity: low
•LCD_VSYNC and LCD_HSYNC polarity: high
•Pixel formats: 24 bits
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load CL = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Table 108. DCMI characteristics(1)
1. 1.Guaranteed based on test during characterization.
Symbol Parameter Min Max Unit
- Frequency ratio DCMI_PIXCLK/fHCLK -0.4 -
DCMI_PIXCLK Pixel clock input - 54 MHz
DPixel Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 4 -
ns
th(DATA) Data input hold time 1 -
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input setup time 3.5 -
th(HSYNC)
th(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time 0 -
069
'&0,B3,;&/.
WVX96<1&
WVX+6<1&
'&0,B+6<1&
'&0,B96<1&
'$7$>@
'&0,B3,;&/.
WK+6<1&
WK+6<1&
WVX'$7$ WK'$7$
DocID028196 Rev 4 187/217
STM32F469xx Electrical characteristics
190
Figure 76. LCD-TFT horizontal timing diagram
Table 109. LTDC characteristics(1)
1. Based on test during characterization.
Symbol Parameter Min Max Unit
fCLK LTDC clock output frequency - 65 MHz
DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH)
tw(CLKL)
Clock High time, low time tw(CLK)/2 −0.5 tw(CLK)/2+0.5
ns
tv(DATA) Data output valid time - 1.5
th(DATA) Data output hold time 0 -
tv(HSYNC)
HSYNC/VSYNC/DE output valid time - 0.5tv(VSYNC)
tv(DE)
th(HSYNC)
HSYNC/VSYNC/DE output hold time 0 -th(VSYNC)
th(DE)
069
/&'B&/.
WY+6<1&
/&'B+6<1&
/&'B'(
/&'B5>@
/&'B*>@
/&'B%>@
W&/.
/&'B96<1&
WY+6<1&
WY'( WK'(
1JYFM
1JYFM
WY'$7$
WK'$7$
1JYFM
/
+6<1&
ZLGWK
+RUL]RQWDO
EDFNSRUFK
$FWLYHZLGWK +RUL]RQWDO
EDFNSRUFK
2QHOLQH
Electrical characteristics STM32F469xx
188/217 DocID028196 Rev 4
Figure 77. LCD-TFT vertical timing diagram
5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 110 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
•Output speed is set to OSPEEDRy[1:0] = 11
•Capacitive load C = 30 pF
•Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output characteristics.
Figure 78. SDIO high-speed mode
069
/&'B&/.
WY96<1&
/&'B5>@
/&'B*>@
/&'B%>@
W&/.
/&'B96<1&
WY96<1&
-LINESDATA
96<1&
ZLGWK
9HUWLFDO
EDFNSRUFK
$FWLYHZLGWK 9HUWLFDO
EDFNSRUFK
2QHIUDPH
T7#+(
#+
$#-$
OUTPUT
$#-$
INPUT
T#
T7#+,
T/6 T/(
T)35 T)(
TFTR
AI
DocID028196 Rev 4 189/217
STM32F469xx Electrical characteristics
190
Figure 79. SD default mode
AI
#+
$#-$
OUTPUT
T/6$ T/($
Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 50 MHz
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time
fpp =50 MHz
9.5 10.5 -
ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU Input setup time HS
fpp =50 MHz
2.0 - -
ns
tIH Input hold time HS 2.0 - -
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time HS
fpp =50 MHz
-1313.5
ns
tOH Output hold time HS 12.5 - -
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD
fpp =25 MHz
2.0 - -
ns
tIHD Input hold time SD 2.5 - -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD
fpp =25 MHz
-1.52.0
ns
tOHD Output hold default time SD 1.0 - -
1. Guaranteed based on test during characterization.
Electrical characteristics STM32F469xx
190/217 DocID028196 Rev 4
5.3.34 RTC characteristics
Table 111. Dynamic characteris tics: SD / MMC ch arac terist ic s, VDD = 1.71 to 1.9 V(1)(2)
Symbol Parameter Conditions Min Typ Max Unit
fPP Clock frequency in data transfer mode - 0 - 50 MHz
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time
fpp =50 MHz
9.5 10.5 -
ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS
fpp =50 MHz
0.5 - -
ns
tIH Input hold time HS 3.5 - -
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS
fpp =50 MHz
- 13.5 14.5
ns
tOH Output hold time HS 13.0 - -
1. Guaranteed based on test during characterization.
2. Cload = 20 pF.
Table 112. RTC characteristics
Symbol Parameter Conditions Min Max
-f
PCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 -
DocID028196 Rev 4 191/217
STM32F469xx Package information
215
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1 LQFP100 package information
Figure 80. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
1. Drawing is not to scale.
E
)$%.4)&)#!4)/.
0).
'!5'%0,!.%
MM
3%!4).'0,!.%
$
$
$
%
%
%
+
CCC #
#
,?-%?6
!
!
!
,
,
C
B
!
Package information STM32F469xx
192/217 DocID028196 Rev 4
Table 113. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
DocID028196 Rev 4 193/217
STM32F469xx Package information
215
Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
1. Dimensions are expressed in millimeters.
Device Marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location. Other optional marking or inset/upset marks, which identify the parts throughout
supply chain operations, are not indicated below.
Figure 82. LQFP100 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
AIC
069
670)
9,7 5
3URGXFWLGHQWLILFDWLRQ 5HYLVLRQFRGH
::<
'DWHFRGH
3LQLGHQWLILHU
DocID028196 Rev 4 195/217
STM32F469xx Package information
215
Table 114. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
Package information STM32F469xx
196/217 DocID028196 Rev 4
Figure 84. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
Device Marking for LQFP144
Figure 85 gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 85. LQFP144 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
DLH
069
3LQLGHQWLILHU
5
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
'DWHFRGH
<::
670)=,7
DocID028196 Rev 4 197/217
STM32F469xx Package information
215
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
6.3 WLCSP168 package information
Figure 86. W LC SP1 68 - 168-p in , 4. 89 1 x 5. 69 2 mm, 0.4 mm pitch waf e r le ve l chip
scale package outline
$6B0(B9
H
)
*
H
H
%RWWRPYLHZ
%XPSVLGH
H
$EDOOORFDWLRQ
'
$RULHQWDWLRQ
UHIHUHQFH
7RSYLHZ
:DIHUEDFNVLGH
'HWDLO$
$
$
6LGHYLHZ
$
(
'HWDLO$
5RWDWHG
HHH
%XPS
6HDWLQJ
SODQH
E
$
$
FFF
GGG
=
=
;<
=
DDD
;
=EEE
=
;<
Package information STM32F469xx
198/217 DocID028196 Rev 4
Table 115. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.170 - - 0.0067 -
A2 - 0.380 - - 0.0150 -
A3(2)
2. Back side coating.
- 0.025 - - 0.0010 -
b(3)
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
0.220 0.250 0.280 0.0087 0.0098 0.0110
D 4.856 4.891 4.926 0.1912 0.1926 0.1939
E 5.657 5.692 5.727 0.2227 0.2241 0.2255
e - 0.400 - - 0.0157 -
e1 - 4.400 - - 0.1732 -
e2 - 5.200 - - 0.2047 -
F - 0.2455 - - 0.0097 -
G - 0.246 - - 0.0097 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
DocID028196 Rev 4 199/217
STM32F469xx Package information
215
6.4 UFBGA169 package information
Figure 87. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline
1. Drawing is not in scale.
Table 116. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data
Symbol millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217
$<9B0(B9
6HDWLQJSODQH
$
$
$
H)
)
H
1
$
%277209,(:
(
'
7239,(:
EEDOOV
<
;
<HHH0
III0
=
=
;
$EDOO
LGHQWLILHU
$EDOO
LQGH[DUHD
E
'
(
$
$
=
=
GGG
6,'(9,(:
Package information STM32F469xx
200/217 DocID028196 Rev 4
Device Marking for UFBGA169
The following figure gives an example of topside marking orientation versus ball A1 identifier
location. Other optional marking or inset/upset marks, which identify the parts throughout
supply chain operations, are not indicated below.
Figure 88. UFBGA169 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 116. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
Symbol millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
06Y9
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
3LQ
LGHQWLILHU
'DWHFRGH
ztt
^dDϯϮ&
ϰϳϵ/,ϲ
DocID028196 Rev 4 201/217
STM32F469xx Package information
215
6.5 LQFP176 package information
Figure 89. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline
1. Drawing is not to scale.
4?-%?6
!
!
E
%(%
$
($
:$
:%
B
MM
GAUGEPLANE
! ,
,
K
C
)$%.4)&)#!4)/.
0).
3EATINGPLANE
#
!
Table 117. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data
Symbol millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 - 1.450 0.0531 - 0.0060
b 0.170 - 0.270 0.0067 - 0.0106
C 0.090 - 0.200 0.0035 - 0.0079
D 23.900 - 24.100 0.9409 - 0.9488
E 23.900 - 24.100 0.9409 - 0.9488
Package information STM32F469xx
202/217 DocID028196 Rev 4
e - 0.500 - - 0.0197 -
HD 25.900 - 26.100 1.0200 - 1.0276
HE 25.900 - 26.100 1.0200 - 1.0276
L 0.450 - 0.750 0.0177 - 0.0295
L1 - 1.000 - - 0.0394 -
ZD - 1.250 - - 0.0492 -
ZE - 1.250 - - 0.0492 -
ccc - - 0.080 - - 0.0031
k 0 ° - 7 ° 0 ° - 7 °
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 117. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data (continued)
Symbol millimeters inches(1)
Min Typ Max Min Typ Max
Package information STM32F469xx
204/217 DocID028196 Rev 4
Device Marking for LQFP176
The following figure gives an example of topside marking orientation versus pin 1 identifier
location. Other optional marking or inset/upset marks, which identify the parts throughout
supply chain operations, are not indicated below.
Figure 91. LQFP176 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
ttz
^ϯϮ&ϰϳϵ//dϲh
'DWHFRGH
5HYLVLRQFRGH
06Y9
3LQ
LGHQWLILHU
3URGXFWLGHQWLILFDWLRQ
DocID028196 Rev 4 205/217
STM32F469xx Package information
215
6.6 UFBGA176+25 package information
Figure 92. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package outline
1. Drawing is not to scale.
Table 118. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data
Symbol millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 9.950 10.000 10.050 0.3917 0.3937 0.3957
E 9.950 10.000 10.050 0.3917 0.3937 0.3957
e - 0.650 - - 0.0256 -
F 0.400 0.450 0.500 0.0157 0.0177 0.0197
ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
ϬϳͺDͺsϲ
^ĞĂƚŝŶŐƉůĂŶĞ
Ϯ ĚĚĚ
ϭ
Ğ&
&
Ğ
Z
ϭϱ ϭ
KddKDs/t
dKWs/t
EEDOOV
$
HHH 0
III0
&
&
$
&
$EDOO
LGHQWLILHU
$EDOO
LQGH[
DUHD
ď
ϰ
Package information STM32F469xx
206/217 DocID028196 Rev 4
Figure 93. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package recommended footprint
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch 0.65 mm
Dpad 0.300 mm
Dsm 0.400 mm typ. (depends on the soldermask registration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Ϭϳͺ&Wͺsϭ
'SDG
'VP
DocID028196 Rev 4 207/217
STM32F469xx Package information
215
6.7 LQFP208 package information
Figure 94. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline
1. Drawing is not to scale.
'
'
'
(
(
(
H
/
*$8*(3/$1(
PP
E
&
6($7,1*
3/$1(
FFF &
,'(17,),&$7,21
3,1
F
/
$
$
$
$
6)@.&@7
.
Table 120. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data
Symbol millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 -- - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
Package information STM32F469xx
208/217 DocID028196 Rev 4
c 0.090 - 0.200 0.0035 - 0.0079
D 29.800 30.000 30.200 1.1732 1.1811 1.1890
D1 27.800 28.000 28.200 1.0945 1.1024 1.1102
D3 - 25.500 - - 1.0039 -
E 29.800 30.000 30.200 1.1732 1.1811 1.1890
E1 27.800 28.000 28.200 1.0945 1.1024 1.1102
E3 - 25.500 - - 1.0039 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7.0° 0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 120. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data (continued)
Symbol millimeters inches(1)
Min Typ Max Min Typ Max
Package information STM32F469xx
210/217 DocID028196 Rev 4
Device Marking for LQFP208
The following figure gives an example of topside marking orientation versus pin 1 identifier
location. Other optional marking or inset/upset marks, which identify the parts throughout
supply chain operations, are not indicated below.
Figure 96. LQFP208 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
06Y9
3LQ
LGHQWLILHU
tt
z
^dDϯϮ&ϰϳϵ/dϲ
'DWHFRGH
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
DocID028196 Rev 4 211/217
STM32F469xx Package information
215
6.8 TFBGA216 package information
Figure 97. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm, package outline
1. Drawing is not to scale.
$/B0(B9
6HDWLQJSODQH
$
H)
*
'
5
EEDOOV
$
(
7239,(:%277209,(:
H
$
$
<
;
=
GGG =
'
(
HHH = < ;
III
0
0=
$EDOO
LGHQWLILHU
$EDOO
LQGH[DUHD
Table 121. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm
package mechan ical data
Symbol millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
A4 - 0.210 - - 0.0083 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 12.850 13.000 13.150 0.5118 0.5118 0.5177
D1 - 11.200 - - 0.4409 -
E 12.850 13.000 13.150 0.5118 0.5118 0.5177
E1 - 11.200 - - 0.4409 -
e - 0.800 - - 0.0315 -
F - 0.900 - - 0.0354 -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package information STM32F469xx
212/217 DocID028196 Rev 4
Device Marking for TFBGA216
The following figure gives an example of topside marking orientation versus ball A1 identifier
location. Other optional marking or inset/upset marks, which identify the parts throughout
supply chain operations, are not indicated below.
Figure 98. TFBGA216 marking example (package top view)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
06Y9
'DWHFRGH
ztt
5HYLVLRQFRGH
^ϯϮ&
3URGXFWLGHQWLILFDWLRQ
%DOO
LGHQWLILHU
ϰϳϵE/,ϲh
DocID028196 Rev 4 213/217
STM32F469xx Package information
215
6.9 Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x Θ
JA)
Where:
•TA max is the maximum ambient temperature in °C,
•Θ
JA is the package junction-to-ambient thermal resistance, in °C/W,
•PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 122. Package thermal characteristics
Symbol Parameter Value Unit
Θ
JA
Thermal resistance junction-amb ient
LQFP100 43
°C/W
Thermal resistance junction-amb ient
LQFP144 40
Thermal resistance junction-amb ient
WLCSP168 31
Thermal resistance junction-amb ient
LQFP176 - 24 × 24 mm / 0.5 mm pitch 38
Thermal resistance junction-amb ient
LQFP208 - 28 × 28 mm / 0.5 mm pitch 19
Thermal resistance junction-amb ient
UFBGA169 - 7 × 7mm / 0.5 mm pitch 52
Thermal resistance junction-amb ient
UFBGA176 - 10 × 10 mm / 0.5 mm pitch 39
Thermal resistance junction-amb ient
TFBGA216 - 13 × 13 mm / 0.8 mm pitch 29
Part numbering STM32F469xx
214/217 DocID028196 Rev 4
7 Part numbering
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 123. Ordering information scheme
Example: STM32 F 469 V I T 6 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
469= STM32F469xx, USB OTG FS/HS, camera interface,
Ethernet, LCD-TFT, DSIHost, Quad-SPI,
Chrom-ART graphical accelerator.
Pin count
V = 100 pins
Z = 144 pins
A = 168 and 169 pins
I = 176 pins
B = 208 pins
N = 216 pins
Flash memory size
E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
I = 2048 Kbytes of Flash memory
Package
T = LQFP
H = BGA
Y = WLCSP
Temp erature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
DocID028196 Rev 4 215/217
STM32F469xx Recommendations when using internal reset OFF
215
Appendix A Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•The brownout reset (BOR) circuitry must be disabled.
•The embedded programmable voltage detector (PVD) is disabled.
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
•The over-drive mode is not supported.
A.1 Operating conditions
Table 124. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
with no wait
states
(fFlashmax)
Maximum Flash
memory access
frequency with
wait states (1)(2)
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does
not impact the execution speed from Flash memory since the ART accelerator allows to achieve a
performance equivalent to 0 wait state program execution.
I/O operation Possible Flash
memory
operations
VDD =1.7 to
2.1 V(3)
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 2.19.1: Internal reset ON).
Conversion
time up to
1.2 Msps
20 MHz(4)
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and
power.
168 MHz with 8
wait states and
over-drive OFF
– No I/O
compensation
8-bit erase and
program
operations only
Revision history STM32F469xx
216/217 DocID028196 Rev 4
Revision history
Table 125. Document revision history
Date Revision Changes
01-Sep-2015 1 Initial release.
13-Oct-2015 2
Updated Table 4: Regulator ON/OFF and internal reset ON/OFF
availability and Table 54: EMI characteristics.
Updated Figure 35: PLL output clock waveforms in center spread
mode and Figure 36: PLL output clock waveforms in down spread
mode.
Updated title of Section 6.8: TFBGA216 package information.
08-Mar-2016 3
Updated cover page with introduction of LQFP100 and LQFP144
packages.
Updated Section 1: Description and Section 1.1: Compatibility
throughout the family.
Updated Figure 1 : Incompatible board design for LQFP176 package
and its footnote.
Updated Table 1: Device summary, Table 2: STM32F469xx features
and peripheral counts, Table 4 : Regulator ON/OFF and internal reset
ON/OFF availability, Table 10: STM32F 469xx pin and ball definitions,
Table 11: FMC pin definition, Table 12: Alternate function, Table 17:
General operating conditions, Table 55: ESD absolute maximum
ratings, Table 76: ADC characteristics, Table 122: Package thermal
characteristics and Table 123: Ordering information scheme.
Removed former Table 73: Ethernet DC electrical characteri stics.
Added Figure 13: STM32F46x LQFP100 pinout and Figure 14:
STM32F46x LQFP144 pinout.
Updated Figure 17: STM32F46x UFBGA176 ballout, Figure 18:
STM32F46x LQFP176 pinout and Figure 33: ACCHSI vs. temperature.
Added Section 6.1: LQFP100 package information and Section 6.2:
LQFP144 package information.
Replaced former footnote 7 of Table 10: STM32F469xx pin and ball
definitions with footnote 2.
Added footnote 3 to Table 14: Voltage characteristics.
Updated footnote 1 of Figure 56 and footnote 1 of Figure 57.
02-Mar-2017 4
Updated Table 12: Alternate function.
Corrected maximum characterized wakeup timing values for Stop
mode in Table 34: Low-power mode wakeup timings.
Updated Figure 14: STM32F46x LQFP144 pinout.
Updated Device Marki ng for LQFP 100, Device Marking for
UFBGA169, Device Marking for LQFP176, Device Marking for
LQFP176 and Device Marking for LQFP176.
Updated footnotes of figures 82, 85, 88, 91, 96 and 98 in Section 6:
Package information.
DocID028196 Rev 4 217/217
STM32F469xx
217
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
