R5106N Series
Compact Watchdog Timer Equipped with Inhibit Pin with VD
No.EK-169-111001 CMOS Microprocessor Supervisory
The R5106N Series are CMOS-b ased s ystem pow er ICs with a voltage detector (VD) and watchdog timer (WDT ) integrated in a single
chip. R5106N monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset
signal when a malfunction occurs. The output delay time of the VD and watchdog timeout period/reset time can be adjusted high
accuracy by an external capacitor. The R5106N is equipped with the function that inhibits clock monitoring of the WDT (INH).
FEATURES
• Supply Current (ISS) ························Typ. 11μA (VDD=-VDET+0.5V,
Clock pulse input)
• Operating Voltage (VDD)··················0.9V to 6.0V
(VD Section)
•
Detector Threshold Range (-V
DET
)
···1.5V to 5.5V (internally fixed)
•
Detector Threshold Accuracy
··········± 1%
•
Temp. coeff. of Detector Threshold
···Typ. ± 100ppm/°C
• Output Delay Time (tPLH)················· Typ. 370ms (CT=0.1μF)
• Output Delay Time Accuracy·········· ± 16% (-40°C ≤ Topt ≤ 105°C)
(WDT Section)
• Watchdog Timeout Period (tWD)······ Typ. 310ms (CT=0.1μF)
• Reset Hold Time of WDT (tWR) ······· Typ. 34ms (CT=0.1μF)
•
Watchdog Timeout Period Accuracy
···· ± 33% (-40°C ≤ Topt ≤ 105°C)
• Able to stop watchdog timer··········· Inhibit (INH) Pin
• Package ········································· SOT-23-6
(The above shows specification at Topt=25°C. Design assurance value at -40°C ≤ To pt ≤ 105°C is also available. For details, please refer to the datasheet.)
BLOCK DIAGRAMS
TYPICAL APPLICATION
R5106Nxx1A
(Nch. open drain output)
VDD
GND
SCK
RESETB
CT
WATCHDOG
TIMER
CLOCK
DETECTOR
3
6
4
5
1
2INH
SW1
SW2
Vref1Vref2
R5106Nxx1C
(CMOS output)
RESETB
VDD
GND
SCK
CT
WATCHDOG
TIMER
CLOCK
DETECTOR
3
6
4
5
1
2INH
SW1
SW2
Vref1Vref2
R5106Nxx1A
Series
SW
VDD
RESET
I/O
R
CT
GND
VDD
INH
RESETB
SCK
CT
3
2
5
6
4
1
MicroprocessorPower Supply
SELECTION GUIDE TIMING CHART
Halogen Free
Package
Q'ty per Reel
Part No.
SOT-23-6 3,000 pcs R5106N
.
xx
.
1
.
∗
-TR-FE
.
xx
: Specify the detector threshold within the range of
1.5V (
.
15
.
)
to 5.5V
(
.
55
.
) in 0.1V steps.
.
∗
: Select the output type from (
.
A
.
) Nch. open drain or (
.
C
.
) CMOS.
PACKAGE (Top View)
SOT-23-6
6 5 4
1 2 3
1 SCK Watchdog timer clock input pin
2 INH Inhibit pin
3 VDD Power supply pin
4 RESETB Output pin for Reset "L" signal
5 GND Ground pin
6 CT
Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
and output delay time of VD
APPLICATION
• Monitoring of the power system of devices equipped with microprocessors
-VDE T
+VDET
VRESETB
VCT
VSCK
VDD
Vref2H
Vref2L
VINH
tPLH tWDI
t
WD
tPLH
t
W
R
tPHL
∗
Vref2H : CTW pin voltage at the end of WDT timeout period.
∗
Vref2L : CTW pin voltage at the begin of WDT timeout period.
∗
tPHL : Output delay time
∗
tWDI : tWD/10 (SCK pulses input during this period are ignored.)
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