LM2904DR2GH - ON SEMICONDUCTOR - searchdatasheet.com

July, 2019 − Rev. 33

1Publication Order Number:

LM358/D

LM258, LM358, LM358A,

LM358E, LM2904, LM2904A,

LM2904E, LM2904V,

NCV2904

Single Supply Dual

Operational Amplifiers

Utilizing the circuit designs perfected for Quad Operational

Amplifiers, these dual operational amplifiers feature low power drain,

a common mode input voltage range extending to ground/VEE, and

single supply or split supply operation. The LM358 series is

equivalent to one−half of an LM324.

These amplifiers have several distinct advantages over standard

operational amplifier types in single supply applications. They can

operate at supply voltages as low as 3.0 V or as high as 32 V, with

quiescent currents about one−fifth of those associated with the

MC1741 (on a per amplifier basis). The common mode input range

includes the negative supply, thereby eliminating the necessity for

external biasing components in many applications. The output voltage

range also includes the negative power supply voltage.

Features

•Short Circuit Protected Outputs

•True Differential Input Stage

•Single Supply Operation: 3.0 V to 32 V

•Low Input Bias Currents

•Internally Compensated

•Common Mode Range Extends to Negative Supply

•Single and Split Supply Operation

•ESD Clamps on the Inputs Increase Ruggedness of the Device

without Affecting Operation

•NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

PDIP−8

N, AN, VN SUFFIX

CASE 626

SOIC−8

D, VD SUFFIX

CASE 751

PIN CONNECTIONS

VEE/Gnd

Inputs A

Inputs B

Output B

Output A VCC

−

(Top View)

See general marking information in the device marking

section on page 11 of this data sheet.

DEVICE MARKING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

Micro8]

DMR2 SUFFIX

CASE 846A

www.onsemi.com

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

www.onsemi.com

Single Supply Split Supplies

VCC

VEE/Gnd

3.0 V to VCC(max)

VCC

VEE

1.5 V to VCC(max)

1.5 V to VEE(max)

Output

Bias Circuitry

Common to Both

Amplifiers

VCC

VEE/Gnd

Inputs

Q3 Q4

Q26

Q11

Q10

Q1 2.4 k

Q25

Q22

40 k

Q13

Q14

Q15

Q16

Q19

5.0 pF

Q18

Q17

Q20

Q21

2.0 k

Q24

Q23

Q12

Figure 1.

Figure 2. Representative Schematic Diagram

(One−Half of Circuit Shown)

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)

Rating Symbol Value Unit

Power Supply Voltages

Single Supply

Split Supplies

VCC

VCC, VEE

±16

Vdc

Input Differential Voltage Range (Note 1) VIDR ±32 Vdc

Input Common Mode Voltage Range VICR −0.3 to 32 Vdc

Output Short Circuit Duration tSC Continuous

Junction Temperature TJ150 °C

Thermal Resistance, Junction−to−Air (Note 2) Case 846A

Case 751

Case 626

RJA 238

212

161

°C/W

Storage Temperature Range Tstg −65 to +150 °C

Operating Ambient Temperature Range

LM258

LM358, LM358A, LM358E

LM2904, LM2904A, LM2904E

LM2904V, NCV2904 (Note 3)

−25 to +85

0 to +70

−40 to +105

−40 to +125

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Split Power Supplies.

2. All RJA measurements made on evaluation board with 1 oz. copper traces of minimum pad size. All device outputs were active.

3. NCV2904 is qualified for automotive use.

ESD RATINGS

Rating HBM MM Unit

ESD Protection at any Pin (Human Body Model − HBM, Machine Model − MM)

NCV2904 (Note 3)

LM358E, LM2904E

LM358DG/DR2G, LM2904DG/DR2G

All Other Devices

2000

250

2000

200

100

200

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.)

Characteristic Symbol

LM258 LM358, LM358E LM358A

Unit

Min Typ Max Min Typ Max Min Typ Max

Input Offset Voltage

VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V,

VO ] 1.4 V, RS = 0 

VIO mV

TA = 25°C−2.0 5.0 −2.0 7.0 −2.0 3.0

TA = Thigh (Note 4) − − 7.0 − − 9.0 − − 5.0

TA = Tlow (Note 4) − − 7.0 − − 9.0 − − 5.0

Average Temperature Coefficient of Input Offset

Voltage

VIO/T−7.0 − − 7.0 − − 7.0 −V/°C

TA = Thigh to Tlow (Note 4)

Input Offset Current IIO −3.0 30 −5.0 50 −5.0 30 nA

TA = Thigh to Tlow (Note 4) − − 100 − − 150 − − 75

Input Bias Current IIB − −45 −150 − −45 −250 − −45 −100

TA = Thigh to Tlow (Note 4) − −50 −300 − −50 −500 − −50 −200

Average Temperature Coefficient of Input Offset

Current

IIO/T−10 − − 10 − − 10 −pA/°C

TA = Thigh to Tlow (Note 4)

Input Common Mode Voltage Range (Note 5),

VCC = 30 V

VICR 0−28.3 0 −28.3 0 −28.5 V

VCC = 30 V, TA = Thigh to Tlow 0−28 0 −28 0 −28

Differential Input Voltage Range VIDR − − VCC − − VCC − − VCC V

Large Signal Open Loop Voltage Gain AVOL V/mV

RL = 2.0 k, VCC = 15 V, For Large VO Swing, 50 100 −25 100 −25 100 −

TA = Thigh to Tlow (Note 4) 25 − − 15 − − 15 − −

Channel Separation CS − −120 − − −120 − − −120 −dB

1.0 kHz ≤ f ≤ 20 kHz, Input Referenced

Common Mode Rejection CMR 70 85 −65 70 −65 70 −dB

RS ≤ 10 k

Power Supply Rejection PSR 65 100 −65 100 −65 100 −dB

Output Voltage−High Limit

TA = Thigh to Tlow (Note 4)

VOH V

VCC = 5.0 V, RL = 2.0 k, TA = 25°C3.3 3.5 −3.3 3.5 −3.3 3.5 −

VCC = 30 V, RL = 2.0 k26 − − 26 − − 26 − −

VCC = 30 V, RL = 10 k27 28 −27 28 −27 28 −

Output Voltage−Low Limit VOL −5.0 20 −5.0 20 −5.0 20 mV

VCC = 5.0 V, RL = 10 k,

TA = Thigh to Tlow (Note 4)

Output Source Current IO+mA

VID = +1.0 V, VCC = 15 V 20 40 −20 40 −20 40 −

TA = Thigh to Tlow (LM358A Only) 10 − −

Output Sink Current IO−

VID = −1.0 V, VCC = 15 V 10 20 −10 20 −10 20 −mA

TA = Thigh to Tlow (LM358A Only) 5.0 − − mA

VID = −1.0 V, VO = 200 mV 12 50 −12 50 −12 50 −A

Output Short Circuit to Ground (Note 6) ISC −40 60 −40 60 −40 60 mA

Power Supply Current (Total Device)

TA = Thigh to Tlow (Note 4)

ICC mA

VCC = 30 V, VO = 0 V, RL = ∞−1.5 3.0 −1.5 3.0 −1.5 2.0

VCC = 5 V, VO = 0 V, RL = ∞−0.7 1.2 −0.7 1.2 −0.7 1.2

4. LM258: Tlow = −25°C, Thigh = +85°C LM358, LM358A, LM358E: Tlow = 0°C, Thigh = +70°C

LM2904/A/E: Tlow = −40°C, Thigh = +105°C LM2904V & NCV2904: Tlow = −40°C, Thigh = +125°C

NCV2904 is qualified for automotive use.

5. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of

the common mode voltage range is VCC − 1.7 V.

6. Short circuits from the output to VCC can cause excessive heating and eventual destruction. Destructive dissipation can result from

simultaneous shorts on all amplifiers.

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = Gnd, TA = 25°C, unless otherwise noted.)

Characteristic Symbol

LM2904/LM2904E LM2904A LM2904V, NCV2904

Unit

Min Typ Max Min Typ Max Min Typ Max

Input Offset Voltage

VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V,

VO ] 1.4 V, RS = 0 

VIO mV

TA = 25°C−2.0 7.0 −2.0 7.0 − − 7.0

TA = Thigh (Note 7) − − 10 − − 10 − − 13

TA = Tlow (Note 7) − − 10 − − 10 − − 10

Average Temperature Coefficient of Input Offset

Voltage

VIO/T−7.0 − − 7.0 − − 7.0 −V/°C

TA = Thigh to Tlow (Note 7)

Input Offset Current IIO −5.0 50 −5.0 50 −5.0 50 nA

TA = Thigh to Tlow (Note 7) −45 200 −45 200 −45 200

Input Bias Current IIB − −45 −250 − −45 −100 − −45 −250

TA = Thigh to Tlow (Note 7) − −50 −500 − −50 −250 − −50 −500

Average Temperature Coefficient of Input Offset

Current

IIO/T−10 − − 10 − − 10 −pA/°C

TA = Thigh to Tlow (Note 7)

Input Common Mode Voltage Range (Note 8),

VCC = 30 V

VICR 0−28.3 0 −28.3 0 −28.3 V

VCC = 30 V, TA = Thigh to Tlow 0−28 0 −28 0 −28

Differential Input Voltage Range VIDR − − VCC − − VCC − − VCC V

Large Signal Open Loop Voltage Gain AVOL V/mV

RL = 2.0 k, VCC = 15 V, For Large VO Swing, 25 100 −25 100 −25 100 −

TA = Thigh to Tlow (Note 7) 15 − − 15 − − 15 − −

Channel Separation CS − −120 − − −120 − − −120 −dB

1.0 kHz ≤ f ≤ 20 kHz, Input Referenced

Common Mode Rejection CMR 50 70 −50 70 −50 70 −dB

RS ≤ 10 k

Power Supply Rejection PSR 50 100 −50 100 −50 100 −dB

Output Voltage−High Limit

TA = Thigh to Tlow (Note 7)

VOH V

VCC = 5.0 V, RL = 2.0 k, TA = 25°C3.3 3.5 −3.3 3.5 −3.3 3.5 −

VCC = 30 V, RL = 2.0 k26 − − 26 − − 26 − −

VCC = 30 V, RL = 10 k27 28 −27 28 −27 28 −

Output Voltage−Low Limit VOL −5.0 20 −5.0 20 −5.0 20 mV

VCC = 5.0 V, RL = 10 k,

TA = Thigh to Tlow (Note 7)

Output Source Current IO+20 40 −20 40 −20 40 −mA

VID = +1.0 V, VCC = 15 V

Output Sink Current IO−

VID = −1.0 V, VCC = 15 V 10 20 −10 20 −10 20 −mA

VID = −1.0 V, VO = 200 mV − − − − − − − − − A

Output Short Circuit to Ground (Note 9) ISC −40 60 −40 60 −40 60 mA

Power Supply Current (Total Device)

TA = Thigh to Tlow (Note 7)

ICC mA

VCC = 30 V, VO = 0 V, RL = ∞−1.5 3.0 −1.5 3.0 −1.5 3.0

VCC = 5 V, VO = 0 V, RL = ∞−0.7 1.2 −0.7 1.2 −0.7 1.2

7. LM258: Tlow = −25°C, Thigh = +85°C LM358, LM358A, LM358E: Tlow = 0°C, Thigh = +70°C

LM2904/A/E: Tlow = −40°C, Thigh = +105°C LM2904V & NCV2904: Tlow = −40°C, Thigh = +125°C

NCV2904 is qualified for automotive use.

8. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of

the common mode voltage range is VCC − 1.7 V.

9. Short circuits from the output to VCC can cause excessive heating and eventual destruction. Destructive dissipation can result from

simultaneous shorts on all amplifiers.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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CIRCUIT DESCRIPTION

The LM358 series is made using two internally

compensated, two−stage operational amplifiers. The first

stage of each consists of differential input devices Q20 and

Q18 with input buffer transistors Q21 and Q17 and the

differential to single ended converter Q3 and Q4. The first

stage performs not only the first stage gain function but also

performs the level shifting and transconductance reduction

functions. By reducing the transconductance, a smaller

compensation capacitor (only 5.0 pF) can be employed, thus

saving chip area. The transconductance reduction is

accomplished by splitting the collectors of Q20 and Q18.

Another feature of this input stage is that the input common

mode range can include the negative supply or ground, in

single supply operation, without saturating either the input

devices or the differential to single−ended converter. The

second stage consists of a standard current source load

amplifier stage.

Each amplifier is biased from an internal−voltage

regulator which has a low temperature coefficient thus

giving each amplifier good temperature characteristics as

well as excellent power supply rejection.

Figure 3. Large Signal Voltage

Follower Response

5.0 s/DIV

1.0 V/DIV

VCC = 15 Vdc

RL = 2.0 k

TA = 25°C

AVOL, OPEN LOOP VOLTAGE GAIN (dB)

V , INPUT VOLTAGE (V)

Figure 4. Input Voltage Range Figure 5. Large−Signal Open Loop Voltage Gain

8.0

6.0

4.0

2.0

0 2.0 4.0 6.0 8.0 10 12 14 16 18 20

VCC/VEE, POWER SUPPLY VOLTAGES (V)

120

100

-20

1.0 10 100 1.0 k 10 k 100 k 1.0 M

f, FREQUENCY (Hz)

Negative

Positive

VCC = 15 V

VEE = Gnd

TA = 25°C

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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VOR, OUTPUT VOLTAGE RANGE (V )

VO, OUTPUT VOLTAGE (mV)

Figure 6. Large−Signal Frequency Response Figure 7. Small Signal Voltage Follower

Pulse Response (Noninverting)

Figure 8. Power Supply Current versus

Power Supply Voltage

Figure 9. Input Bias Current versus

Supply Voltage

8.0

6.0

4.0

2.0

1.0 10 100 1000

f, FREQUENCY (kHz)

550

500

450

400

350

300

250

200

00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

t, TIME s)

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

00 5.0 10 15 20 25 30 35

VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V)

70 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20

I , POWER SUPPLY CURRENT (mA)

I , INPUT BIAS CURRENT (nA)

RL = 2.0 k

VCC = 15 V

VEE = Gnd

Gain = -100

RI = 1.0 k

RF = 100 k

Input

Output

TA = 25°C

RL = R

VCC = 30 V

VEE = Gnd

TA = 25°C

CL = 50 pF

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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TBP

R1 + R2

eo = C (1 + a + b) (e2 - e1)

R1 a R1

b R1

1/2

LM358

1/2

LM358

Vref

Vin

VOH

VOL

VinL = R1 (VOL - Vref)+ Vref

VinH =(VOH - Vref) + Vref

H = R1 + R2 (VOH - VOL)

100 k

C1 R2

100 k

Vin

Vref

Bandpass

Output

fo = 2 

R1 = QR

R2 =

R3 = TN R2

C1 = 10 C

Notch Output

Vref =V

Hysteresis

1/2

LM358

1/2

LM358

VinL VinH

Vref

1/2

LM358

1/2

LM358 1/2

LM358

TBP = Center Frequency Gain

TN = Passband Notch Gain

For:

TBP

= 1.0 kHz

= 10

= 1

= 160 k

= 0.001 F

= 1.6 M

Where:

MC1403

1/2

LM358

VCC

2.5 V

50 k

10 k

Vref

Vref = VCC

5.0 k

1/2

LM358

2  RC

For: fo = 1.0 kHz

R = 16 k

C = 0.01 F

VO = 2.5 V (1 + R1

R2 )

VCC

fo =

Figure 10. Voltage Reference Figure 11. Wien Bridge Oscillator

Figure 12. High Impedance Differential Amplifier Figure 13. Comparator with Hysteresis

Figure 14. Bi−Quad Filter

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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Vref =V

Figure 15. Function Generator Figure 16. Multiple Feedback Bandpass Filter

For less than 10% error from operational amplifier.

If source impedance varies, filter may be preceded with voltage

follower buffer to stabilize filter parameters.

Where fo and BW are expressed in Hz.

Qo fo

BW < 0.1

Given: fo = center frequency

A(fo) = gain at center frequency

Choose value fo, C

Then: R3 = Q

 fo C

R1 = 2 A(fo)

R1 R3

4Q2 R1 -R3

R2 =

Vref =V

Vref

f = R1 + RC

4 CRf R1 R3 = R2 R1

R2 + R1

300 k

75 k

Triangle Wave

Output

Square

Wave

Output

VCC

Vref

Vin

CO = 10 C

if,

1/2

LM358

Vref

1/2

LM358

1/2

LM358

100 k

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

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ORDERING INFORMATION

Device Operating Temperature Range Package Shipping†

LM358ADR2G

0°C to +70°C

SOIC−8

(Pb−Free)

2500 / Tape & Reel

LM358DG 98 Units / Rail

LM358DR2G 2500 / Tape & Reel

LM358EDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

LM358DMR2G Micro8

(Pb−Free)

4000 / Tape & Reel

LM358NG PDIP−8

(Pb−Free)

50 Units / Rail

LM258DG

−25°C to +85°C

SOIC−8

(Pb−Free)

98 Units / Rail

LM258DR2G 2500 / Tape & Reel

LM258DMR2G Micro8

(Pb−Free)

4000 / Tape & Reel

LM258NG PDIP−8

(Pb−Free)

50 Units / Rail

LM2904DG

−40°C to +105°C

SOIC−8

(Pb−Free)

98 Units / Rail

LM2904DR2G 2500 / Tape & Reel

LM2904EDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

LM2904DMR2G Micro8

(Pb−Free)

2500 / Tape & Reel

LM2904NG PDIP−8

(Pb−Free)

50 Units / Rail

LM2904ADMG Micro8

(Pb−Free)

4000 / Tape & Reel

LM2904ADMR2G 4000 / Tape & Reel

LM2904ANG PDIP−8

(Pb−Free)

50 Units / Rail

LM2904VDG

−40°C to +125°C

SOIC−8

(Pb−Free)

98 Units / Rail

LM2904VDR2G 2500 / Tape & Reel

LM2904VDMR2G Micro8

(Pb−Free)

4000 / Tape & Reel

LM2904VNG PDIP−8

(Pb−Free)

50 Units / Rail

NCV2904DR2G* SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCV2904DMR2G* Micro8

(Pb−Free)

4000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

LM258, LM358, LM358A, LM358E, LM2904, LM2904A, LM2904E, LM2904V, NCV2904

www.onsemi.com

PDIP−8

N SUFFIX

CASE 626

SOIC−8

D SUFFIX

CASE 751

MARKING DIAGRAMS

x = 2 or 3

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Package

G= Pb−Free Package − (Note: Microdot may be in either location)

PDIP−8

AN SUFFIX

CASE 626

SOIC−8

VD SUFFIX

CASE 751

PDIP−8

VN SUFFIX

CASE 626

LMx58N

AWL

YYWWG

LM2904AN

AWL

YYWWG

LM2904N

AWL

YYWWG

LM2904VN

AWL

YYWWG

Micro8

DMR2 SUFFIX

CASE 846A

x58

AYWG

2904

AYWG

904A

AYWG

904V

AYWG

*This diagram also applies to NCV2904

LM358

ALYWA

2904

ALYW

2904V

ALYW

LMx58

ALYW

358E

ALYWA

2904E

ALYW

PDIP−8

CASE 626−05

ISSUE P

DATE 22 APR 2015

SCALE 1:1

NOTE 8

XXXXXXXXX

AWL

YYWWG

GENERIC

MARKING DIAGRAM*

XXXX = Specific Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

TOP VIEW

SEATING

PLANE

0.010 CA

SIDE VIEW

END VIEW

WITH LEADS CONSTRAINED

DIM MIN MAX

INCHES

A−−−− 0.210

A1 0.015 −−−−

b0.014 0.022

C0.008 0.014

D0.355 0.400

D1 0.005 −−−−

e0.100 BSC

E0.300 0.325

M−−−− 10

−−− 5.33

0.38 −−−

0.35 0.56

0.20 0.36

9.02 10.16

0.13 −−−

2.54 BSC

7.62 8.26

−−− 10

MIN MAX

MILLIMETERS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-

AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.

4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE

NOT TO EXCEED 0.10 INCH.

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM

PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR

TO DATUM C.

6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE

LEADS UNCONSTRAINED.

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE

LEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE

CORNERS).

E1 0.240 0.280 6.10 7.11

eB −−−− 0.430 −−− 10.92

0.060 TYP 1.52 TYP

A2 0.115 0.195 2.92 4.95

L0.115 0.150 2.92 3.81

°°

NOTE 5

e/2 A2

NOTE 3

MBMNOTE 6

STYLE 1:

PIN 1. AC IN

2. DC + IN

3. DC − IN

4. AC IN

5. GROUND

6. OUTPUT

7. AUXILIARY

8. VCC

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42420B

DOCUMENT NUMBER:

DESCRIPTION:

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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

PDIP−8

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

XXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

XXXXX

ALYWX

IC Discrete

XXXXXX

AYWW

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXX

AYWW

(Pb−Free)

XXXXX

ALYWX

(Pb−Free)

XXXXXX = Specific Device Code

A = Assembly Location

Y = Year

WW = Work Week

G= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42564B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 3:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 7:

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 15:

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 23:

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42564B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

SOIC−8 NB

Micro8

CASE 846A−02

ISSUE K

DATE 16 JUL 2020

SCALE 2:1

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 2:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

STYLE 3:

PIN 1. N-SOURCE

2. N-GATE

3. P-SOURCE

4. P-GATE

5. P-DRAIN

6. P-DRAIN

7. N-DRAIN

8. N-DRAIN

GENERIC

MARKING DIAGRAM*

XXXX = Specific Device Code

A = Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

XXXX

AYWG

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

(Note: Microdot may be in either location)

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB14087C

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

MICRO8

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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

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