© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 9
1Publication Order Number:
MC14555B/D
MC14555B, MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
Features
•Diode Protection on All Inputs
•Active High or Active Low Outputs
•Expandable
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•All Outputs Buffered
•Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter Symbol Value Unit
DC Supply Voltage Range VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout −0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout ±10 mA
Power Dissipation, per Package (Note 1) PD500 mW
Ambient Temperature Range TA−55 to +125 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (8−Second Soldering) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/°C From 65°C To 125°C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
x = 5 or 6
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B 1
16
1455xBG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC1455xB
ALYWG
16
1
MC1455xBCP
AWLYYWWG
1
1
1
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q0B
BB
AB
EB
VDD
Q3B
Q2B
Q1B
Q0A
BA
AA
EA
VSS
Q3A
Q2A
Q1A
MC14555B
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q0B
BB
AB
EB
VDD
Q3B
Q2B
Q1B
Q0A
BA
AA
EA
VSS
Q3A
Q2A
Q1A
MC14556B
PIN ASSIGNMENTS
MC14555B, MC14556B
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2
TRUTH TABLE
Inputs Outputs
Enable Select MC14555B MC14556B
EB A Q3 Q2 Q1 Q0 Q3Q2Q1Q0
0 0 0 0 0011110
0 0 1 0 0101101
0 1 0 0 1001011
0 1 1 1 0000111
1 X X 0 0001111
X = Don’t Care
BLOCK DIAGRAM
24
MC14555B MC14556B
3
1
14
13
15
5
6
7
12
11
10
9
24
3
1
14
13
15
5
6
7
12
11
10
9
VDD = PIN 16
VSS = PIN 8
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q0
Q1
Q2
Q3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55°C 25°C 125°C
Unit
Min Max Min
Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current Iin 15 −±0.1 −±0.00001 ±0.1 −±1.0 mAdc
Input Capacitance, (Vin = 0) Cin − − − − 5.0 7.5 − − pF
Quiescent Current (Per Package) IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (0.85 mA/kHz) f + IDD
IT = (1.70 mA/kHz) f + IDD
IT = (2.60 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
MC14555B, MC14556B
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25°C)
Characteristic Symbol VDD Min
Typ
(Note 6) Max Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay Time − A, B to Output
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns
tPLH, tPHL = (0.66 ns/pF) CL + 62 ns
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns
tPLH,
tPHL 5.0
10
15
−
−
−
220
95
70
440
190
140
ns
Propagation Delay Time − E to Output
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns
tPLH, tPHL = (0.66 ns/pF) CL + 52 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
tPLH,
tPHL 5.0
10
15
−
−
−
200
85
65
400
170
130
ns
5. The formulas given are for the typical characteristics only at 25°C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms
All 8 outputs connect to respective CL loads.
f in respect to a system clock.
INPUT E LOW
20 ns 20 ns
90%
50%
10%
2f
1
VDD
VSS
VDD
VSS
VOH
VOL
A INPUTS
(50% DUTY CYCLE)
B INPUTS
(50% DUTY CYCLE)
OUTPUT Q1
20 ns 20 ns
VDD
VSS
VOH
VOL
VOH
VOL
90%
50%
10%
90%
50%
10%
90%
50%
10%
tPLH
tTLH
tPHL
tPHL
tTHL
tPLH
tTLH tTHL
INPUT A HIGH, INPUT E LOW
INPUT B
OUTPUT Q3
MC14556B
OUTPUT Q3
MC14555B
LOGIC DIAGRAM
(1/2 of Dual)
*Eliminated for MC14555B
*
*
*
*
Q0
Q1
Q2
Q3
E
B
A
MC14555B, MC14556B
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4
ORDERING INFORMATION
Device Package Shipping†
MC14555BCPG PDIP−16
(Pb−Free) 500 Units / Rail
MC14555BDG SOIC−16
(Pb−Free) 48 Units / Rail
MC14555BDR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
MC14555BFELG SOEIAJ−16
(Pb−Free) 2000 / Tape & Reel
MC14556BCPG PDIP−16
(Pb−Free) 500 Units / Rail
MC14556BDR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
MC14556BFELG SOEIAJ−16
(Pb−Free) 2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC14555B, MC14556B
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5
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
MC14555B, MC14556B
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6
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
MC14555B/D
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