SCBS134K - SEPTEMBER 1992 - REVISED JANUARY 2004 D Supports Mixed-Mode Signal Operation D D D D D DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) (5-V Input and Output Voltages With 3.3-V VCC ) Supports Unregulated Battery Operation Down To 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 description/ordering information This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. ORDERING INFORMATION TOP-SIDE MARKING Tube SN74LVT240ADW Tape and reel SN74LVT240ADWR SOP - NS Tape and reel SN74LVT240ANSR LVT240A SSOP - DB Tape and reel SN74LVT240ADBR LX240A Tube SN74LVT240APW Tape and reel SN74LVT240APWR Tape and reel SN74LVT240ADGVR SOIC - DW -40C -40 C to 85 85C C ORDERABLE PART NUMBER PACKAGE TA TSSOP - PW TVSOP - DGV LVT240A LX240A LX240A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"# $ %&'# "$ (&)*%"# +"#' +&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$ $#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+' #'$#0 "** (""!'#'$ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCBS134K - SEPTEMBER 1992 - REVISED JANUARY 2004 FUNCTION TABLE (each 4-bit buffer) INPUTS OE A OUTPUT Y L H L L L H H X Z logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCBS134K - SEPTEMBER 1992 - REVISED JANUARY 2004 recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 5.5 V IOH IOL High-level output current -32 mA t/v Input transition rise or fall rate t/VCC TA Power-up ramp rate 200 Operating free-air temperature -40 High-level input voltage 2 V 0.8 Low-level output current Outputs enabled V V 64 mA 5 ns/V s/V 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS TYP MAX UNIT -1.2 V VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = -18 mA IOH = -100 A VCC = 2.7 V, VCC = 3 V, IOH = - 8 mA IOH = - 32 mA IOL = 100 A IOL = 24 mA 0.2 VCC = 2.7 V 0.4 VCC = 3 V IOL = 16 mA IOL = 32 mA 0.55 VCC = 0 or 3.6 V, IOL = 64 mA VI = 5.5 V VCC = 3.6 V VI = VCC or GND VI = VCC VOL II MIN VCC-0.2 2.4 V 2 0.5 V 0.5 10 1 Control inputs 1 VI = 0 VI or VO = 0 to 4.5 V Data inputs A A -5 100 A 5 A -5 A 100 A Ioff IOZH VCC = 0, VCC = 3.6 V, IOZL VCC = 3.6 V, VO = 3 V VO = 0.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care 100 A Outputs high 0.19 ICC VCC = 3.6 V, VI = VCC or GND IO = 0, Outputs disabled ICC VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 Co 5 Outputs low mA 0.19 0.2 mA 4 pF 7 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCBS134K - SEPTEMBER 1992 - REVISED JANUARY 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y PARAMETER All typical values are at VCC = 3.3 V, TA = 25C. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VCC = 3.3 V 0.3 V VCC = 2.7 V MIN TYP MAX 1.1 2.2 3.8 4.6 1.3 2.6 4 4.2 1.1 2.6 4.6 5.6 1.4 2.7 4.4 5 2 2.9 4.4 4.6 1.8 3 4.3 4.3 MIN UNIT MAX ns ns ns SCBS134K - SEPTEMBER 1992 - REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 2.7 V 1.5 V Input Output Control 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V tPLZ 3V 1.5 V tPZH tPLH tPHL 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPHL tPLH 1.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVT240ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVT240APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVT240ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVT240ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LVT240ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74LVT240APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT240ADBR SN74LVT240ADWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74LVT240ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVT240APWR TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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