SCLS103E - MARCH 1984 - REVISED JULY 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Interface D Directly With System Bus or Can Drive Up To 15 LSTTL Loads Low Power Consumption, 80-A Max ICC D Typical tpd = 11 ns D 6-mA Output Drive at 5 V D Low Input Current of 1 A Max SN54HC126 . . . FK PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1Y NC 2OE NC 2A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A 1OE 1A 1Y 2OE 2A 2Y GND 1A 1OE NC VCC 4OE SN54HC126 . . . J OR W PACKAGE SN74HC126 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC - No internal connection description/ordering information These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION PACKAGE TA PDIP - N SN74HC126N Tube of 50 SN74HC126D Reel of 2500 SN74HC126DR Reel of 250 SN74HC126DT SOP - NS Reel of 2000 SN74HC126NSR HC126 SSOP - DB Reel of 2000 SN74HC126DBR HC126 Tube of 90 SN74HC126PW Reel of 2000 SN74HC126PWR Reel of 250 SN74HC126PWT CDIP - J Tube of 25 SNJ54HC126J SNJ54HC126J CFP - W Tube of 150 SNJ54HC126W SNJ54HC126W LCCC - FK Tube of 55 SNJ54HC126FK TSSOP - PW -55C -55 C to 125 125C C TOP-SIDE MARKING Tube of 25 SOIC - D -40C -40 C to 85 85C C ORDERABLE PART NUMBER SN74HC126N HC126 HC126 SNJ54HC126FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. *"!-('%& '!#*,$% %! 45 $,, *$"$#)%)"& $") %)&%)(,)&& !%/)"1&) !%)-. $,, !%/)" *"!-('%& *"!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS103E - MARCH 1984 - REVISED JULY 2003 FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y H H H H L L L X Z logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 3A 4 5 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS103E - MARCH 1984 - REVISED JULY 2003 recommended operating conditions (see Note 3) SN54HC126 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO t/v MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time NOM 1.5 0 Output voltage MIN 1.5 VCC = 4.5 V VCC = 6 V Low-level input voltage SN74HC126 0 VCC VCC 0 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VI = VCC or 0, MIN MAX SN74HC126 MIN MAX UNIT 1.9 1.998 1.9 1.9 IOH = -20 A 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = -6 mA IOH = -7.8 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 A 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 6V 0.01 0.5 10 5 A 8 160 80 A 10 10 10 pF IOL = 6 mA IOL = 7.8 mA ICC Ci SN54HC126 2V VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 TA = 25C MIN TYP MAX 4.5 V VI = VIH or VIL II IOZ VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 * DALLAS, TEXAS 75265 V V 3 SCLS103E - MARCH 1984 - REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25C TYP MAX SN54HC126 SN74HC126 PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 47 120 180 150 tpd A Y 4.5 V 14 24 36 30 6V 11 20 31 26 ten OE tdis Y OE Y tt Any MIN MIN MAX MIN MAX 2V 57 120 180 150 4.5 V 16 24 36 30 6V 12 20 31 26 2V 35 120 180 150 4.5 V 17 24 36 30 6V 15 20 31 26 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 UNIT ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten FROM (INPUT) TA = 25C MIN TYP MAX SN54HC126 SN74HC126 TO (OUTPUT) VCC 2V 67 150 225 188 Y 4.5 V 19 30 45 38 6V 15 25 39 33 2V 100 135 202 169 4.5 V 20 27 40 36 6V 17 23 36 30 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 A OE Y tt Any MIN MAX MIN MAX UNIT ns ns ns operating characteristics, TA = 25C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 No load * DALLAS, TEXAS 75265 TYP 45 UNIT pF SCLS103E - MARCH 1984 - REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 tPZH ten RL CL (see Note A) 1 k tPZL tPHZ tdis S2 RL 1 k CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF tPLZ tpd or tt -- LOAD CIRCUIT 50 pF or 150 pF VCC Input 50% 50% 0V tPLH In-Phase Output 50% 10% tPHL 90% VOH 50% 10% V OL tf 90% tr tPHL Out-of-Phase Output 90% tPLH 50% 10% 50% 10% 90% VOH VOL tf tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Control VCC 50% 50% 0V tPZL Output Waveform 1 (See Note B) tPLZ VCC 50% 10% tPZH Input 50% 10% 90% VCC 90% 50% 10% 0 V tr Output Waveform 2 (See Note B) VOL tPHZ 50% 90% VOH 0 V tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-8684801CA ACTIVE CDIP J 14 1 TBD Call TI Call TI SN54HC126J ACTIVE CDIP J 14 1 TBD SN74HC126D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) SN74HC126DBLE OBSOLETE SSOP DB 14 SN74HC126DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126DTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 25 Pb-Free (RoHS) TBD SN74HC126N ACTIVE PDIP N 14 SN74HC126N3 OBSOLETE PDIP N 14 SN74HC126NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) SN74HC126NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) TBD Addendum-Page 1 N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM Call TI Call TI CU NIPDAU N / A for Pkg Type Call TI Samples (Requires Login) 5962-86848012A A42 (3) Call TI CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 5-Sep-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74HC126NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC126PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HC126FK ACTIVE LCCC FK 20 1 TBD SNJ54HC126J ACTIVE CDIP J 14 1 TBD POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC126, SN74HC126 : * Catalog: SN74HC126 * Military: SN54HC126 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC126DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC126DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC126DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC126NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC126PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC126PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC126DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HC126DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC126DT SOIC D 14 250 367.0 367.0 38.0 SN74HC126NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC126PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC126PWT TSSOP PW 14 250 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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