Using the HI5703 Evaluation Board Application Note Description The HI5703EVAL evaluation board for the HI5703 can be used to evaluate the performance of the HI5703 10-bit 40 MSPS analog-to-digital converter (ADC). As shown in the Evaluation Board Block Diagram, this evaluation board includes clock driver circuitry, reference voltage generators, and a choice of analog input drive circuits. Buffered digital data outputs are conveniently provided for easy interfacing to a ribbon connector or logic probes. The evaluation board is provided with some prototyping area for the addition of user designed custom interfaces or circuits. Additionally, the evaluation board is provided with eight removable jumpers to allow for various operational configurations. HI5703 A/D Theory of Operation The HI5703 is a 10-bit fully differential sampling pipelined A/D converter with digital error correction. Figure 1 depicts the circuit for the converters front-end differential-in-differential-out sample-and-hold (S/H). The switches are controlled by an internal clock which is a non-overlapping two phase signal, 1 and 2, derived from the master clock (CLK) driving the converter. During the sampling phase, 1, the input signal is applied to the sampling capacitors, CS. At the same time the holding capacitors, CH, are discharged to analog ground. At the falling edge of 1 the input signal is sampled January 1996 AN9534.1 on the bottom plates of the sampling capacitors. In the next clock phase, 2, the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH, completing one sample-and-hold cycle. The output of the sample-and-hold is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function, but can also convert a single-ended input to a fullydifferential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of the switches and CS. The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. As illustrated in the HI5703 Functional Block Diagram and the timing diagram in Figure 2, nine identical pipeline subconverter stages, each containing a two-bit flash converter and a two-bit multiplying digital-to-analog converter, follow the front end S/H circuit with the tenth stage being a one bit flash converter. Each converter stage in the pipeline will be sampling in one clock phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal so that alternate stages in the pipeline will perform the same operation. Evaluation Board Block Diagram TTL COMP CLK CLOCK OUT 50 +5VD -5.2VD 2.5V REF CLK VREF + +3.25V +2V EXTREF+ VREF - VIDEO 10 DOUT EXTREF- DATA OUT BUFFER 75 VIN RF IN RF XFORMER HI5702 DGND AGND 50 +5VD -5.2VD +5VA 1 1-888-INTERSIL or 321-724-7143 | Copyright -5VA (c) Intersil Corporation 1999 Application Note 9534 HI5703 Functional Block Diagram CLOCK BIAS VDC CLK VINVIN+ S/H STAGE 1 DFS 2-BIT FLASH 2-BIT DAC OE + - X2 D9 (MSB) D8 D7 D6 DIGITAL DELAY AND DIGITAL ERROR CORRECTION STAGE 9 D5 D4 D3 2-BIT FLASH 2-BIT DAC D2 D1 + D0 (LSB) - X2 STAGE 10 1-BIT FLASH AVCC 2 AGND DVCC1 DVCC2 DGND VREF + VREF - Application Note 9534 1 VIN + 1 1 1 CH CS 2 VIN - digital delay line is to time align the digital outputs of the nine identical two-bit subconverter stages with the corresponding output of the tenth stage flash converter before inputting the nineteen bit result into the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. VOUT + -+ + - VOUT- CS CH 1 1 FIGURE 1. ANALOG INPUT SAMPLE-AND-HOLD The output of each of the nine identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal clock. The function of the Because of the pipeline nature of this converter, the digital data representing an analog input sample is output on the bus at the 7th cycle of the clock after the analog sample is taken. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The output data is synchronized to the external clock by a double buffered latching technique. The output of the digital correction circuit is available in two's complement or offset binary format depending on the condition of the Data Format Select (DFS) input. ANALOG INPUT CLOCK INPUT SN-1 HN-1 SN HN SN+1 HN+1 SN+2 SN+5 HN+5 SN+6 HN+6 SN+7 HN+7 SN+8 HN+8 INPUT S/H 1ST STAGE 2ND STAGE B1, N-1 B2, N-2 10TH STAGE DATA OUTPUT B1, N B2, N-1 B1, N+1 B1, N+4 B1, N+5 B2, N+4 B2, N B10, N-5 B10, N-4 B10, N-3 B10, N DN-6 DN-5 DN-4 DN-1 B2, N+5 B10, N+1 DN tLAT NOTES: 1. 2. 3. 4. SN: N-th sampling period. HN: N-th holding period. BM, N: M-th stage digital output corresponding to N-th sampled input. DN: Final data output corresponding to N-th sampled input. FIGURE 2. 3 B1, N+6 HI5703 INTERNAL CIRCUIT TIMING B1, N+7 B2, N+6 B10, N+2 B10, N+3 DN+1 DN+2 Application Note 9534 Layout and Power Supplies The HI5703 evaluation board is a three layer board with a layout optimized for the best performance of the ADC. The application note includes an electrical schematic of the evaluation board, a component layout and the various board layers. The user should feel free to copy the layout in their application. Refer to the component layout and the evaluation board electrical schematic for the following discussion. The HI5703 A/D has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The evaluation board provides separate low impedance analog and digital ground planes. Since the analog and digital ground planes are connected together under the ADC, DO NOT tie them together back at the power supplies. The analog and digital supplies are also kept separate on the evaluation board and should be driven by clean linear regulated supplies. They can be hooked up with external 20 gauge wires to the holes marked AVCC1, AVCC2, AVEE, DVCC1, DVCC2, DVEE, AGND and DGND in the prototyping area. DVCC1, DVCC2, and DVEE are digital supplies and should be returned to DGND. AVCC1, AVCC2, and AVEE are the analog supplies and should be returned to AGND. Table 1 lists the operational supply voltages for the evaluation board. Single supply operation of the converter is possible but the overall performance of the converter may degrade. TABLE 1. EVALUATION BOARD POWER SUPPLIES POWER SUPPLY MIN TYP MAX AVCC1 +4.75V +5.0V +5.25V AVCC2 +4.75V +5.0V +5.25V AVEE -5.25V -5.0V -4.75V DVCC1 +4.75V +5.0V +5.25V DVCC2 +4.75V +5.0V +5.25V DVEE -5.45V -5.2V -4.95V Configuration Jumpers The evaluation board is provided with eight removable jumpers (JP1-8) that allow for various operational configurations. The following is a description of the feature provided by each of the configuration jumpers. JP1 is used to establish the analog signal path input to the HI5703 A/D through the VIDEO SMA input connector. JP5 is used to connect the evaluation board positive reference voltage generator output, nominally +3.25V, to the HI5703 positive reference voltage input pin, VREF+. JP6 is used to connect the evaluation board negative reference voltage generator output, nominally +2.0V, to the HI5703 negative reference voltage input pin, VREF-. JP7 is used to control the operational state of the HI5703 digital output drivers. With JP7 installed the digital Output Enable (OE) control input pin is set to a logic "0" enabling the digital data outputs. To place the digital data outputs in the three-state high impedance mode, JP7 is removed and and a TTL logic "1" needs to be applied to the jumper pin connected to the HI5703 digital Output Enable (OE) control input pin. JP8 is used to supply the HI5703 digital output supply pin (DVCC2) with the desired output logic operating voltage level. With JP8 installed the HI5703 digital output supply is connected to the evaluation board +5V digital supply, DVCC1. For operation of the digital outputs at voltages from +3.3V to +5V, JP8 is removed and the desired operating voltage needs to be applied to the jumper pin connected to the HI5703 A/D digital output supply pin (DVCC2, pin 23). Reference Voltage Generator Circuit The HI5703 A/D contains a resistive ladder between the reference voltage input pins. The A/D requires two reference voltages, one connected to the VREF+ input pin and the other connected to the VREF- input pin. The reference voltage that drives VREF+ must be able to source the maximum reference current which will then flow into the VREF- reference. The HI5703 is tested with VREF- equal to 2V and VREF+ equal to 3.25V for a fully differential analog input voltage range of 1.25V. VREF+ and VREF- can differ from the above voltages as long as the reference common mode voltage, (VREF+ + VREF-)/2, at the reference pins does not exceed 2.625V 50mV. The reference circuit on the evaluation board contains a precision +2.5V reference (U4) along with operational amplifiers (U5A and U5B) that are utilized to generate the reference voltages for the HI5703. The reference voltages are set at the factory to the levels required by the HI5703 as follows. The VREF- reference input is set FIRST by monitoring JP6 with a DVM and adjusting R11 until a reading of 2.0V 5mV is obtained. Next the VREF+ reference input is set by monitoring JP5 with a DVM and adjusting R15 until a reading of 3.25V 5mV is obtained. JP2 is used to connect the HI5703 bias voltage output (VDC) to the differential inputs, VIN+ and VIN-, of the A/D. Sample Clock Driver, Timing and I/O JP3 is used to connect an external user supplied DC bias voltage to the differential inputs, VIN+ and VIN-, of the A/D. In order to ensure rated performance of the HI5703, the duty cycle of the sample clock should be held at 50%. It must also have low phase noise and operate at standard TTL levels. JP4 configures the digital output data format of the HI5703 by setting the logic level of the Data Format Select (DFS) input pin. With the JP4 jumper installed DFS is set to a logic "0" establishing the digital data output format to offset binary. With the JP4 jumper removed DFS is set to a logic "1" establishing the digital data output format to two's complement. It can be difficult to find a low phase noise generator that will provide a 40MHz squarewave at TTL logic levels. Therefore, a TTL voltage comparator (U3) is provided on the evaluation board to generate a TTL level sampling clock for the HI5703 when a sinewave (< 3V) or squarewave clock is applied to 4 Application Note 9534 the CLK input of the evaluation board. A potentiometer (R2) is provided to allow the user to adjust the duty cycle of the sampling clock to obtain the best performance from the ADC. The trigger level for the CLK input to the converter is approximately 1.5V. Therefore, the duty cycle of the sampling clock should be measured at the 1.5V trigger level. Figure 3 shows the clock/data timing relationship for the evaluation board. The data corresponding to a particular sample will be available at the digital outputs of the HI5703 after the data latency (7 cycles) plus the HI5703 digital data output delay. Table 2 lists the values that can be expected for the indicated timing delays. Refer to the HI5703 data sheet for additional timing information. The sample clock and digital output data signals are buffered using TTL line drivers and are made available through two connectors contained on the evaluation board. The line buffering allows for driving long leads or analyzer inputs. These drivers are not necessary for the digital output data if the load presented to the converter does not exceed the the data sheet load limits of one standard TTL load and 20pF. P1 allows the evaluation board to be interfaced to the DSP evaluation boards available from Intersil. The digital output data and sample clock can also be accessed by clipping the test leads of a logic analyzer or data acquisition system onto the I/O pins of connector P2. As was mentioned earlier, the A/D converters OE control input pin allows the digital output data bus to be switched to a three-state high impedance mode. This feature enables the testing and debugging of systems which are utilizing one or more converters. This three-state control signal is not intended for use as an enable/disable function on a common data bus and could result in possible bus contention issues. TABLE 2. TIMING SPECIFICATIONS PARAMETER DESCRIPTION - 7ns - tPD1 U3 Prop Delay - 4.5ns 7.0ns tPD2 U6 Prop Delay 1.5ns 3.0ns 5.0ns tPD3 U6/U7 Prop Delay 1.5ns 3.0ns 5.0ns Analog Input The fully differential analog input of the HI5703 A/D can be configured in various ways depending on the signal source and the required level of performance. HI5703 SAMPLE CLOCK INPUT tOD DATA N-1 DATA N tPD2 CLOCK OUT (74F541) tPD3 DATA N-1 DATA N FIGURE 3. EVALUATION BOARD CLOCK/DATA TIMING 5 MAX HI5703 Digital Output Data Delay tPD1 DATA OUT (74F541) TYP tOD CLK INPUT HI5703 DIGITAL DATA OUTPUT MIN Application Note 9534 Differential Analog Input Configuration VIN A fully differential connection (Figure 4) will yield the best performance from the converter. Since the HI5703 is powered off a single +5V supply, the analog input must have an offset that is within the analog input common mode voltage range. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. Assume the difference between the HI5703 reference voltage inputs, VREF + (typically +3.25V) and VREF - (typically +2.0V) , is 1.25V. If VIN is a 1.25VP-P sinewave then VIN+ and VIN- are 1.25VP-P sinewaves riding on a common mode voltage equal to the converters DC bias voltage output, VDC . The converter will be at positive fullscale when the VIN+ input is at VDC + 0.625V and the VIN- input is at VDC- 0.625V (VIN+ - VIN- = +1.25V). Conversely, the converter will be at negative fullscale when the VIN+ input is equal to VDC- 0.625V and the VIN- input is at VDC + 0.625V (VIN+ - VIN- = -1.25V). Consequently, the HI5703 analog input has a fully differential input voltage range of 1.25V. It should be noted that overdriving the analog input beyond the 1.25V fullscale input voltage range will not damage the converter as long as the overdrive voltage stays within the converters analog supply voltages. In the event of an overdrive condition the converter will recover within one sample clock cycle. VIN+ VIN HI5703 VDC -VIN VIN - FIGURE 5. AC COUPLED DIFFERENTIAL INPUTY Transformer Coupled Input Configuration A single-ended input will give better overall system performance if it is first converted to differential before driving the HI5703. An RF transformer can be connected to the HI5703 input, as shown in Figure 5, to provide the single-ended to differential conversion. The particular transformer used will depend on the input voltage level, the impedance desired, and the input frequency range. The transformer will tend to have a bandpass response making it more suitable for narrow band applications. 6 VIN+ HI5703 VDC VIN- FIGURE 6. TRANSFORMER COUPLED INPUT This is the type of single-ended to differential conversion circuit that is provided on the HI5703EVAL evaluation board at the RFIN SMA connector (refer to the HI5703EVAL evaluation board parts layout and the electrical schematic). The impedance seen looking into the RFIN input connector will be 50 when the transformer installed has a 1:2.5 primary to secondary impedance ratio. This is derived as follows. The 200 secondary load (two 100 resistors, R8 and R9, connected across the transformer secondary) are transformed to 80 (200/2.5 = 80) at the transformer primary side input. Now, the impedance seen looking into the RFIN SMA connector is 130 (R5) in parallel with 80 for an effective impedance of 50. A good candidate transformer for this configuration is the Mini-Circuits TMO2.5-6T. The TMO2.5-6T transformer provides a 1dB passband from 0.05MHz to 20MHz. Alternate transformers could be used with minor modifications to the input circuit. For example, if one desired a higher input frequency range than that provided by the TMO2.5-6T transformer one could replace the TMO2.56T with a Mini-Circuits TMO4-1. The TMO4-1 transformer provides a 1dB passband from 2MHz to 100MHz. Since this transformer has a 1:4 primary to secondary impedance ratio it would be necessary to remove R5 to maintain a 50 impedance looking into the RFIN SMA input connector, i.e. the 200 secondary impedance is now transformed to 50 at the transformer primary side (200/4 = 50). When using transformer coupling, care should be excersied in the area of impedance matching or undesirable distortion components could result from mismatching and affect the overall measured performance of the converter. When the single-ended to differential input path (RFIN) is to be used, install transformer T1 and jumper JP2 or JP3 and remove jumper JP1. Jumper JP2 is installed if it is desired to use the +2.8V (typical) DC bias voltage output of the HI5703, otherwise jumper JP3 is installed and an externally supplied DC bias voltage is connected to the VDC(EXT) jumper pin. The acceptable range of VDC(EXT) for a differential input configuration to the HI5703 and a +5V analog supply voltage is from +0.625V to +4.375V, i.e. the HI5703 differential analog input common mode voltage range specification. Figure 6 illustrates the differential analog input common mode voltage range that the converter will accomodate. Application Note 9534 +5V VIN+ VINVDC = 4.375V 1.25VP-P VIN+ +5V +5V +5V VIN+ OR VIN- 2.5VP-P VDC = 3.75V VIN+ OR VIN- 2.5VP-P 1.25V < VDC < 3.75V VIN+ OR VIN- 2.5VP-P VDC = 1.25V VIN0.625V < VDC < 4.375V 1.25VP-P VIN+ VINVDC = 0.625V 1.25VP-P 0V 0V 0V FIGURE 7. DIFFERENTIAL ANALOG INPUT COMMON MODE VOLTAGE RANGE 0V FIGURE 9. DC OFFSET VOLTAGE RANGE FOR SINGLEENDED ANALOG INPUT Single-Ended Input Configuration The configuration shown in Figure 7 may be used to directly drive the HI5703 with a single-ended DC coupled input. Sufficient headroom must be provided such that the analog input voltage never goes above +5V or below AGND. Again, assume the difference between VREF + and VREF - is 1.25V. If VIN (and therefore VIN+) is a 2.5VP-P sinewave riding on a positive voltage equal to VDC, the converter will be at positive fullscale when VIN+ is at VDC + 1.25V (VIN+ - VIN- = +1.25V) and will be at negative fullscale when VIN+ is equal to VDC -1.25V (VIN+ - VIN- = -1.25V). Consequently, the HI5703 analog input has a single-ended input voltage range of 2.5VPP. In this case, with a +5V analog supply voltage, VDC could range between 1.25V and 3.75V (see Figure 8). Optimum single-ended performance can be obtained with a DC bias voltage, VDC, of 1.8V. It should be noted that overdriving the analog input beyond the 2.5VP-P fullscale input voltage range will not damge the converter as long as the overdrive voltage stays within the converters analog supply voltages. In the event of an overdrive condition the converter will recover within one sample clock cycle. VIN VIN+ VDC R HI5703 VDC VIN- FIGURE 8. DC COUPLED SINGLE-ENDED INPUT 7 Video Input Configuration The HI5703EVAL evaluation board provides a single-ended, DC coupled input at the VIDEO SMA input connector (refer to the HI5703EVAL evaluation board parts layout and the electrical schematic). This input drive configuration consists of an inverting buffer circuit (HFA1102 operational amplifier, U2) which will amplify and DC offset (adjustable via potentiometer R12) video signals to the analog input of the HI5703. The nominal input impedance seen at this input connector is 75. This will allow most commercially available video sources to drive the evaluation board directly. When utilizing this analog input path install jumper JP1 and remove RF transformer T1 and jumpers JP2 and JP3. For a single-ended, DC coupled VIDEO input the following procedure can be used to adjust the input analog signal level and DC offset (R12) to obtain a 0V to +2.5V (2.5VP-P) AC signal swing into the converter. Initially set the DC offset potentiometer (R12) to 0V by turning the potentiometer adjustment screw clockwise (CW) until the potentiometer CW stops are felt. Using an oscilloscope, monitor the signal level at the JP1 jumper pin connected to R7 (JP1 jumper must be removed). Adjust the analog input signal level until a (1.39 x 2.5VP-P) = 3.475VP-P signal is obtained on the oscilloscope. The scaling factor of 1.39 is a result of the AC voltage division between R9 (100) and R7 (39). Adjust the DC offset, using potentiometer R12, so the signal at JP1 swings between -0.487V and +2.988V. The DC offset can be adjusted further, for example, to provide a signal at JP1 that swings between +0V and +3.475V, but one should not let the peak signal at JP1 go much beyond the +3.5V level since the signal at the output of the HFA1102 operational amplifier (U2) will start running into the operational amplifier output voltage limit and cause signal distortion. Now reinstall jumper JP1. Using an oscilloscope to look at the signal on JP1, verify the signal into the converter is swinging between 0V and +2.5V. Make any minor adjustments to the input signal level or the DC offset as required. In addition, the input signal bandwidth should be kept below approximately 7.5MHz in order to avoid operational amplifier induced harmonic distortion. Application Note 9534 HI5703 Performance Characterization Dynamic testing is used to evaluate the HI5703 performance. Among these tests are Signal-to-Noise Ratio (SNR), Signal-to-Noise and Distortion Ratio (SINAD), Total Harmonic Distortion (THD), Spurious Free Dynamic Range (SFDR) and InterModulation Distortion (IMD). Figure 9 shows the test system used to perform dynamic testing on high-speed ADC's at Intersil. The clock (CLK) and analog input (AIN) signals are sourced from low phase noise HP8662A synthesized signal generators that are phase locked to each other to ensure coherence. The output of the signal generator driving the ADC analog input is bandpass filtered to improve the harmonic distortion of the analog input signal. The comparator on the evaluation board will convert the sine wave CLK input signal to a square wave at TTL logic levels to drive the sample clock input of the HI5703. The ADC data is captured by a logic analyzer and then transferred over the GPIB bus to the PC. The PC has the required software to perform the Fast Fourier Transform (FFT) and do the data analysis. Coherent testing is recommended in order to avoid the inaccuracies of windowing. The sampling frequency and analog input frequency have the following relationship: FI/FS = M/N, where FI is the frequency of the input analog sinusoid, FS is the sampling frequency, N is the number of samples, and M is the number of cycles over which the samples are taken. By making M an integer and odd number (1, 3, 5, ...) the samples are assured of being nonrepetitive. Refer to the HI5703 data sheet for a complete list of test definitions and the results that can be expected using the evaluation board with the test setup shown. Evaluating the part with a reconstruction DAC is only suggested when doing bandwidth or video testing. Video Testing Finally, mate the DAC reconstruction board P1 connector to the HI5703EVAL evaluation board P2 connector. Correct alignment between the two boards will have P1 pin 34 of the DAC reconstruction board plugged into P2 pin 25 of the HI5703EVAL evaluation board. See Application Note AN9419 "Using the DAC Reconstruct Board" for additional applications information. HP8662A HP8662A REF BANDPASS FILTER CLK RFIN COMPARATOR VIN HI5703 CLK DIGITAL DATA OUTPUT HI5703EVAL EVALUATION BOARD 10 DAS9200 12-BIT DAC GPIB PC OSCILLOSCOPE FIGURE 10. HIGH-SPEED A/D TEST SYSTEM VIDEO SIGNAL SOURCE CLOCK GEN CLK Figure 10 shows how a test system can be configured to do video testing of the HI5703 with the DAC reconstruction board and the HI5703EVAL evaluation board. The appropriate test waveform is generated by a video source such as the TSG100 or TEK1001 from Tektronix and applied to the converter. The digitized video is converted back to analog by the reconstruction DAC for evaluation by a video analyzer, TEK VM700. Since the HI5703 is a 10-bit A/D, install jumpers JP1 and JP2 on the DAC reconstruction board to tie the DAC two LSB's high. Install JP3 so that the video out of the reconstruction board will have negative going sync. JP5-9 on the DAC reconstruction board are utilized to establish the correct clock/data timing relationship into the DAC. Setup the HI5703EVAL evaluation board for video testing by following the procedures outlined previously in the HI5703EVAL evaluation board application note on the video input configuration and single-ended DC coupled analog inputs. Input the video signal to the HI5703EVAL evaluation board through the SMA connector marked VIDEO. Note that all cables carrying video should be 75. 8 VIDEO COMPARATOR VIN HI5703 CLK DIGITAL DATA OUTPUT HI5703EVAL EVALUATION BOARD 10 (P2) 12-BIT DAC RECONSTRUCT BOARD (DACRECON-EV) VIDEO TEK VM700 FIGURE 11. VIDEO TEST SETUP Application Note 9534 TABLE 3. HI5703 PIN DESCRIPTION PIN NO. NAME DESCRIPTION 1 DVCC1 Digital Supply 2 DGND Digital Ground 3 DVCC1 Digital Supply 4 DGND Digital Ground 5 AVCC Analog Supply 6 AGND Analog Ground 7 VREF+ Positive Reference Voltage Input 8 VREF - Negative Reference Voltage Input 9 VIN+ Positive Analog Input 10 VIN- Negative Analog Input 11 VDC DC Bias Voltage Output 12 AGND Analog Ground 13 AVCC Analog Supply 14 OE Digital Output Enable Control Input 15 DFS Data Format Select Input 16 D9 Data Bit 9 Output (MSB) 17 D8 Data Bit 8 Output 18 D7 Data Bit 7 Output 19 D6 Data Bit 6 Output 20 D5 Data Bit 5 Output 21 DGND 22 CLK 23 DVCC2 24 D4 Data Bit 4 Output 25 D3 Data Bit 3 Output 26 D2 Data Bit 2 Output 27 D1 Data Bit 1 Output 28 D0 Data Bit 0 Output (LSB) Digital Ground Sample Clock Input Digital Output Supply (+3.3V to +5V) 9 Application Note 9534 FIGURE 11. HI5703EVAL EVALUATION BOARD PARTS LAYOUT FIGURE 12. HI5703EVAL EVALUATION BOARD COMPONENT SIDE 10 Application Note 9534 FIGURE 13. HI5703EVAL EVALUATION BOARD GROUND LAYER FIGURE 14. HI5703EVAL EVALUATION BOARD SOLDER SIDE 11 Application Note 9534 HI5703EVAL Evaluation Board Schematic Diagrams C5 RFIN 2 1 T1 4 R5 130 R8 100 + 10F C2 R9 100 6 7, 8 VR 0.01F CCW VIN+ JP2 AVCC2 C4 0.1F CW DVCC1 3 2 R21 VIDEO U2 1 7 VIN - 10 V IN VREF + 7 V REF + VREF - 8 V - R22 DVCC2 499 3 23 13 5 HI5703 REF 1 CLK U3 5 V+ 2 R6 51 3 R1 DVCC2 820 R2 R3 2K LE + Q Q - GND V6 4 C1 0.1F DVEE 820 22 TP1 DVCC2 R4 8 1K CLOCK 7 JP4 15 16 17 18 19 20 24 25 26 27 28 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DC HFA1102 AVEE AVCC1 JP8 VIN + 9 V + IN VDC 11 V 39 4 R10 200 130 VIN- DVCC1 DVCC1DVCC2 AVCCAVCC R7 6 + - C3 33pF VDC (EXT) JP3 JP1 R12 10K VDC CLK DFS DGND AGND DGND DGND AGND OE 2 4 21 6 12 14 AD9696 U1 JP7 DVEE AVCC2 R14 1 2 + - 4 CA158A AVEE AVCC2 2 4 VIN GND 0.01F 10K U4 VOUT TRIM REF03 5 R11 10K 8 5 R17 51 4 CA158A JP6 + C11 10F C8 0.01F R19 10K VREF + 2.0V U5B 7 6 + - C6 0.1F C10 0.1F R16 AVCC2 AVEE 12 + C9 10F 15K R13 8.2K 6 JP5 51 C7 R15 VR 3.25V U5A 8 3 R18 10K C12 0.1F VREF - D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Application Note 9534 HI5703EVAL Evaluation Board Schematic Diagrams U7 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 1 19 P2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 (Continued) 18 17 16 15 14 13 12 11 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 G1 G2 74F541 DOUT0 1 DOUT1 3 DOUT2 5 DOUT3 7 DOUT4 9 DOUT5 11 DOUT6 13 DOUT7 15 DOUT8 17 DOUT9 19 21 CLKOUT 23 25 P1C 2 4 6 8 10 12 14 16 18 20 22 24 DOUT1 DOUT2 DOUT4 DOUT6 DOUT8 U8 D8 D9 CLOCK R20 1K DVCC2 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 DOUT8 18 DOUT9 17 16 CLKOUT 15 14 13 12 11 CLKOUT G1 G2 74F541 FB5 DVCC2 +5V +5V AVCC2 + C13 10F +5V FB4 DVCC1 DVCC2 DVCC1 AVCC1 + C14 10F +5V DGND DVEE FB6 DOUT3 DOUT5 DOUT7 DOUT9 FB1 AVCC2 FB3 AVCC1 FB2 AVEE + C29 10F AVEE -5V DVCC2 DVCC1 C18 0.1F U1 C17 0.1F U1 AVCC1 C21 0.1F U6 DVEE C31 0.1F U3 C22 0.1F U7 AVCC2 C24 0.1F U1 13 DOUT0 + C28 10F + C30 10F DVEE -5.2V C23 0.1F U1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 AGND + C15 10F C16 0.1F U1 P1A C25 0.1F U2 C26 0.1F U5 C27 0.1F U3 AVEE C32 0.1F U4 C19 0.1F U2 C20 0.1F U5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 Application Note 9534 HI5703EVAL Evaluation Board Parts List REFERENCE DESIGNATOR QTY DESCRIPTION R4, R20 2 1k, 1/8W, 5% R1, R3 2 820, 1/8W, 5% R6, R14, R17 3 51, 1/8W, 5% R18, R19 2 10k, 1/8W, 5% R8, R9 2 100, 1/8W, 5% R7 1 39, 1/8W, 5% R21 1 200, 1/8W, 5% R16 1 15k, 1/8W, 5% R13 1 8.2k, 1/8W, 5% R5, R10 2 130, 1/4W, 5% R22 1 499, 1206 CHIP R2 1 2k Trim Pot R12, R11, R15 3 10k Trim Pot C5, C9, C11, C13, C14, C15, C19, C25, C28, C29, C30 11 10F Tant Cap, 35WVDC, 20% C2, C7, C8 3 0.01F Ceramic Cap, 100WVDC, 10% C33, C34 2 1000pF 1206 Chip Cap, 50WVDC, XR7 10% C1, C4, C6, C20, C26, C27, C31 7 0.1F Ceramic Cap, 50WVDC, 10% C10, C12, C16, C17, C18, C21, C22, C23, C24, C32 10 0.1F 1206 Chip Cap, 50WVDC, Z5U, 20% C3 1 33pF 1206 Chip Cap, 100WVDC, COG(NPO), 5% FB1-6 6 10H Ferrite Bead T1 1 RF Transformer TP1 1 Probe Tip Adapter JP1-8 8 1 x 2 Header J1-8 8 1 x 2 Header Jumper P2 1 2 x 13 Header VDC, AGND, DGND 3 Test Point P1 1 64-Lead DIN RT Angle SMA1-3 3 SMA, Straight Female Jack PCB MNT SU2-5, ST1 5 8-Lead Socket SU6-7 2 20-Lead Socket U1 1 Intersil HI5703KCB 10-Bit 40MHz A/D Converter U2 1 Intersil HFA1102IP Operational Amplifier U3 1 Ultrafast Voltage Comparator U4 1 +2.5V Precision Voltage Reference U5 1 Intersil CA158AE Operational Amplifier U6-7 2 Octal Buffer/Line Driver All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 14