www.irf.com 11/17/02
IRFP450N
SMPS MOSFET
HEXFET® Power MOSFET
lSwitch Mode Power Supply (SMPS)
lUninterruptible Power Supply
lHigh Speed Power Switching
Benefits
Applications
lLow Gate Charge Qg results in Simple
Drive Requirement
lImproved Gate, Avalanche and Dynamic
dv/dt Ruggedness
lFully Characterized Capacitance and
Avalanche Voltage and Current
lEffective Coss Specified (See AN 1001)
VDSS Rds(on) max ID
500V 0.37Ω14A
Typical SMPS Topologies
l Two transistor Forward
l Half Bridge and Full Bridge
l PFC Boost
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 14
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 8.8 A
IDM Pulsed Drain Current 56
PD @TC = 25°C Power Dissipation 200 W
Linear Derating Factor 1.6 W/°C
VGS Gate-to-Source Voltage ± 30 V
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
PD- 94216
Notes through are on page 8
TO-247AC
IRFP450N
2www.irf.com
Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 7.9 ––– ––– SV
DS = 50V, ID = 8.4A
QgTotal Gate Charge ––– ––– 77 ID = 14A
Qgs Gate-to-Source Charge ––– ––– 26 nC VDS = 400V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 34 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 20 ––– VDD = 250V
trRise Time ––– 63 ––– ID = 14A
td(off) Turn-Off Delay Time ––– 29 ––– RG = 6.2Ω
tfFall Time ––– 25 ––– VGS = 10V,See Fig. 10
Ciss Input Capacitance ––– 2260 ––– VGS = 0V
Coss Output Capacitance ––– 210 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 14 ––– pF ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 2410 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 59 ––– VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 110 ––– VGS = 0V, VDS = 0V to 400V
Dynamic @ TJ = 25°C (unless otherwise specified)
ns
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy––– 170 mJ
IAR Avalanche Current––– 14 A
EAR Repetitive Avalanche Energy––– 20 mJ
Avalanche Characteristics
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.4 V TJ = 25°C, IS = 14A, VGS = 0V
trr Reverse Recovery Time ––– 430 650 ns TJ = 25°C, IF = 14A
Qrr Reverse RecoveryCharge ––– 3.7 5.6 µC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Diode Characteristics
14
56
A
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.64
RθCS Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W
RθJA Junction-to-Ambient ––– 40
Thermal Resistance
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 500 ––– ––– VV
GS = 0V, I D = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.59 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.37 ΩVGS = 10V, ID = 8.4A
VGS(th) Gate Threshold Voltage 3 . 0 ––– 5.0 V VDS = VGS, ID = 250µA
––– ––– 25 µA VDS = 500V, VGS = 0V
––– ––– 250 VDS = 400V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -30V
IGSS
IDSS Drain-to-Source Leakage Current
IRFP450N
www.irf.com 3
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
-60 -40 -20 020 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
14A
1
10
100
1 10 100
20µs PU LSE WIDTH
T = 150 C
J°
TOP
BOTTOM
VGS
15V
12V
10V
8.0V
7.5V
7.0V
6.5V
6.0V
V , Drain-to-Sou rce Voltage (V)
I , Drain-to-Source Current (A)
DS
D
6.0V
0.1
1
10
100
6.0 7.0 8.0 9.0 10.0
V = 50 V
20µs PULSE WIDTH
DS
V , Gate-to -Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 150 C
J°
0.1
1
10
100
0.1 1 10 100
20µs PU LSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
12V
10V
8.0V
7.5V
7.0V
6.5V
6.0V
V , Drain-to-Sou rce Voltage (V)
I , Drain-to-Source Current (A)
DS
D
6.0V
IRFP450N
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
020 40 60 80
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
14A
V = 100V
DS
V = 250V
DS
V = 400V
DS
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
110 100 1000
VDS, Drain-t o-S our ce V olt age (V )
1
10
100
1000
10000
100000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C
gs + C
gd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds + C
gd
1 10 100 1000 10000
VDS , Drain-t oSource V oltage ( V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150°C
Single P ulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
IRFP450N
www.irf.com 5
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1
Notes:
1. D u ty fa c to r D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Durati on ( s ec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
25 50 75 100 125 150
0
2
4
6
8
10
12
14
T , Case Temperature ( C )
I , Drain Current (A)
°
C
D
IRFP450N
6www.irf.com
25 50 75 100 125 150
0
50
100
150
200
250
300
Starting T , Junct ion Te m pera t ur e ( C)
E , Single Pulse Avalanche Energy (m J)
J
AS
°
ID
TOP
BOTTOM
6.3A
8.9A
14A
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VGS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
IRFP450N
www.irf.com 7
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRFP450N
8www.irf.com
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ISD ≤ 14A, di/dt ≤ 510A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Notes:
Starting TJ = 25°C, L = 1.7mH
RG = 25Ω, IAS = 14A. (See Figure 12)
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
TO-247AC Part Marking Information
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
LEAD ASSI GNMENT S
NOTES:
- D - 5.30 (.209)
4.70 ( .185)
2.50 (.089)
1.50 (.059)
4
3X 0.80 (.031)
0.40 (.016)
2.60 (.102)
2.20 (.087)
3.40 (.133)
3.00 (.118)
3X
0.25 (.010) MCA
S
4.30 ( .170)
3.70 ( .145)
- C -
2X 5.50 (.217)
4.50 (.177)
5. 50 (.217)
0.25 (.010)
1.40 (.056)
1.00 (.039)
3. 65 (.143)
3. 55 (.140) D
MM
B
- A -
15.90 (.62 6)
15.30 (.60 2)
- B -
123
20.30 (.800)
19.70 (.775)
14.80 (.583)
14.20 (.559)
2.40 (.094)
2.00 (.079)
2X
2X
5.45 (.215)
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE
TO-247-AC.
1 - GATE
2 - DRAIN
3 - SOU RCE
4 - DRAIN
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
E
XAMPLE : THIS IS AN IRF PE30
WITH ASSEMBLY
LOT CODE 3A1 Q PART NUMBER
DA T E CODE
(YYWW)
YY = YEAR
WW WEEK
3A1Q 9302
IRFPE30
A
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 1/02
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
