SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCTOBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Eight D-Type Flip-Flops in a Single
Package
•3-State Bus-Driving True Outputs
•Full Parallel Access for Loading
•Buffered Control Inputs
•Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This 8-bit flip-flop features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock
(CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.
A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
The output enable (OE) does not affect the internal operations of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74F574 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
OE CLK D Q
L↑H H
L↑LL
LLX Q
0
HXX Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
DW OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCTOBER 1993
2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†logic diagram (positive logic)
OE
1D
2
1D 3
2D 4
3D 5
4D 6
5D
11
CLK
1Q
19
2Q
18
3Q
17
4Q
16
5Q
15
6Q
14
7Q
13
8Q
12
7
6D 8
7D 9
8D
EN
1OE
CLK
1D 1Q
1
11
219
To Seven Other Channels
1D
C1
C1
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –3 mA
IOL Low-level output current 24 mA
TAOperating free-air temperature 0 70 °C
SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCTOBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = – 18 mA – 1.2 V
VCC =45V
IOH = – 1 mA 2.5 3.4
VOH
V
CC =
4
.
5
V
IOH = – 3 mA 2.4 3.3 V
VCC = 4.75 V, IOH = – 1 mA to – 3 mA 2.7
VOL VCC = 4.5 V, IOL = 24 mA 0.35 0.5 V
IOZH VCC = 5.5 V, VO = 2.7 V 50 µA
IOZL VCC = 5.5 V, VO = 0.5 V –50 µA
IIVCC = 5.5 V, VI = 7 V 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 µA
IIL VCC = 5.5 V, VI = 0.5 V – 0.6 mA
IOS‡VCC = 5.5 V, VO = 0 –60 – 150 mA
ICCZ VCC = 5.5 V, See Note 2 55 86 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICCZ is measured with OE at 4.5 V and all other inputs grounded.
timing requirements
VCC = 5 V,
TA = 25°CVCC = 4.5 V to 5.5 V,
TA = MIN to MAX§UNIT
MIN MAX MIN MAX
fclock Clock frequency 0 100 0 100 MHz
t
Pulse duration
CLK high 7 7
ns
t
w
P
u
lse
d
u
ration
CLK low 6 6
ns
t
Setup time before CLK↑
Data high 2 2
ns
t
su
S
e
t
up
ti
me
b
e
f
ore
CLK↑
Data low 2 2
ns
th
Hold time after CLK↑
Data high 2 2
ns
t
h
Hold
time
after
CLK↑
Data low 2 2
ns
switching characteristics (see Note 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX§UNIT
MIN TYP MAX MIN MAX
fmax 100 100 MHz
tPLH
CLK
Any Q
3.2 6.1 8.5 3.2 10
ns
tPHL
CLK
An
y
Q
3.2 6.1 8.5 3.2 10
ns
tPZH
OE
Any Q
1.2 8.6 11.5 1.2 12.5
ns
tPZL
OE
An
y
Q
1.2 4.9 7.5 1.2 8.5
ns
tPHZ
OE
Any Q
1.2 4.9 7 1.2 8
ns
tPLZ
OE
An
y
Q
1.2 3.9 5.5 1.2 6.5
ns
§For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
SN74F574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCTOBER 1993
2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74F574DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574DWE4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574DWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74F574NE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74F574NSR ACTIVE SO NS 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574NSRE4 ACTIVE SO NS 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F574NSRG4 ACTIVE SO NS 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74F574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74F574NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74F574DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74F574NSR SO NS 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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