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Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
32K - 384KBytes of in-system self-programmable flash
4K - 8KBytes boot section
1K - 4KBytes EEPROM
4K - 32KBytes internal SRAM
Peripheral features
Four-channel event system
Five 16-bit timer/counters
Four timer/counters with four output compare or input capture channels
One timer/counter with two output compare or input capture channels
High resolution extension on two timer/counters
Advanced waveform extension (AWeX) on one timer/counter
Three USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Two serial peripheral interfaces (SPIs)
CRC-16 (CRC-CCITT) and CRC-32 (IEEE®802.3) generator
16-bit real time counter (RTC) with separate oscillator
One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter
Two Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
Atmel QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interface
PDI (program and debug interface)
I/O and packages
50 programmable I/O pins
64-lead TQFP
64-pad QFN
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
8/16-bit Atmel AVR XMEGA D3 Microcontroller
ATxmega32D3 / ATxmega64D3 / ATxmega128D3 /
ATxmega192D3 / ATxmega256D3 / ATxmega384D3
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1. Ordering Information
Ordering code Flash [bytes]
EEPROM
[bytes]
SRAM
[bytes] Speed [MHz]
Power
supply
Package
(1)(2)(3) Temp.
ATxmega32D3-AU 32K + 4K 1K 4K
32 1.6 - 3.6V
64A
-40C - 85C
ATxmega32D3-AUR (4) 32K + 4K 1K 4K
ATxmega64D3-AU 64K + 4K 2K 4K
ATxmega64D3-AUR (4) 64K + 4K 2K 4K
ATxmega128D3-AU 128K + 8K 2K 8K
ATxmega128D3-AUR (4) 128K + 8K 2K 8K
ATxmega192D3-AU 192K + 8K 2K 16K
ATxmega192D3-AUR (4) 192K + 8K 2K 16K
ATxmega256D3-AU 256K + 8K 4K 16K
ATxmega256D3-AUR (4) 256K + 8K 4K 16K
ATxmega384D3-AU 384K + 8K 4K 32K
ATxmega384D3-AUR (4) 384K + 8K 4K 32K
ATxmega32D3-MH 32K + 4K 1K 4K
64M
ATxmega32D3-MHR (4) 32K + 4K 1K 4K
ATxmega64D3-MH 64K + 4K 2K 4K
ATxmega64D3-MHR (4) 64K + 4K 2K 4K
ATxmega128D3-MH 128K + 8K 2K 8K
ATxmega128D3-MHR (4) 128K + 8K 2K 8K
ATxmega192D3-MH 192K + 8K 2K 16K
ATxmega192D3-MHR (4) 192K + 8K 2K 16K
ATxmega256D3-MH 256K + 8K 4K 16K
ATxmega256D3-MHR (4) 256K + 8K 4K 16K
ATxmega384D3-MH 384K + 8K 4K 32K
ATxmega384D3-MHR (4) 384K + 8K 4K 32K
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Notes: 1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see “Packaging Information” on page 61.
4. Tape and Reel.
ATxmega32D3-AN 32K + 4K 1K 4K
32 1.6 - 3.6V
64A
-40C - 105C
ATxmega32D3-ANR (4) 32K + 4K 1K 4K
ATxmega64D3-AN 64K + 4K 2K 4K
ATxmega64D3-ANR (4) 64K + 4K 2K 4K
ATxmega128D3-AN 128K + 8K 2K 8K
ATxmega128D3-ANR (4) 128K + 8K 2K 8K
ATxmega192D3-AN 192K + 8K 2K 16K
ATxmega192D3-ANR (4) 192K + 8K 2K 16K
ATxmega256D3-AN 256K + 8K 4K 16K
ATxmega256D3-ANR (4) 256K + 8K 4K 16K
ATxmega384D3-AN 384K + 8K 4K 32K
ATxmega384D3-ANR (4) 384K + 8K 4K 32K
ATxmega32D3-MN 32K + 4K 1K 4K
64M
ATxmega32D3-MNR (4) 32K + 4K 1K 4K
ATxmega64D3-MN 64K + 4K 2K 4K
ATxmega64D3-MNR (4) 64K + 4K 2K 4K
ATxmega128D3-MN 128K + 8K 2K 8K
ATxmega128D3-MNR (4) 128K + 8K 2K 8K
ATxmega192D3-MN 192K + 8K 2K 16K
ATxmega192D3-MNR (4) 192K + 8K 2K 16K
ATxmega256D3-MN 256K + 8K 4K 16K
ATxmega256D3-MNR (4) 256K + 8K 4K 16K
ATxmega384D3-MN 384K + 8K 4K 32K
ATxmega384D3-MNR (4) 384K + 8K 4K 32K
Ordering code Flash [bytes]
EEPROM
[bytes]
SRAM
[bytes] Speed [MHz]
Power
supply
Package
(1)(2)(3) Temp.
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Typical applications
Package type
64A 64-lead, 14 * 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
64M 64-pad, 9 * 9 * 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN)
Industrial control Climate control Low power battery applications
Factory automation RF and ZigBee®Power tools
Building control Motor control HVAC
Board control Sensor control Utility metering
White goods Optical Medical applications
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2. Pinout/block Diagram
Figure 2-1. Block Diagram and Pinout
Notes: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 50.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good
mechanical stability.
1
2
3
4
64
63
62
61
60
59
58
VCC
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
GND
VCC
AVCC
GND
PB0
PB1
PB3
PB2
PB7
PB5
PB4
PB6
PA7
PA6
PA0
PA1
PA2
PA3
PA4
PA5
_RESET/PDI
PDI
PR0
PR1
VCC
GND
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC
GND
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
VCC
GND
Power
Supervision
Port A
EVENT ROUTING NETWORK
SRAM
FLASH
ADC
AC0:1
OCD
Port EPort D
Prog/Debug
Interface
EEPROM
Port C
TC0:1
Event System
Controller
Watchdog
Timer
Internal
oscillators
OSC/CLK
Control
Real Time
Counter
Interrupt
Controller
DATA BUS
DATA BUS
Port R
USART0
TWI
SPI
TC0
USART0
SPI
TC0
USART0
TWI
Port B
AREF
AREF
Sleep
Controller
Reset
Controller
Internal
references
IRCOM
Port F
TC0
CPU
XOSC
TOSC
CRC
Watchdog
oscillator
BUS
matrix
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I /O
Ground
Power
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3. Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices
achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA D3 devices provide the following features: in-system programmable flash with read-while-write capabilities;
internal EEPROM and SRAM; four-channel event system and programmable multilevel interrupt controller, 50 general
purpose I/O lines, 16-bit real-time counter (RTC); five, 16-bit timer/counters with compare and PWM channels; three
USARTs; two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); one sixteen-channel, 12-bit ADC
with programmable gain; two analog comparators (ACs) with window mode; programmable watchdog timer with separate
internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.
The AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode
saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-
change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the
application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal
oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal,
combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer
continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be
stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the
application program to the flash memory. The boot loader software in the boot flash section will continue to run while the
application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with
in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible
and cost effective solution for many embedded applications.
All AVR XMEGA devices are supported with a full suite of program and system development tools, including: C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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3.1 Block Diagram
Figure 3-1. XMEGA D3 Block Diagram
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
SRAMADCA
ACA
OCD
Int. Refs.
PDI
PA[0..7]
PB[0..7]
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
AREFA
AREFB
PDI_DATA
RESET/
PDI_CLK
Sleep
Controller
CRC
PORT C (8)
PC[0..7]
TCC0:1
USARTC0
TWIC
SPIC
PD[0..7] PE[0..7]
PORT D (8)
TCD0
USARTD0
SPID
TCE0
USARTE0
TWIE
PORT E (8)
Tempref
VCC/10
PORT R (2)
XTAL1
XTAL2
PR[0..1]
DATA BUS
NVM Controller
Flash EEPROM
IRCOM
BUS Matrix
CPU
TOSC1
TOSC2
TCF0 PF[0..7]
PORT F (8)
EVENT ROUTING NETWORK
To Clock
Generator
Digital function
Analog function / Oscillators
Programming, debug,
External clock / Crystal pins
General Purpose I /O
Ground
Power
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4. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
www.atmel.com/avr.
4.1 Recommended Reading
Atmel AVR XMEGA D manual
XMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA D manual describes the modules and peripherals in depth. The XMEGA application notes contain example code
and show applied use of the modules and peripherals.
All documentation are available from www.atmel.com/avr.
5. Capacitive Touch Sensing
The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent Key Suppression™ (AKS™) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and Atmel QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
http://www.atmel.com/tools/qtouchlibrary.aspx. For implementation details and other information, refer to the QTouch
library user guide - also available for download from the Atmel website.
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6. AVR CPU
6.1 Features
8/16-bit, high-performance Atmel AVR RISC CPU
137 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
6.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 28.
6.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to www.atmel.com/avr.
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Figure 6-1. Block Diagram of the AVR CPU Architecture
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 * 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for safe storing of nonvolatile data in the program memory.
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6.4 ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The Stack Pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
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after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 16.
6.8 Register File
The register file consists of 32 * 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
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7. Memories
7.1 Features
Flash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or boot loader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
Data memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
I/O memory
Configuration and status registers for all peripherals and modules
Four bit-accessible general purpose registers for global variables or flags
Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2 Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number etc.
7.3 Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
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device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 7-1. Flash Program Memory (hexadecimal address)
7.3.1 Application Section
The application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, the application
code can be stored here.
7.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 63.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 15.
Word address
ATxmega 32D3 64D3 128D3 192D3 256D3 384D3
Application section
(32K/64K/128K/192K/256K/384K)
000000
...
37FF 77FF EFFF 16FFF 1EFFF 2EFFF
Application table section
(4K/4K/8K/8K/8K/8K)
3800 7800 F000 17000 1F000 2F000
3FFF 7FFF FFFF 17FFF 1FFFF 2FFFF
Boot section (4K/4K/8K/8K/8K/8K) 4000 8000 10000 18000 20000 30000
47FF 87FF 10FFF 18FFF 20FFF 30FFF
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The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-1. Device ID Bytes
7.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
7.4 Fuses and Lock Bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, and startup configuration.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5 Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory
if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 16. To simplify
development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA
devices.
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega32D3 4A 95 1E
ATxmega64D3 4A 96 1E
ATxmega128D3 48 97 1E
ATxmega192D3 49 97 1E
ATxmega256D3 44 98 1E
ATxmega384D3 47 98 1E
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Figure 7-2. Data Memory Map (hexadecimal address)
7.6 EEPROM
All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or
memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
Byte address ATxmega32D3 Byte address ATxmega64D3
0
I/O registers (4K)
0
I/O registers (4K)
FFF FFF
1000
EEPROM (1K)
1000
EEPROM (2K)
17FF 17FF
RESERVED RESERVED
2000
Internal SRAM (4K)
2000
Internal SRAM (4K)
2FFF 2FFF
Byte address ATxmega128D3 Byte address ATxmega192D3
0
I/O registers (4K)
0
I/O registers (4K)
FFF FFF
1000
EEPROM (2K)
1000
EEPROM (2K)
17FF 17FF
RESERVED RESERVED
2000
Internal SRAM (8K)
2000
Internal SRAM (16K)
3FFF 5FFF
Byte address ATxmega256D3 Byte address ATxmega384D3
0
I/O registers (4K)
0
I/O registers (4K)
FFF FFF
1000
EEPROM (4K)
1000
EEPROM (4K)
1FFF 1FFF
2000
Internal SRAM (16K)
2000
Internal SRAM (32K)
5FFF 9FFF
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7.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules is shown in the “Peripheral Module Address Map” on page 55.
7.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.8 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst
read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and
instruction timing.
7.9 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
7.10 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.11 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 18 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and
erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash
access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page
number and the least significant address bits (FWORD) give the word in the page.
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Table 7-2. Number of Words and Pages in the Flash
Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or
one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address
register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number
and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3. Number of Bytes and Pages in the EEPROM
Devices PC size Flash size Page size FWORD FPAGE Application Boot
[bits] [bytes] [words] Size No. of
pages Size No. of
pages
ATxmega32D3 15 32K + 4K 128 Z[7:1] Z[15:7] 32K 128 4K 16
ATxmega64D3 16 64K + 4K 128 Z[7:1] Z[16:9] 64K 256 4K 16
ATxmega128D3 17 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16
ATxmega192D3 17 192K + 8K 256 Z[8:1] Z[17:9] 192K 384 8K 16
ATxmega256D3 18 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16
ATxmega384D3 18 384K + 8K 256 Z[8:1] Z[19:9] 384K 768 8K 16
Devices EEPROM Page size E2BYTE E2PAGE No. of pages
size [bytes]
ATxmega32D3 1K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega64D3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128D3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192D3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256D3 4K 32 ADDR[4:0] ADDR[11:5] 128
ATxmega384D3 4K 32 ADDR[4:0] ADDR[11:5] 128
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8. Event System
8.1 Features
System for direct peripheral-to-peripheral communication and signaling
Peripherals can directly send, receive, and react to peripheral events
CPU independent operation
100% predictable signal timing
Short and guaranteed response time
Four event channels for up to four different and parallel signal routing configurations
Events can be sent and/or used by most peripherals, clock system, and software
Additional functions include
Quadrature decoders
Digital filtering of I/O pin state
Works in active mode and idle sleep mode
8.2 Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts or CPU resources, and is thus a powerful tool for reducing the complexity, size and
execution time of application code. It also allows for synchronized timing of actions in several peripheral modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 8-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog to
digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, and IR communication module
(IRCOM). Events can also be generated from software and the peripheral clock.
Figure 8-1. Event System Overview and Connected Peripherals
The event routing network consists of four software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
Timer /
Counters
ADC
Real Time
Counter
Port pins
CPU /
Software
IRCOM
Event Routing Network
Event
System
Controller
clkPER
Prescaler
AC
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9. System Clock and Clock Options
9.1 Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
32MHz run-time calibrated and tuneable oscillator
2MHz run-time calibrated oscillator
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
PLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1× to 31× multiplication
Lock detector
Clock prescalers with 1× to 2048× division
Fast peripheral clocks running at two and four times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator and PLL lock failure detection with optional non-maskable interrupt
9.2 Overview
Atmel AVR XMEGA D3 devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)
is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over
voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the
internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 9-1 on page 21 presents the principal clock system. Not all of the clocks need to be active at a given time. The
clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in
“Power Management and Sleep Modes” on page 23.
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Figure 9-1. The Clock System, Clock Sources, and Clock Distribution
9.3 Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
Real Time
Counter Peripherals RAM AVR CPU Non-Volatile
Memory
Watchdog
Timer
Brown-out
Detector
System Clock Prescalers
System Clock Multiplexer
(SCLKSEL)
PLLSRC
RTCSRC
DIV32
32kHz
Int. ULP
32.768kHz
Int. OSC
32.768kHz
TOSC
2MHz
Int. Osc
32MHz
Int. Osc
0.4 – 16MHz
XTAL
DIV32
DIV32
DIV4
XOSCSEL
PLL
TOSC1
TOSC2
XTAL1
XTAL2
clk
SYS
clk
RTC
clk
PER2
clk
PER
clk
CPU
clk
PER4
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9.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
9.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
9.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
9.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
9.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
9.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.
9.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a
32.768kHz crystal oscillator.
9.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
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10. Power Management and Sleep Modes
10.1 Features
Power management for adjusting power consumption and functions
Five sleep modes
Idle
Power down
Power save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
10.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
10.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
10.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller and event system are kept running. Any enabled interrupt will wake the
device.
10.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt and asynchronous port interrupts.
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10.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
10.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
10.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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11. System Control and Reset
11.1 Features
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
Asynchronous operation
No running system clock in the device is required for reset
Reset status register for reading the reset source from the application code
11.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
11.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
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11.4 Reset Sources
11.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
11.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
11.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
11.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 27.
11.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register. The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
11.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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12. WDT – Watchdog Timer
12.1 Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
12.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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13. Interrupts and Programmable Multilevel Interrupt Controller
13.1 Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium, and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
13.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
13.3 Interrupt Vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA D3 devices are shown in Table 13-1 on page 29. Offset
addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA D manual. For
peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1 on page 29. The program
address is the word address.
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Table 13-1. Reset and Interrupt Vectors
Program address
(base address) Source Interrupt description
0x000 RESET
0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI)
0x004 PORTC_INT_base Port C interrupt base
0x008 PORTR_INT_base Port R interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base
0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base
0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base
0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base
0x030 SPIC_INT_vect SPI on port C Interrupt vector
0x032 USARTC0_INT_base USART 0 on port C Interrupt base
0x040 NVM_INT_base Non-Volatile Memory Interrupt base
0x044 PORTB_INT_base Port B Interrupt base
0x056 PORTE_INT_base Port E INT base
0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base
0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base
0x074 USARTE0_INT_base USART 0 on port E Interrupt base
0x080 PORTD_INT_base Port D Interrupt base
0x084 PORTA_INT_base Port A Interrupt base
0x088 ACA_INT_base Analog Comparator on Port A Interrupt base
0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base
0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base
0x0AE SPID_INT_vector SPI D Interrupt vector
0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base
0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base
0x0D0 PORTF_INT_base Port F Interrupt base
0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base
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14. I/O Ports
14.1 Features
50 general purpose input and output pins with individual configuration
Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Optional pull-up and pull-down resistor on input and Wired-OR/AND configuration
Asynchronous pin change sensing that can wake the device from all sleep modes
Two port interrupts with pin masking per I/O port
Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
Peripheral clocks output on port pin
Real-time counter clock output to port pin
Event channels can be output on port pin
Remapping of digital peripheral pin functions
Selectable USART, SPI, and timer/counter input/output pin locations
14.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, and PORTR.
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14.3 Output Driver
All port pins (Pn) have programmable output configuration.
14.3.1 Push-pull
Figure 14-1. I/O Configuration - Totem-pole
14.3.2 Pull-down
Figure 14-2. I/O Configuration - Totem-pole with Pull-down (on input)
14.3.3 Pull-up
Figure 14-3. I/O Configuration - Totem-pole with Pull-up (on input)
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
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14.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
Figure 14-4. I/O Configuration - Totem-pole with Bus-keeper
14.3.5 Others
Figure 14-5. Output Configuration - Wired-OR with Optional Pull-down
Figure 14-6. I/O Configuration - Wired-AND with Optional Pull-up
INn
OUTn
DIRn
Pn
INn
OUTn
Pn
INn
OUTn
Pn
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14.4 Input Sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 14-7.
Figure 14-7. Input Sensing System Overview
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
14.5 Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 50 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
DQ
R
INVERTED I/O
Interrupt
Control
DQ
R
Pxn Synchronizer
INn EDGE
DETECT
Synchronous sensing
EDGE
DETECT
Asynchronous sensing
IRQ
Synchronous
Events
Asynchronous
Events
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15. TC0/1 – 16-bit Timer/Counter Type 0 and 1
15.1 Features
Five 16-bit timer/counters
Four timer/counters of type 0
One timer/counter of type 1
Split-mode enabling two 8-bit timer/counter from each timer/counter type 0
32-bit timer/counter support by cascading two timer/counters
Up to four compare or capture (CC) channels
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
Double buffered timer period setting
Double buffered capture or compare channels
Waveform generation:
Frequency generation
Single-slope pulse width modulation
Dual-slope pulse width modulation
Input capture:
Input capture with noise cancelling
Frequency capture
Pulse width capture
32-bit input capture
Timer overflow and error interrupts/events
One compare match or input capture interrupt/event per CC channel
Can be used with event system for:
Quadrature decoding
Count and direction control
Capture
High-resolution extension
Increases frequency and waveform resolution by 4× (2-bit) or 8× (3-bit)
Advanced waveform extension:
Low- and high-side output with programmable dead-time insertion (DTI)
Event controlled fault protection for safe disabling of drivers
15.2 Overview
Atmel AVR XMEGA D3 devices have a set of five flexible 16-bit timer/counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency measurement
of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
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There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels
each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-
side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 37 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 38 for more details.
Figure 15-1. Overview of a Timer/Counter and Closely Related Peripherals
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD, PORTE and PORTF each has one Timer/Counter
0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCE0, and TCF0, respectively.
AWeX
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
Waveform
Generation
Buffer
Comparator
Hi-Res
Fault
Protection
Capture
Control
Base Counter
Counter
Control Logic
Timer Period
Prescaler
Dead-Time
Insertion
Pattern
Generation
clkPER4
PORT
Event
System
clkPER
Timer/Counter
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16. TC2 – Timer/Counter Type 2
16.1 Features
Eight 8-bit timer/counters
Four Low-byte timer/counter
Four High-byte timer/counter
Up to eight compare channels in each Timer/Counter 2
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
16.2 Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation
(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of
PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and
compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event
system. The counters are always counting down.
PORTC, PORTD, PORTE, and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Timer/Counter C2),
TCD2, TCE2, and TCF2, respectively.
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17. AWeX – Advanced Waveform Extension
17.1 Features
Waveform output with complementary output from each compare channel
Four dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
Double buffered dead time
Optionally halts timer during dead-time insertion
Pattern generation unit creating synchronised bit pattern across the port pins
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
Event controlled fault protection for instant and predictable fault triggering
17.2 Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-
inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
The AWeX is available for TCC0. The notation of this is AWEXC.
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18. Hi-Res – High Resolution Extension
18.1 Features
Increases waveform generator resolution up to 8× (three bits)
Supports frequency, single-slope PWM, and dual-slope PWM generation
Supports the AWeX when this is used for the same timer/counter
18.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4× clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4× clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res
extension is enabled.
There is one hi-res extensions that can be enabled for timer/counters pair on PORTC. The notation of this is HIRESC.
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19. RTC – 16-bit Real-Time Counter
19.1 Features
16-bit resolution
Selectable clock source
32.768kHz external crystal
External clock
32.768kHz internal oscillator
32kHz internal ULP oscillator
Programmable 10-bit clock prescaling
One compare register
One period register
Clear counter on period overflow
Optional interrupt/event on overflow and compare match
19.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 19-1. Real-time Counter Overview
32.768kHz Crystal Osc
32.768kHz Int. Osc
TOSC1
TOSC2
External Clock
DIV32
DIV32
32kHz int ULP (DIV32)
RTCSRC
10-bit
prescaler
clkRTC
CNT
PER
COMP
=
=
”match”/
Compare
TOP/
Overflow
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20. TWI – Two-Wire Interface
20.1 Features
Two Identical two-wire interface peripherals
Bidirectional, two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
Bus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start/repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
20.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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21. SPI – Serial Peripheral Interface
21.1 Features
Two identical SPI peripherals
Full-duplex, three-wire synchronous data transfer
Master or slave operation
Lsb first or msb first data transfer
Eight programmable bit rates
Interrupt flag at the end of transmission
Write collision flag to indicate data collision
Wake up from idle sleep mode
Double speed master mode
21.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID, respectively.
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22. USART
22.1 Features
Three identical USART peripherals
Full-duplex operation
Asynchronous or synchronous operation
Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Fractional baud rate generator
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
Built-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
Noise filtering includes false start bit detection and digital low-pass filter
Separate interrupts for
Transmit complete
Transmit data register empty
Receive complete
Multiprocessor communication mode
Addressing scheme to address a specific devices on a multidevice bus
Enable unaddressed devices to automatically ignore all frames
Master SPI mode
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
IRCOM module for IrDA compliant pulse modulation/demodulation
22.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2kbps.
PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are USARTC0, USARTD0, and
USARTE0, respectively.
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23. IRCOM – IR Communication Module
23.1 Features
Pulse modulation/demodulation for infrared communication
IrDA compatible for baud rates up to 115.2kbps
Selectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
Pulse modulation disabled
Built-in filtering
Can be connected to and used by any USART
23.2 Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates
up to 115.2kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
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24. CRC – Cyclic Redundancy Check generator
24.1 Features
Cyclic redundancy check (CRC) generation and checking for
Communication data
Program or data in flash memory
Data in SRAM and I/O memory space
Integrated with flash memory and CPU
Automatic CRC of the complete or a selectable range of the flash memory
CPU can load data to the CRC generator through the I/O interface
CRC polynomial software selectable to
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
Zero remainder detection
24.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-
CCITT) and CRC-32 (IEEE 802.3).
CRC-16:
Polynominal: x16+x12+x5+1
Hex value: 0x1021
CRC-32:
Polynominal: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value: 0x04C11DB7
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25. ADC – 12-bit Analog to Digital Converter
25.1 Features
One Analog to Digital Converter (ADC)
12-bit resolution
Up to 300 thousand samples per second
Down to 2.3µs conversion time with 8-bit resolution
Down to 3.35µs conversion time with 12-bit resolution
Differential and single-ended input
16 single-ended inputs
16 * 4 differential inputs without gain
8 * 4 differential input with gain
Built-in differential gain stage
1/2×, 1×, 2×, 4×, 8×, 16×, 32×, and 64× gain options
Single, continuous and scan conversion options
Three internal inputs
Internal temperature sensor
AVCC voltage divided by 10
1.1V bandgap voltage
Internal and external reference options
Compare function for accurate monitoring of user defined thresholds
Optional event triggered conversion for accurate timing
Optional interrupt/event on compare result
25.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300
thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential
measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic
range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
The ADC measurements can either be started by application software or an incoming event from another peripheral in
the device. The ADC measurements can be started with predictable timing, and without software intervention.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
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Figure 25-1. ADC Overview
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from
3.35µs for 12-bit to 2.3µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
CH0 Result
Compare
Register
<
>
Threshold
(Int Req)
Internal 1.00V
Internal AVCC/1.6V
AREFA
AREFB
VINP
VINN
Internal
signals
InternalAVCC/2
ADC0
ADC15
•
•
•
ADC0
ADC7
•
•
•
Reference
Voltage
ADC
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26. AC – Analog Comparator
26.1 Features
Two analog comparators (AC)
Selectable hysteresis
No
Small
Large
Analog comparator output available on pin
Flexible input selection
All pins on the port
Bandgap reference voltage
A 64-level programmable voltage scaler of the internal AVCC voltage
Interrupt and event generation on:
Rising edge
Falling edge
Toggle
Window function interrupt and event generation on:
Signal above window
Signal inside window
Signal below window
Constant current source with configurable output pin selection
26.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
The analog comparator hysteresis can be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA has one AC pair. Notation is ACA.
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Figure 26-1. Analog Comparator Overview
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 26-2.
Figure 26-2. Analog Comparator Window Function
ACnMUXCTRL ACnCTRL
Interrupt
Mode
Enable
Enable
Hysteresis
Hysteresis
AC1OUT
WINCTRL
Interrupt
Sensititivity
Control
&
Window
Function
Events
Interrupts
AC0OUT
Pin Input
Pin Input
Pin Input
Pin Input
Voltage
Scaler
Bandgap
+
-
+
-
AC0
+
-
AC1
+
-
Input signal
Upper limit of window
Lower limit of window
Interrupt
sensitivity
control
Interrupts
Events
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27. Programming and Debugging
27.1 Features
Programming
External programming through PDI interface
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
Boot loader support for programming through any communication interface
Debugging
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
No limitation on device clock frequency
Program and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
No I/O pins required during programming or debugging
27.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset
pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external
programmer or on-chip debugger/emulator can be directly connected to this interface.
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28. Pinout and Pin Functions
The device pinout is shown in “Pinout/block Diagram” on page 5. In addition to general purpose I/O functionality, each pin
can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
28.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
28.1.1 Operation/power Supply
28.1.2 Port Interrupt Functions
28.1.3 Analog Functions
28.1.4 Timer/counter and AWEX Functions
VCC Digital supply voltage
AVCC Analog supply voltage
GND Ground
SYNC Port pin with full synchronous and limited asynchronous interrupt function
ASYNC Port pin with full synchronous and full asynchronous interrupt function
ACn Analog comparator input pin n
ACnOUT Analog comparator n output
ADCn Analog to digital converter input pin n
AREF Analog reference input pin
OCnxLS Output compare channel x low side for Timer/Counter n
OCnxHS Output compare channel x high side for Timer/Counter n
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28.1.5 Communication Functions
28.1.6 Oscillators, Clock, and Event
28.1.7 Debug/system Functions
28.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
first table where this apply.
SCL Serial Clock for TWI
SDA Serial Data for TWI
SCLIN Serial Clock In for TWI when external driver interface is enabled
SCLOUT Serial Clock Out for TWI when external driver interface is enabled
SDAIN Serial Data In for TWI when external driver interface is enabled
SDAOUT Serial Data Out for TWI when external driver interface is enabled
XCKn Transfer Clock for USART n
RXDn Receiver Data for USART n
TXDn Transmitter Data for USART n
SS Slave Select for SPI
MOSI Master Out Slave In for SPI
MISO Master In Slave Out for SPI
SCK Serial Clock for SPI
TOSCn Timer Oscillator pin n
XTALn Input/Output for Oscillator pin n
CLKOUT Peripheral Clock Output
EVOUT Event Channel Output
RTCOUT RTC Clock Source Output
RESET Reset pin
PDI_CLK Program and Debug Interface Clock pin
PDI_DATA Program and Debug Interface Data pin
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Table 28-1. Port A - Alternate Functions
Table 28-2. Port B - Alternate Functions
Table 28-3. Port C - Alternate Functions
PORT A PIN # INTERRUPT
ADCA POS/
GAINPOS ADCA NEG
ADCA
GAINNEG ACA POS ACA NEG ACA OUT REFA
GND 60
AVCC 61
PA0 62 SYNC ADC0 ADC0 AC0 AC0 AREFA
PA1 63 SYNC ADC1 ADC1 AC1 AC1
PA2 64 SYNC/ASYNC ADC2 ADC2 AC2
PA3 1SYNC ADC3 ADC3 AC3 AC3
PA4 2SYNC ADC4 ADC4 AC4
PA5 3SYNC ADC5 ADC5 AC5 AC5
PA6 4SYNC ADC6 ADC6 AC6 AC1OUT
PA7 5SYNC ADC7 ADC7 AC7 AC0OUT
PORT B PIN # INTERRUPT ADCA POS REFB
PB0 6SYNC ADC8 AREFB
PB1 7SYNC ADC91
PB2 8SYNC/ASYNC ADC10
PB3 9SYNC ADC11
PB4 10 SYNC ADC12
PB5 11 SYNC ADC13
PB6 12 SYNC ADC14
PB7 13 SYNC ADC15
GND 14
VCC 15
PORT C PIN # INTERRUPT TCC0 (1)(2) AWEXC TCC1 USARTC0 (3) SPIC (4) TWIC CLOCKOUT (5) EVENTOUT (6)
PC0 16 SYNC OC0A OC0ALS SDA
PC1 17 SYNC OC0B OC0AHS XCK0 SCL
PC2 18 SYNC/ASYNC OC0C OC0BLS RXD0
PC3 19 SYNC OC0D OC0BHS TXD0
PC4 20 SYNC OC0CLS OC1A SS
PC5 21 SYNC OC0CHS OC1B MOSI
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Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. If TC0 is configured as TC2 all eight pins can be used for PWM output.
3. Pin mapping of all USART0 can optionally be moved to high nibble of port.
4. Pins MOSI and SCK for all SPI can optionally be swapped.
5. CLKOUT can optionally be moved between port C, D, and E and between pin 4 and 7.
6. EVOUT can optionally be moved between port C, D, and E and between pin 4 and 7.
Table 28-4. Port D - Alternate Functions
Table 28-5. Port E - Alternate Functions
PC6 22 SYNC OC0DLS MISO RTCOUT
PC7 23 SYNC OC0DHS SCK clkPER EVOUT
GND 24
VCC 25
PORT C PIN # INTERRUPT TCC0 (1)(2) AWEXC TCC1 USARTC0 (3) SPIC (4) TWIC CLOCKOUT (5) EVENTOUT (6)
PORT D PIN # INTERRUPT TCD0 USARTD0 SPID CLOCKOUT EVENTOUT
PD0 26 SYNC OC0A
PD1 27 SYNC OC0B XCK0
PD2 28 SYNC/ASYNC OC0C RXD0
PD3 29 SYNC OC0D TXD0
PD4 30 SYNC SS
PD5 31 SYNC MOSI
PD6 32 SYNC MISO
PD7 33 SYNC SCK ClkPER EVOUT
GND 34
VCC 35
PORT E PIN # INTERRUPT TCE0 USARTE0 TOSC TWIE CLOCKOUT EVENTOUT
PE0 36 SYNC OC0A SDA
PE1 37 SYNC OC0B XCK0 SCL
PE2 38 SYNC/ASYNC OC0C RXD0
PE3 39 SYNC OC0D TXD0
PE4 40 SYNC
PE5 41 SYNC
PE6 42 SYNC TOSC2
PE7 43 SYNC TOSC1 ClkPER EVOUT
GND 44
VCC 45
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Table 28-6. Port F - Alternate Functions
Table 28-7. Port R - Alternate Functions
PORT F PIN # INTERRUPT TCF0
PF0 46 SYNC OC0A
PF1 47 SYNC OC0B
PF2 48 SYNC/ASYNC OC0C
PF3 49 SYNC OC0D
PF4 50 SYNC
PF5 51 SYNC
PF6 54 SYNC
PF7 55 SYNC
GND 52
VCC 53
PORT R PIN # INTERRUPT PDI XTAL
PDI 56 PDI_DATA
RESET 57 PDI_CLOCK
PRO 58 SYNC XTAL2
PR1 59 SYNC XTAL1
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29. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D3. For complete
register description and summary for each peripheral module, refer to the XMEGA D manual.
Table 29-1. Peripheral Module Address Map
Base address Name Description
0x0000 GPIO General Purpose IO Registers
0x0010 VPORT0 Virtual Port 0
0x0014 VPORT1 Virtual Port 1
0x0018 VPORT2 Virtual Port 2
0x001C VPORT3 Virtual Port 2
0x0030 CPU CPU
0x0040 CLK Clock Control
0x0048 SLEEP Sleep Controller
0x0050 OSC Oscillator Control
0x0060 DFLLRC32M DFLL for the 32MHz Internal Oscillator
0x0068 DFLLRC2M DFLL for the 2MHz Internal Oscillator
0x0070 PR Power Reduction
0x0078 RST Reset Controller
0x0080 WDT Watchdog Timer
0x0090 MCU MCU Control
0x00A0 PMIC Programmable Multilevel Interrupt Controller
0x00B0 PORTCFG Port Configuration
0x0180 EVSYS Event System
0x00D0 CRC CRC Module
0x01C0 NVM Non Volatile Memory (NVM) Controller
0x0200 ADCA Analog to Digital Converter on port A
0x0380 ACA Analog Comparator pair on port A
0x0400 RTC Real-Time Counter
0x0480 TWIC Two-Wire Interface on port C
0x04A0 TWIE Two-Wire Interface on port E
0x0600 PORTA Port A
0x0620 PORTB Port B
0x0640 PORTC Port C
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0x0660 PORTD Port D
0x0680 PORTE Port E
0x06A0 PORTF Port F
0x07E0 PORTR Port R
0x0800 TCC0 Timer/Counter 0 on port C
0x0840 TCC1 Timer/Counter 1 on port C
0x0880 AWEXC Advanced Waveform Extension on port C
0x0890 HIRESC High Resolution Extension on port C
0x08A0 USARTC0 USART 0 on port C
0x08C0 SPIC Serial Peripheral Interface on port C
0x08F8 IRCOM Infrared Communication Module
0x0900 TCD0 Timer/Counter 0 on port D
0x09A0 USARTD0 USART 0 on port D
0x09C0 SPID Serial Peripheral Interface on port D
0x0A00 TCE0 Timer/Counter 0 on port E
0x0A80 AWEXE Advanced Waveform Extension on port E
0x0AA0 USARTE0 USART 0 on port E
0x0AC0 SPIE Serial Peripheral Interface on port E
0x0B00 TCF0 Timer/Counter 0 on port F
Base address Name Description
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30. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and logic instructions
ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd Rd Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd Rd K Z,N,V,S 1
OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd Rd Rr Z,N,V,S 1
COM Rd One’s Complement Rd $FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd $00 - Rd Z,C,N,V,S,H 1
SBR Rd, K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1
CBR Rd, K Clear Bit(s) in Register Rd Rd ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V,S 1
CLR Rd Clear Register Rd Rd Rd Z,N,V,S 1
SER Rd Set Register Rd $FF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr (UU) Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr (SS) Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr (SU) Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 Rd x Rr<<1 (UU) Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 Rd x Rr<<1 (SU) Z,C 2
Branch instructions
RJMP kRelative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z,
0None 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z,
EIND None 2
JMP kJump PC kNone 3
RCALL kRelative Call Subroutine PC PC + k + 1 None 2 / 3 (1)
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
Z,
0None 2 / 3 (1)
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EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16)
Z,
EIND None 3 (1)
CALL kcall Subroutine PC kNone 3 / 4 (1)
RET Subroutine Return PC STACK None 4 / 5 (1)
RETI Interrupt Return PC STACK I4 / 5 (1)
CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3
CP Rd, Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd, Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd, K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC PC + 2 or 3 None 1 / 2 / 3
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC PC + 2 or 3 None 2 / 3 / 4
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC PC + 2 or 3 None 2 / 3 / 4
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC PC + k + 1 None 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC + k + 1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1 / 2
BRLT k Branch if Less Than, Signed if (N V= 1) then PC PC + k + 1 None 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None 1 / 2
Data transfer instructions
MOV Rd, Rr Copy Register Rd Rr None 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd KNone 1
LDS Rd, k Load Direct from data space Rd (k) None 2 (1)(2)
LD Rd, X Load Indirect Rd (X) None 1 (1)(2)
Mnemonics Operands Description Operation Flags #Clocks
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LD Rd, X+ Load Indirect and Post-Increment Rd
X
(X)
X + 1 None 1 (1)(2)
LD Rd, -X Load Indirect and Pre-Decrement X X - 1,
Rd (X)
X - 1
(X) None 2 (1)(2)
LD Rd, Y Load Indirect Rd (Y) (Y) None 1 (1)(2)
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y
(Y)
Y + 1 None 1 (1)(2)
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
Y - 1
(Y) None 2 (1)(2)
LDD Rd, Y+q Load Indirect with Displacement Rd (Y + q) None 2 (1)(2)
LD Rd, Z Load Indirect Rd (Z) None 1 (1)(2)
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
(Z),
Z+1 None 1 (1)(2)
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
Z - 1,
(Z) None 2 (1)(2)
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 (1)(2)
STS k, Rr Store Direct to Data Space (k) Rd None 2 (1)
ST X, Rr Store Indirect (X) Rr None 1 (1)
ST X+, Rr Store Indirect and Post-Increment (X)
X
Rr,
X + 1 None 1 (1)
ST -X, Rr Store Indirect and Pre-Decrement X
(X)
X - 1,
Rr None 2 (1)
ST Y, R r Store Indirect (Y) Rr None 1 (1)
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y
Rr,
Y + 1 None 1 (1)
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y)
Y - 1,
Rr None 2 (1)
STD Y+q, Rr Store Indirect with Displacement (Y + q) Rr None 2 (1)
ST Z, Rr Store Indirect (Z) Rr None 1 (1)
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z
Rr
Z + 1 None 1 (1)
ST -Z, Rr Store Indirect and Pre-Decrement ZZ - 1 None 2 (1)
STD Z+q, Rr Store Indirect with Displacement (Z + q) Rr None 2 (1)
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Increment Rd
Z
(Z),
Z + 1 None 3
ELPM Extended Load Program Memory R0 (RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd (RAMPZ:Z) None 3
ELPM Rd, Z+ Extended Load Program Memory and Post-
Increment
Rd
Z
(RAMPZ:Z),
Z + 1 None 3
SPM Store Program Memory (RAMPZ:Z) R1:R0 None -
SPM Z+ Store Program Memory and Post-Increment by 2 (RAMPZ:Z)
Z
R1:R0,
Z + 2 None -
IN Rd, A In From I/O Location Rd I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 1 (1)
POP Rd Pop Register from Stack Rd STACK None 2 (1)
Mnemonics Operands Description Operation Flags #Clocks
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Notes: 1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing internal SRAM.
Bit and bit-test instructions
LSL Rd Logical Shift Left Rd(n+1)
Rd(0)
Rd(n),
0, Z,C,N,V,H 1
LSR Rd Logical Shift Right Rd(n)
Rd(7)
Rd(n+1),
0, Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)
Rd(n+1)
C,
Rd(n), Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry Rd(7)
Rd(n)
C,
Rd(n+1), Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1
BSET sFlag Set SREG(s) 1SREG(s) 1
BCLR sFlag Clear SREG(s) 0SREG(s) 1
SBI A, b Set Bit in I/O Register I/O(A, b) 1None 1
CBI A, b Clear Bit in I/O Register I/O(A, b) 0None 1
BST Rr, b Bit Store from Register to T TRr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) TNone 1
SEC Set Carry C1 C 1
CLC Clear Carry C0 C 1
SEN Set Negative Flag N1 N 1
CLN Clear Negative Flag N0 N 1
SEZ Set Zero Flag Z1 Z 1
CLZ Clear Zero Flag Z0 Z 1
SEI Global Interrupt Enable I1 I 1
CLI Global Interrupt Disable I0 I 1
SES Set Signed Test Flag S1 S 1
CLS Clear Signed Test Flag S0 S 1
SEV Set Two’s Complement Overflow V1 V 1
CLV Clear Two’s Complement Overflow V0 V 1
SET Set T in SREG T1 T 1
CLT Clear T in SREG T0 T 1
SEH Set Half Carry Flag in SREG H1 H 1
CLH Clear Half Carry Flag in SREG H0 H 1
MCU control instructions
BREAK Break (See specific descr. for BREAK) None 1
NOP No Operation None 1
SLEEP Sleep (See specific descr. for Sleep) None 1
WDR Watchdog Reset (See specific descr. for WDR) None 1
Mnemonics Operands Description Operation Flags #Clocks
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31. Packaging Information
31.1 64A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO. REV.
64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.8mm Lead Pitch, Thin Prole Plastic Quad Flat Package (TQFP) C
64A
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
e
E1 E
B
COMMON DIMENSIONS
(Unit of measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
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31.2 64M
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32. Electrical Characteristics
All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
32.1 Atmel ATxmega32D3
32.1.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-1 may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 32-1. Absolute Maximum Ratings
32.1.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-31 on page 82 in order for all other electrical characteristics
and typical characteristics of the device to be valid.
Table 32-2. General Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage -0.3 4 V
IVCC Current into a VCC pin 200
mA
IGND Current out of a Gnd pin 200
VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC + 0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150
°C
TjJunction temperature 150
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage 1.60 3.6
V
AVCC Analog supply voltage 1.60 3.6
TATemperature range -40 85
°C
TjJunction temperature -40 105
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Table 32-3. Operating Voltage and Frequency
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83 the frequency vs. VCC curve is
linear between 1.8V < VCC <2.7V.
Figure 32-1. Maximum Frequency vs. VCC
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe operating area
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32.1.3 Current Consumption
Table 32-4. Current Consumption for Active Mode and Sleep Modes
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 50
µA
VCC = 3.0V 130
1MHz, Ext. Clk
VCC = 1.8V 215
VCC = 3.0V 475
2MHz, Ext. Clk
VCC = 1.8V 445 600
VCC = 3.0V
0.95 1.5
mA
32MHz, Ext. Clk 7.8 12.0
Idle power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 2.8
µA
VCC = 3.0V 3
1MHz, Ext. Clk
VCC = 1.8V 46
VCC = 3.0V 92
2MHz, Ext. Clk
VCC = 1.8V 93 225
VCC = 3.0V
184 350
32MHz, Ext. Clk 2.9 5.0 mA
Power-down power
consumption
T=25°C
VCC = 3.0V
0.07 1.0
µA
T=85°C 1.3 5.0
T = 105°C 4.0 8.0
WDT and sampled BOD enabled, T = 25°C
VCC = 3.0V
1.3 2.0
WDT and sampled BOD enabled, T = 85°C 2.6 6.0
WDT and sampled BOD enabled, T= 105°C 5.0 10
Power-save power
consumption (2)
RTC from ULP clock, WDT and sampled
BOD enabled, T = 25°C
VCC = 1.8V 1.7
VCC = 3.0V 1.8
RTC from 1.024kHz low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.5 2.0
VCC = 3.0V 0.7 2.0
RTC from low power 32.768kHz TOSC,
T=25°C
VCC = 1.8V 0.9 3.0
VCC = 3.0V 1.2 3.0
Reset power consumption Current through RESET pin substracted VCC = 3.0V 120
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Table 32-5. Current Consumption for Modules and Peripherals
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition (1) Min. Typ. Max. Units
ICC
ULP oscillator 0.9
µA
32.768kHz int. oscillator 29
2MHz int. oscillator
82
DFLL enabled with 32.768kHz int. osc. as reference 114
32MHz int. oscillator
250
DFLL enabled with 32.768kHz int. osc. as reference 400
PLL 20× multiplication factor,
32MHz int. osc. DIV4 as reference 300
Watchdog timer 1.0
BOD
Continuous mode 140
Sampled mode, includes ULP oscillator 1.4
Internal 1.0V reference 180
Temperature sensor 175
ADC
16ksps
VREF = Ext. ref.
1.23
mA
CURRLIMIT = LOW 1.1
CURRLIMIT = MEDIUM 0.98
CURRLIMIT = HIGH 0.87
75ksps
VREF = Ext. ref. CURRLIMIT = LOW 1.7
300ksps
VREF = Ext. ref. 3.1
USART Rx and Tx enabled, 9600 BAUD 9.7 µA
Flash memory and EEPROM programming 5mA
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32.1.4 Wake-up Time from Sleep Modes
Table 32-6. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-2. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-2. Wake-up Time Definition
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from idle,
standby, and extended standby
mode
External 2MHz clock 2.0
µs
32.768kHz internal oscillator 125
2MHz internal oscillator 2.0
32MHz internal oscillator 0.2
Wake-up time from power-save
and power-down mode
External 2MHz clock 4.6
32.768kHz internal oscillator 330
2MHz internal oscillator 9.5
32MHz internal oscillator 5.6
Wakeup request
Clock output
Wakeup time
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32.1.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low-level input and output
voltage limits reflect or exceed this specification.
Table 32-7. I/O Pin Characteristics
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/ IOL (2) I/O pin source/sink current -15 15 mA
VIH High level input voltage
VCC = 2.4 - 3.6V 0.7 * VCC VCC + 0.5
V
VCC = 1.6 - 2.4V 0.8 * VCC VCC + 0.5
VIL Low level input voltage
VCC = 2.4 - 3.6V -0.5 0.3 * VCC
VCC = 1.6 - 2.4V -0.5 0.2 * VCC
VOH High level output voltage
VCC = 3.3V IOH = -4mA 2.6 2.9
VCC = 3.0V IOH = -3mA 2.1 2.6
VCC = 1.8V IOH = -1mA 1.4 1.6
VOL Low level output voltage
VCC = 3.3V IOL = 8mA 0.4 0.76
VCC = 3.0V IOL = 5mA 0.3 0.64
VCC = 1.8V IOL = 3mA 0.2 0.46
IIN Input leakage current I/O pin T = 25°C <0.01 1µA
RPPull/buss keeper resistor 25 k
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32.1.6 ADC Characteristics
Table 32-8. Power Supply, Reference, and Input Range
Table 32-9. Clock and Timing
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC - 0.3 VCC + 0.3
V
VREF Reference voltage 1AVCC - 0.6
Rin Input resistance Switched 4.5 k
Cin Input capacitance Switched 5pF
RAREF Reference input resistance (leakage only) >10 M
CAREF Reference input capacitance Static load 7pF
Vin Input range 0 VREF
VConversion range Differential mode, Vinp - Vinn -VREF VREF
Conversion range Single ended unsigned mode, Vinp -V VREF - V
VFixed offset voltage 200 lsb
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC clock frequency
Maximum is 1/4 of peripheral clock frequency 100 1800
kHz
Measuring internal signals 100 125
fClkADC Sample rate 16 300
ksps
fADC Sample rate
Current limitation (CURRLIMIT) off 16 300
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time Configurable in steps of 1/2 ClkADC cycle up
to 32 ClkADC cycles 0.28 320 µs
Conversion time (latency) (RES+2)/2 + 1 + GAIN
RES (Resolution) = 8 or 12, GAIN = 0 to 3 5.5 10
ClkADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
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Table 32-10. Accuracy Characteristics
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 812 12
BitsSingle ended signed 711 11
Single ended unsigned 812 12
INL (1) Integral non-linearity
Differential mode
16ksps, VREF = 3V 0.5 1
lsb
16ksps, all VREF 0.8 2
300ksps, VREF = 3V 0.6 1
300ksps, all VREF 1 2
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.5 1
16ksps, all VREF 1.3 2
DNL (1) Differential non-linearity
Differential mode
16ksps, VREF = 3V 0.3 1
16ksps, all VREF 0.5 1
300ksps, VREF = 3V 0.3 1
300ksps, all VREF 0.5 1
Single ended
unsigned mode
16ksps, VREF = 3V 0.6 1
16ksps, all VREF 0.6 1
Offset error Differential mode
300ksps, VREF = 3V -7 mV
Temperature drift, VREF = 3V 0.01 mV/K
Operating voltage drift 0.16 mV/V
Gain error Differential mode
External reference -5
mV
AVCC/1.6 -5
AVCC/2.0 -6
Bandgap ±10
Temperature drift 0.02 mV/K
Operating voltage drift 2mV/V
Gain error Single ended
unsigned mode
External reference -8
mV
AVCC/1.6 -8
AVCC/2.0 -8
Bandgap ±10
Temperature drift 0.03 mV/K
Operating voltage drift 2mV/V
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Table 32-11. Gain Stage Characteristics
32.1.7 Analog Comparator Characteristics
Table 32-12. Analog Comparator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 k
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0AVCC - 0.6 V
Propagation delay ADC conversion rate 1/2 1 3 ClkADC cycles
Clock frequency Same as ADC 100 1800 kHz
Gain error
0.5× gain, normal mode -1
%
1× gain, normal mode -1
8× gain, normal mode -1
64× gain, normal mode 5
Offset error, input
referred
0.5× gain, normal mode 10
mV
1× gain, normal mode 5
8× gain, normal mode -20
64× gain, normal mode -126
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input offset voltage 10 mV
Ilk Input leakage current <10 50 nA
Input voltage range -0.1 AVCC V
AC startup time 50 µs
Vhys1 Hysteresis, none VCC = 1.6V - 3.6V 0
mVVhys2 Hysteresis, small VCC = 1.6V - 3.6V 15
Vhys3 Hysteresis, large VCC = 1.6V - 3.6V 30
tdelay Propagation delay
VCC = 3.0V, T = 85°C 20 40
ns
VCC = 3.0V 17
64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb
Current source accuracy after calibration 5 %
Current source calibration range Single mode 4 6 µA
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32.1.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-13. Bandgp and Internal 1.0V Reference Characteristics
32.1.9 Brownout Detection Characteristics
Table 32-14. Brownout Detection Characteristics (1)
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.1.10 External Reset Characteristics
Table 32-15. External Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1
V
INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 11.01
Variation over voltage and temperature Calibrated at T = 85°C 1 %
Symbol Parameter (BOD level 0 at 85°C) Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.40 1.60 1.70
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 1000 90 ns
VRST Reset threshold voltage
VCC = 2.7 - 3.6V 0.45 * VCC V
VCC = 1.6 - 2.7V 0.42 * VCC
RRST Reset pin pull-up resistor 25 k
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32.1.11 Power-on Reset Characteristics
Table 32-16. Power-on Reset Characteristics
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
32.1.12 Flash and EEPROM Memory Characteristics
Table 32-17. Endurance and Data Retention
Table 32-18. Programming Time
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
VVCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle
85°C 10K
105°C 2K
Data retention
25°C 100
Year
85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle
85°C 100K
105°C 30K
Data retention
25°C 100
Year
85°C 25
105°C 10
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip erase (2) 32KB Flash, EEPROM 50
ms
Application erase Section erase 6
Flash
Page erase 4
Page write 4
Atomic page erase and write 8
EEPROM
Page erase 4
Page write 4
Atomic page erase and write 8
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32.1.13 Clock and Oscillator Characteristics
32.1.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-19. 32.768kHz Internal Oscillator Characteristics
32.1.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-20. 2MHz Internal Oscillator Characteristics
32.1.13.3 Calibrated 32MHz Internal Oscillator Characteristics
Table 32-21. 32MHz Internal Oscillator Characteristics
32.1.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-22. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -0.5 0.5
%
User calibration accuracy -0.5 0.5
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.0 2.2
MHz
Factory calibrated frequency 2.0
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration stepsize 0.18
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 32 55
MHz
Factory calibrated frequency 32
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration step size 0.19
Symbol Parameter Condition Min. Typ. Max. Units
Factory calibrated frequency 32 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -12 12
%
Accuracy -30 30
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32.1.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-23. Internal PLL Characteristics
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.1.13.6 External Clock Characteristics
Figure 32-3. External Clock Drive Waveform
Table 32-24. External Clock used as System Clock without Prescaling
Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol Parameter Condition Min. Typ. Max. Units
fIN Input frequency Output frequency must be within fOUT 0.4 64
MHz
fOUT Output frequency (1) VCC = 1.6 - 1.8V 20 48
VCC = 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCK Change in period from one clock cycle to the next 10 %
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Table 32-25. External Clock with Prescaler (1) for System Clock
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.1.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-26. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 0
ns
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Long term jitter
XOSCPWR=0
FRQRANGE=0 0
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Frequency error
XOSCPWR=0
FRQRANGE=0 0.03
%
FRQRANGE=1 0.03
FRQRANGE=2 or 3 0.03
XOSCPWR=1 0.003
Duty cycle
XOSCPWR=0
FRQRANGE=0 50
FRQRANGE=1 50
FRQRANGE=2 or 3 50
XOSCPWR=1 50
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RQNegative impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 44k
1MHz crystal, CL=20pF 67k
2MHz crystal, CL=20pF 67k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 82k
8MHz crystal 1500
9MHz crystal 1500
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 2700
9MHz crystal 2700
12MHz crystal 1000
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 3600
12MHz crystal 1300
16MHz crystal 590
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 390
12MHz crystal 50
16MHz crystal 10
RQNegative impedance (1)
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 1500
12MHz crystal 650
16MHz crystal 270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 1000
16MHz crystal 440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 1300
16MHz crystal 590
ESR SF = safety factor min(RQ)/SF k
Start-up time
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 1.0
ms
XOSCPWR=0,
FRQRANGE=1 2MHz crystal, CL=20pF 2.6
XOSCPWR=0,
FRQRANGE=2 8MHz crystal, CL=20pF 0.8
XOSCPWR=0,
FRQRANGE=3 12MHz crystal, CL=20pF 1.0
XOSCPWR=1,
FRQRANGE=3 16MHz crystal, CL=20pF 1.4
Symbol Parameter Condition Min. Typ. Max. Units
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.1.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-27. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Note: See Figure 32-11 on page 97 for definition.
Figure 32-4. TOSC Input Capacitance
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
CXTAL1
Parasitic capacitance
XTAL1 pin 5.9
pF
CXTAL2
Parasitic capacitance
XTAL2 pin 8.3
CLOAD Parasitic capacitance load 3.5
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kCrystal load capacitance 9.0pF 35
Crystal load capacitance 12pF 28
CTOSC1 Parasitic capacitance TOSC1 pin 3.5
pF
CTOSC2 Parasitic capacitance TOSC2 pin 3.5
Recommended safety factor Capacitance load matched to crystal
specification 3
Symbol Parameter Condition Min. Typ. Max. Units
CL1 CL2
2CS
O
T
1
CS
O
TDevice internal
External
32.768 kHz crystal
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32.1.14 SPI Characteristics
Figure 32-5. SPI Timing Requirements in Master Mode
Figure 32-6. SPI Timing Requirements in Slave Mode
MSB LSB
BSLBSM
tMOS
tMIS tMIH
tSCKW
tSCK
tMOH tMOH
tSCKF
tSCKR
tSCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
tSIS tSIH
tSSCKW
tSSCKW
tSSCK
tSSH
tSOSSH
tSCKR tSCKF
tSOS
tSSS
tSOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 32-28. SPI Timing Characteristics and Requirements
32.1.15 Two-wire Interface Characteristics
Table 32-29 on page 81 describes the requirements for devices connected to the two-wire interface bus. The Atmel AVR
XMEGA two-wire interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to
Figure 32-7.
Figure 32-7. Two-wire Interface Bus Timing
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK period Master (See Table 20-3 in
XMEGA D manual)
ns
tSCKW SCK high/low width Master 0.5 * SCK
tSCKR SCK rise time Master 2.7
tSCKF SCK fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5 * SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4 * t ClkPER
tSSCKW SCK high/low width Slave 2 * t ClkPER
tSSCKR SCK rise time Slave 1600
tSSCKF SCK fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tClk
PER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
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Table 32-29. Two-wire Interface Characteristics
Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input high voltage 0.7VCC VCC + 0.5
V
VIL Input low voltage -0.5 0.3VCC
Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)
VOL Output low voltage 3mA, sink current 00.4
trRise time for both SDA and SCL 20 + 0.1Cb (1)(2) 300
nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20 + 0.1Cb (1)(2) 250
tSP Spikes suppressed by input filter 050
IIInput current for each I/O pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O pin 10 pF
fSCL SCL clock frequency fPER (3) > max(10fSCL, 250kHz) 0400 kHz
RPValue of pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold time (repeated) START condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low period of SCL clock
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
tHIGH High period of SCL clock
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz 4.7
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL 100kHz 03.45
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL 100kHz 250
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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32.2 Atmel ATxmega64D3
32.2.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-30 may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 32-30. Absolute Maximum Ratings
32.2.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-31 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-31. General Operating Conditions
Table 32-32. Operating Voltage and Frequency
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83 the frequency vs. VCC curve is
linear between 1.8V < VCC <2.7V.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage -0.3 4 V
IVCC Current into a VCC pin 200
mA
IGND Current out of a Gnd pin 200
VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC + 0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150
°C
TjJunction temperature 150
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage 1.60 3.6
V
AVCC Analog supply voltage 1.60 3.6
TATemperature range -40 85
°C
TjJunction temperature -40 105
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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Figure 32-8. Maximum Frequency vs. VCC
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe operating area
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32.2.3 Current Consumption
Table 32-33. Current Consumption for Active Mode and Sleep Modes
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 50
µA
VCC = 3.0V 130
1MHz, Ext. Clk
VCC = 1.8V 215
VCC = 3.0V 475
2MHz, Ext. Clk
VCC = 1.8V 445 600
VCC = 3.0V
0.95 1.5
mA
32MHz, Ext. Clk 7.8 12.0
Idle power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 2.8
µA
VCC = 3.0V 3
1MHz, Ext. Clk
VCC = 1.8V 46
VCC = 3.0V 92
2MHz, Ext. Clk
VCC = 1.8V 93 225
VCC = 3.0V
184 350
32MHz, Ext. Clk 2.9 5.0 mA
Power-down power
consumption
T=25°C
VCC = 3.0V
0.07 1.0
µA
T=85°C 1.3 5.0
T = 105°C 4.0 8.0
WDT and sampled BOD enabled, T = 25°C
VCC = 3.0V
1.3 2.0
WDT and sampled BOD enabled, T = 85°C 2.6 6.0
WDT and sampled BOD enabled, T= 105°C 5.0 10
Power-save power
consumption (2)
RTC from ULP clock, WDT and sampled
BOD enabled, T = 25°C
VCC = 1.8V 1.7
VCC = 3.0V 1.8
RTC from 1.024kHz low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.5 2.0
VCC = 3.0V 0.7 2.0
RTC from low power 32.768kHz TOSC,
T=25°C
VCC = 1.8V 0.9 3.0
VCC = 3.0V 1.2 3.0
Reset power consumption Current through RESET pin substracted VCC = 3.0V 120
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Table 32-34. Current Consumption for Modules and Peripherals
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition (1) Min. Typ. Max. Units
ICC
ULP oscillator 0.9
µA
32.768kHz int. oscillator 29
2MHz int. oscillator
82
DFLL enabled with 32.768kHz int. osc. as reference 114
32MHz int. oscillator
250
DFLL enabled with 32.768kHz int. osc. as reference 400
PLL 20× multiplication factor,
32MHz int. osc. DIV4 as reference 300
Watchdog timer 1.0
BOD
Continuous mode 140
Sampled mode, includes ULP oscillator 1.4
Internal 1.0V reference 180
Temperature sensor 175
ADC
16ksps
VREF = Ext. ref.
1.23
mA
CURRLIMIT = LOW 1.1
CURRLIMIT = MEDIUM 0.98
CURRLIMIT = HIGH 0.87
75ksps
VREF = Ext. ref. CURRLIMIT = LOW 1.7
300ksps
VREF = Ext. ref. 3.1
USART Rx and Tx enabled, 9600 BAUD 9.7 µA
Flash memory and EEPROM programming 5mA
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32.2.4 Wake-up Time from Sleep Modes
Table 32-35. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-9. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-9. Wake-up Time Definition
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from idle,
standby, and extended standby
mode
External 2MHz clock 2.0
µs
32.768kHz internal oscillator 125
2MHz internal oscillator 2.0
32MHz internal oscillator 0.2
Wake-up time from power-save
and power-down mode
External 2MHz clock 4.6
32.768kHz internal oscillator 330
2MHz internal oscillator 9.5
32MHz internal oscillator 5.6
Wakeup request
Clock output
Wakeup time
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32.2.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-36. I/O Pin Characteristics
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/ IOL (2) I/O pin source/sink current -15 15 mA
VIH High level input voltage
VCC = 2.4 - 3.6V 0.7 * VCC VCC + 0.5
V
VCC = 1.6 - 2.4V 0.8 * VCC VCC + 0.5
VIL Low level input voltage
VCC = 2.4 - 3.6V -0.5 0.3 * VCC
VCC = 1.6 - 2.4V -0.5 0.2 * VCC
VOH High level output voltage
VCC = 3.3V IOH = -4mA 2.6 2.9
VCC = 3.0V IOH = -3mA 2.1 2.6
VCC = 1.8V IOH = -1mA 1.4 1.6
VOL Low level output voltage
VCC = 3.3V IOL = 8mA 0.4 0.76
VCC = 3.0V IOL = 5mA 0.3 0.64
VCC = 1.8V IOL = 3mA 0.2 0.46
IIN Input leakage current I/O pin T = 25°C <0.01 1µA
RPPull/buss keeper resistor 25 k
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32.2.6 ADC Characteristics
Table 32-37. Power Supply, Reference, and Input Range
Table 32-38. Clock and Timing
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC - 0.3 VCC + 0.3
V
VREF Reference voltage 1AVCC - 0.6
Rin Input resistance Switched 4.5 k
Cin Input capacitance Switched 5pF
RAREF Reference input resistance (leakage only) >10 M
CAREF Reference input capacitance Static load 7pF
Vin Input range 0 VREF
VConversion range Differential mode, Vinp - Vinn -VREF VREF
Conversion range Single ended unsigned mode, Vinp -V VREF - V
VFixed offset voltage 200 lsb
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC clock frequency
Maximum is 1/4 of peripheral clock frequency 100 1800
kHz
Measuring internal signals 100 125
fClkADC Sample rate 16 300
ksps
fADC Sample rate
Current limitation (CURRLIMIT) off 16 300
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time Configurable in steps of 1/2 ClkADC cycle up
to 32 ClkADC cycles 0.28 320 µs
Conversion time (latency) (RES+2)/2 + 1 + GAIN
RES (Resolution) = 8 or 12, GAIN = 0 to 3 5.5 10
ClkADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
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Table 32-39. Accuracy Characteristics
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 812 12
BitsSingle ended signed 711 11
Single ended unsigned 812 12
INL (1) Integral non-linearity
Differential mode
16ksps, VREF = 3V 0.5 1
lsb
16ksps, all VREF 0.8 2
300ksps, VREF = 3V 0.6 1
300ksps, all VREF 1 2
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.5 1
16ksps, all VREF 1.3 2
DNL (1) Differential non-linearity
Differential mode
16ksps, VREF = 3V 0.3 1
16ksps, all VREF 0.5 1
300ksps, VREF = 3V 0.3 1
300ksps, all VREF 0.5 1
Single ended
unsigned mode
16ksps, VREF = 3V 0.6 1
16ksps, all VREF 0.6 1
Offset error Differential mode
300ksps, VREF = 3V -7 mV
Temperature drift, VREF = 3V 0.01 mV/K
Operating voltage drift 0.16 mV/V
Gain error Differential mode
External reference -5
mV
AVCC/1.6 -5
AVCC/2.0 -6
Bandgap ±10
Temperature drift 0.02 mV/K
Operating voltage drift 2mV/V
Gain error Single ended
unsigned mode
External reference -8
mV
AVCC/1.6 -8
AVCC/2.0 -8
Bandgap ±10
Temperature drift 0.03 mV/K
Operating voltage drift 2mV/V
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Table 32-40. Gain Stage Characteristics
32.2.7 Analog Comparator Characteristics
Table 32-41. Analog Comparator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 k
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0AVCC - 0.6 V
Propagation delay ADC conversion rate 1/2 1 3 ClkADC cycles
Clock frequency Same as ADC 100 1800 kHz
Gain error
0.5× gain, normal mode -1
%
1× gain, normal mode -1
8× gain, normal mode -1
64× gain, normal mode 5
Offset error, input referred
0.5× gain, normal mode 10
mV
1× gain, normal mode 5
8× gain, normal mode -20
64× gain, normal mode -126
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input offset voltage 10 mV
Ilk Input leakage current <10 50 nA
Input voltage range -0.1 AVCC V
AC startup time 50 µs
Vhys1 Hysteresis, none VCC = 1.6V - 3.6V 0
mVVhys2 Hysteresis, small VCC = 1.6V - 3.6V 15
Vhys3 Hysteresis, large VCC = 1.6V - 3.6V 30
tdelay Propagation delay
VCC = 3.0V, T = 85°C 20 40
ns
VCC = 3.0V 17
64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb
Current source accuracy after calibration 5 %
Current source calibration range Single mode 4 6 µA
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32.2.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-42. Bandgap and Internal 1.0V Reference Characteristics
32.2.9 Brownout Detection Characteristics
Table 32-43. Brownout Detection Characteristics (1)
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.2.10 External Reset Characteristics
Table 32-44. External Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1
V
INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 11.01
Variation over voltage and temperature Calibrated at T = 85°C 1 %
Symbol Parameter (BOD level 0 at 85°C) Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.40 1.60 1.70
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 1000 90 ns
VRST Reset threshold voltage
VCC = 2.7 - 3.6V 0.45 * VCC V
VCC = 1.6 - 2.7V 0.42 * VCC
RRST Reset pin pull-up resistor 25 k
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32.2.11 Power-on Reset Characteristics
Table 32-45. Power-on Reset Characteristics
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
32.2.12 Flash and EEPROM Memory Characteristics
Table 32-46. Endurance and Data Retention
Table 32-47. Programming Time
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
V
VCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle
85°C 10K
105°C 2K
Data retention
25°C 100
Year
85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle
85°C 100K
105°C 30K
Data retention
25°C 100
Year
85°C 25
105°C 10
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip erase (2) 64KB Flash, EEPROM 55
ms
Application erase Section erase 6
Flash
Page erase 4
Page write 4
Atomic page erase and write 8
EEPROM
Page erase 4
Page write 4
Atomic page erase and write 8
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32.2.13 Clock and Oscillator Characteristics
32.2.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-48. 32.768kHz Internal Oscillator Characteristics
32.2.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-49. 2MHz Internal Oscillator Characteristics
32.2.13.3 Calibrated 32MHz Internal Oscillator Characteristics
Table 32-50. 32MHz Internal Oscillator Characteristics
32.2.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-51. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -0.5 0.5
%
User calibration accuracy -0.5 0.5
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.0 2.2
MHz
Factory calibrated frequency 2.0
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration stepsize 0.18
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 32 55
MHz
Factory calibrated frequency 32
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration step size 0.19
Symbol Parameter Condition Min. Typ. Max. Units
Factory calibrated frequency 32 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -12 12
%
Accuracy -30 30
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32.2.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-52. Internal PLL Characteristics
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.2.13.6 External Clock Characteristics
Figure 32-10.External Clock Drive Waveform
Table 32-53. External Clock used as System Clock without Prescaling
Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol Parameter Condition Min. Typ. Max. Units
fIN Input frequency Output frequency must be within fOUT 0.4 64
MHz
fOUT Output frequency (1) VCC = 1.6 - 1.8V 20 48
VCC = 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCK Change in period from one clock cycle to the next 10 %
95
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Table 32-54. External Clock with Prescaler (1) for System Clock
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.2.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-55. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 0
ns
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Long term jitter
XOSCPWR=0
FRQRANGE=0 0
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Frequency error
XOSCPWR=0
FRQRANGE=0 0.03
%
FRQRANGE=1 0.03
FRQRANGE=2 or 3 0.03
XOSCPWR=1 0.003
Duty cycle
XOSCPWR=0
FRQRANGE=0 50
FRQRANGE=1 50
FRQRANGE=2 or 3 50
XOSCPWR=1 50
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RQNegative impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator, CL=100pF 44k
1MHz crystal, CL=20pF 67k
2MHz crystal, CL=20pF 67k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 82k
8MHz crystal 1500
9MHz crystal 1500
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 2700
9MHz crystal 2700
12MHz crystal 1000
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 3600
12MHz crystal 1300
16MHz crystal 590
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 390
12MHz crystal 50
16MHz crystal 10
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 1500
12MHz crystal 650
16MHz crystal 270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 1000
16MHz crystal 440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 1300
16MHz crystal 590
ESR SF = safety factor min(RQ)/SF k
Start-up time
XOSCPWR=0,
FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0
ms
XOSCPWR=0,
FRQRANGE=1 2MHz crystal, CL=20pF 2.6
XOSCPWR=0,
FRQRANGE=2 8MHz crystal, CL=20pF 0.8
XOSCPWR=0,
FRQRANGE=3 12MHz crystal, CL=20pF 1.0
XOSCPWR=1,
FRQRANGE=3 16MHz crystal, CL=20pF 1.4
Symbol Parameter Condition Min. Typ. Max. Units
97
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.2.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-56. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Note: See Figure 32-11 for definition.
Figure 32-11.TOSC Input Capacitance
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
CXTAL1
Parasitic capacitance
XTAL1 pin 5.9
pF
CXTAL2
Parasitic capacitance
XTAL2 pin 8.3
CLOAD Parasitic capacitance load 3.5
Symbo
lParameter Condition Min. Typ. Max. Units
ESR/
R1
Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kCrystal load capacitance 9.0pF 35
Crystal load capacitance 12pF 28
CTOSC1 Parasitic capacitance TOSC1 pin 3.5
pF
CTOSC2 Parasitic capacitance TOSC2 pin 3.5
Recommended safety factor Capacitance load matched to crystal
specification 3
Symbol Parameter Condition Min. Typ. Max. Units
CL1 CL2
2CS
O
T
1
CS
O
TDevice internal
External
32.768 kHz crystal
98
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32.2.14 SPI Characteristics
Figure 32-12. SPI Timing Requirements in Master Mode
Figure 32-13.SPI Timing Requirements in Slave Mode
MSB LSB
BSLBSM
tMOS
tMIS tMIH
tSCKW
tSCK
tMOH tMOH
tSCKF
tSCKR
tSCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
tSIS tSIH
tSSCKW
tSSCKW
tSSCK
tSSH
tSOSSH
tSCKR tSCKF
tSOS
tSSS
tSOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
99
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Table 32-57. SPI Timing Characteristics and Requirements
32.2.15 Two-wire Interface Characteristics
Table 32-58 on page 100 describes the requirements for devices connected to the two-wire interface bus. The Atmel
AVR XMEGA two-wire interface meets or exceeds these requirements under the noted conditions. Timing symbols refer
to Figure 32-14.
Figure 32-14.Two-wire Interface Bus Timing
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK period Master (See Table 20-3 in
XMEGA D manual)
ns
tSCKW SCK high/low width Master 0.5 * SCK
tSCKR SCK rise time Master 2.7
tSCKF SCK fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5 * SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4 * t ClkPER
tSSCKW SCK high/low width Slave 2 * t ClkPER
tSSCKR SCK rise time Slave 1600
tSSCKF SCK fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tClk
PER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
100
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Table 32-58. Two-wire Interface Characteristics
Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input high voltage 0.7VCC VCC + 0.5
V
VIL Input low voltage -0.5 0.3VCC
Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)
VOL Output low voltage 3mA, sink current 00.4
trRise time for both SDA and SCL 20 + 0.1Cb (1)(2) 300
nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20 + 0.1Cb (1)(2) 250
tSP Spikes suppressed by input filter 050
IIInput current for each I/O pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O pin 10 pF
fSCL SCL clock frequency fPER (3) > max(10fSCL, 250kHz) 0400 kHz
RPValue of pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold time (repeated) START condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low period of SCL clock
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
tHIGH High period of SCL clock
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz 4.7
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL 100kHz 250
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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32.3 Atmel ATxmega128D3
32.3.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-59 may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 32-59. Absolute Maximum Ratings
32.3.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-60 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-60. General Operating Conditions
Table 32-61. Operating Voltage and Frequency
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-15 on page 102 the frequency vs. VCC
curve is linear between 1.8V < VCC <2.7V.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage -0.3 4 V
IVCC Current into a VCC pin 200
mA
IGND Current out of a Gnd pin 200
VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC + 0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150
°C
TjJunction temperature 150
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage 1.60 3.6
V
AVCC Analog supply voltage 1.60 3.6
TATemperature range -40 85
°C
TjJunction temperature -40 105
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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Figure 32-15.Maximum Frequency vs. VCC
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe operating area
103
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32.3.3 Current Consumption
Table 32-62. Current Consumption for Active Mode and Sleep Modes
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 55
µA
VCC = 3.0V 135
1MHz, Ext. Clk
VCC = 1.8V 237
VCC = 3.0V 515
2MHz, Ext. Clk
VCC = 1.8V 425 700
VCC = 3.0V
0.9 1.5
mA
32MHz, Ext. Clk 8.3 12
Idle power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 2.8
µA
VCC = 3.0V 3.1
1MHz, Ext. Clk
VCC = 1.8V 47
VCC = 3.0V 95
2MHz, Ext. Clk
VCC = 1.8V 94 200
VCC = 3.0V
190 400
32MHz, Ext. Clk 3.0 7.0 mA
Power-down power
consumption
T=25°C
VCC = 3.0V
0.1 1.0
µA
T=85°C 1.9 4.0
T = 105°C 4.0 8.0
WDT and sampled BOD enabled, T = 25°C
VCC = 3.0V
1.5 2.0
WDT and sampled BOD enabled, T = 85°C 3.0 8.0
WDT and sampled BOD enabled, T= 105°C 5.0 10
Power-save power
consumption (2)
RTC from ULP clock, WDT and sampled
BOD enabled, T = 25°C
VCC = 1.8V 1.3
VCC = 3.0V 1.4
RTC from 1.024kHz low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.7 2.0
VCC = 3.0V 0.8 2.0
RTC from low power 32.768kHz TOSC,
T=25°C
VCC = 1.8V 0.9 3.0
VCC = 3.0V 1.1 3.0
Reset power consumption Current through RESET pin substracted VCC = 3.0V 145
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Table 32-63. Current Consumption for Modules and Peripherals
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition (1) Min. Typ. Max. Units
ICC
ULP oscillator 0.9
µA
32.768kHz int. oscillator 26
2MHz int. oscillator
79
DFLL enabled with 32.768kHz int. osc. as reference 110
32MHz int. oscillator
245
DFLL enabled with 32.768kHz int. osc. as reference 415
PLL 20× multiplication factor,
32MHz int. osc. DIV4 as reference 305
Watchdog timer 1.0
BOD
Continuous mode 138
Sampled mode, includes ULP oscillator 1.4
Internal 1.0V reference 185
Temperature sensor 173
ADC
16ksps
VREF = Ext. ref.
1.3
mA
CURRLIMIT = LOW 1.15
CURRLIMIT = MEDIUM 1.0
CURRLIMIT = HIGH 0.9
75ksps
VREF = Ext. ref. CURRLIMIT = LOW 1.7
300ksps
VREF = Ext. ref. 3.1
USART Rx and Tx enabled, 9600 BAUD 7.5 µA
Flash memory and EEPROM programming 4mA
105
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32.3.4 Wake-up Time from Sleep Modes
Table 32-64. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-16. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-16.Wake-up Time Definition
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from idle,
standby, and extended standby
mode
External 2MHz clock 2.0
µs
32.768kHz internal oscillator 130
2MHz internal oscillator 2.0
32MHz internal oscillator 0.2
Wake-up time from power-save
and power-down mode
External 2MHz clock 4.5
32.768kHz internal oscillator 320
2MHz internal oscillator 9.0
32MHz internal oscillator 5.0
Wakeup request
Clock output
Wakeup time
106
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32.3.5 I/O Pin Characteristics
The I/O pins compiles with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits or exceeds this specification.
Table 32-65. I/O Pin Characteristics
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/ IOL (2) I/O pin source/sink current -15 15 mA
VIH High level input voltage
VCC = 2.4 - 3.6V 0.7 * VCC VCC + 0.5
V
VCC = 1.6 - 2.4V 0.8 * VCC VCC + 0.5
VIL Low level input voltage
VCC = 2.4 - 3.6V -0.5 0.3 * VCC
VCC = 1.6 - 2.4V -0.5 0.2 * VCC
VOH High level output voltage
VCC = 3.3V IOH = -4mA 2.6 2.9
VCC = 3.0V IOH = -3mA 2.1 2.6
VCC = 1.8V IOH = -1mA 1.4 1.6
VOL Low level output voltage
VCC = 3.3V IOL = 8mA 0.4 0.76
VCC = 3.0V IOL = 5mA 0.3 0.64
VCC = 1.8V IOL = 3mA 0.2 0.46
IIN Input leakage current I/O pin T = 25°C <0.01 1.0 µA
RPPull/buss keeper resistor 25 k
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32.3.6 ADC Characteristics
Table 32-66. Power Supply, Reference, and Input Range
Table 32-67. Clock and Timing
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC - 0.3 VCC + 0.3
V
VREF Reference voltage 1AVCC - 0.6
Rin Input resistance Switched 4.5 k
Cin Input capacitance Switched 5pF
RAREF Reference input resistance (leakage only) >10 M
CAREF Reference input capacitance Static load 7pF
Vin Input range 0 VREF
VConversion range Differential mode, Vinp - Vinn -VREF VREF
Conversion range Single ended unsigned mode, Vinp -V VREF - V
VFixed offset voltage 200 lsb
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC clock frequency
Maximum is 1/4 of peripheral clock frequency 100 1800
kHz
Measuring internal signals 100 125
fClkADC Sample rate 16 300 ksps
fADC Sample rate
Current limitation (CURRLIMIT) off 16 300
ksps
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time 1/2 ClkADC cycle 0.28 320 µs
Conversion time (latency) (RES+2)/2 + GAIN
RES (Resolution) = 8 or 12, GAIN = 0 to 3 5.5 10
ClkADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
108
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Table 32-68. Accuracy Characteristics
Notes: 1. Maximum numbers are based on characterization and not tested in production and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 812 12
BitsSingle ended signed 711 11
Single ended unsigned 812 12
INL (1) Integral non-linearity
Differential mode
16ksps, VREF = 3V 0.5 1
lsb
16ksps, all VREF 0.8 2
300ksps, VREF = 3V 0.6 1
300ksps, all VREF 1.0 2
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.5 1
16ksps, all VREF 1.3 2
DNL (1) Differential non-linearity
Differential mode
16ksps, VREF = 3V 0.3 1
lsb
16ksps, all VREF 0.5 1
300ksps, VREF = 3V 0.3 1
300ksps, all VREF 0.5 1
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.6 1
16ksps, all VREF 0.6 1
Offset error Differential mode
300ksps, VREF = 3V -7 mV
Temperature drift, VREF = 3V 0.01 mV/K
Operating voltage drift 0.16 mV/V
Gain error Differential mode
External reference -5
mV
AVCC/1.6 -5
AVCC/2.0 -6
Bandgap ±10
Temperature drift 0.02 mV/K
Operating voltage drift 2mV/V
Gain error Single ended
unsigned mode
External reference -8
mV
AVCC/1.6 -8
AVCC/2.0 -8
Bandgap ±10
Temperature drift 0.03 mV/K
Operating voltage drift 2mV/V
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Table 32-69. Gain Stage Characteristics
32.3.7 Analog Comparator Characteristics
Table 32-70. Analog Comparator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 k
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0AVCC - 0.6 V
Propagation delay ADC conversion rate 1/2 1 3 ClkADC cycles
Clock frequency Same as ADC 100 1800 kHz
Gain error
0.5x gain, normal mode -1
%
1x gain, normal mode -1
8x gain, normal mode -1
64x gain, normal mode 5
Offset error, input referred
0.5x gain, normal mode 10
mV
1x gain, normal mode 5
8x gain, normal mode -20
64x gain, normal mode -126
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input offset voltage 10 mV
Ilk Input leakage current <10 50 nA
Input voltage range -0.1 AVCC V
AC startup time 50 µs
Vhys1 Hysteresis, none VCC = 1.6V - 3.6V 0
mVVhys2 Hysteresis, small VCC = 1.6V - 3.6V 15
Vhys3 Hysteresis, large VCC = 1.6V - 3.6V 30
tdelay Propagation delay
VCC = 3.0V, T = 85°C 20 90
ns
VCC = 3.0V 17
64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb
Current source accuracy after calibration 5 %
Current source calibration range Single mode 4 6 µA
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32.3.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-71. Bandgap and Internal 1.0V Reference Characteristics
32.3.9 Brownout Detection Characteristics
Table 32-72. Brownout Detection Characteristics (1)
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.3.10 External Reset Characteristics
Table 32-73. External Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1
V
INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1.0 1.01
Variation over voltage and temperature Calibrated at T = 85°C 1 %
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.40 1.60 1.70
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 1000 100 ns
VRST Reset threshold voltage
VCC = 2.7 - 3.6V 0.45 * VCC V
VCC = 1.6 - 2.7V 0.45 * VCC
RRST Reset pin pull-up resistor 27 k
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32.3.11 Power-on Reset Characteristics
Table 32-74. Power-on Reset Characteristics
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
32.3.12 Flash and EEPROM Memory Characteristics
Table 32-75. Endurance and Data Retention
Table 32-76. Programming Time
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
VVCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip erase (2) 128KB Flash, EEPROM 75
ms
Application erase Section erase 6
Flash
Page erase 4
Page write 4
Atomic page erase and write 8
EEPROM
Page erase 4
Page write 4
Atomic page erase and write 8
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32.3.13 Clock and Oscillator Characteristics
32.3.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-77. 32.768kHz Internal Oscillator Characteristics
32.3.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-78. 2MHz Internal Oscillator Characteristics
32.3.13.3 Calibrated 32MHz Internal Oscillator Characteristics
Table 32-79. 32MHz Internal Oscillator Characteristics
32.3.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-80. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -0.5 0.5
%
User calibration accuracy -0.5 0.5
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.0 2.2
MHz
Factory calibrated frequency 2.0
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration stepsize 0.18
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 32 55
MHz
Factory calibrated frequency 32
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration step size 0.2
Symbol Parameter Condition Min. Typ. Max. Units
Factory calibrated frequency 32 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -12 12
%
Accuracy -30 30
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32.3.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-81. Internal PLL Characteristics
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.3.13.6 External Clock Characteristics
Figure 32-17.External Clock Drive Waveform
Table 32-82. External Clock used as System Clock without Prescaling
Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol Parameter Condition Min. Typ. Max. Units
fIN Input frequency Output frequency must be within fOUT 0.4 64
MHz
fOUT Output frequency (1) VCC = 1.6 - 1.8V 20 48
VCC = 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCK Change in period from one clock cycle to the next 10 %
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Table 32-83. External Clock with Prescaler (1) for System Clock
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.3.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-84. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 0
ns
FRQRANGE=0 0
XOSCPWR=1 0
Long term jitter
XOSCPWR=0
FRQRANGE=0 0
FRQRANGE=0 0
XOSCPWR=1 0
Frequency error
XOSCPWR=0
FRQRANGE=0 0.03
%
FRQRANGE=0 0.03
FRQRANGE=0 0.03
XOSCPWR=1 0.003
Duty cycle
XOSCPWR=0
FRQRANGE=0 50
FRQRANGE=0 50
FRQRANGE=0 50
XOSCPWR=1 50
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RQNegative impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator, CL=100pF 44k
1MHz resonator, CL=20pF 67k
2MHz resonator, CL=20pF 67k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 82k
8MHz crystal 1500
9MHz crystal 1500
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 2700
9MHz crystal 2700
12MHz crystal 1000
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 3600
12MHz crystal 1300
16MHz crystal 590
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 390
12MHz crystal 50
16MHz crystal 10
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 1500
12MHz crystal 650
16MHz crystal 270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 1000
16MHz crystal 440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 1300
16MHz crystal 590
ESR SF = safety factor min(RQ)/SF k
Start-up time
XOSCPWR=0,
FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0
ms
XOSCPWR=0,
FRQRANGE=1 2MHz crystal, CL=20pF 2.6
XOSCPWR=0,
FRQRANGE=2 8MHz crystal, CL=20pF 0.8
XOSCPWR=0,
FRQRANGE=3 12MHz crystal, CL=20pF 1.0
XOSCPWR=1,
FRQRANGE=3 16MHz crystal, CL=20pF 1.4
Symbol Parameter Condition Min. Typ. Max. Units
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.3.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-85. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Note: See Figure 32-18 for definition.
Figure 32-18.TOSC Input Capacitance
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
CXTAL1
Parasitic capacitance
XTAL1 pin 5.9
pF
CXTAL2
Parasitic capacitance
XTAL1 pin 8.3
CLOAD Parasitic capacitance load 3.5
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1
Recommended crystal
equivalent series
resistance (ESR)
Crystal load capacitance 6.5pF 60
kCrystal load capacitance 9.0pF 35
Crystal load capacitance 12pF 28
CTOSC1
Parasitic capacitance
TOSC1 pin 3.5
pF
CTOSC2
Parasitic capacitance
TOSC2 pin 3.5
Recommended safety
factor Capacitance load matched to crystal specification 3
Symbol Parameter Condition Min. Typ. Max. Units
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768 kHz crystal
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32.3.14 SPI Characteristics
Figure 32-19.SPI Timing Requirements in Master Mode
Figure 32-20.SPI Timing Requirements in Slave Mode
MSB LSB
BSLBSM
tMOS
tMIS tMIH
tSCKW
tSCK
tMOH tMOH
tSCKF
tSCKR
tSCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
tSIS tSIH
tSSCKW
tSSCKW
tSSCK
tSSH
tSOSSH
tSCKR tSCKF
tSOS
tSSS
tSOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 32-86. SPI Timing Characteristics and Requirements
32.3.15 Two-wire Interface Characteristics
Table 32-87 on page 119 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel
AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 32-21.
Figure 32-21.Two-wire Interface Bus Timing
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK period Master (See Table 20-3 in
XMEGA D manual)
ns
tSCKW SCK high/low width Master 0.5 * SCK
tSCKR SCK rise time Master 2.7
tSCKF SCK fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5 * SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4 * t ClkPER
tSSCKW SCK high/low width Slave 2 * t ClkPER
tSSCKR SCK rise time Slave 1600
tSSCKF SCK fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tClk
PER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
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Table 32-87. Two-wire Interface Characteristics
Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input high voltage 0.7VCC VCC + 0.5
V
VIL Input low voltage -0.5 0.3VCC
Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)
VOL Output low voltage 3mA, sink current 00.4
trRise time for both SDA and SCL 20 + 0.1Cb (1)(2) 300
nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20 + 0.1Cb (1)(2) 250
tSP Spikes suppressed by input filter 050
IIInput current for each I/O pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O pin 10 pF
fSCL SCL clock frequency fPER (3) > max(10fSCL, 250kHz) 0400 kHz
RPValue of pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold time (repeated) START condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low period of SCL clock
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
tHIGH High period of SCL clock
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz 4.7
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL 100kHz 250
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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32.4 Atmel ATxmega192D3
32.4.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-88 may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 32-88. Absolute Maximum Ratings
32.4.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-89 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-89. General Operating Conditions
Table 32-90. Operating Voltage and Frequency
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-22 on page 121 the frequency vs. VCC
curve is linear between 1.8V < VCC <2.7V.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage -0.3 4 V
IVCC Current into a VCC pin 200
mA
IGND Current out of a Gnd pin 200
VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC + 0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150
°C
TjJunction temperature 150
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage 1.60 3.6
V
AVCC Analog supply voltage 1.60 3.6
TATemperature range -40 85
°C
TjJunction temperature -40 105
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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Figure 32-22.Maximum Frequency vs. VCC
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe operating area
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32.4.3 Current Consumption
Table 32-91. Current Consumption for Active Mode and Sleep Modes
Notes: 1. All power reduction registers set including FPRM and EPRM.
2. All power reduction registers set without FPRM and EPRM.
3. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 60
µA
VCC = 3.0V 140
1MHz, Ext. Clk
VCC = 1.8V 245
VCC = 3.0V 550
2MHz, Ext. Clk
VCC = 1.8V 440 700
VCC = 3.0V
0.9 1.5
mA
32MHz, Ext. Clk 9.0 15
Idle power
consumption (2)
32kHz, Ext. Clk
VCC = 1.8V 3.0
µA
VCC = 3.0V 3.5
1MHz, Ext. Clk
VCC = 1.8V 55
VCC = 3.0V 110
2MHz, Ext. Clk
VCC = 1.8V 105 350
VCC = 3.0V
215 650
32MHz, Ext. Clk 3.4 8.0 mA
Power-down power
consumption
T=25°C
VCC = 3.0V
0.1 1.0
µA
T=85°C 3.5 6.0
T = 105°C 10 15
WDT and sampled BOD enabled, T = 25°C
VCC = 3.0V
1.5 2.0
WDT and sampled BOD enabled, T = 85°C 5.8 10
WDT and sampled BOD enabled, T= 105°C 12 20
Power-save power
consumption (3)
RTC from ULP clock, WDT and sampled
BOD enabled, T = 25°C
VCC = 1.8V 1.3
VCC = 3.0V 1.4
RTC from 1.024kHz low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.7 2.0
VCC = 3.0V 0.8 2.0
RTC from low power 32.768kHz TOSC,
T=25°C
VCC = 1.8V 0.9 3.0
VCC = 3.0V 1.1 3.0
Reset power consumption Current through RESET pin substracted VCC = 3.0V 170
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Table 32-92. Current Consumption for Modules and Peripherals
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition (1) Min. Typ. Max. Units
ICC
ULP oscillator 0.9
µA
32.768kHz int. oscillator 25
2MHz int. oscillator
78
DFLL enabled with 32.768kHz int. osc. as reference 110
32MHz int. oscillator
250
DFLL enabled with 32.768kHz int. osc. as reference 440
PLL 20× multiplication factor,
32MHz int. osc. DIV4 as reference 310
Watchdog timer 1.0
BOD
Continuous mode 132
Sampled mode, includes ULP oscillator 1.4
Internal 1.0V reference 185
Temperature sensor 182
ADC
16ksps
VREF = Ext. ref.
1.12
mA
CURRLIMIT = LOW 1.01
CURRLIMIT = MEDIUM 0.9
CURRLIMIT = HIGH 0.8
75ksps
VREF = Ext. ref. CURRLIMIT = LOW 1.7
300ksps, VREF = Ext. ref. 3.1
USART Rx and Tx enabled, 9600 BAUD 9.5 µA
Flash memory and EEPROM programming 10 mA
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32.4.4 Wake-up Time from Sleep Modes
Table 32-93. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-23. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-23.Wake-up Time Definition
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from idle,
standby, and extended standby
mode
External 2MHz clock 2.0
µs
32.768kHz internal oscillator 125
2MHz internal oscillator 2.0
32MHz internal oscillator 0.2
Wake-up time from power-save
and power-down mode
External 2MHz clock 4.6
32.768kHz internal oscillator 330
2MHz internal oscillator 9.5
32MHz internal oscillator 5.6
Wakeup request
Clock output
Wakeup time
125
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32.4.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-94. I/O Pin Characteristics
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/ IOL (2) I/O pin source/sink current -15 15 mA
VIH High level input voltage
VCC = 2.4 - 3.6V 0.7 * VCC VCC + 0.5
V
VCC = 1.6 - 2.4V 0.8 * VCC VCC + 0.5
VIL Low level input voltage
VCC = 2.4 - 3.6V -0.5 0.3 * VCC
VCC = 1.6 - 2.4V -0.5 0.2 * VCC
VOH High level output voltage
VCC = 3.3V IOH = -4mA 2.6 2.9
VCC = 3.0V IOH = -3mA 2.1 2.6
VCC = 1.8V IOH = -1mA 1.4 1.6
VOL Low level output voltage
VCC = 3.3V IOL = 8mA 0.4 0.76
VCC = 3.0V IOL = 5mA 0.3 0.64
VCC = 1.8V IOL = 3mA 0.2 0.46
IIN Input leakage current I/O pin T = 25°C <0.01 1.0 µA
RPPull/buss keeper resistor 25 k
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32.4.6 ADC Characteristics
Table 32-95. Power Supply, Reference, and Input Range
Table 32-96. Clock and Timing
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC - 0.3 VCC + 0.3
V
VREF Reference voltage 1AVCC - 0.6
Rin Input resistance Switched 4.5 k
Cin Input capacitance Switched 5pF
RAREF Reference input resistance (leakage only) >10 M
CAREF Reference input capacitance Static load 7pF
Vin
Input range 0 VREF
VConversion range Differential mode, Vinp - Vinn -VREF VREF
Conversion range Single ended unsigned mode, Vinp -V VREF - V
VFixed offset voltage 200 lsb
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC clock frequency
Maximum is 1/4 of peripheral clock frequency 100 1800
kHz
Measuring internal signals 100 125
fClkADC Sample rate 16 300
ksps
fADC Sample rate
Current limitation (CURRLIMIT) off 16 300
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time Configurable in steps of 1/2 ClkADC cycles up
to 32 ClkADC cycles 0.28 320 µs
Conversion time (latency) (RES+2)/2 + 1 + GAIN
RES (Resolution) = 8 or 12, GAIN = 0 to 3 5.5 10
ClkADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
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Table 32-97. Accuracy Characteristics
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset, and gain error numbers are valid under the condition that external VREF is used.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 812 12
BitsSingle ended signed 711 11
Single ended unsigned 812 12
INL (1) Integral non-linearity
Differential mode
16ksps, VREF = 3V 0.5 1
lsb
16ksps, all VREF 0.8 2
300ksps, VREF = 3V 0.6 1
300ksps, all VREF 1 2
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.5 1
16ksps, all VREF 1.3 2
DNL (1) Differential non-linearity
Differential mode
16ksps, VREF = 3V 0.3 1
16ksps, all VREF 0.5 1
300ksps, VREF = 3V 0.3 1
300ksps, all VREF 0.5 1
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.6 1
16ksps, All VREF 0.6 1
Offset error Differential mode
300ksps, VREF = 3V -7 mV
Temperature drift, VREF = 3V 0.01 mV/K
Operating voltage drift 0.16 mV/V
Gain error Differential mode
External reference -5
mV
AVCC/1.6 -5
AVCC/2.0 -6
Bandgap ±10
Temperature drift 0.02 mV/K
Operating voltage drift 2mV/V
Gain error Single ended
unsigned mode
External reference -8
mV
AVCC/1.6 -8
AVCC/2.0 -8
Bandgap ±10
Temperature drift 0.03 mV/K
Operating voltage drift 2mV/V
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Table 32-98. Gain Stage Characteristics
32.4.7 Analog Comparator Characteristics
Table 32-99. Analog Comparator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 k
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0AVCC - 0.6 V
Propagation delay ADC conversion rate 1/2 1 3 ClkADC cycles
Clock frequency Same as ADC 100 1800 kHz
Gain error
0.5× gain, normal mode -1
%
1× gain, normal mode -1
8× gain, normal mode -1
64× gain, normal mode 5
Offset error, input referred
0.5× gain, normal mode 10
mV
1× gain, normal mode 5
8× gain, normal mode -20
64× gain, normal mode -126
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input offset voltage 10 mV
Ilk Input leakage current <10 50 nA
Input voltage range -0.1 AVCC V
AC startup time 50 µs
Vhys1 Hysteresis, none VCC = 1.6V - 3.6V 0
mVVhys2 Hysteresis, small VCC = 1.6V - 3.6V 15
Vhys3 Hysteresis, large VCC = 1.6V - 3.6V 30
tdelay Propagation delay
VCC = 3.0V, T = 85°C 20 40
ns
VCC = 3.0V 17
64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb
Current source accuracy after calibration 5 %
Current source calibration range Single mode 4 6 µA
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32.4.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-100. Bandgap and Internal 1.0V Reference Characteristics
32.4.9 Brownout Detection Characteristics
Table 32-101.Brownout Detection Characteristics (1)
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.4.10 External Reset Characteristics
Table 32-102.External Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1
V
INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1.0 1.01
Variation over voltage and temperature Calibrated at T = 85°C 1 %
Symbol Parameter (BOD level 0 at 85°C) Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.40 1.60 1.70
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 1000 90 ns
VRST Reset threshold voltage
VCC = 2.7 - 3.6V 0.45 * VCC V
VCC = 1.6 - 2.7V 0.45 * VCC
RRST Reset pin pull-up resistor 25 k
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32.4.11 Power-on Reset Characteristics
Table 32-103.Power-on Reset Characteristics
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
32.4.12 Flash and EEPROM Memory Characteristics
Table 32-104.Endurance and Data Retention
Table 32-105. Programming Time
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
VVCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip erase (2) 192KB flash, EEPROM 90
ms
Application erase Section erase 6
Flash
Page erase 4
Page write 4
Atomic page erase and write 8
EEPROM
Page erase 4
Page write 4
Atomic page erase and write 8
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32.4.13 Clock and Oscillator Characteristics
32.4.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-106. 32.768kHz Internal Oscillator Characteristics
32.4.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-107. 2MHz Internal Oscillator Characteristics
32.4.13.3 Calibrated 32MHz Internal Oscillator Characteristics
Table 32-108. 32MHz Internal Oscillator Characteristics
32.4.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-109. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -0.5 0.5
%
User calibration accuracy -0.5 0.5
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.0 2.2
MHz
Factory calibrated frequency 2.0
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration stepsize 0.18
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 32 55
MHz
Factory calibrated frequency 32
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration step size 0.19
Symbol Parameter Condition Min. Typ. Max. Units
Factory calibrated frequency 32 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -12 12
%
Accuracy -30 30
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32.4.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-110. Internal PLL Characteristics
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.4.13.6 External Clock Characteristics
Figure 32-24. External Clock Drive Waveform
Table 32-111.External Clock used as System Clock without Prescaling
Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol Parameter Condition Min. Typ. Max. Units
fIN Input frequency Output frequency must be within fOUT 0.4 64
MHz
fOUT Output frequency (1) VCC = 1.6 - 1.8V 20 48
VCC = 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCK Change in period from one clock cycle to the next 10 %
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Table 32-112.External Clock with Prescaler (1) for System Clock
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.4.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-113. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 0
ns
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Long term jitter
XOSCPWR=0
FRQRANGE=0 0
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Frequency error
XOSCPWR=0
FRQRANGE=0 0.03
%
FRQRANGE=1 0.03
FRQRANGE=2 or 3 0.03
XOSCPWR=1 0.003
Duty cycle
XOSCPWR=0
FRQRANGE=0 50
FRQRANGE=1 50
FRQRANGE=2 or 3 50
XOSCPWR=1 50
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RQNegative impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator, CL=100pF 44k
1MHz crystal, CL=20pF 67k
2MHz crystal, CL=20pF 67k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 82k
8MHz crystal 1500
9MHz crystal 1500
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 2700
9MHz crystal 2700
12MHz crystal 1000
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 3600
12MHz crystal 1300
16MHz crystal 590
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 390
12MHz crystal 50
16MHz crystal 10
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 1500
12MHz crystal 650
16MHz crystal 270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 1000
16MHz crystal 440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 1300
16MHz crystal 590
ESR SF = safety factor
min
(RQ)/
SF
k
Start-up time
XOSCPWR=0,
FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0
ms
XOSCPWR=0,
FRQRANGE=1 2MHz resonator, CL=20pF 2.6
XOSCPWR=0,
FRQRANGE=2 8MHz resonator, CL=20pF 0.8
XOSCPWR=0,
FRQRANGE=3 12MHz resonator, CL=20pF 1.0
XOSCPWR=1,
FRQRANGE=3 16MHz resonator, CL=20pF 1.4
Symbol Parameter Condition Min. Typ. Max. Units
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Notes: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.4.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-114. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Note: See Figure 32-25 for definition.
Figure 32-25. TOSC Input Capacitance
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
CXTAL1
Parasitic capacitance
XTAL1 pin 5.9
pF
CXTAL2
Parasitic capacitance
XTAL2 pin 8.3
CLOAD Parasitic capacitance load 3.5
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kCrystal load capacitance 9.0pF 35
Crystal load capacitance 12pF 28
CTOSC1 Parasitic capacitance TOSC1 pin 3.5
pF
CTOSC2 Parasitic capacitance TOSC2 pin 3.5
Recommended safety factor Capacitance load matched to crystal specification 3
Symbol Parameter Condition Min. Typ. Max. Units
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768 kHz crystal
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32.4.14 SPI Characteristics
Figure 32-26. SPI Timing Requirements in Master Mode
Figure 32-27.SPI Timing Requirements in Slave Mode
MSB LSB
BSLBSM
tMOS
tMIS tMIH
tSCKW
tSCK
tMOH tMOH
tSCKF
tSCKR
tSCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
tSIS tSIH
tSSCKW
tSSCKW
tSSCK
tSSH
tSOSSH
tSCKR tSCKF
tSOS
tSSS
tSOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 32-115. SPI Timing Characteristics and Requirements
32.4.15 Two-wire Interface Characteristics
Table 32-116 on page 138 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel
AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 32-28.
Figure 32-28. Two-wire Interface Bus Timing
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK period Master (See Table 20-3 in
XMEGA D manual)
ns
tSCKW SCK high/low width Master 0.5 * SCK
tSCKR SCK rise time Master 2.7
tSCKF SCK fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5 * SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4 * t ClkPER
tSSCKW SCK high/low width Slave 2 * t ClkPER
tSSCKR SCK rise time Slave 1600
tSSCKF SCK fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tClk
PER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
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Table 32-116. Two-wire Interface Characteristics
Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input high voltage 0.7VCC VCC + 0.5
V
VIL Input low voltage -0.5 0.3VCC
Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)
VOL Output low voltage 3mA, sink current 00.4
trRise time for both SDA and SCL 20 + 0.1Cb (1)(2) 300
nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20 + 0.1Cb (1)(2) 250
tSP Spikes suppressed by input filter 050
IIInput current for each I/O pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O pin 10 pF
fSCL SCL clock frequency fPER (3) > max(10fSCL, 250kHz) 0400 kHz
RPValue of pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold time (repeated) START condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low period of SCL clock
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
tHIGH High period of SCL clock
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz 4.7
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL 100kHz 250
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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32.5 Atmel ATxmega256D3
32.5.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-117 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 32-117. Absolute Maximum Ratings
32.5.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-118 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-118. General Operating Conditions
Table 32-119. Operating Voltage and Frequency
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-29 on page 140 the frequency vs. VCC
curve is linear between 1.8V < VCC <2.7V.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage -0.3 4 V
IVCC Current into a VCC pin 200
mA
IGND Current out of a Gnd pin 200
VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC + 0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150
°C
TjJunction temperature 150
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage 1.60 3.6
V
AVCC Analog supply voltage 1.60 3.6
TATemperature range -40 85
°C
TjJunction temperature -40 105
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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Figure 32-29. Maximum Frequency vs. VCC
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe operating area
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32.5.3 Current Consumption
Table 32-120. Current Consumption for Active Mode and Sleep Modes
Notes: 1. All power reduction registers set including FPRM and EPRM.
2. All power reduction registers set without FPRM and EPRM.
3. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 60
µA
VCC = 3.0V 140
1MHz, Ext. Clk
VCC = 1.8V 245
VCC = 3.0V 550
2MHz, Ext. Clk
VCC = 1.8V 440 700
VCC = 3.0V
0.9 1.5
mA
32MHz, Ext. Clk 9.0 15
Idle power
consumption (2)
32kHz, Ext. Clk
VCC = 1.8V 3.0
µA
VCC = 3.0V 3.5
1MHz, Ext. Clk
VCC = 1.8V 55
VCC = 3.0V 110
2MHz, Ext. Clk
VCC = 1.8V 105 350
VCC = 3.0V
215 650
32MHz, Ext. Clk 3.4 8.0 mA
Power-down power
consumption
T=25°C
VCC = 3.0V
0.1 1.0
µA
T=85°C 3.5 6.0
T = 105°C 10 15
WDT and sampled BOD enabled, T = 25°C
VCC = 3.0V
1.5 2.0
WDT and sampled BOD enabled, T = 85°C 5.8 10
WDT and sampled BOD enabled, T= 105°C 12 20
Power-save power
consumption (3)
RTC from ULP clock, WDT and sampled
BOD enabled, T = 25°C
VCC = 1.8V 1.3
VCC = 3.0V 1.4
RTC from 1.024kHz low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.7 2.0
VCC = 3.0V 0.8 2.0
RTC from low power 32.768kHz TOSC,
T=25°C
VCC = 1.8V 0.9 3.0
VCC = 3.0V 1.1 3.0
Reset power consumption Current through RESET pin substracted VCC = 3.0V 170
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Table 32-121. Current Consumption for Modules and Peripherals
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition (1) Min. Typ. Max. Units
ICC
ULP oscillator 0.9
µA
32.768kHz int. oscillator 25
2MHz int. oscillator
78
DFLL enabled with 32.768kHz int. osc. as reference 110
32MHz int. oscillator
250
DFLL enabled with 32.768kHz int. osc. as reference 440
PLL 20× multiplication factor,
32MHz int. osc. DIV4 as reference 310
Watchdog timer 1.0
BOD
Continuous mode 132
Sampled mode, includes ULP oscillator 1.4
Internal 1.0V reference 185
Temperature sensor 182
ADC
16ksps
VREF = Ext. ref.
1.12
mA
CURRLIMIT = LOW 1.01
CURRLIMIT = MEDIUM 0.9
CURRLIMIT = HIGH 0.8
75ksps
VREF = Ext. ref. CURRLIMIT = LOW 1.7
300ksps
VREF = Ext. ref. 3.1
USART Rx and Tx enabled, 9600 BAUD 9.5 µA
Flash memory and EEPROM programming 10 mA
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32.5.4 Wake-up Time from Sleep Modes
Table 32-122. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-30. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-30. Wake-up Time Definition
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from idle,
standby, and extended standby
mode
External 2MHz clock 2.0
µs
32.768kHz internal oscillator 125
2MHz internal oscillator 2.0
32MHz internal oscillator 0.2
Wake-up time from power-save
and power-down mode
External 2MHz clock 4.6
32.768kHz internal oscillator 330
2MHz internal oscillator 9.5
32MHz internal oscillator 5.6
Wakeup request
Clock output
Wakeup time
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32.5.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-123. I/O Pin Characteristics
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/ IOL (2) I/O pin source/sink current -15 15 mA
VIH High level input voltage
VCC = 2.4 - 3.6V 0.7 * VCC VCC + 0.5
V
VCC = 1.6 - 2.4V 0.8 * VCC VCC + 0.5
VIL Low level input voltage
VCC = 2.4 - 3.6V -0.5 0.3 * VCC
VCC = 1.6 - 2.4V -0.5 0.2 * VCC
VOH High level output voltage
VCC = 3.3V IOH = -4mA 2.6 2.9
VCC = 3.0V IOH = -3mA 2.1 2.6
VCC = 1.8V IOH = -1mA 1.4 1.6
VOL Low level output voltage
VCC = 3.3V IOL = 8mA 0.4 0.76
VCC = 3.0V IOL = 5mA 0.3 0.64
VCC = 1.8V IOL = 3mA 0.2 0.46
IIN Input leakage current I/O pin T = 25°C <0.01 1.0 µA
RPPull/buss keeper resistor 25 k
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32.5.6 ADC Characteristics
Table 32-124. Power Supply, Reference, and Input Range
Table 32-125. Clock and Timing
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC - 0.3 VCC + 0.3
V
VREF Reference voltage 1AVCC - 0.6
Rin Input resistance Switched 4.5 k
Cin Input capacitance Switched 5pF
RAREF Reference input resistance (leakage only) >10 M
CAREF Reference input capacitance Static load 7pF
Vin
Input range 0 VREF
VConversion range Differential mode, Vinp - Vinn -VREF VREF
Conversion range Single ended unsigned mode, Vinp -V VREF - V
VFixed offset voltage 200 lsb
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC clock frequency
Maximum is 1/4 of peripheral clock frequency 100 1800
kHz
Measuring internal signals 100 125
fClkADC Sample rate 16 300
ksps
fADC Sample rate
Current limitation (CURRLIMIT) off 16 300
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time Configurable in steps of 1/2 ClkADC cycles up
to 32 ClkADC cycles 0.28 320 µs
Conversion time (latency) (RES+2)/2 + 1 + GAIN
RES (Resolution) = 8 or 12, GAIN = 0 to 3 5.5 10
ClkADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
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Table 32-126. Accuracy Characteristics
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset, and gain error numbers are valid under the condition that external VREF is used.
Symbol Parameter Condition (2) Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 812 12
BitsSingle ended signed 711 11
Single ended unsigned 812 12
INL (1) Integral non-linearity
Differential mode
16ksps, VREF = 3V 0.5 1
lsb
16ksps, all VREF 0.8 2
300ksps, VREF = 3V 0.6 1
300ksps, all VREF 1 2
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.5 1
16ksps, all VREF 1.3 2
DNL (1) Differential non-linearity
Differential mode
16ksps, VREF = 3V 0.3 1
16ksps, all VREF 0.5 1
300ksps, VREF = 3V 0.3 1
300ksps, all VREF 0.5 1
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.6 1
16ksps, All VREF 0.6 1
Offset error Differential mode
300ksps, VREF = 3V -7 mV
Temperature drift, VREF = 3V 0.01 mV/K
Operating voltage drift 0.16 mV/V
Gain error Differential mode
External reference -5
mV
AVCC/1.6 -5
AVCC/2.0 -6
Bandgap ±10
Temperature drift 0.02 mV/K
Operating voltage drift 2mV/V
Gain error Single ended
unsigned mode
External reference -8
mV
AVCC/1.6 -8
AVCC/2.0 -8
Bandgap ±10
Temperature drift 0.03 mV/K
Operating voltage drift 2mV/V
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Table 32-127. Gain Stage Characteristics
32.5.7 Analog Comparator Characteristics
Table 32-128. Analog Comparator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 k
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0AVCC - 0.6 V
Propagation delay ADC conversion rate 1/2 1 3 ClkADC cycles
Clock frequency Same as ADC 100 1800 kHz
Gain error
0.5× gain, normal mode -1
%
1× gain, normal mode -1
8× gain, normal mode -1
64× gain, normal mode 5
Offset error, input referred
0.5× gain, normal mode 10
mV
1× gain, normal mode 5
8× gain, normal mode -20
64× gain, normal mode -126
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input offset voltage 10 mV
Ilk Input leakage current <10 50 nA
Input voltage range -0.1 AVCC V
AC startup time 50 µs
Vhys1 Hysteresis, none VCC = 1.6V - 3.6V 0
mVVhys2 Hysteresis, small VCC = 1.6V - 3.6V 15
Vhys3 Hysteresis, large VCC = 1.6V - 3.6V 30
tdelay Propagation delay
VCC = 3.0V, T = 85°C 20 40
ns
VCC = 3.0V 17
64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb
Current source accuracy after calibration 5 %
Current source calibration range Single mode 4 6 µA
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32.5.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-129. Bandgap and Internal 1.0V Reference Characteristics
32.5.9 Brownout Detection Characteristics
Table 32-130. Brownout Detection Characteristics (1)
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.5.10 External Reset Characteristics
Table 32-131. External Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1
V
INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1.0 1.01
Variation over voltage and temperature Calibrated at T = 85°C 1 %
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.40 1.60 1.70
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 1000 90 ns
VRST Reset threshold voltage
VCC = 2.7 - 3.6V 0.45 * VCC V
VCC = 1.6 - 2.7V 0.45 * VCC
RRST Reset pin pull-up resistor 25 k
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32.5.11 Power-on Reset Characteristics
Table 32-132. Power-on Reset Characteristics
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
32.5.12 Flash and EEPROM Memory Characteristics
Table 32-133. Endurance and Data Retention
Table 32-134. Programming Time
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
VVCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip erase (2) 256KB flash, EEPROM 105
ms
Application erase Section erase 6
Flash
Page erase 4
Page write 4
Atomic page erase and write 8
EEPROM
Page erase 4
Page write 4
Atomic page erase and write 8
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32.5.13 Clock and Oscillator Characteristics
32.5.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-135. 32.768kHz Internal Oscillator Characteristics
32.5.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-136. 2MHz Internal Oscillator Characteristics
32.5.13.3 Calibrated 32MHz Internal Oscillator Characteristics
Table 32-137. 32MHz Internal Oscillator Characteristics
32.5.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-138. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -0.5 0.5
%
User calibration accuracy -0.5 0.5
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.0 2.2
MHz
Factory calibrated frequency 2.0
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration stepsize 0.18
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 32 55
MHz
Factory calibrated frequency 32
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration step size 0.19
Symbol Parameter Condition Min. Typ. Max. Units
Factory calibrated frequency 32 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -12 12 %
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32.5.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-139. Internal PLL Characteristics
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.5.13.6 External Clock Characteristics
Figure 32-31.External Clock Drive Waveform
Table 32-140.External Clock used as System Clock without Prescaling
Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol Parameter Condition Min. Typ. Max. Units
fIN Input frequency Output frequency must be within fOUT 0.4 64
MHz
fOUT Output frequency (1) VCC = 1.6 - 1.8V 20 48
VCC = 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 1.8V 012
MHz
VCC = 2.7 - 3.6V 032
tCK Clock Period
VCC = 1.6 - 1.8V 83.3
ns
VCC = 2.7 - 3.6V 31.5
tCH Clock High Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCL Clock Low Time
VCC = 1.6 - 1.8V 30.0
VCC = 2.7 - 3.6V 12.5
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 10
VCC = 2.7 - 3.6V 3
tCK Change in period from one clock cycle to the next 10 %
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Table 32-141.External Clock with Prescaler (1) for System Clock
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.5.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-142. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 0
ns
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Long term jitter
XOSCPWR=0
FRQRANGE=0 0
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Frequency error
XOSCPWR=0
FRQRANGE=0 0.03
%
FRQRANGE=1 0.03
FRQRANGE=2 or 3 0.03
XOSCPWR=1 0.003
Duty cycle
XOSCPWR=0
FRQRANGE=0 50
FRQRANGE=1 50
FRQRANGE=2 or 3 50
XOSCPWR=1 50
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RQNegative impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator, CL=100pF 44k
1MHz crystal, CL=20pF 67k
2MHz crystal, CL=20pF 67k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 82k
8MHz crystal 1500
9MHz crystal 1500
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 2700
9MHz crystal 2700
12MHz crystal 1000
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 3600
12MHz crystal 1300
16MHz crystal 590
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 390
12MHz crystal 50
16MHz crystal 10
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 1500
12MHz crystal 650
16MHz crystal 270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 1000
16MHz crystal 440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 1300
16MHz crystal 590
ESR SF = safety factor min(RQ)/SF k
Start-up time
XOSCPWR=0,
FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0
ms
XOSCPWR=0,
FRQRANGE=1 2MHz resonator, CL=20pF 2.6
XOSCPWR=0,
FRQRANGE=2 8MHz resonator, CL=20pF 0.8
XOSCPWR=0,
FRQRANGE=3 12MHz resonator, CL=20pF 1.0
XOSCPWR=1,
FRQRANGE=3 16MHz resonator, CL=20pF 1.4
Symbol Parameter Condition Min. Typ. Max. Units
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Notes: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.5.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-143. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Note: See Figure 32-32 for definition.
Figure 32-32. TOSC Input Capacitance
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
CXTAL1
Parasitic capacitance
XTAL1 pin 5.9
pF
CXTAL2
Parasitic capacitance
XTAL2 pin 8.3
CLOAD Parasitic capacitance load 3.5
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kCrystal load capacitance 9.0pF 35
Crystal load capacitance 12pF 28
CTOSC1 Parasitic capacitance TOSC1 pin 3.5
pF
CTOSC2 Parasitic capacitance TOSC2 pin 3.5
Recommended safety factor Capacitance load matched to crystal
specification 3
Symbol Parameter Condition Min. Typ. Max. Units
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768 kHz crystal
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32.5.14 SPI Characteristics
Figure 32-33. SPI Timing Requirements in Master Mode
Figure 32-34.SPI Timing Requirements in Slave Mode
MSB LSB
BSLBSM
tMOS
tMIS tMIH
tSCKW
tSCK
tMOH tMOH
tSCKF
tSCKR
tSCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
tSIS tSIH
tSSCKW
tSSCKW
tSSCK
tSSH
tSOSSH
tSCKR tSCKF
tSOS
tSSS
tSOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
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Table 32-144. SPI Timing Characteristics and Requirements
32.5.15 Two-wire Interface Characteristics
Table 32-145 on page 157 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel
AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 32-35.
Figure 32-35. Two-wire Interface Bus Timing
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK period Master (See Table 20-3 in
XMEGA D manual)
ns
tSCKW SCK high/low width Master 0.5 * SCK
tSCKR SCK rise time Master 2.7
tSCKF SCK fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5 * SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4 * t ClkPER
tSSCKW SCK high/low width Slave 2 * t ClkPER
tSSCKR SCK rise time Slave 1600
tSSCKF SCK fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tClk
PER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
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Table 32-145. Two-wire Interface Characteristics
Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.69
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input high voltage 0.7VCC VCC + 0.5
V
VIL Input low voltage -0.5 0.3VCC
Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)
VOL Output low voltage 3mA, sink current 00.4
trRise time for both SDA and SCL 20 + 0.1Cb (1)(2) 300
nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20 + 0.1Cb (1)(2) 250
tSP Spikes suppressed by input filter 050
IIInput current for each I/O pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O pin 10 pF
fSCL SCL clock frequency fPER (3) > max(10fSCL, 250kHz) 0400 kHz
RPValue of pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold time (repeated) START condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low period of SCL clock
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
tHIGH High period of SCL clock
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz 4.7
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL 100kHz 250
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
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32.6 Atmel ATxmega384D3
32.6.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 32-146 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 32-146. Absolute Maximum Ratings
32.6.2 General Operating Ratings
The device must operate within the ratings listed in Table 32-147 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-147. General Operating Conditions
Table 32-148. Operating Voltage and Frequency
The maximum CPU clock frequency depends on VCC. As shown in Figure 32-36 on page 159 the frequency vs. VCC
curve is linear between 1.8V < VCC <2.7V.
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage -0.3 4 V
IVCC Current into a VCC pin 200
mA
IGND Current out of a Gnd pin 200
VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC + 0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150
°C
TjJunction temperature 150
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage 1.60 3.6
V
AVCC Analog supply voltage 1.60 3.6
TATemperature range -40 85
°C
TjJunction temperature -40 105
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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Figure 32-36. Maximum Frequency vs. VCC
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe operating area
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32.6.3 Current Consumption
Table 32-149. Current Consumption for Active Mode and Sleep Modes
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 150
µA
VCC = 3.0V 320
1MHz, Ext. Clk
VCC = 1.8V 410
VCC = 3.0V 830
2MHz, Ext. Clk
VCC = 1.8V 660 800
VCC = 3.0V
1.3 1.8
mA
32MHz, Ext. Clk 10 15
Idle power
consumption (1)
32kHz, Ext. Clk
VCC = 1.8V 4
µA
VCC = 3.0V 5
1MHz, Ext. Clk
VCC = 1.8V 50
VCC = 3.0V 100
2MHz, Ext. Clk
VCC = 1.8V 100 350
VCC = 3.0V
200 600
32MHz, Ext. Clk 3.3 7mA
Power-down power
consumption
T=25°C
VCC = 3.0V
0.2 1.0
µA
T=85°C 3.5 6.0
T = 105°C 15 20
WDT and sampled BOD enabled, T = 25°C
VCC = 3.0V
1.5 2.0
WDT and sampled BOD enabled, T = 85°C 6.0 10
WDT and sampled BOD enabled, T= 105°C 16 27
Power-save power
consumption (2)
RTC from ULP clock, WDT and sampled
BOD enabled, T = 25°C
VCC = 1.8V 1.4
VCC = 3.0V 1.5
RTC from 1.024kHz low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.7 2
VCC = 3.0V 0.8 2
RTC from low power 32.768kHz TOSC,
T=25°C
VCC = 1.8V 0.9 3
VCC = 3.0V 1.1 3
Reset power consumption Current through RESET pin substracted VCC = 3.0V 300
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Table 32-150. Current Consumption for Modules and Peripherals
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition (1) Min. Typ. Max. Units
ICC
ULP oscillator 0.93
µA
32.768kHz int. oscillator 27
2MHz int. oscillator
85
DFLL enabled with 32.768kHz int. osc. as reference 115
32MHz int. oscillator
240
DFLL enabled with 32.768kHz int. osc. as reference 430
PLL 20× multiplication factor, 32MHz int. osc. DIV4 as reference 300
Watchdog timer 1.0
BOD
Continuous mode 140
Sampled mode, includes ULP oscillator 1.3
Internal 1.0V reference 220
Temperature sensor 215
ADC
16ksps, VREF = Ext. ref.
1.12
mA
CURRLIMIT = LOW 1.01
CURRLIMIT = MEDIUM 0.9
CURRLIMIT = HIGH 0.8
75ksps, VREF = Ext. ref. CURRLIMIT = LOW 1.7
300ksps, VREF = Ext. ref. 3.1
USART Rx and Tx enabled, 9600 BAUD 9.5 µA
Flash memory and EEPROM programming 4.0 mA
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32.6.4 Wake-up Time from Sleep Modes
Table 32-151. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-37. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 32-37. Wake-up Time Definition
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from idle,
standby, and extended
standby mode
External 2MHz clock 2.0
µs
32.768kHz internal oscillator 130
2MHz internal oscillator 2.0
32MHz internal oscillator 0.2
Wake-up time from
power-save and power-
down mode
External 2MHz clock 4.5
32.768kHz internal oscillator 320
2MHz internal oscillator 9.0
32MHz internal oscillator 5.0
Wakeup request
Clock output
Wakeup time
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32.6.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 32-152. I/O Pin Characteristics
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, and PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA.
32.6.6 ADC Characteristics
Table 32-153. Power Supply, Reference, and Input Range
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/ IOL (2) I/O pin source/sink current -15 15 mA
VIH High level input voltage
VCC = 2.4 - 3.6V 0.7 * VCC VCC + 0.5
V
VCC = 1.6 - 2.4V 0.8 * VCC VCC + 0.5
VIL Low level input voltage
VCC = 2.4 - 3.6V -0.5 0.3 * VCC
VCC = 1.6 - 2.4V -0.5 0.2 * VCC
VOH High level output voltage
VCC = 3.3V IOH = -4mA 2.6 2.9
VCC = 3.0V IOH = -3mA 2.1 2.6
VCC = 1.8V IOH = -1mA 1.4 1.6
VOL Low level output voltage
VCC = 3.3V IOL = 8mA 0.4 0.76
VCC = 3.0V IOL = 5mA 0.3 0.64
VCC = 1.8V IOL = 3mA 0.2 0.46
IIN Input leakage current I/O pin T = 25°C <0.01 1µA
RPPull/buss keeper resistor 25 k
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC - 0.3 VCC + 0.3
V
VREF Reference voltage 1AVCC - 0.6
Rin Input resistance Switched 4.5 k
Cin Input capacitance Switched 5pF
RAREF Reference input resistance (leakage only) >10 M
CAREF Reference input capacitance Static load 7pF
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Table 32-154. Clock and Timing
Vin Input range 0 VREF
VConversion range Differential mode, Vinp - Vinn -VREF VREF
Conversion range Single ended unsigned mode, Vinp -V VREF - V
VFixed offset voltage 200 lsb
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC clock frequency
Maximum is 1/4 of peripheral clock frequency 100 1800
kHz
Measuring internal signals 100 125
fClkADC Sample rate 16 300
ksps
fADC Sample rate
Current limitation (CURRLIMIT) off 16 300
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time Configurable in steps of 1/2 ClkADC cycles up
to 32 ClkADC cycles 0.28 320 µs
Conversion time (latency) (RES+1)/2 + GAIN
RES (Resolution) = 8 or 12, GAIN = 0 to 3 5.5 10
ClkADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
Symbol Parameter Condition Min. Typ. Max. Units
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Table 32-155. Accuracy Characteristics
Notes: 1. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
2. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
Symbol Parameter Condition (1) Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 812 12
BitsSingle ended signed 711 11
Single ended unsigned 812 12
INL (2) Integral non-linearity
Differential mode
16ksps, VREF = 3V 0.5 1
lsb
16ksps, all VREF 0.8 2
300ksps, VREF = 3V 0.6 1
300ksps, all VREF 1 2
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.5 1
16ksps, all VREF 1.3 2
DNL (2) Differential non-linearity
Differential mode
16ksps, VREF = 3V 0.3 1
16ksps, all VREF 0.5 1
300ksps, VREF = 3V 0.35 1
300ksps, all VREF 0.5 1
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.6 1
16ksps, all VREF 0.6 1
Offset error Differential mode
300ksps, VREF = 3V -7 mV
Temperature drift, VREF = 3V 0.01 mV/K
Operating voltage drift 0.16 mV/V
Gain error Differential mode
External reference -5
mV
AVCC/1.6 -5
AVCC/2.0 -6
Bandgap ±10
Temperature drift 0.02 mV/K
Operating voltage drift 2mV/V
Gain error Single ended
unsigned mode
External reference -8
mV
AVCC/1.6 -8
AVCC/2.0 -8
Bandgap ±10
Temperature drift 0.03 mV/K
Operating voltage drift 2mV/V
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Table 32-156. Gain Stage Characteristics
32.6.7 Analog Comparator Characteristics
Table 32-157. Analog Comparator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 k
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0AVCC - 0.6 V
Propagation delay ADC conversion rate 1/2 1 3 ClkADC cycles
Clock rate Same as ADC 100 1800 kHz
Gain error
0.5x gain, normal mode -1
%
1x gain, normal mode -1
8x gain, normal mode -1
64x gain, normal mode 5
Offset error, input referred
0.5x gain, normal mode 10
mV
1x gain, normal mode 5
8x gain, normal mode -20
64x gain, normal mode -126
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input offset voltage 10 mV
Ilk Input leakage current <10 50 nA
Input voltage range -0.1 AVCC V
AC startup time 50 µs
Vhys1 Hysteresis, none VCC = 1.6V - 3.6V 0
mVVhys2 Hysteresis, small VCC = 1.6V - 3.6V 15
Vhys3 Hysteresis, large VCC = 1.6V - 3.6V 30
tdelay Propagation delay
VCC = 3.0V, T = 85°C 20 90
ns
VCC = 3.0V, T = 85°C 17
64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb
Current source accuracy after calibration 5 %
Current source calibration range 4 6 µA
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32.6.8 Bandgap and Internal 1.0V Reference Characteristics
Table 32-158. Bandgap and Internal 1.0V Reference Characteristics
32.6.9 Brownout Detection Characteristics
Table 32-159. Brownout Detection Characteristics (1)
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
32.6.10 External Reset Characteristics
Table 32-160. External Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1
V
INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 11.01
Variation over voltage and temperature Calibrated at T = 85°C 2 %
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.60 1.62 1.72
V
BOD level 1 falling VCC 1.9
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.0 %
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 1000 90 ns
VRST Reset threshold voltage
VCC = 2.7 - 3.6V 0.45 * VCC V
VCC = 1.6 - 2.7V 0.42 * VCC
RRST Reset pin pull-up resistor 25 k
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32.6.11 Power-on Reset Characteristics
Table 32-161. Power-on Reset Characteristics
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
32.6.12 Flash and EEPROM Memory Characteristics
Table 32-162. Endurance and Data Retention
Table 32-163. Programming Time
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
VVCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
Symbol Parameter Condition Min. Typ. (1) Max. Units
Chip erase (2) 384KB Flash, EEPROM 130
ms
Application erase Section erase 6
Flash
Page erase 6
Page write 6
Atomic page erase and write 12
EEPROM
Page erase 6
Page write 6
Atomic page erase and write 12
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32.6.13 Clock and Oscillator Characteristics
32.6.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
Table 32-164. 32.768kHz Internal Oscillator Characteristics
32.6.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
Table 32-165. 2MHz Internal Oscillator Characteristics
32.6.13.3 Calibrated 32MHz Internal Oscillator Characteristics
Table 32-166. 32MHz Internal Oscillator Characteristics
32.6.13.4 32kHz Internal ULP Oscillator Characteristics
Table 32-167. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -0.5 0.5
%
User calibration accuracy -0.5 0.5
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.2
MHz
Factory calibrated frequency 2.0
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration stepsize 0.23
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 32 35
MHz
Factory calibrated frequency 32
Factory calibration accuracy T = 85C, VCC = 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration step size 0.24
Symbol Parameter Condition Min. Typ. Max. Units
Factory calibrated frequency 26 kHz
Factory calibration accuracy T = 85°C, VCC = 3.0V -12 12
%
Accuracy -30 30
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32.6.13.5 Internal Phase Locked Loop (PLL) Characteristics
Table 32-168. Internal PLL Characteristics
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.6.13.6 External Clock Characteristics
Figure 32-38. External Clock Drive Waveform
Table 32-169.External Clock used as System Clock without Prescaling
Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol Parameter Condition Min. Typ. Max. Units
fIN Input frequency Output frequency must be within fOUT 0.4 64
MHz
fOUT Output frequency (1) VCC = 1.6 - 1.8V 20 48
VCC = 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (1) VCC = 1.6 - 012 MHz
VCC = 2.7 - 032
tCK Clock Period VCC = 1.6 - 83.3
ns
VCC = 2.7 - 31.5
tCH Clock High Time VCC = 1.6 - 30.0
VCC = 2.7 - 12.5
tCL Clock Low Time VCC = 1.6 - 30.0
VCC = 2.7 - 12.5
tCR Rise Time (for maximum frequency) VCC = 1.6 - 10
VCC = 2.7 - 3
tCF Fall Time (for maximum frequency) VCC = 1.6 - 10
VCC = 2.7 - 3
tCK Change in period from one clock cycle to the next 10 %
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Table 32-170.External Clock with Prescaler (1) for System Clock
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
32.6.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 32-171. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock Frequency (2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock Period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7
tCH Clock High Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCL Clock Low Time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
tCR Rise Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCF Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V 1.5
VCC = 2.7 - 3.6V 1.0
tCK Change in period from one clock cycle to the next 10 %
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 0
ns
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Long term jitter
XOSCPWR=0
FRQRANGE=0 0
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Frequency error
XOSCPWR=0
FRQRANGE=0 0.03
%
FRQRANGE=1 0.03
FRQRANGE=2 or 3 0.03
XOSCPWR=1 0.003
Duty cycle
XOSCPWR=0
FRQRANGE=0 50
%
FRQRANGE=1 50
FRQRANGE=2 or 3 50
XOSCPWR=1 50
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RQNegative impedance (1)
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 44k
1MHz crystal, CL=20pF 67k
2MHz crystal, CL=20pF 67k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 82k
8MHz crystal 1500
9MHz crystal 1500
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 2700
9MHz crystal 2700
12MHz crystal 1000
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 3600
12MHz crystal 1300
16MHz crystal 590
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 390
12MHz crystal 50
16MHz crystal 10
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 1500
12MHz crystal 650
16MHz crystal 270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 1000
16MHz crystal 440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 1300
16MHz crystal 590
ESR SF = safety factor min(RQ)/SF k
Start-up time
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 1.0
ms
XOSCPWR=0,
FRQRANGE=1 2MHz crystal, CL=20pF 2.6
XOSCPWR=0,
FRQRANGE=2 8MHz crystal, CL=20pF 0.8
XOSCPWR=0,
FRQRANGE=3 12MHz crystal, CL=20pF 1.0
XOSCPWR=1,
FRQRANGE=3 16MHz crystal, CL=20pF 1.4
Symbol Parameter Condition Min. Typ. Max. Units
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Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
32.6.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
Table 32-172. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Note: See Figure 32-39 on page 173 for definition.
Figure 32-39. TOSC Input Capacitance
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
CXTAL1
Parasitic capacitance
XTAL1 pin 5.9
pF
CXTAL2
Parasitic capacitance
XTAL2 pin 8.3
CLOAD Parasitic capacitance load 3.5
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
kCrystal load capacitance 9.0pF 35
Crystal load capacitance 12pF 28
CTOSC1 Parasitic capacitance TOSC1 pin 3.5
pF
CTOSC2 Parasitic capacitance TOSC2 pin 3.5
Recommended safety factor Capacitance load matched to crystal
specification 3
Symbol Parameter Condition Min. Typ. Max. Units
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768 kHz crystal
174
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32.6.14 SPI Characteristics
Figure 32-40. SPI Timing Requirements in Master Mode
Figure 32-41.SPI Timing Requirements in Slave Mode
MSB LSB
BSLBSM
tMOS
tMIS tMIH
tSCKW
tSCK
tMOH tMOH
tSCKF
tSCKR
tSCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
tSIS tSIH
tSSCKW
tSSCKW
tSSCK
tSSH
tSOSSH
tSCKR tSCKF
tSOS
tSSS
tSOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
175
XMEGA D3 [DATASHEET]
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Table 32-173. SPI Timing Characteristics and Requirements
32.6.15 Two-wire Interface Characteristics
Table 32-174 on page 176 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel
AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 32-42.
Figure 32-42. Two-wire Interface Bus Timing
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK period Master (See Table 20-3 in
XMEGA D manual)
ns
tSCKW SCK high/low width Master 0.5 * SCK
tSCKR SCK rise time Master 2.7
tSCKF SCK fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5 * SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4 * t ClkPER
tSSCKW SCK high/low width Slave 2 * t ClkPER
tSSCKR SCK rise time Slave 1600
tSSCKF SCK fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tClk
PER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
176
XMEGA D3 [DATASHEET]
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Table 32-174. Two-wire Interface Characteristics
Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input high voltage 0.7VCC VCC + 0.5
V
VIL Input low voltage -0.5 0.3VCC
Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)
VOL Output low voltage 3mA, sink current 00.4
trRise time for both SDA and SCL 20 + 0.1Cb (1)(2) 300
nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20 + 0.1Cb (1)(2) 250
tSP Spikes suppressed by input filter 050
IIInput current for each I/O pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O pin 10 pF
fSCL SCL clock frequency fPER (3) > max(10fSCL, 250kHz) 0400 kHz
RPValue of pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold time (repeated) START condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low period of SCL clock
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
tHIGH High period of SCL clock
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz 4.7
fSCL > 100kHz 0.6
tHD;DAT Data hold time
fSCL 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL 100kHz 250
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
177
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33. Typical Characteristics
33.1 Atmel ATxmega32D3
33.1.1 Current Consumption
33.1.1.1 Active Mode Supply Current
Figure 33-1. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
Figure 33-2. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
100
200
300
400
500
600
700
800
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
IccV [
µA
]
Frequency [MHz]
3.6 V
3.3 V
3.0 V
2.7 V
0
2
4
6
8
10
12
0 4 8 12 16 20 24 28 32
Icc [
mA
]
Frequency [MHz]
1.6 V
1.8 V
2.2 V
178
XMEGA D3 [DATASHEET]
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Figure 33-3. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
Figure 33-4. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
105 °C
85 °C
25 °C
-40 °C
50
75
100
125
150
175
200
225
250
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
105 °C
85 °C
25 °C
-40°C
200
300
400
500
600
700
800
900
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
179
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-5. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
Figure 33-6. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
105 °C
85 °C
25 °C
-40 °C
400
500
600
700
800
900
1000
1100
1200
1300
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [mA]
V
CC
[V]
180
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-7. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
33.1.1.2 Idle Mode Supply Current
Figure 33-8. Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
105 °C
85 °C
25 °C
-40 °C
6.0
7.0
8.0
9.0
10.0
11.0
12.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
VCC [V]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
20
40
60
80
100
120
140
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Icc [µA]
Frequency[MHz]
181
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-9. Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
Figure 33-10. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
3.6 V
3.3 V
3.0 V
2.7 V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 4 8 121620242832
Icc [mA]
Frequency [MHz]
1.6 V
1.8 V
2.2 V
105°C
85 °C
25 °C
-40 °C
28
30
32
34
36
38
40
42
44
46
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
182
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-11. Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
Figure 33-12. Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
35
45
55
65
75
85
95
105
115
125
135
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
140
165
190
215
240
265
290
315
340
365
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
183
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-13. Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
Figure 33-14. Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
105 °C
85 °C
25 °C
- 40 °C
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
V
CC
[V]
184
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.1.3 Power-down Mode Supply Current
Figure 33-15. Power-down Mode Supply Current vs. VCC
All functions disabled
Figure 33-16. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
105 ° C
85 °C
25
°
C
- 40
°
C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
185
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-17. Power-down Mode Supply Current vs. Temperature
All functions disabled
Figure 33-18. Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-0.2
0.3
0.8
1.3
1.8
2.3
2.8
3.3
3.8
4.3
4.8
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Icc [µA]
Temperature [°C]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-45-35-25-15-5 5 152535455565758595105
Icc [µA]
Temperature [°C]
186
XMEGA D3 [DATASHEET]
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33.1.2 I/O Pin Characteristics
33.1.2.1 Pull-up
Figure 33-19. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
Figure 33-20. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
105 ° C
85 °C
25 °C
- 40 °C
0
10
20
30
40
50
60
70
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I [µA]
VPIN [V]
105 ° C
85 °C
25 °C
- 40 °C
0
12
24
36
48
60
72
84
96
108
120
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
I [µA]
V
PIN
[V]
187
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-21. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
33.1.2.2 Output Voltage vs. Sink/Source Current
Figure 33-22. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
105 ° C
85 °C
25 °C
- 40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
I [µA]
V
PIN
[V]
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
V
PIN
[V]
IPIN [mA]
188
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-23. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
Figure 33-24. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
105 ° C
85 °C
25 °C
- 40 °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-16-14-12-10 -8 -6 -4 -2 0
V
PIN
[V]
IPIN [mA]
105 °C
85 °C
25 °C
- 40 °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
V
PIN
[V]
IPIN [mA]
189
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-25. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
Figure 33-26. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0123456789
VPIN [V]
I
PIN
[mA]
105 ° C
105 °C
85 °C
25 °C
-40 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0246810121416
V
PIN
[V]
IPIN [mA]
190
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-27. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
33.1.2.3 Thresholds and Hysteresis
Figure 33-28. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 2 4 6 8 101214161820
V
PIN
[V]
IPIN [mA]
105 °C
85 °C
25 °C
-40 °C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
threshold
[V]
VCC [V]
191
XMEGA D3 [DATASHEET]
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Figure 33-29. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
Figure 33-30. I/O Pin Input Hysteresis vs. VCC
105 ° C
85 °C
25 °C
-40 °C
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
0.15
0.18
0.21
0.24
0.27
0.30
0.33
0.36
0.39
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
threshold
[V]
V
CC
[V]
192
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.3 ADC Characteristics
Figure 33-31. INL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
Figure 33-32. INL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Differential mode
Single -ended signed mode
Single-ended unsigned mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
INL[LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
ADC sample rate [ksps]
INL[LSB]
50 100 150 200 250 300
193
XMEGA D3 [DATASHEET]
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Figure 33-33. INL Error vs. Input Code
Figure 33-34. DNL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL[LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
DNL [LSB]
194
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-35. DNL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Figure 33-36. DNL Error vs. Input Code
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
50 100 150 200 250 300
ADC sample rate [ksps]
DNL [LSB]
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
195
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-37. Gain Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Figure 33-38. Gain Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Differential mode
Single-ended signed mode
Single-ended unsigned mode
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
1.01.21.41.61.82.02.22.42.62.83.0
V
REF
[V]
Gain error [mV]
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
-9
-8
-7
-6
-5
-4
-3
-2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC [V]
Gain error [mV]
196
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-39. Offset error vs. VREF.
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps.
Figure 33-40. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
Differential mode
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
Offset error [mV]
Differential mode
Single-ended signed mode
Single-ended unsigned
mod e
-14
-12
-10
-8
-6
-4
-2
0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Gain error [mV]
Temperature [
°
C]
197
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-41. Offset Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
33.1.4 Analog Comparator Characteristics
Figure 33-42. Analog Comparator Hysteresis vs. VCC
Small hysteresis
Differential mode
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Offset error [mV]
-40°
C
25°C
85°C
10
11
12
13
14
15
16
17
18
19
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC [V]
105°C
198
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-43. Analog Comparator Hysteresis vs. VCC
Large hysteresis
Figure 33-44. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
-40 °C
25°C
85°C
105 °C
22
24
26
28
30
32
34
36
38
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
VCC[V]
105 °C
85 °C
25 °C
-40 °C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I
CURRENTSOURCE
[µA]
CURRCALIBA[3..0]
199
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-45. Voltage Scaler INL vs. SCALEFAC
T = 25
C, VCC = 3.0V
33.1.5 Internal 1.0V Reference Characteristics
Figure 33-46. ADC Internal 1.0V Reference vs. Temperature
0.25
0.275
0.3
0.325
0.35
0.375
0.4
0.425
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INL [LSB]
SCALEFAC
25°C
3.0 V
2.7 V
1.8 V
0.975
0.980
0.985
0.990
0.995
1.000
1.005
1.010
-45-35-25-15-5 5 152535455565758595105
Bandgap Voltage [V]
Temperature [°C]
200
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.6 BOD Characteristics
Figure 33-47. BOD Thresholds vs. Temperature
BOD level = 1.6V
Figure 33-48. BOD Thresholds vs. Temperature
BOD level = 3.0V
1.615
1.616
1.617
1.618
1.619
1.620
1.621
1.622
1.623
-45-35-25-15-5 5 152535455565758595105
V
BOT
[V]
Temperature [°C]
3.039
3.042
3.045
3.048
3.051
3.054
3.057
3.060
3.063
3.066
-45-35-25-15-5 5 152535455565758595105
V
BOT
[V]
Temperature [°C]
201
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.7 External Reset Characteristics
Figure 33-49. Minimum Reset Pin Pulse Width vs. VCC
Figure 33-50. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
105 °C
85 °C
25 °C
-40 ° C
80
88
96
104
112
120
128
136
144
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
t
RST
[ns]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
0
10
20
30
40
50
60
70
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
IRESET [µA]
VRESET [V]
202
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-51. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
Figure 33-52. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
105 °C
85 °C
25 °C
- 40 °C
0
12
24
36
48
60
72
84
96
108
120
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
IRESET [µA]
VRESET [V]
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IRESET [µA]
VRESET [V]
-40 °C
85 °C
25 °C
105 °C
203
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-53. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
33.1.8 Oscillator Characteristics
33.1.8.1 Ultra Low-power Internal Oscillator
Figure 33-54. Ultra Low-power Internal Oscillator Frequency vs. Temperature
105 °C
85 °C
25 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VTHRESHOLD [V]
VCC [V]
- 40 °C
3.3 V
3.0 V
2.7 V
1.8 V
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
204
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.8.2 32.768kHz Internal Oscillator
Figure 33-55. 32.768kHz Internal Oscillator Frequency vs. Temperature
Figure 33-56. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.5
32.6
32.6
32.7
32.7
32.8
32.8
32.9
32.9
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
3.0 V
20
23
26
29
32
35
38
41
44
47
50
-4 16 36 56 76 96 116 136 156 176 196 216 236 256
Frequency [kHz]
RC32KCAL[7..0]
205
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.8.3 2MHz Internal Oscillator
Figure 33-57. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-58. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V 1.6 V
1.985
1.988
1.991
1.994
1.997
2.000
2.003
2.006
2.009
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
206
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-59. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3V
33.1.8.4 32MHz Internal Oscillator
Figure 33-60. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
105
°
C
85 °C
25 °C
-40 °C
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
0 163248648096112128
Frequency [MHz]
CALA
°
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
-45-35-25-15-5 5 152535455565758595105
Frequency[MHz]
Temperatuire [°C]
207
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-61. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
Figure 33-62. 32MHz Internal Oscillator CALA Calibration Step Size
T = -40°C, VCC = 3.0V
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.83
31.86
31.89
31.92
31.95
31.98
32.01
32.04
32.07
32.10
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
-40 °C
0.13 %
0.15 %
0.17 %
0.18 %
0.20 %
0.22 %
0.24 %
0.26 %
0.27 %
0.29 %
0.31 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
208
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-63. 32MHz Internal Oscillator CALA Calibration Step Size
T = 25°C, VCC = 3.0V
Figure 33-64. 32MHz Internal Oscillator CALA Calibration Step Size
T = 85°C, VCC = 3.0V
25 °C
0.12 %
0.14 %
0.16 %
0.18 %
0.20 %
0.22 %
0.24 %
0.26 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
85 °C
0.13 %
0.14 %
0.15 %
0.17 %
0.18 %
0.19 %
0.20 %
0.21 %
0.23 %
0.24 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
209
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-65. 32MHz Internal Oscillator CALA Calibration Step Size
T = 105°C, VCC = 3.0V
Figure 33-66. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V
105 °C
0.14 %
0.15 %
0.16 %
0.17 %
0.18 %
0.19 %
0.20 %
0.21 %
0.22 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
105 °C
85 °C
25 °C
-40 °C
20
25
30
35
40
45
50
55
60
65
70
75
0 7 14 21 28 35 42 49 56 63
Frequency [MHz]
CALB
210
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.8.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-67. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-68. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
46
47
48
49
50
51
52
53
54
55
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
47.75
47.80
47.85
47.90
47.95
48.00
48.05
48.10
48.15
48.20
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
211
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.9 Two-Wire Interface Characteristics
Figure 33-69. SDA Hold Time vs. Temperature
Figure 33-70. SDA Hold Time vs. Supply Voltage
3
2
1
0
50
100
150
200
250
300
350
400
450
500
-45-35-25-15-5 5 1525354555657585
Temperature [°C]
Hold time [ns]
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
212
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.1.10 PDI Characteristics
Figure 33-71. Maximum PDI Frequency vs. VCC
105 ° C
85 °C
25 °C
- 40 °C
6
8
10
12
14
16
18
20
22
24
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
fMAX [MHz]
VCC [V]
213
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2 Atmel ATxmega64D3
33.2.1 Current Consumption
33.2.1.1 Active Mode Supply Current
Figure 33-72. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
Figure 33-73. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
100
200
300
400
500
600
700
800
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
IccV [
µA
]
Frequency [MHz]
3.6 V
3.3 V
3.0 V
2.7 V
0
2
4
6
8
10
12
0 4 8 12 16 20 24 28 32
Icc [
mA
]
Frequency [MHz]
1.6 V
1.8 V
2.2 V
214
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-74. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
Figure 33-75. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
105 °C
85 °C
25 °C
-40 °C
50
75
100
125
150
175
200
225
250
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
105 °C
85 °C
25 °C
-40°C
200
300
400
500
600
700
800
900
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
215
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-76. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
Figure 33-77. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
105 °C
85 °C
25 °C
-40 °C
400
500
600
700
800
900
1000
1100
1200
1300
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [mA]
V
CC
[V]
216
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-78.Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
33.2.1.2 Idle Mode Supply Current
Figure 33-79.Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
105 °C
85 °C
25 °C
-40 °C
6.0
7.0
8.0
9.0
10.0
11.0
12.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
V
CC
[V]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
0
20
40
60
80
100
120
140
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Icc [µA]
Frequency[MHz]
217
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-80.Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
Figure 33-81. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
3.6 V
3.3 V
3.0 V
2.7 V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 4 8 121620242832
Icc [mA]
Frequency [MHz]
1.6 V
1.8 V
2.2 V
105°C
85 °C
25 °C
-40 °C
28
30
32
34
36
38
40
42
44
46
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
218
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-82. Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
Figure 33-83. Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
35
45
55
65
75
85
95
105
115
125
135
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
140
165
190
215
240
265
290
315
340
365
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
219
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-84. Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
Figure 33-85. Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
105 °C
85 °C
25 °C
- 40 °C
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
V
CC
[V]
220
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.1.3 Power-down Mode Supply Current
Figure 33-86. Power-down Mode Supply Current vs. VCC
All functions disabled
Figure 33-87. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
105 ° C
85 °C
25
°
C
- 40
°
C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
221
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-88. Power-down Mode Supply Current vs. Temperature
All functions disabled
Figure 33-89. Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-0.2
0.3
0.8
1.3
1.8
2.3
2.8
3.3
3.8
4.3
4.8
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Icc [µA]
Temperature [°C]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-45-35-25-15-5 5 152535455565758595105
Icc [µA]
Temperature [°C]
222
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.2 I/O Pin Characteristics
33.2.2.1 Pull-up
Figure 33-90. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
Figure 33-91. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
105 ° C
85 °C
25 °C
- 40 °C
0
10
20
30
40
50
60
70
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I [µA]
VPIN [V]
105 ° C
85 °C
25 °C
- 40 °C
0
12
24
36
48
60
72
84
96
108
120
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
I [µA]
V
PIN
[V]
223
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-92. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
33.2.2.2 Output Voltage vs. Sink/Source Current
Figure 33-93. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
105 ° C
85 °C
25 °C
- 40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
I [µA]
V
PIN
[V]
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
V
PIN
[V]
IPIN [mA]
224
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-94. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
Figure 33-95. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
105 ° C
85 °C
25 °C
- 40 °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-16-14-12-10 -8 -6 -4 -2 0
V
PIN
[V]
IPIN [mA]
105 °C
85 °C
25 °C
- 40 °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
V
PIN
[V]
IPIN [mA]
225
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-96. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
Figure 33-97. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0123456789
VPIN [V]
I
PIN
[mA]
105 ° C
105 °C
85 °C
25 °C
-40 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0246810121416
V
PIN
[V]
IPIN [mA]
226
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-98. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
33.2.2.3 Thresholds and Hysteresis
Figure 33-99. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 2 4 6 8 101214161820
V
PIN
[V]
IPIN [mA]
105 °C
85 °C
25 °C
-40 °C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
threshold
[V]
VCC [V]
227
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-100. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
Figure 33-101. I/O Pin Input Hysteresis vs. VCC
105 ° C
85 °C
25 °C
-40 °C
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
0.15
0.18
0.21
0.24
0.27
0.30
0.33
0.36
0.39
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
threshold
[V]
V
CC
[V]
228
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.3 ADC Characteristics
Figure 33-102. INL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
Figure 33-103. INL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Differential mode
Single -ended signed mode
Single-ended unsigned mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
INL[LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
ADC sample rate [ksps]
INL[LSB]
50 100 150 200 250 300
229
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-104. INL Error vs. Input Code
Figure 33-105. DNL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL[LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
DNL [LSB]
230
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-106. DNL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Figure 33-107. DNL Error vs. Input Code
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
50 100 150 200 250 300
ADC sample rate [ksps]
DNL [LSB]
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
231
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-108. Gain Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Figure 33-109. Gain Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Differential mode
Single-ended signed mode
Single-ended unsigned mode
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
1.01.21.41.61.82.02.22.42.62.83.0
V
REF
[V]
Gain error [mV]
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
-9
-8
-7
-6
-5
-4
-3
-2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC [V]
Gain error [mV]
232
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-110. Offset Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Figure 33-111. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
Differential mode
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
Offset error [mV]
Differential mode
Single-ended signed mode
Single-ended unsigned
mod e
-14
-12
-10
-8
-6
-4
-2
0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Gain error [mV]
Temperature [
°
C]
233
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-112. Offset Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
33.2.4 Analog Comparator Characteristics
Figure 33-113. Analog Comparator Hysteresis vs. VCC
Small hysteresis
Differential mode
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Offset error [mV]
-40°
C
25°C
85°C
10
11
12
13
14
15
16
17
18
19
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC [V]
105°C
234
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-114. Analog Comparator Hysteresis vs. VCC
Large hysteresis
Figure 33-115. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
-40 °C
25°C
85°C
105 °C
22
24
26
28
30
32
34
36
38
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
VCC[V]
105 °C
85 °C
25 °C
-40 °C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ICURRENTSOURCE
[µA]
CURRCALIBA[3..0]
235
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-116. Voltage Scaler INL vs. SCALEFAC
T = 25
C, VCC = 3.0V
33.2.5 Internal 1.0V Reference Characteristics
Figure 33-117. ADC Internal 1.0V Reference vs. Temperature
0.25
0.275
0.3
0.325
0.35
0.375
0.4
0.425
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INL [LSB]
SCALEFAC
25°C
3.0 V
2.7 V
1.8 V
0.975
0.980
0.985
0.990
0.995
1.000
1.005
1.010
-45-35-25-15-5 5 152535455565758595105
Bandgap Voltage [V]
Temperature [°C]
236
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.6 BOD Characteristics
Figure 33-118. BOD Thresholds vs. Temperature
BOD level = 1.6V
Figure 33-119. BOD Thresholds vs. Temperature
BOD level = 3.0V
1.615
1.616
1.617
1.618
1.619
1.620
1.621
1.622
1.623
-45-35-25-15-5 5 152535455565758595105
V
BOT
[V]
Temperature [°C]
3.039
3.042
3.045
3.048
3.051
3.054
3.057
3.060
3.063
3.066
-45-35-25-15-5 5 152535455565758595105
V
BOT
[V]
Temperature [°C]
237
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.7 External Reset Characteristics
Figure 33-120. Minimum Reset Pin Pulse Width vs. VCC
Figure 33-121. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
105 °C
85 °C
25 °C
-40 ° C
80
88
96
104
112
120
128
136
144
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
t
RST
[ns]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
0
10
20
30
40
50
60
70
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
IRESET [µA]
VRESET [V]
238
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-122. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
Figure 33-123. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
105 °C
85 °C
25 °C
- 40 °C
0
12
24
36
48
60
72
84
96
108
120
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
IRESET [µA]
VRESET [V]
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IRESET [µA]
VRESET [V]
-40 °C
85 °C
25 °C
105 °C
239
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-124. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
33.2.8 Oscillator Characteristics
33.2.8.1 Ultra Low-Power Internal Oscillator
Figure 33-125. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
105 °C
85 °C
25 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VTHRESHOLD [V]
VCC [V]
- 40 °C
3.3 V
3.0 V
2.7 V
1.8 V
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
240
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.8.2 32.768kHz Internal Oscillator
Figure 33-126. 32.768kHz Internal Oscillator Frequency vs. Temperature
Figure 33-127. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.5
32.6
32.6
32.7
32.7
32.8
32.8
32.9
32.9
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
3.0 V
20
23
26
29
32
35
38
41
44
47
50
-4 16 36 56 76 96 116 136 156 176 196 216 236 256
Frequency [kHz]
RC32KCAL[7..0]
241
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.8.3 2MHz Internal Oscillator
Figure 33-128. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-129. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V 1.6 V
1.985
1.988
1.991
1.994
1.997
2.000
2.003
2.006
2.009
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
242
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-130. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3V
33.2.8.4 32MHz Internal Oscillator
Figure 33-131. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
105
°
C
85 °C
25 °C
-40 °C
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
0 163248648096112128
Frequency [MHz]
CALA
°
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
-45-35-25-15-5 5 152535455565758595105
Frequency[MHz]
Temperatuire [°C]
243
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-132. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
Figure 33-133. 32MHz Internal Oscillator CALA Calibration Step Size
T = -40°C, VCC = 3.0V
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.83
31.86
31.89
31.92
31.95
31.98
32.01
32.04
32.07
32.10
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
-40 °C
0.13 %
0.15 %
0.17 %
0.18 %
0.20 %
0.22 %
0.24 %
0.26 %
0.27 %
0.29 %
0.31 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
244
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-134. 32MHz Internal Oscillator CALA Calibration Step Size
T = 25°C, VCC = 3.0V
Figure 33-135. 32MHz Internal Oscillator CALA Calibration Step Size
T = 85°C, VCC = 3.0V
25 °C
0.12 %
0.14 %
0.16 %
0.18 %
0.20 %
0.22 %
0.24 %
0.26 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
85 °C
0.13 %
0.14 %
0.15 %
0.17 %
0.18 %
0.19 %
0.20 %
0.21 %
0.23 %
0.24 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
245
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-136. 32MHz Internal Oscillator CALA Calibration Step Size
T = 105°C, VCC = 3.0V
Figure 33-137. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V
105 °C
0.14 %
0.15 %
0.16 %
0.17 %
0.18 %
0.19 %
0.20 %
0.21 %
0.22 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
105 °C
85 °C
25 °C
-40 °C
20
25
30
35
40
45
50
55
60
65
70
75
0 7 14 21 28 35 42 49 56 63
Frequency [MHz]
CALB
246
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.8.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-138. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-139. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
46
47
48
49
50
51
52
53
54
55
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
47.75
47.80
47.85
47.90
47.95
48.00
48.05
48.10
48.15
48.20
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
247
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.9 Two-Wire Interface Characteristics
Figure 33-140. SDA Hold Time vs. Temperature
Figure 33-141. SDA Hold Time vs. Supply Voltage
3
2
1
0
50
100
150
200
250
300
350
400
450
500
-45-35-25-15-5 5 1525354555657585
Temperature [°C]
Hold time [ns]
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
248
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.2.10 PDI Characteristics
Figure 33-142. Maximum PDI Frequency vs. VCC
105 ° C
85 °C
25 °C
- 40 °C
6
8
10
12
14
16
18
20
22
24
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
fMAX [MHz]
VCC [V]
249
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3 Atmel ATxmega128D3
33.3.1 Current Consumption
33.3.1.1 Active Mode Supply Current
Figure 33-143. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
Figure 33-144. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
0
100
200
300
400
500
600
700
800
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Icc [µA]
Frequency [MHz]
3.6V
3.3V
3.0V
2.7V
0
2
4
6
8
10
12
0 4 8 121620242832
Icc [mA]
Frequency [MHz]
1.8V
2.2V
250
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-145. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
Figure 33-146. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
105 °C
85 °C
25 °C
-40 °C
0
50
100
150
200
250
300
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [uA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
100
200
300
400
500
600
700
800
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Iccl [µA]
VCC [V]
251
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-147. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
Figure 33-148. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
105
°C
85
°C
25 °C
- 40 °C
0
200
400
600
800
1000
1200
1400
1600
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0.0
1.0
2.0
3.0
4.0
5.0
6.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [mA]
VCC [V]
252
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-149. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
33.3.1.2 Idle Mode Supply Current
Figure 33-150. Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
105 °C
85 °C
25 °C
-40 °C
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
2.22.42.62.8 3 3.23.43.6
Icc [mA]
VCC [V]
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
0
20
40
60
80
100
120
140
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Icc [µA]
Frequency [MHz]
253
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-151. Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
Figure 33-152. Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
3.6V
3.3V
3.0V
2.7V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 4 8 121620242832
Icc [mA]
Frequency [MHz]
2.2V
1.8V
105 °C
85 °C
25 °C
-
40
°C
24
26
28
30
32
34
36
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
254
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-153. Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
Figure 33-154. Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
- 40 °C
20
40
60
80
100
120
140
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
100
150
200
250
300
350
400
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
255
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-155. Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
Figure 33-156. Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
400
600
800
1000
1200
1400
1600
1800
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
2500
3000
3500
4000
4500
5000
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [µA]
VCC [V]
256
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3.1.3 Power-down Mode Supply Current
Figure 33-157. Power-down Mode Supply Current vs. VCC
All functions disabled
Figure 33-158. Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
105 °C
85 °C
25 °C
- 40 °C
0
1
2
3
4
5
6
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
1.82.02.22.42.62.83.03.23.43.6
Icc [µA]
VCC [V]
257
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-159. Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
33.3.2 I/O Pin Characteristics
33.3.2.1 Pull-up
Figure 33-160. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1
2
3
4
5
6
7
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Icc [µA]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
ICC [µA]
VPIN [V]
258
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-161. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
Figure 33-162. I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
ICC [µA]
VPIN [V]
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
ICC [µA]
VPIN [V]
259
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3.2.2 Output Voltage vs. Sink/Source Current
Figure 33-163. I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
Figure 33-164. I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
VPIN [V]
IPIN [mA]
105 °C
85 °C
25 °C
-40 °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
260
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-165. I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
Figure 33-166. I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
105 °C
85 °C
25 °C
-40 °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
105 °C
85 °C
25 °C
-40 °C
0.0
0.5
1.0
1.5
2.0
2.5
0123456789
VPIN [V]
IPIN [mA]
261
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-167. I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
Figure 33-168. I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
105 °C
85 °C
25 °C
-40
°
C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 2 4 6 8 10121416
VPIN [V]
IPIN [mA]
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 2 4 6 8 101214161820
VPIN [V]
IPIN [mA]
262
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3.2.3 Thresholds and Hysteresis
Figure 33-169. I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
Figure 33-170. I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
105 °C
85 °C
25 °C
-40 °C
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
105 °C
85 °C
25
°C
-40 °C
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
263
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-171. I/O Pin Input Hysteresis vs. VCC
33.3.3 ADC Characteristics
Figure 33-172. INL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
105 °C
85 °C
25 °C
-40 °C
0.15
0.20
0.25
0.30
0.35
0.40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
Differential mode
Single -ended signed mode
Single-ended unsigned mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
INL[LSB]
264
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-173. INL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Figure 33-174. INL Error vs. Input Code
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
ADC sample rate [ksps]
INL[LSB]
50 100 150 200 250 300
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL[LSB]
265
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-175. DNL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
Figure 33-176. DNL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
50 100 150 200 250 300
ADC sample rate [ksps]
DNL [LSB]
266
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-177. DNL Error vs. Input Code
Figure 33-178. Gain Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
1.01.21.41.61.82.02.22.42.62.83.0
V
REF
[V]
Gain error [mV]
267
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-179. Gain Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Figure 33-180. Offset Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
-9
-8
-7
-6
-5
-4
-3
-2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC [V]
Gain error [mV]
Differential mode
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
Offset error [mV]
268
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-181. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
Figure 33-182. Offset Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Differential mode
Single-ended signed mode
Single-ended unsigned
mod e
-14
-12
-10
-8
-6
-4
-2
0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Gain error [mV]
Temperature [
°
C]
Differential mode
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Offset error [mV]
269
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3.4 Analog Comparator Characteristics
Figure 33-183. Analog Comparator Hysteresis vs. VCC
Small hysteresis
Figure 33-184. Analog Comparator Hysteresis vs. VCC
Large hysteresis
-40°
C
25°C
85°C
10
11
12
13
14
15
16
17
18
19
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC [V]
105°C
-40 °C
25°C
85°C
105 °C
22
24
26
28
30
32
34
36
38
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
VCC[V]
270
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-185. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
Figure 33-186. Voltage Scaler INL vs. SCALEFAC
T = 25
C, VCC = 3.0V
105 °C
85 °C
25 °C
-40 °C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ICURRENTSOURCE
[µA]
CURRCALIBA[3..0]
0.25
0.275
0.3
0.325
0.35
0.375
0.4
0.425
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INL [LSB]
SCALEFAC
25°C
271
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3.5 Internal 1.0V Reference Characteristics
Figure 33-187. ADC Internal 1.0V Reference vs. Temperature
33.3.6 BOD Characteristics
Figure 33-188. BOD Thresholds vs. Temperature
BOD level = 1.6V
3.6 V
2.7 V
1.6 V
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
1.006
1.007
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Bandgap Voltage [V]
T [°C]
Rising Vcc
Falling Vcc
1.582
1.584
1.586
1.588
1.590
1.592
1.594
1.596
1.598
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
VBOT [V]
Temperature [°C]
272
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-189. BOD Thresholds vs. Temperature
BOD level = 3.0V
33.3.7 External Reset Characteristics
Figure 33-190. Minimum Reset Pin Pulse Width vs. VCC
Rising Vcc
Falling Vcc
2.98
2.99
3.00
3.01
3.02
3.03
3.04
3.05
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
VBOT [V]
T emperature[°C]
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
160
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
tRST [ns]
VCC [V]
273
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-191. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 33-192. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
IRESET [µA]
VRESET [V]
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
IRESET [µA]
VRESET [V]
274
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-193. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
Figure 33-194. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IRESET [µA]
VRESET [V]
105 °C
85 °C
25 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VTHRESHOLD [V]
VCC [V]
- 40 °C
275
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3.8 Oscillator Characteristics
33.3.8.1 Ultra Low-Power Internal Oscillator
Figure 33-195. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
33.3.8.2 32.768kHz Internal Oscillator
Figure 33-196. 32.768kHz Internal Oscillator Frequency vs. Temperature
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
32.35
32.41
32.47
32.53
32.59
32.65
32.71
32.77
32.83
32.89
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
276
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-197. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
33.3.8.3 2MHz Internal Oscillator
Figure 33-198. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
3.0V
20
23
26
29
32
35
38
41
44
47
50
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Frequency [kHz]
RC32KCAL[7..0]
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.94
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
2.16
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
277
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-199. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
Figure 33-200. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.970
1.975
1.980
1.985
1.990
1.995
2.000
2.005
2.010
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
105 °C
85 °C
25 °C
- 40 °C
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
0 16 32 48 64 80 96 112 128
Frequency [MHz]
CALA
278
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.3.8.4 32MHz Internal Oscillator
Figure 33-201. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-202. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
31.6
31.7
31.8
31.9
32.0
32.1
32.2
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
279
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-203. 32MHz Internal Oscillator CALA Calibration Step Size
T = -40°C, VCC = 3.0V
Figure 33-204. 32MHz Internal Oscillator CALA Calibration Step Size
T = 25°C, VCC = 3.0V
-40 °C
0.10 %
0.13 %
0.15 %
0.18 %
0.20 %
0.23 %
0.25 %
0.28 %
0.30 %
0.33 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
25 °C
0.14 %
0.15 %
0.16 %
0.18 %
0.19 %
0.20 %
0.21 %
0.22 %
0.24 %
0.25 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
280
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-205. 32MHz Internal Oscillator CALA Calibration Step Size
T = 85°C, VCC = 3.0V
Figure 33-206. 32MHz Internal Oscillator CALA Calibration Step Size
T = 105°C, VCC = 3.0V
85 °C
0.13 %
0.14 %
0.15 %
0.16 %
0.17 %
0.18 %
0.19 %
0.20 %
0.21 %
0.22 %
0.23 %
0 16 32 48 64 80 96 112 128
Frequency Step size [%]
CALA
105 °C
0.13 %
0.14 %
0.15 %
0.16 %
0.17 %
0.19 %
0.20 %
0.21 %
0.22 %
0.23 %
0.24 %
0163248648096112128
Frequency Step size [%]
CALA
281
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-207. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V
33.3.8.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-208. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
20
25
30
35
40
45
50
55
60
65
70
0 7 14 21 28 35 42 49 56 63
Freq uency [MHz]
DFLLRC32MCALB
-40 °C
25 °C
85 °C
105 °C
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
46
47
48
49
50
51
52
53
54
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
282
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-209. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
33.3.9 Two-Wire Interface Characteristics
Figure 33-210. SDA Hold Time vs. Temperature
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
47.2
47.3
47.4
47.5
47.6
47.7
47.8
47.9
48.0
48.1
48.2
-45-35-25-15-5 5 152535455565758595105
Freq uency [MHz]
Temperature [°C]
3
2
1
0
50
100
150
200
250
300
350
400
450
500
-45-35-25-15-5 5 1525354555657585
Temperature [°C]
Hold time [ns]
283
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-211. SDA Hold Time vs. Supply Voltage
33.3.10 PDI Characteristics
Figure 33-212. Maximum PDI Frequency vs. VCC
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
105 °C
85 °C
25 °C
- 40 °C
6
8
10
12
14
16
18
20
22
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
fMAX [MHz]
VCC [V]
284
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4 Atmel ATxmega192D3
33.4.1 Current Consumption
33.4.1.1 Active Mode Supply Current
Figure 33-213.Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
Figure 33-214.Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
3.3V
3.0V
2.7V
2.2V
1.8V
0
50
100
150
200
250
300
350
400
450
500
550
600
650
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
3.3V
3.0V
2.7V
0
1
2
3
4
5
6
7
8
9
10
11
0 2 4 6 8 101214161820222426283032
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
285
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-215.Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
Figure 33-216.Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
105 °C
85 °C
25 °C
-40 °C
50
70
90
110
130
150
170
190
210
230
250
270
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
200
250
300
350
400
450
500
550
600
650
700
750
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
286
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-217.Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
Figure 33-218.Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
105 °C
85 °C
25 °C
-40 °C
400
550
700
850
1000
1150
1300
1450
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85
°
C
25 °C
-40 °C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [mA]
VCC [V]
287
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-219.Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
33.4.1.2 Idle Mode Supply Current
Figure 33-220.Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
105 °C
85 °C
25 °C
-40 °C
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
VCC [V]
3.3V
3.0V
2.7V
2.2V
1.8V
0
13
26
39
52
65
78
91
104
117
130
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
288
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-221.Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
Figure 33-222.Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
3.3V
3.0V
2.7V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
02468101214161820222426283032
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
105 °C
85 °C
25 °C
-40 °C
25
27
29
31
33
35
37
39
41
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
289
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-223.Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
Figure 33-224.Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
40
55
70
85
100
115
130
145
160
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
75
95
115
135
155
175
195
215
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
290
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-225.Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
Figure 33-226.Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
300
400
500
600
700
800
900
1000
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
VCC [V]
291
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4.1.3 Power-down Mode Supply Current
Figure 33-227.Power-down Mode Supply Current vs. VCC
All functions disabled
Figure 33-228.Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
105 °C
85 °C
25 °C
-40 °C
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
292
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-229.Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
33.4.2 I/O Pin Characteristics
33.4.2.1 Pull-up
Figure 33-230.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
3.0 V
2.7 V
2.2 V
1.8 V
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Icc [µA]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
0
8
16
24
32
40
48
56
64
72
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I [µA]
VPIN [V]
293
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-231.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
Figure 33-232.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
I [µA]
VPIN [V]
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
I [µA]
VPIN [V]
294
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4.2.2 Output Voltage vs. Sink/Source Current
Figure 33-233.I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
Figure 33-234.I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
VPIN [V]
IPIN [mA]
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
-16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
25 °C
85 °C 105 °C
-40 °C
295
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-235.I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
Figure 33-236.I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
-40 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
25 °C
85 °C
105 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
012345678
VPIN [V]
IPIN [mA]
-40 °C
25 °C
85 °C
105 °C
296
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-237.I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
Figure 33-238.I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0246810121416
VPIN [V]
IPIN [mA]
105 °C
85 °C
25 °C
-40 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 2 4 6 8 101214161820
VPIN [V]
IPIN [mA]
105 °C 85 °C
-40 °C
25 °C
297
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4.2.3 Thresholds and Hysteresis
Figure 33-239.I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
Figure 33-240.I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
105 °C
85 °C
25 °C
-40 °C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.65
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
p
298
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-241.I/O Pin Input Hysteresis vs. VCC
33.4.3 ADC Characteristics
Figure 33-242.INL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
105 °C
85 °C
25 °C
-40 °C
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0.37
0.40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
Differential mode
Single -ended signed mode
Single-ended unsigned mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
INL[LSB]
299
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-243.INL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Figure 33-244.INL Error vs. Input Code
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
ADC sample rate [ksps]
INL[LSB]
50 100 150 200 250 300
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL[LSB]
300
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-245.DNL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
Figure 33-246.DNL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
50 100 150 200 250 300
ADC sample rate [ksps]
DNL [LSB]
301
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-247.DNL Error vs. Input Code
Figure 33-248.Gain Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
1.01.21.41.61.82.02.22.42.62.83.0
V
REF
[V]
Gain error [mV]
302
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-249.Gain Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Figure 33-250.Offset Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
-9
-8
-7
-6
-5
-4
-3
-2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC [V]
Gain error [mV]
Differential mode
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
Offset error [mV]
303
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-251.Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
Figure 33-252.Offset Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Differential mode
Single-ended signed mode
Single-ended unsigned
mode
-14
-12
-10
-8
-6
-4
-2
0
-45-35-25-15-5 5 152535455565758595105
Gain error [mV]
Temperature [°C]
Differential mode
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Offset error [mV]
304
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4.4 Analog Comparator Characteristics
Figure 33-253.Analog Comparator Hysteresis vs. VCC
Small hysteresis
Figure 33-254.Analog Comparator Hysteresis vs. VCC
Large hysteresis
-40°C
25°C
85°C
105°C
10
11
12
13
14
15
16
17
18
19
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
-40°C
25°C
85°C
105
°
C
18
20
22
24
26
28
30
32
34
36
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
305
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-255.Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
Figure 33-256.Voltage Scaler INL vs. SCALEFAC
T = 25
C, VCC = 3.0V
105 °C
85 °C
25 °C
- 40 °C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I
CURRENTSOURCE
[µA]
CURRCALIBA[3..0]
25°C
0.15
0.18
0.21
0.24
0.27
0.3
0.33
0.36
0.39
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
INL [LSB]
306
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4.5 Internal 1.0V Reference Characteristics
Figure 33-257.ADC Internal 1.0V Reference vs. Temperature
33.4.6 BOD Characteristics
Figure 33-258.BOD Thresholds vs. Temperature
BOD level = 1.6V
3.6 V
2.7 V
1.6 V
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
1.006
1.007
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Bandgap Voltage [V]
T [°C]
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
-45-35-25-15-5 5 152535455565758595105
VBOT [V]
Temperature [°C]
307
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-259.BOD Thresholds vs. Temperature
BOD level = 3.0V
33.4.7 External Reset Characteristics
Figure 33-260.Minimum Reset Pin Pulse Width vs. VCC
3.00
3.02
3.04
3.06
3.08
3.10
3.12
3.14
3.16
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
VBOT [V]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
80
88
96
104
112
120
128
136
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
tRST [ns]
VCC [V]
308
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-261.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 33-262.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
105 °C
85 °C
25 °C
-40 °C
0
8
16
24
32
40
48
56
64
72
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I [µA]
VPIN [V]
-40 °C
25 °C
85 °C
105°C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
IRESET [µA]
V
RESET
[V]
309
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-263.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
Figure 33-264.Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
0
18
36
54
72
90
108
126
144
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IRESET [µA]
VRESET [V]
-40 °C
25 °C
85 °C
105°C
105 °C
85 °C
25 °C
-40 °C
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VTHRESHOLD [V]
VCC [V]
310
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4.8 Oscillator Characteristics
33.4.8.1 Ultra Low-Power Internal Oscillator
Figure 33-265.Ultra Low-Power Internal Oscillator Frequency vs. Temperature
33.4.8.2 32.768kHz Internal Oscillator
Figure 33-266.32.768kHz Internal Oscillator Frequency vs. Temperature
3.6 V
3.3 V
3.0 V
2.7 V
2.0 V
1.8 V
1.6 V
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [kHz]
Temperature [°C]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.50
32.55
32.60
32.65
32.70
32.75
32.80
32.85
32.90
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
32.768kHz internal oscillator f requency vs. temperature
311
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-267.32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
33.4.8.3 2MHz Internal Oscillator
Figure 33-268. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
3.0 V
23
26
29
32
35
38
41
44
47
50
53
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
RC32KCAL[7..0]
Frequency [kHz]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
2.16
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
312
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-269. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
Figure 33-270. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3V
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.970
1.975
1.980
1.985
1.990
1.995
2.000
2.005
2.010
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
105 °C
85 °C
25
°
C
-40
°
C
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
Frequency [MHz]
CALA
313
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.4.8.4 32MHz Internal Oscillator
Figure 33-271. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-272. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
1.8V
2.7V
3.3V
3.0V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
-45-35-25-15-5 5 152535455565758595105
Freq uen cy [MHz]
Temp erature [°C]
2.2V
1.8V
2.7V
3.3V
3.0V
2.2V
31.75
31.80
31.85
31.90
31.95
32.00
32.05
32.10
32.15
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temp erature [°C]
314
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-273. 32MHz Internal Oscillator CALA Calibration Step Size
T = -40°C, VCC = 3.0V
Figure 33-274. 32MHz Internal Oscillator CALA Calibration Step Size
T = 25°C, VCC = 3.0V
-40 °C
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 16 32 48 64 80 96 112 128
Frequency Step Size [%]
CALA
25 °C
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0.28
0 16 32 48 64 80 96 112 128
Frequency Step Size [%]
CALA
315
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-275. 32MHz Internal Oscillator CALA Calibration Step Size
T = 85°C, VCC = 3.0V
Figure 33-276. 32MHz Internal Oscillator CALA Calibration Step Size
T = 105°C, VCC = 3.0V
85 °C
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0 16 32 48 64 80 96 112 128
Frequency Step Size [%]
CALA
105 °C
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0 163248648096112128
Frequency Step Size [%]
CALA
316
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-277. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V
33.4.8.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-278. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
105 °C
85 °C
25 °C
-40 °C
20
25
30
35
40
45
50
55
60
65
70
0 7 14 21 28 35 42 49 56 63
Frequency [MHz]
CALB
1.8V
2.7V
3.3V
3.0V
2.2V
46
47
48
49
50
51
52
53
54
55
-45-35-25-15-5 5 152535455565758595105
Frequench [MHz]
Temperature [°C]
32MHz internal oscillator f requency vs. temperature
Using 48MHz calibration value f rom signature row. DFLL disabled
317
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-279. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
33.4.9 Two-Wire Interface Characteristics
Figure 33-280.SDA Hold Time vs. Temperature
1.8V 2.7V
3.3V
3.0V
2.2V
47.6
47.7
47.8
47.9
48.0
48.1
48.2
48.3
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
3
2
1
0
50
100
150
200
250
300
350
400
450
500
-45-35-25-15-5 5 1525354555657585
Temperature [°C]
Hold time [ns]
318
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-281.SDA Hold Time vs. Supply Voltage
33.4.10 PDI Characteristics
Figure 33-282.Maximum PDI Frequency vs. VCC
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
85°C
25°C
-40°C
11
16
21
26
31
36
V
CC
[V]
f
MAX
[MHz]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
319
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5 Atmel ATxmega256D3
33.5.1 Current Consumption
33.5.1.1 Active Mode Supply Current
Figure 33-283.Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
Figure 33-284.Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
3.3V
3.0V
2.7V
2.2V
1.8V
0
50
100
150
200
250
300
350
400
450
500
550
600
650
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
3.3V
3.0V
2.7V
0
1
2
3
4
5
6
7
8
9
10
11
0 2 4 6 8 101214161820222426283032
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
320
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-285.Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
Figure 33-286.Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
105 °C
85 °C
25 °C
-40 °C
50
70
90
110
130
150
170
190
210
230
250
270
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
200
250
300
350
400
450
500
550
600
650
700
750
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
321
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-287.Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
Figure 33-288.Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
105 °C
85 °C
25 °C
-40 °C
400
550
700
850
1000
1150
1300
1450
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85
°
C
25 °C
-40 °C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [mA]
VCC [V]
322
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-289.Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
33.5.1.2 Idle Mode Supply Current
Figure 33-290.Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
105 °C
85 °C
25 °C
-40 °C
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
VCC [V]
3.3V
3.0V
2.7V
2.2V
1.8V
0
13
26
39
52
65
78
91
104
117
130
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
323
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-291.Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
Figure 33-292.Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
3.3V
3.0V
2.7V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
02468101214161820222426283032
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
105 °C
85 °C
25 °C
-40 °C
25
27
29
31
33
35
37
39
41
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
324
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-293.Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
Figure 33-294.Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
40
55
70
85
100
115
130
145
160
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
75
95
115
135
155
175
195
215
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
325
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-295.Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
Figure 33-296.Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
300
400
500
600
700
800
900
1000
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
VCC [V]
326
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5.1.3 Power-down Mode Supply Current
Figure 33-297.Power-down Mode Supply Current vs. VCC
All functions disabled
Figure 33-298.Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
105 °C
85 °C
25 °C
-40 °C
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
327
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-299.Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
33.5.2 I/O Pin Characteristics
33.5.2.1 Pull-up
Figure 33-300.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
3.0 V
2.7 V
2.2 V
1.8 V
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Icc [µA]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
0
8
16
24
32
40
48
56
64
72
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I [µA]
VPIN [V]
328
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-301.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
Figure 33-302.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
I [µA]
VPIN [V]
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
I [µA]
VPIN [V]
329
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5.2.2 Output Voltage vs. Sink/Source Current
Figure 33-303.I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
Figure 33-304.I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
105 °C
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
VPIN [V]
IPIN [mA]
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
-16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
25 °C
85 °C 105 °C
-40 °C
330
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-305.I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
Figure 33-306.I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
-40 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
25 °C
85 °C
105 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
012345678
VPIN [V]
IPIN [mA]
-40 °C
25 °C
85 °C
105 °C
331
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-307.I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
Figure 33-308.I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0246810121416
VPIN [V]
IPIN [mA]
105 °C
85 °C
25 °C
-40 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 2 4 6 8 101214161820
VPIN [V]
IPIN [mA]
105 °C 85 °C
-40 °C
25 °C
332
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5.2.3 Thresholds and Hysteresis
Figure 33-309.I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
Figure 33-310.I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
105 °C
85 °C
25 °C
-40 °C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
105 °C
85 °C
25 °C
- 40 °C
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
1.65
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
333
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-311.I/O Pin Input Hysteresis vs. VCC
33.5.3 ADC Characteristics
Figure 33-312.INL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
105 °C
85 °C
25 °C
-40 °C
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0.37
0.40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
Differential mode
Single -ended signed mode
Single-ended unsigned mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
INL[LSB]
334
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-313.INL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Figure 33-314.INL Error vs. Input Code
, ,
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
ADC sample rate [ksps]
INL[LSB]
50 100 150 200 250 300
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL[LSB]
335
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-315.DNL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
Figure 33-316.DNL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
50 100 150 200 250 300
ADC sample rate [ksps]
DNL [LSB]
336
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-317.DNL Error vs. Input Code
Figure 33-318.Gain Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584 4096
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
1.01.21.41.61.82.02.22.42.62.83.0
V
REF
[V]
Gain error [mV]
337
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-319. Gain Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Figure 33-320. Offset Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Single-ended unsigned mode
Single-ended signed mode
Differential mode
-10
-8
-6
-4
-2
0
2
4
VREF [V]
Gain error [mV]
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Differential mode
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
Offset error [mV]
338
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-321. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
Figure 33-322. Offset Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Differential mode
Single-ended signed mode
Single-ended unsigned
mode
-14
-12
-10
-8
-6
-4
-2
0
-45-35-25-15-5 5 152535455565758595105
Gain error [mV]
Temperature [°C]
Differential mode
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Offset error [mV]
339
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5.4 Analog Comparator Characteristics
Figure 33-323. Analog Comparator Hysteresis vs. VCC
Small hysteresis
Figure 33-324. Analog Comparator Hysteresis vs. VCC
Large hysteresis
-40°C
25°C
85°C
105°C
10
11
12
13
14
15
16
17
18
19
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
High speed mode, small hysteresis
-40°C
25°C
85°C
105
°
C
18
20
22
24
26
28
30
32
34
36
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
High speed mode, large hysteresis
340
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-325. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
Figure 33-326. Voltage Scaler INL vs. SCALEFAC
T = 25
C, VCC = 3.0V
105 °C
85 °C
25 °C
- 40 °C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I
CURRENTSOURCE
[µA]
CURRCALIBA[3..0]
25°C
0.15
0.18
0.21
0.24
0.27
0.3
0.33
0.36
0.39
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
INL [LSB]
341
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5.5 Internal 1.0V Reference Characteristics
Figure 33-327. ADC Internal 1.0V Reference vs. Temperature
33.5.6 BOD Characteristics
Figure 33-328. BOD Thresholds vs. Temperature
BOD level = 1.6V
3.6 V
2.7 V
1.6 V
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
1.006
1.007
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Bandgap Voltage [V]
T [°C]
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
-45-35-25-15-5 5 152535455565758595105
VBOT [V]
Temperature [°C]
342
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-329. BOD Thresholds vs. Temperature
BOD level = 3.0V
33.5.7 External Reset Characteristics
Figure 33-330. Minimum Reset Pin Pulse Width vs. VCC
3.00
3.02
3.04
3.06
3.08
3.10
3.12
3.14
3.16
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
VBOT [V]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
80
88
96
104
112
120
128
136
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
tRST [ns]
VCC [V]
343
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-331. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 33-332. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
-40 °C
25 °C
85 °C
105°C
0
10
20
30
40
50
60
70
80
0.00.20.40.60.81.01.21.41.61.8
IRESET [µA]
VRESET [V]
-40 °C
25 °C
85 °C
105°C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
IRESET [µA]
VRESET [V]
344
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-333. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
Figure 33-334. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
0
18
36
54
72
90
108
126
144
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IRESET [µA]
VRESET [V]
VCC 3.3 V
-40 °C
25 °C
85 °C
105°C
105 °C
85 °C
25 °C
-40 °C
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VTHRESHOLD [V]
VCC [V]
345
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5.8 Oscillator Characteristics
33.5.8.1 Ultra Low-Power Internal Oscillator
Figure 33-335. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
33.5.8.2 32.768kHz Internal Oscillator
Figure 33-336. 32.768kHz Internal Oscillator Frequency vs. Temperature
3.6 V
3.3 V
3.0 V
2.7 V
2.0 V
1.8 V
1.6 V
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [kHz]
Temperature [°C]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.50
32.55
32.60
32.65
32.70
32.75
32.80
32.85
32.90
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
346
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-337. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
33.5.8.3 2MHz Internal Oscillator
Figure 33-338. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
3.0 V
23
26
29
32
35
38
41
44
47
50
53
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
RC32KCAL[7..0]
Frequency [kHz]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
2.16
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
347
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-339. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
Figure 33-340. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3V
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.970
1.975
1.980
1.985
1.990
1.995
2.000
2.005
2.010
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
105 °C
85 °C
25
°
C
-40
°
C
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
Frequency [MHz]
CALA
348
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.5.8.4 32MHz Internal Oscillator
Figure 33-341. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-342. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
1.8V
2.7V
3.3V
3.0V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
-45-35-25-15-5 5 152535455565758595105
Freq uen cy [MHz]
Temp erature [°C]
2.2V
1.8V
2.7V
3.3V
3.0V
2.2V
31.75
31.80
31.85
31.90
31.95
32.00
32.05
32.10
32.15
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temp erature [°C]
349
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-343. 32MHz Internal Oscillator CALA Calibration Step Size
T = -40°C, VCC = 3.0V
Figure 33-344. 32MHz Internal Oscillator CALA Calibration Step Size
T = 25°C, VCC = 3.0V
-40 °C
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 16 32 48 64 80 96 112 128
Frequency Step Size [%]
CALA
25 °C
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0.28
0 16 32 48 64 80 96 112 128
Frequency Step Size [%]
CALA
350
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-345. 32MHz Internal Oscillator CALA Calibration Step Size
T = 85°C, VCC = 3.0V
Figure 33-346. 32MHz Internal Oscillator CALA Calibration Step Size
T = 105°C, VCC = 3.0V
85 °C
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0 16 32 48 64 80 96 112 128
Frequency Step Size [%]
CALA
105 °C
0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0 163248648096112128
Frequency Step Size [%]
CALA
351
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-347. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V
33.5.8.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-348. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
105 °C
85 °C
25 °C
-40 °C
20
25
30
35
40
45
50
55
60
65
70
0 7 14 21 28 35 42 49 56 63
Frequency [MHz]
CALB
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
46
47
48
49
50
51
52
53
54
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
352
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-349. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
33.5.9 Two-Wire Interface Characteristics
Figure 33-350. SDA Hold Time vs. Temperature
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
47.3
47.4
47.5
47.6
47.7
47.8
47.9
48.0
48.1
48.2
48.3
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
3
2
1
0
50
100
150
200
250
300
350
400
450
500
-45-35-25-15-5 5 1525354555657585
Temperature [°C]
Hold time [ns]
353
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-351. SDA Hold Time vs. Supply Voltage
33.5.10 PDI Characteristics
Figure 33-352. Maximum PDI Frequency vs. VCC
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
85°C
25°C
-40°C
11
16
21
26
31
36
V
CC
[V]
f
MAX
[MHz]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
354
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6 Atmel ATxmega384D3
33.6.1 Current Consumption
33.6.1.1 Active Mode Supply Current
Figure 33-353.Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
Figure 33-354.Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
3.3V
3.0V
2.7V
2.2V
1.8V
0
50
100
150
200
250
300
350
400
450
500
550
600
650
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
3.3V
3.0V
2.7V
0
1
2
3
4
5
6
7
8
9
10
11
0 2 4 6 8 101214161820222426283032
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
355
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-355.Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
Figure 33-356.Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
105 °C
85 °C
25 °C
-40 °C
0
50
100
150
200
250
300
350
400
450
500
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
I
CC
[µA]
V
CC
[V]
105 °C
85 °C
25 °C
-40 °C
200
320
440
560
680
800
920
1040
1160
1280
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
356
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-357.Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
Figure 33-358.Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
105 °C
85 °C
25 °C
-40 °C
380
580
780
980
1180
1380
1580
1780
1980
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
1.0
2.0
3.0
4.0
5.0
6.0
7.0
1.61.82.02.22.42.62.83.03.23.43.6
Icc [mA]
VCC [V]
357
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-359.Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
33.6.1.2 Idle Mode Supply Current
Figure 33-360.Idle Mode Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
105 °C
85 °C
25 °C
-40 °C
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
V
CC
[V]
3.3V
3.0V
2.7V
2.2V
1.8V
0
13
26
39
52
65
78
91
104
117
130
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
358
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-361.Idle Mode Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
Figure 33-362.Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
3.3V
3.0V
2.7V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
02468101214161820222426283032
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
105 °C
85 °
C
25 °
C
-40
°
C
28
30
32
34
36
38
40
42
44
46
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
V
CC
[V]
359
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-363.Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
Figure 33-364.Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
90
120
150
180
210
240
270
300
330
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
190
240
290
340
390
440
490
540
590
640
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
360
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-365.Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
Figure 33-366.Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
500
700
900
1100
1300
1500
1700
1900
1.61.82.02.22.42.62.83.03.23.43.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-
40
°C
3000
3300
3600
3900
4200
4500
4800
5100
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [µA]
V
CC
[V]
361
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.1.3 Power-down Mode Supply Current
Figure 33-367.Power-down Mode Supply Current vs. VCC
All functions disabled
Figure 33-368.Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
105 °C
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
18
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
362
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-369.Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
33.6.2 I/O Pin Characteristics
33.6.2.1 Pull-up
Figure 33-370.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 1.8V
3.0 V
2.7 V
2.2 V
1.8 V
0
2
4
6
8
10
12
14
-45-35-25-15-5 5 152535455565758595105
Icc [µA]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I
PIN
[µA]
VPIN [V]
CC
363
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-371.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.0V
Figure 33-372.I/O Pin Pull-up Resistor Current vs. Input Voltage
VCC = 3.3V
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
I
PIN
[µA]
VPIN [V]
105
°
°C
85 °C
25 °°C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
I
PIN
[µA]
V
PIN
[V]
364
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.2.2 Output Voltage vs. Sink/Source Current
Figure 33-373.I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
Figure 33-374.I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
VPIN [V]
IPIN [mA]
-40 °C
25 °C
85 °C
105 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
-16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
85 °C
105 °C25 °C
-40 °C
365
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-375.I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
Figure 33-376.I/O Pin Output Voltage vs. Sink Current
VCC = 1.8V
85 °C
105 °C
25 °C
-40 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
-16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0123456789
VPIN [V]
IPIN [mA]
105 °C
366
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-377.I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
Figure 33-378.I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
105 °C
85 °C
25 °C
-40 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 2 4 6 8 10121416
VPIN [V]
IPIN [mA]
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 2 4 6 8 101214161820
VPIN [V]
IPIN [mA]
105 °C
85 °C
-40 °C
25 °C
367
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.2.3 Thresholds and Hysteresis
Figure 33-379.I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
Figure 33-380.I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
105 °C
85 °C
25 °C
-40 °C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
,p
368
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-381.I/O Pin Input Hysteresis vs. VCC
33.6.3 ADC Characteristics
Figure 33-382. INL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
105 °C
85 °C
25 °C
-40 °C
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0.37
0.40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
Differential mode
Single -ended signed mode
Single-ended unsigned mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
INL[LSB]
369
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-383. INL Error vs. Sample Rate
T = 25°C, VCC = 3.6V, VREF = 3.0V external
Figure 33-384. INL Error vs. Input Code
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
ADC sample rate [ksps]
INL[LSB]
50 100 150 200 250 300
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL[LSB]
370
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-385. DNL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
Figure 33-386. DNL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
50 100 150 200 250 300
ADC sample rate [ksps]
DNL [LSB]
371
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-387. DNL Error vs. Input Code
Figure 33-388. Gain Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
1.01.21.41.61.82.02.22.42.62.83.0
V
REF
[V]
Gain error [mV]
372
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-389. Gain Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Figure 33-390. Offset Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
-9
-8
-7
-6
-5
-4
-3
-2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC [V]
Gain error [mV]
Differential mode
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
Offset error [mV]
373
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-391. Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
Figure 33-392. Offset Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Differential mode
Single-ended signed mode
Single-ended unsigned
mode
-14
-12
-10
-8
-6
-4
-2
0
-45-35-25-15-5 5 152535455565758595105
Gain error [mV]
Temperature [°C]
Differential mode
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Offset error [mV]
374
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.4 Analog Comparator Characteristics
Figure 33-393. Analog Comparator Hysteresis vs. VCC
Small hysteresis
Figure 33-394. Analog Comparator Hysteresis vs. VCC
Large hysteresis
-40°C
25°C
85°C
105°C
10
11
12
13
14
15
16
17
18
19
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
-40°C
25°C
85°C
105
°
C
18
20
22
24
26
28
30
32
34
36
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
375
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-395. Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
Figure 33-396. Voltage Scaler INL vs. SCALEFAC
T = 25
C, VCC = 3.0V
105 °C
85 °C
25 °C
- 40 °C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I
CURRENTSOURCE
[µA]
CURRCALIBA[3..0]
25°C
0.2
0.23
0.26
0.29
0.32
0.35
0.38
0.41
0.44
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
INL [LSB]
376
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.5 Internal 1.0V Reference Characteristics
Figure 33-397. ADC Internal 1.0V Reference vs. Temperature
33.6.6 BOD Characteristics
Figure 33-398. BOD Thresholds vs. Temperature
BOD level = 1.6V
3.6 V
2.7 V
1.6 V
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
1.006
1.007
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Bandgap Voltage [V]
T [°C]
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
-45-35-25-15-5 5 152535455565758595105
VBOT [V]
Temperature [°C]
377
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-399. BOD Thresholds vs. Temperature
BOD level = 3.0V
33.6.7 External Reset Characteristics
Figure 33-400. Minimum Reset Pin Pulse Width vs. VCC
3.00
3.02
3.04
3.06
3.08
3.10
3.12
3.14
3.16
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
VBOT [V]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
80
88
96
104
112
120
128
136
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
tRST [ns]
VCC [V]
378
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-401. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 33-402. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
-40 °C
25 °C
85 °C
105°C
0
10
20
30
40
50
60
70
80
0.00.20.40.60.81.01.21.41.61.8
IRESET [µA]
VRESET [V]
-40 °C
25 °C
85 °C
105°C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
IRESET [µA]
VRESET [V]
379
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-403. Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
Figure 33-404. Reset Pin Input Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
0
18
36
54
72
90
108
126
144
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IRESET [µA]
VRESET [V]
-40 °C
25 °C
85 °C
105°C
105 °C
85 °C
25 °C
-40 °C
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VTHRESHOLD [V]
VCC [V]
380
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.8 Oscillator Characteristics
33.6.8.1 Ultra Low-Power Internal Oscillator
Figure 33-405. Ultra Low-Power Internal Oscillator Frequency vs. Temperature
33.6.8.2 32.768kHz Internal Oscillator
Figure 33-406. 32.768kHz Internal Oscillator Frequency vs. Temperature
3.6 V
3.3 V
3.0 V
2.7 V
2.0 V
1.8 V
1.6 V
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [kHz]
Temperature [°C]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.50
32.55
32.60
32.65
32.70
32.75
32.80
32.85
32.90
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
381
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-407. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
33.6.8.3 2MHz Internal Oscillator
Figure 33-408. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
3.0 V
23
26
29
32
35
38
41
44
47
50
53
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
RC32KCAL[7..0]
Frequency [kHz]
3.3V
3.0V
2.7V
2.2V
1.8V
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
2.16
2.18
2.20
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
382
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-409. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
Figure 33-410. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3V
1.8V
2.2V
1.986
1.988
1.990
1.992
1.994
1.996
1.998
2.000
2.002
2.004
2.006
2.008
2.010
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Freq uency [MHz]
Temp erature [°C]
2.7V
3.3V
3.0V
105 °C
85 °C
25
°
C
-40
°
C
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
Frequency [MHz]
CALA
383
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.8.4 32MHz Internal Oscillator
Figure 33-411. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-412. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
1.8V
2.7V
3.3V
3.0V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
-45-35-25-15-5 5 152535455565758595105
Freq uen cy [MHz]
Temp erature [°C]
2.2V
1.8V
2.7V
3.3V
3.0V
2.2V
31.75
31.80
31.85
31.90
31.95
32.00
32.05
32.10
32.15
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temp erature [°C]
384
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 33-413. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
Figure 33-414. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V
25°C
105°C
85°C
-40°C
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
0.33
0.35
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
Step si ze [%]
CALA
105 °C
85 °C
25 °C
-40 °C
20
26
32
38
44
50
56
62
68
74
80
0 7 14 21 28 35 42 49 56 63
Frequency [MHz]
DFLLRC2MCALB
385
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.8.5 32MHz Internal Oscillator Calibrated to 48MHz
Figure 33-415. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 33-416. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
1.8V
2.7V
3.3V
3.0V
2.2V
46
47
48
49
50
51
52
53
54
55
-45-35-25-15-5 5 152535455565758595105
Frequench [MHz]
Temperature [°C]
1.8V 2.7V
3.3V
3.0V
2.2V
47.6
47.7
47.8
47.9
48.0
48.1
48.2
48.3
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
386
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.9 Two-Wire Interface Characteristics
Figure 33-417. SDA Hold Time vs. Temperature
Figure 33-418. SDA Hold Time vs. Supply Voltage
3
2
1
0
50
100
150
200
250
300
350
400
450
500
-45-35-25-15-5 5 1525354555657585
Temperature [°C]
Hold time [ns]
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
387
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
33.6.10 PDI Characteristics
Figure 33-419. Maximum PDI Frequency vs. VCC
85°C
25°C
-40°C
11
16
21
26
31
36
V
CC
[V]
f
MAX
[MHz]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
388
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
34. Errata
34.1 Atmel ATxmega32D3
34.1.1 Rev. I
AC system status flags are only valid if AC-system is enabled
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. AC system status flags are only valid if AC-system is enabled
The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not
possible to clear the AC interrupt flags without enabling either of the Analog comparators.
Problem fix/workaround
Software should clear the AC system flags once, after enabling the AC system before using the AC system status
flags.
2. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC, and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
3. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
34.1.2 Rev A - H
Not sampled.
389
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
34.2 Atmel ATxmega64D3
34.2.1 Rev. I
AC system status flags are only valid if AC-system is enabled
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. AC system status flags are only valid if AC-system is enabled
The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not
possible to clear the AC interrupt flags without enabling either of the Analog comparators.
Problem fix/workaround
Software should clear the AC system flags once, after enabling the AC system before using the AC system status
flags.
2. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC, and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
3. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
34.2.2 Rev. H
Not sampled.
34.2.3 Rev. G
Not sampled.
34.2.4 Rev. F
Not sampled.
390
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
34.2.5 Rev. E
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
Disabling of the USART transmitter does not automatically set the TxD pin direction to input.
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
391
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Figure 34-1. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
392
XMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
393
XMEGA D3 [DATASHEET]
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-1. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
394
XMEGA D3 [DATASHEET]
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
18. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
19. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
20. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
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if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
21. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
22. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
23. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
24. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or
configure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
396
XMEGA D3 [DATASHEET]
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PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
25. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
26. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
27. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
Problem fix/workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
34.2.6 Rev. D
Not sampled.
34.2.7 Rev. C
Not sampled.
397
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34.2.8 Rev. B
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Writing EEPROM or Flash while reading any of them will not work
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
Disabling the USART transmitter does not automatically set the TxD pin direction to input
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
398
XMEGA D3 [DATASHEET]
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Figure 34-2. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
399
XMEGA D3 [DATASHEET]
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Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
400
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-2. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
401
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in
Active mode.
Problem fix/workaround
Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an
EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt.
Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has
started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode.
18. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
19. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
20. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
21. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
402
XMEGA D3 [DATASHEET]
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Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
22. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
23. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
24. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
25. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or config-
ure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
403
XMEGA D3 [DATASHEET]
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CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
26. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
27. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
28. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to
zero will not automatically set the TxD pin direction to input.
404
XMEGA D3 [DATASHEET]
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Problem fix/workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
34.2.9 Rev. A
Not sampled.
405
XMEGA D3 [DATASHEET]
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34.3 Atmel ATxmega128D3
34.3.1 Rev. J
AC system status flags are only valid if AC-system is enabled
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. AC system status flags are only valid if AC-system is enabled
The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not
possible to clear the AC interrupt flags without enabling either of the Analog comparators.
Problem fix/workaround
Software should clear the AC system flags once, after enabling the AC system before using the AC system status
flags.
2. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
3. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
34.3.2 Rev. I
Not sampled.
34.3.3 Rev. H
Not sampled.
34.3.4 Rev. G
Not sampled.
34.3.5 Rev. F
Not sampled.
406
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34.3.6 Rev. E
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
Disabling the USART transmitter does not automatically set the TxD pin direction to input.
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
407
XMEGA D3 [DATASHEET]
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Figure 34-3. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
408
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Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-3. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
18. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
19. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
20. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
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if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
21. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
22. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
23. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
24. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or
configure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
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PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
25. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
26. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
27. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
Problem fix/workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
34.3.7 Rev. D
Not sampled.
34.3.8 Rev. C
Not sampled.
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34.3.9 Rev. B
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Writing EEPROM or Flash while reading any of them will not work
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
Disabling the USART transmitter does not automatically set the TxD pin direction to input
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
414
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Figure 34-4. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
415
XMEGA D3 [DATASHEET]
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Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-4. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in
Active mode.
Problem fix/workaround
Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an
EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt.
Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has
started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode.
18. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
19. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
20. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
21. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
418
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Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
22. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
23. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
24. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
25. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or config-
ure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
419
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CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
27. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
28. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
28. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
420
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Problem fix/workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
34.3.10 Rev. A
Not sampled.
421
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34.4 Atmel ATxmega192D3
34.4.1 Rev. I
AC system status flags are only valid if AC-system is enabled
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. AC system status flags are only valid if AC-system is enabled
The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not
possible to clear the AC interrupt flags without enabling either of the Analog comparators.
Problem fix/workaround
Software should clear the AC system flags once, after enabling the AC system before using the AC system status
flags.
2. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
3. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
34.4.2 Rev. H
Not sampled.
34.4.3 Rev. G
Not sampled.
34.4.4 Rev. F
Not sampled.
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34.4.5 Rev. E
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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Figure 34-5. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
424
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Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-5. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
18. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
19. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
20. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
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if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
21. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
22. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
23. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
24. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or
configure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
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PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
25. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
26. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
34.4.6 Rev. D
Not sampled.
34.4.7 Rev. C
Not sampled.
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34.4.8 Rev. B
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Writing EEPROM or Flash while reading any of them will not work
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
430
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Figure 34-6. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
431
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Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-6. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in
Active mode.
Problem fix/workaround
Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an
EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt.
Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has
started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode.
18. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
19. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
20. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
21. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
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Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
22. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
23. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
24. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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25. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or config-
ure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
26. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
27. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
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34.4.9 Rev. A
Not sampled.
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34.5 Atmel ATxmega256D3
34.5.1 Rev. I
AC system status flags are only valid if AC-system is enabled
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. AC system status flags are only valid if AC-system is enabled
The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not
possible to clear the AC interrupt flags without enabling either of the Analog comparators.
Problem fix/workaround
Software should clear the AC system flags once, after enabling the AC system before using the AC system status
flags.
2. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
3. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
34.5.2 Rev. H
Not sampled.
34.5.3 Rev. G
Not sampled.
34.5.4 Rev. F
Not sampled.
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34.5.5 Rev. E
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
Disabling the USART transmitter does not automatically set the TxD pin direction to input
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
439
XMEGA D3 [DATASHEET]
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Figure 34-7. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
440
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Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-7. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
442
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
18. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
19. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
20. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
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if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
21. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
22. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
23. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
24. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or
configure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
444
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PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
25. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
26. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
27. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
Problem fix/workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
34.5.6 Rev. D
Not sampled.
34.5.7 Rev. C
Not sampled.
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34.5.8 Rev. B
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8× – 64× gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in the XMEGA D Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Writing EEPROM or Flash while reading any of them will not work
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
Non available functions and options
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
Disabling the USART transmitter does not automatically set the TxD pin to input
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as
input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong
comparison result.
Problem fix/workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before
enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
446
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Figure 34-8. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and started from soft-
ware or event system.
Problem fix/workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
6LSB for reference voltage below 1.1V when VCC is above 3.0V.
20LSB for ambient temperature below 0°C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC
in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4V
The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only
give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range
of:
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
447
XMEGA D3 [DATASHEET]
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Problem fix/workaround
Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or
keep ADC voltage reference below 2.4V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8× – 64× gain is used
The propagation delay will increase by only one ADC clock cycle for all gain settings.
Problem fix/workaround
None.
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be
disregarded to achieve 12-bit accuracy.
Problem fix/workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA D Manual
Enabling Common Waveform Channel Mode will enable Pattern Generation Mode (PGM), but not Common
Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable
both Pattern Generation Mode and Common Waveform Channel Mode.
— 1× gain: 2.4 V
— 2× gain: 1.2 V
— 4× gain: 0.6 V
— 8× gain: 300 mV
— 16× gain: 150 mV
— 32× gain: 75 mV
— 64× gain: 38 mV
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Problem fix/workaround
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal
operation at first update after fault condition is no longer present.
Problem fix/workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is
below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the
programmed BOD level even if the BOD is disabled.
Problem fix/workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if
EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction
is executed, will be ignored until the device is woken from another source or the source triggers again. This
applies when entering all sleep modes where the System Clock is stopped.
Problem fix/workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output.
Problem fix/workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to
the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator
output.
Table 34-8. Configure PWM and CWCM According to this Table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in
Active mode.
Problem fix/workaround
Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an
EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt.
Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has
started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode.
18. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
19. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/workaround
None.
20. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/workaround
Clear the flag in software after address interrupt.
21. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.
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Problem fix/workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for
the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
22. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected,
the transaction will be dropped.
Problem fix/workaround
None.
23. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the
data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/workaround
Add one NOP instruction before checking DIF.
24. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register,
the counter can be cleared without giving a system reset.
Problem fix/workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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25. Non available functions and options
The below function and options are not available. Writing to any registers or fuse to try and enable or config-
ure these functions or options will have no effect, and will be as writing to a reserved address location.
TWIE, the TWI module on PORTE
TWI SDAHOLD option in the TWI CTRL register is one bit
CRC generator module
ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register
ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL
register
ADC option to use internal Gnd as negative input in differential measurements and this configuration option
in the MUXNEG bits in the ADC Channel MUXCTRL register
ADC channel scan and the ADC SCAN register
ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register
ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register
Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0
CTRLE register
Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers
PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0
and SPI, and the PORT REMAP register
PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register
PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in
the PORT CLKEVOUT register
TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2
Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and
32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the
Clock RTCTRL register
PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register
PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register
The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register
The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control
memory
Problem fix/workaround
None.
26. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
27. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
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28. Disabling of USART transmitter does not automatically set the TxD pin direction to input
If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD
pin direction to input.
Problem fix/workaround
The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register
to input will be immediate. Ongoing transmissions will be truncated.
34.5.9 Rev. A
Not sampled.
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34.6 Atmel ATxmega384D3
34.6.1 Rev. B
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Temperature sensor not calibrated
1. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in
sampled mode.
2. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/workaround
None.
34.6.2 Rev. A
Not sampled.
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35. Datasheet revision history
Note that the referring page numbers in this section are referred to this document. The referring revisions in this section
are referring to the document revision.
35.1 8134Q – 10/2015
35.2 8134P – 11/2014
35.3 8134O – 09/2014
35.4 8134N – 03/2014
1. Updated “Ordering Information” on page 2.
All ATxmegayyD3-MT and ATxmegayyD3-MTR changed respectively to ATxmegayyD3-MN and ATxmegayyD3-MNR
1. Changed EEPROM value for ATxmega32D3 to 1K in Section 1. “Ordering Information” on page 2, in Figure 7-2 on
page 16 and in Table 7-3 on page 18.
2. Section naming in Chapter “Typical Characteristics” has been corrected.
1. Updated “Ordering Information” on page 2. Added Ordering codes for the devices characterized @ 105C.
2. Updated “Electrical Characteristics” on page 63:
Updated Table 32-4 on page 65, Table 32-33 on page 84, Table 32-62 on page 103, Table 32-91 on page 122,
Table 32-120 on page 141 and Table 32-149 on page 160. Added ICC Power-down power consumption for
T=105C for all functions disabled and for WDT and sampled BOD enabled.
Updated,Table 32-17 on page 73, Table 32-46 on page 92, Table 32-75 on page 111, Table 32-104 on page
130, Table 32-133 on page 149, and Table 32-162 on page 168. Updated all tables to include values for T=85C
and T=105C. Removed T=55C.
3. Updated “Typical Characteristics” on page 177. Added 105C characteristics.
4. Changed Vcc to AVCC in Section 25. “ADC – 12-bit Analog to Digital Converter” on page 45 and Section 26. “AC –
Analog Comparator” on page 47.
5. Added ERRATA concerning disabling of the USART transmitter in Section 34.2 “Atmel ATxmega64D3” on page
389, Section 34.3 “Atmel ATxmega128D3” on page 405 and Section 34.5 “Atmel ATxmega256D3” on page 437.
1. Updated Table 28-2 on page 52. PORT PB1 has PIN# 7
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35.5 8134M – 07/2013
35.6 8134L – 07/2013
35.7 8134K – 05/2013
35.8 8134J – 03/2013
2. Updated Table 32-5 on page 66 and Table 32-34 on page 85: The condition for ADC updated from 200ksps to
16ksps, VREF = Ext. ref.
3. Added “ External 16MHz Crystal Oscillator and XOSC Characteristics” on page 95, 114, 133 and on page 171.
4. Updated the “Errata” on page 388:
Removed errata: “Crystal start-up time required after power-save even if crystal is source for RTC”
Added errata from Rev B and later: “Sampled BOD in Active mode will cause noise when bandgap is used
as reference”
1. “Pinout/block Diagram” on page 5: USART0 removed from Port F.
2. Typical chara, Figure 33-156 on page 255 and Figure 33-226 on page 290: Scale on Y-axis updated from mA to µA.
1. Added errata section for “Atmel ATxmega32D3” on page 388
2. Errata Temperature sensor not calibrated added to:
ATxmega64D3 “Rev. I” , “Rev. E” and “Rev. B” .
ATxmega128D3 “Rev. J” , “Rev. E” and “Rev. B” .
ATxmega192D3 “Rev. I” , “Rev. E” and “Rev. B” .
ATxmega256D3 “Rev. I” , “Rev. E” and “Rev. B” .
ATxmega384D3 “Rev. B” .
1. “Errata” is updated.
1. Almost all figures in Chapter “Typical Characteristics” are updated.
2. Added new Errata “Rev. G” on page 117.
3. Added new Errata “Rev. B” on page 125 and “Rev. E” on page 118. Non available functions and options.
4. Editing updates.
5. Added ATxmega32D3 and ATxmega384D3.
6. New datasheet template is added.
7. A lot of small corrections and a complete reorganization of “Electrical Characteristics” and “Typical Characteristics” .
8. Bullet “Optional Slew Rate Control” in Chapter “I/O Ports” on page 30 is removed.
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35.9 8134I – 12/2010
9. The sentence “The port pins also have configurable slew rate limitation to reduce electromagnetic emission” in
Chapter “I/O Ports” on page 30 is removed.
10.
The sentence “The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low
level input and output voltage limits reflect or exceed this specification” is added to Section 32.1.5 on page 68,
Section 32.2.5 on page 87, Section 32.6.5 on page 163, Section 33.5.2 on page 297 and Section 33.6.2 on
page 331.
11. Figure 2-1 on page 5 is updated by changing VDD to VCC.
12. Table 7-1 on page 15 is updated.
13. Figure 7-2 on page 16 is updated.
14. Figure 14-7 on page 33 is updated.
15.
Former Table 32-24, Table 32-52, Table 32-79, Table 32-107, Table 32-135, Table 32-163 (title: “External clock”) have
each been replaced by two new tables, named respectively “External clock used as system clock without prescaling”
and “External clock with prescaler for system clock”.
16. In Table 32-29 on page 81, Table 32-58 on page 100, Table 32-87 on page 119, Table 32-116 on page 138, Table
32-145 on page 157, and Table 32-174 on page 176 the value for the parameter “Input voltage” has been corrected.
17. In Table 32-18 on page 73, Table 32-47 on page 92, Table 32-76 on page 111, Table 32-105 on page 130, Table 32-
134 on page 149, and Table 32-163 on page 168 the parameter “Application erase” has been added.
18. Table 32-14 on page 72, Table 32-43 on page 91, Table 32-101 on page 129, Table 32-130 on page 148 and Table
32-159 on page 167 (Brownout detection characteristics) are updated.
19. Table 32-20 on page 74 and Table 32-49 on page 93 (2MHz internal oscillator characteristics) are updated.
20. Table 32-21 on page 74 and Table 32-50 on page 93 (32MHz internal oscillator characteristics) are updated.
21. Accuracy added in Table 32-109 on page 131.
22. Table 32-149 on page 160 has been corrected.
23 Table 32-167 on page 169; “Factory calibration accuracy” and “Accuracy” is added.
24. Table 32-150 on page 161, Table 32-152 on page 163, Table 32-154 on page 164, Table 32-155 on page 165, Table
32-156 on page 166, and Table 32-157 on page 166 has been updated.
25. Section 1. “Ordering Information” on page 2 is updated.
26. Former Section 31.3 “64Z3” has been removed.
27. Section 31.2 “64M” on page 62 has replaced the former Section 31.2 “64M2”.
1. Datasheet status changed to complete: Preliminary removed from front page.
2. Updated all tables in the The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83
the frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. on page 64.
3. Replaced Table 31-11 on page 67.
4. Replaced Table 31-17 on page 68 and added the figure “TOSC input capacitance” on page 78.
5. Added “Rev. E” on page 118.
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35.10 8134H – 09/2010
35.11 8134G – 08/2010
35.12 8134F – 02/2010
35.13 8134E – 01/2010
6. Updated ERRATA for ADC (ADC has increased INL error for some operating conditions).
7. Updated ERRATA “Rev. B” on page 125 with twie (TWIE is not available).
8. Updated the last page by Atmel new Brand Style Guide.
1. Updated “Errata” on page 388.
1. Updated the Footnote 3 of “Ordering Information” on page 2.
2. All references to CRC removed. Updated Figure 3-1 on page 5.
3. Updated “Features” on page 30.
4. Updated “DC Characteristics” on page 61 by adding Icc for Flash/EEPROM Programming.
5. Added AVCC in “ADC Characteristics” on page 68.
6. Updated Start up time in “ADC Characteristics” on page 68.
7. Updated and fixed typo in “Errata” on page 388.
1. Added “PDI Speed” on page 105.
1. Updated the device pin-out Figure 2-1 on page 5. PDI_CLK and PDI_DATA renamed only PDI.
2. Updated “ADC – 12-bit Analog to Digital Converter” on page 45.
3. Updated Figure 25-1 on page 46.
4. Updated “Alternate Pin Function Description” on page 50.
5. Updated “Alternate Pin Functions” on page 51.
6. Updated “Timer/counter and AWEX Functions” on page 50.
7. Added Table 31-17 on page 68.
8. Added Table 31-18 on page 69.
9. Changed internal oscillator speed to “Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in
continuous mode.” on page 108.
10. Updated “Errata” on page 388.
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35.14 8134D – 11/2009
35.15 8134C – 10/2009
35.16 8134B – 08/2009
35.17 8134A – 03/2009
1. Added Table 31-3 on page 64, Endurance and data retention.
2. Updated Table 31-10 on page 67, Input hysteresis is in V and not in mV.
3. Added “Errata” on page 388.
4. Editing updates.
1. Updated “Features” on page 1 with two-wire interfaces.
2. Updated “Pinout/block Diagram” on page 5.
3. Updated “Overview” on page 6.
4. Updated “XMEGA D# block diagram” on page 5.
5. Updated Table 13-1 on page 29.
6. Updated “Overview” on page 38.
7. Updated Table 28-5 on page 53.
8. Updated “Peripheral Module Address Map” on page 55.
1. Added The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83 the frequency vs.
VCC curve is linear between 1.8V < VCC < 2.7V. on page 64.
2. Added “Typical Characteristics” on page 177.
1. Initial revision.
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Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pinout/block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5. Capacitive Touch Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.7 Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.8 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.3 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.4 Fuses and Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.5 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.7 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.8 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.9 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.11 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9. System Clock and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.3 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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11. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 28
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.3 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
14.4 Input Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
14.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
16. TC2 – Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
18. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
19. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
20. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
21. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
21.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
22. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
iiiXMEGA D3 [DATASHEET]
Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
23. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
23.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
24. CRC – Cyclic Redundancy Check generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
24.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
25. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
25.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
26. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
26.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
27. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
27.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
28. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
28.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
28.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
29. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
30. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
31. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
31.1 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
31.2 64M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
32. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
32.1 Atmel ATxmega32D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
32.2 Atmel ATxmega64D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
32.3 Atmel ATxmega128D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
32.4 Atmel ATxmega192D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
32.5 Atmel ATxmega256D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
32.6 Atmel ATxmega384D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
33. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
33.1 Atmel ATxmega32D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
33.2 Atmel ATxmega64D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
33.3 Atmel ATxmega128D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
33.4 Atmel ATxmega192D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
33.5 Atmel ATxmega256D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
33.6 Atmel ATxmega384D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
34. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
34.1 Atmel ATxmega32D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
34.2 Atmel ATxmega64D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
34.3 Atmel ATxmega128D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
34.4 Atmel ATxmega192D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
34.5 Atmel ATxmega256D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
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Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015
34.6 Atmel ATxmega384D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
35. Datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
35.1 8134Q – 10/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
35.2 8134P – 11/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
35.3 8134O – 09/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
35.4 8134N – 03/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
35.5 8134M – 07/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
35.6 8134L – 07/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
35.7 8134K – 05/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
35.8 8134J – 03/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
35.9 8134I – 12/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
35.10 8134H – 09/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
35.11 8134G – 08/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
35.12 8134F – 02/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
35.13 8134E – 01/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
35.14 8134D – 11/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
35.15 8134C – 10/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
35.16 8134B – 08/2009. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
35.17 8134A – 03/2009. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
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© 2015 Atmel Corporation. / Rev.: Atmel-8134Q-AVR-ATxmega32D3-64D3-128D3-192D3-256D3-384D3-Datasheet_10/2015.
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