Description
Designed for pulse width modulated (PWM) current control of
DC motors, the A3959 is capable of output currents to ±3 A and
operating voltages to 50 V. Internal fixed off-time PWM current-
control timing circuitry can be adjusted via control inputs to
operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use
in controlling the speed and direction of a DC motor with
externally applied PWM-control signals. Internal synchronous
rectification control circuitry is provided to reduce power
dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge
pump, and crossover-current protection. Special power-up
sequencing is not required.
The A3959 provides a choice of three power packages, a 24-pin
DIP with batwing tabs (package suffix ‘B’), a 24-lead SOIC
with four internally-fused pins (package suffix ‘LB’), and a
thin (<1.2 mm) 28-pin TSSOP with an exposed thermal pad
(suffix ‘LP’). In all cases, the power pins and tabs are at ground
potential and need no electrical isolation. Each package is lead
(Pb) free, with 100% matte tin leadframes.
29319.37L
Features and Benefits
▪ ±3 A, 50 V Output Rating
▪ Low rDS(on) Outputs (270 m, Typical)
▪ Mixed, Fast, and Slow Current-Decay Modes
▪ Synchronous Rectification for Low Power Dissipation
▪ Internal UVLO and Thermal-Shutdown Circuitry
▪ Crossover-Current Protection
▪ Internal Oscillator for Digital PWM Timing
DMOS Full-Bridge PWM Motor Driver
Packages:
Functional Block Diagram
Not to scale
A3959
Package LP, 28-pin TSSOP
with exposed thermal pad
Package B, 24-pin DIP
with exposed tabs
Package LB, 24-pin SOIC
with internally fused pins
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP BANDGAP
REGULATOR
V
DD
V
BB
+
LOGIC
SUPPLY
V
REG
CP1
CP
CP2
LOAD
SUPPLY
GATE DRIVE
Dwg. FP-048-2A
CONTROL LOGIC
SENSE
R
S
SLEEP
EXT MODE
PHASE
ENABLE
BLANK
PFD1
PFD2
REFERENCE
BUFFER &
w10
CURRENT
SENSE
ZERO
CURRENT
DETECT
OUT
A
OUT
B
REF
PWM
TIMER
V
REF
C
S
OSC
ROSC
TO V
DD
TO VDD
DMOS Full-Bridge PWM Motor Driver
A3959
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Package Packing
A3959SB-T 24-pin DIP with exposed tabs 15 per tube
A3959SLBTR-T 24-pin SOIC with internally fused pins 1000 per reel
A3959SLPTR-T 28-pin TSSOP with exposed thermal pad 4000 per reel
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 50 V
Logic Supply Voltage VDD 7.0 V
Input Voltage VIN
Continuous –0.3 to VDD + 0.3 V
tw < 30 ns –1.0 to VDD + 1.0 V
Sense Voltage VS
Continuous 0.5 V
tw < 3 μs 2.5 V
Reference Voltage VREF VDD V
Output Current IOUT
Output current rating may be limited by duty cycle, am-
bient temperature, and heat sinking. Under any set of
conditions, do not exceed the specifi ed current rating
or a junction temperature of 150°C.
Repetitive ±3.0 A
Peak, < 3 μs±6.0 A
Package Power Dissipation PDSee Thermal Characteristics – –
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction Temperature TJ(max)
Fault conditions that produce excessive junction temperature will activate
the device’s thermal shutdown circuitry. These conditions can be toler-
ated but should be avoided.
150 ºC
Storage Temperature Tstg –55 to 150 ºC
DMOS Full-Bridge PWM Motor Driver
A3959
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
50 75 100 125 150
5
1
0
ALLOWABLE PACKAGE POWER DISSIPATION (W)
TEMPERATURE IN oo
ooC
4
3
2
25
SUFFIX 'B', R
QJA
= 36oC/W
SUFFIX 'LP', R
QJA
= 40oC/W
SUFFIX 'LB', R
QJA
= 51oC/W
2-LAYER BOARD,
1 SQ. IN. COPPER EA. SIDE
SUFFIX 'B', R
QJA
= 26oC/W
SUFFIX 'LP', R
QJA
= 28oC/W
SUFFIX 'LB', R
QJA
= 35oC/W
4-LAYER BOARD
Thermal Characteristics
Characteristic Symbol Test Conditions Value Units
Package Power Dissipation PD
B package 3.3 W
LB package 2.5 W
LP package 3.1 W
Package Thermal Resistance, Junction
to Ambient RθJA
B Package
1-layer PCB, minimal exposed copper area 54 ºC/W
2-layer PCB, 1-in.
2 2-oz copper exposed area 36 ºC/W
4-layer PCB, based on JEDEC standard 26 ºC/W
LB Package
1-layer PCB, minimal exposed copper area 77 ºC/W
2-layer PCB, 1-in.
2 2-oz copper exposed area 51 ºC/W
4-layer PCB, based on JEDEC standard 35 ºC/W
LP Package
1-layer PCB, minimal exposed copper area 100 ºC/W
2-layer PCB, 1-in.
2 2-oz copper exposed area 40 ºC/W
4-layer PCB, based on JEDEC standard 28 ºC/W
Package Thermal Resistance, Junction
to Tab RθJT B and LB packages 6 ºC/W
Package Thermal Resistance, Junction
to Pad RθJP LP package 2 ºC/W
*Additional thermal information available on Allegro website.
DMOS Full-Bridge PWM Motor Driver
A3959
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Continued next page …
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range VBB
Operating 9.5 – 50 V
During sleep mode 0 – 50 V
Output Leakage Current IDSS
VOUT = VBB – <1.0 20 μA
VOUT = 0 V – <-1.0 -20 μA
Output On Resistance rDS(on)
Source driver, IOUT = -3 A – 270 300 mΩ
Sink driver, IOUT = 3 A – 270 300 mΩ
Crossover Delay 300 600 1000 ns
Body Diode Forward Voltage VF
Source diode, IF = -3 A – – 1.6 V
Sink diode, IF = 3 A – – 1.6 V
Load Supply Current IBB
fPWM < 50 kHz – 4.0 7.0 mA
Charge pump on, outputs disabled – 2.0 5.0 mA
Sleep mode – – 20 μA
Control Logic
Logic Supply Voltage Range VDD Operating 4.5 5.0 5.5 V
Logic Input Voltage VIN(1) 2.0 – – V
VIN(0) – – 0.8 V
Logic Input Current
(all inputs except ENABLE)
IIN(1) VIN = 2.0 V – <1.0 20 μA
IIN(0) VIN = 0.8 V – <-2.0 -20 μA
Logic Supply Current IDD
fPWM < 50 kHz – 6.0 10 mA
Sleep mode – – 2.0 mA
ENABLE Input Current IIN(1) VIN = 2.0 V – 40 100 μA
IIN(0) VIN = 0.8 V – 16 40 μA
Internal OSC frequency fOSC
ROSC shorted to GROUND 3.25 4.25 5.25 MHz
ROSC = 51 kΩ3.65 4.25 4.85 MHz
Reference Input Volt. Range VREF Operating 0.0 – VDD V
Reference Input Current IREF VREF = VDD – – ±1.0 μA
Comparator Input Offset Voltage VIO VREF = 0 V – ±5.0 – mV
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V,
fPWM < 50 kHz (unless noted otherwise)
DMOS Full-Bridge PWM Motor Driver
A3959
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V,
fPWM < 50 kHz (unless noted otherwise)
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Reference Divider Ratio – – 10 – –
Gm Error
(Note 3) EGm
VREF = VDD – – ±4.0 %
VREF = 0.5 V – – ±14 %
Propagation Delay Times tpd
0.5 Ein to 0.9 Eout:
PWM change to source on 600 750 1200 ns
PWM change to source off 50 150 350 ns
PWM change to sink on 600 750 1200 ns
PWM change to sink off 50 100 150 ns
Thermal Shutdown Temp. TJ– 165 – °C
Thermal Shutdown Hysteresis ∆TJ–15 – °C
UVLO Enable Threshold UVLO Increasing VDD 3.90 4.2 4.45 V
UVLO Hysteresis ∆UVLO 0.05 0.10 – V
NOTES: 1. Typical Data is for design information only.
2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.
3. Gm error = ([VREF/10] – VSENSE)/(VREF/10) where VSENSE = ITRIP•RS.
DMOS Full-Bridge PWM Motor Driver
A3959
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL DESCRIPTION
VREG. This internally generated voltage is used to operate
the sink-side DMOS outputs. The VREG terminal should
be decoupled with a 0.22 μF capacitor to ground. VREG is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump. The charge pump is used to generate a
gate-supply voltage greater than VBB to drive the source-
side DMOS gates. A 0.22 μF ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22 μF ceramic capacitor should be connected between
CP and VBB to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
PHASE Logic. The PHASE input terminal determines if
the device is operating in the “forward” or “reverse” state.
PHASE OUTA OUTB
0 Low High
1 High Low
ENABLE Logic. The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.
ENABLE Outputs
0 Chopped
1 On
EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high, slow
decay mode, both sink drivers are on with ENABLE low.
EXT MODE Decay
0 Fast
1 Slow
Current Regulation. Load current is regulated by an
internal fi xed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (RS) and the
applied analog reference voltage (VREF):
ITRIP = VREF/10RS
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
fi xed off-time period. The current path during recirculation
is determined by the confi guration of slow/mixed/fast
current-decay mode via PFD1 and PFD2.
Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the ROSC
terminal to VDD. Typical value of 4 MHz is set with a
51 kΩ resistor. The allowable range of the resistor is from
20 kΩ to 100 kΩ.
fOSC = 204 x 109/ROSC.
If ROSC is not pulled up to VDD, it must be shorted to
ground.
Fixed Off Time. The A3959 is set for a fi xed off time of
96 cycles of the internal oscillator, typically 24 μs with a
4 MHz oscillator.
DMOS Full-Bridge PWM Motor Driver
A3959
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL DESCRIPTION (continued)
Internal Current-Control Mode. Inputs PFD1 and
PFD2 determine the current-decay method after an
overcurrent event is detected at the SENSE input. In slow-
decay mode, both sink drivers are turned on for the fi xed
off-time period. Mixed-decay mode starts out in fast-decay
mode for a portion (15% or 48%) of the fi xed off time, and
then is followed by slow decay for the remainder of the
period.
PFD2 PFD1 % toff Decay
0 0 0 Slow
0 1 15 Mixed
1 0 48 Mixed
1 1 100 Fast
PWM Blank Timer. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents
of the clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source-enable latch,
the sense comparator is blanked. The blank timer runs
after the off-time counter to provide the blanking function.
The blank timer is reset when ENABLE is chopped or
PHASE is changed. For external PWM control, a PHASE
change or ENABLE on will trigger the blanking function.
The duration is determined by the BLANK input and the
oscilator.
BLANK tblank
0 6/fosc
1 12/fosc
Synchronous Rectifi cation. When a PWM off cycle
is triggered, either by an ENABLE chop command or
internal fi xed off-time cycle, load current will recirculate
according to the decay mode selected by the control logic.
The A3959 synchronous rectifi cation feature will turn on
the appropriate pair of DMOS outputs during the current
decay and effectively short out the body diodes with the
low rDS(on) driver. This will reduce power dissipation
signifi cantly and can eliminate the need for external
Schottky diodes.
Synchronous rectifi cation will prevent reversal of load
current by turning off all outputs when a zero-current level
is detected.
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on CP or VREG) the outputs of
the device are disabled until the fault condition is removed.
At power up, and in the event of low VDD, the UVLO
circuit disables the drivers.
Braking. The braking function is implemented by
driving the device in slow-decay mode via EXTMODE
and applying an enable chop command. Because it is
possible to drive current in either direction through the
DMOS drivers, this confi guration effectively shorts out
the motor-generated BEMF as long as the ENABLE
chop mode is asserted. It is important to note that the
internal PWM current-control circuit will not limit the
current when braking, because the current does not fl ow
through the sense resistor. The maximum brake current
can be approximated by VBEMF/RL. Care should be taken
to ensure that the maximum ratings of the device are not
exceeded in worst-case braking situations of high speed
and high inertial loads.
SLEEP Logic. The SLEEP input terminal is used to
minimize power consumption when when not in use.
This disables much of the internal circuitry including the
regulator and charge pump. Logic low will put the device
into sleep mode, logic high will allow normal operation.
Note: If the sleep mode is not used, connect a 5 kΩ pull-
up resistor between the SLEEP terminal and VDD.
DMOS Full-Bridge PWM Motor Driver
A3959
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
FUNCTIONAL DESCRIPTION (continued)
Current Sensing. To minimize inaccuracies in
sensing the ITRIP current level, which may be caused by
ground trace IR drops, the sense resistor should have an
independent ground return to the ground terminal of the
device. For low-value sense resistors the IR drops in the
PCB sense resistor’s traces can be signifi cant and should
be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their
contact resistance.
The maximum value of RS is given as RS = 0.5/ITRIP.
Thermal Protection. Circuitry turns off all drivers
when the junction temperature reaches 165°C typically. It
is intended only to protect the device from failures due to
excessive junction temperatures and should not imply that
output short circuits are permitted. Thermal shutdown has
a hysteresis of approximately 15°C.
Layout. A star ground system located close to the driver
is recommended. The printed wiring board should use a
heavy ground plane. For optimum electrical and thermal
performance, the driver should be soldered directly onto
the board. The ground side of RS should have an indi-
vidual path to the ground terminals of the device. This path
should be as short as is possible physically and should not
have any other components connected to it. It is recom-
mended that a 0.1 μF capacitor be placed between SENSE
and ground as close to the device as possible; the load sup-
ply terminal, VBB, should be decoupled with an electrolyt-
ic capacitor (> 47 μF is recommended) placed as close to
the device as is possible. On the 28-lead TSSOP package,
the copper ground plane located under the exposed thermal
pad is typically used as a star ground.
DMOS Full-Bridge PWM Motor Driver
A3959
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PWM TIMER
V
BB
24
23
22
21
28
27
26
25
20
17
16
15
NC
SENSE
SLEEP
NO
CONNECTION
OUT
B
NC
LOAD SUPPLY
NC
OUT
A
NO
CONNECTION
EXT MODE
REF
V
REG
1
2
3
4
5
8
9
12
11
14
13
10
GROUND
GROUND
GROUND
CP
CP
2
CP
1
PHASE
NC
NC
V
DD
ENABLE
PFD
2
BLANK
PFD
1
LOGIC SUPPLY
Q
ROSC
LOGIC
NC
NC
CHARGE PUMP
÷
10
6
7
19
18
Terminal List
Package B (DIP)
PWM TIMER
÷10
V
BB
24
23
22
21
20
19
18
17
16
15
14
13
GROUND
GROUND
SLEEP
V
REG
OUT
B
LOAD
SUPPLY
SENSE
OUT
A
EXT MODE
REF
Dwg. PP-069-5A
1
2
3
4
5
6
7
8
9
12
11
10
9
GROUND
GROUND
CPCP
2
CP
1
PHASE
V
DD
LOGIC
SUPPLY
ENABLE
PFD
2
BLANK PFD
1
ıθ
ROSC
LOGIC
CHARGE PUMP
GROUND
GROUND
Package LB (SOIC)
PWM TIMER
V
BB
24
23
22
21
20
17
16
15
14
13
GROUND
GROUND
SLEEP
NO
CONNECTION
OUT
B
LOAD SUPPLY
SENSE
OUT
A
NO
CONNECTION
EXT MODE
REF
V
REG
Dwg. PP-069-4
1
2
3
4
5
8
9
12
11
10
GROUND
GROUND
CP
CP
2
CP
1
PHASE
V
DD
ENABLE
PFD
2
BLANK
PFD
1
LOGIC SUPPLY
Q
ROSC
LOGIC
NC
NC
CHARGE PUMP
÷
10
6
7
19
18
Package LP (TSSOP)
Terminal Name Terminal Description B (DIP) LB (SOIC) LP (TSSOP)
CP Reservoir capacitor (typically 0.22 μF) 24 1 1
CP1 & CP2 The charge pump capacitor (typically 0.22 μF) 1 & 2 2 & 3 2 & 3
NC No (internal) connection — — 4
PHASE Logic input for direction control 3 4 5
ROSC Oscillator resistor 4 5 6
GROUND Grounds 5, 6, 7, 8* 6, 7 7, 8*
LOGIC SUPPLY VDD, the low voltage (typically 5 V) supply 9 8 9
ENABLE Logic input for enable control 10 9 10
NC No (internal) connection – – 11
PFD2 Logic-level input for fast decay 11 10 12
BLANK Logic-level input for blanking control 12 11 13
PFD1 Logic-level input for fast decay 13 12 14
REF VREF, the load current reference input voltage 14 13 15
EXT MODE Logic input for PWM mode control 15 14 16
NO CONNECT No (Internal) connection — 15 17
OUTA One of two DMOS bridge outputs to the motor 16 16 18
NC No (internal) connection – – 19, 20
SENSE Sense resistor 17 17 21
NC No (internal) connection – – 22
GROUND Grounds 18, 19* 18, 19 —
LOAD SUPPLY VBB, the high-current, 9.5 V to 50 V, motor supply 20 20 23
OUTB One of two DMOS bridge outputs to the motor 21 21 24
NO CONNECT No (Internal) connection — 22 25
SLEEP Logic-level Input for sleep operation 22 23 26
VREG Regulator decoupling capacitor (typically 0.22 μF) 23 24 27
GROUND Ground — — 28*
* For the B (DIP) package only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5
and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. For the LP (TSSOP) package, the grounds at terminals 7, 8, and 28
should be connected together at the exposed pad beneath the device.
DMOS Full-Bridge PWM Motor Driver
A3959
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
B package 24-pin DIP
LB package 24-pin SOICW
2
0.018
1
24
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
For Reference Only
(reference JEDEC MS-001 BE)
Dimensions in millimeters
5.33 MAX
0.46 ±0.12
1.27 MIN
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
30.10 +0.25
–0.64
1.52 +0.25
–0.38
0.38 +0.10
–0.05
7.62
2.54
1.27
0.25
BReference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
B
0.20 ±0.10
0.41 ±0.10
2.20
0.65
9.60
1.27
21
24
A
15.40±0.20
2.65 MAX
10.30±0.33
7.50±0.10
C
SEATING
PLANE
C0.10
24X
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
GAUGE PLANE
SEATING PLANE PCB Layout Reference View
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
DMOS Full-Bridge PWM Motor Driver
A3959
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2001-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
LP package 28-pin TSSOP
1.20 MAX
0.10 MAX
C
SEATING
PLANE
C0.10
28X
6.10
0.65
0.45
1.65
3.00
3.00
5.00
5.00
0.25
0.65
21
28
GAUGE PLANE
SEATING PLANE
B
A
28
21
ATerminal #1 mark area
B
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
4.40 ±0.10 6.40 ±0.20
(1.00)
9.70 ±0.10
C
C
0.60 ±0.15
4° ±4
0.15 +0.05
–0.06
0.25 +0.05
–0.06
