OKI Semiconductor ML9261A FEDL9261A-01 Issue Date: Mar. 28, 2002 60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver GENERAL DESCRIPTION The ML9261A is a monolithic IC designed for directly driving the grid and anode of the vacuum fluorescent display (VFD) tube. The device contains a 60-bit shift register, a 60-bit register circuit, and 60 VFD tube driving circuits on a single chip. Display data is serially stored in the shift register at the rising edge of a clock pulse. Setting the CL pin low allows all the VFD tube driving circuits to be driven low, which makes it possible to set the display blanking. Also, setting both of the CL and CHG pins high allows all the VFD tube driving circuits to be driven high, which provides the easy testing of all lights after final assembly of a VFD tube panel. FEATURES * Logic Supply Voltage (VDD) : +3.3 V 10% or +5.0 V 10% * Driver Supply Voltage (VDISP) : +20 to +60 V * Driver Output Current IOHVH1 (Only one driver output: "H") : -40 mA (VDISP = 40 V) IOHVH2 (All the driver outputs: "H") : -120 mA (VDISP = 40 V) IOHVL : 1 mA * Directly connected to VFD tube by using push-pull output (Pull-down resistors are not needed) * Data Transfer Speed : 4 MHz * Package: 70-pin plastic SSOP (SSOP70-P-500-0.80-K) : ML9261AMB 1/16 FEDL9261A-01 OKI Semiconductor ML9261A BLOCK DIAGRAM VDISP VDD CL CHG LS DIN CLK RESET R C SI PO- D-1 O-1 HVO 1 PO-2 D-2 O-2 HVO 2 60-Bit Shift Register P0-60 L-GND D-GND RC 60-Bit Register D-60 O-60 HVO60 SO DOUT 2/16 FEDL9261A-01 OKI Semiconductor ML9261A PIN CONFIGURATION (TOP VIEW) ML9261A HVO 25 HVO 24 HVO 23 HVO 22 HVO 21 HVO 20 HVO 19 HVO 18 HVO 17 HVO 16 HVO 15 HVO 14 HVO 13 HVO 12 HVO 11 HVO 10 HVO 9 HVO 8 HVO 7 HVO 6 HVO 5 HVO 4 HVO 3 HVO 2 HVO 1 VDISP VDD DIN DOUT CLK LS CL CHG L-GND D-GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 HVO 26 HVO 27 HVO 28 HVO 29 HVO 30 HVO 31 HVO 32 HVO 33 HVO 34 HVO 35 HVO 36 HVO 37 HVO 38 HVO 39 HVO 40 HVO 41 HVO 42 HVO 43 HVO 44 HVO 45 HVO 46 HVO 47 HVO 48 HVO 49 HVO 50 HVO 51 HVO 52 HVO 53 HVO 54 HVO 55 HVO 56 HVO 57 HVO 58 HVO 59 HVO 60 70-Pin Plastic SSOP (SSOP70-P-500-0.80-K) 3/16 FEDL9261A-01 OKI Semiconductor ML9261A PIN DESCRIPTION Symbol Type Description CLK l Shift register clock input pin. Shift register reads data from DIN while the CLK pin is low and the data in the shift register is shifted from one stage to the next stage at the rising edge of the clock. DIN I Serial data input pin of the shift register. Display data (positive logic) is input in the DIN pin in synchronization with clock. DOUT O Serial data output pin of the shift register. Data is output from the DOUT pin in synchronization with the CLK signal. I Latch strobe input pin. The contents of the parallel outputs (PO1 to PO60) of the shift register are read at the rising edge of LS (edge-triggered). When the CLK rises while LS is high, the parallel outputs (PO1 to PO60) and latch outputs (O1 to O60) go low. I Clear input pin with a built-in pull-down resistor. The CL pin is normally set high. If the CL pin is high and the CHG pin is low, the driver outputs (HVO1 to HVO60) are in phase with the corresponding register outputs (O1 to O60). If the CL pin is high and the CHG pin is high, the driver outputs (HVO1 to HVO60) are high irrespective of the states of the register outputs. If the CL pin is set low, the driver outputs are driven low irrespective of the states of the CHG pin and register outputs. This allows display blanking to be set. I Input for testing (with a pull-down resistor). The CL pin is normally set low. If the CHG pin is low and the CL pin is high, the driver outputs (HVO1 to HVO60) are in phase with the corresponding register outputs (O1 to O60). If the CHG pin is low and the CL pin is low, the driver outputs (HVO1 to HVO60) are low irrespective of the states of the register outputs. If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the register outputs. This provides the easy testing of all lights after final assembly. O High voltage driver outputs for driving a VFD tube. If the CL pin is high and the CHG pin is low, the driver outputs are in phase with the corresponding register outputs (O1 to O60). The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors. LS CL CHG VHO1-60 VDISP Power supply pin for VFD tube driver circuits VDD Power supply pin for logic D-GND GND pin for VFD tube driver circuits. Since the D-GND pin is not connected internally to the L-GND pin, connect these pins outside of the IC. L-GND GND pin for the logic circuits. Since the L-GND pin is not connected internally to the D-GND pin, connect thiese pins outside of the IC. 4/16 FEDL9261A-01 OKI Semiconductor ML9261A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Supply Voltage (1) *1 VDD Applicable to logic supply pin -0.3 to +6.5 V Supply Voltage (2) *1, *2 VDISP Applicable to driver supply pin -0.3 to +70 V Applicable to all input pins -0.3 to VDD +0.3 V Input Voltage *1 VIN Output Voltage *1 VO Applicable to DOUT -0.3 to VDD +0.3 V lO Applicable to HVO1 to HVO60 -50 to 0.0 mA VHVO Applicable to HVO1 to HVO60 -0.3 to VDISP +0.3 V Power Dissipation PD Ta 25C 1.47 W Package Thermal Resistance *3 Rj-a Ta > 25C 68 C/W Storage Temperature TSTG -- -55 to +150 C Output Current Withstand Output Voltage *1, *2 Notes: *1 Supply Voltage for L-GND and D-GND *2 Permanent damage may be caused if the voltage is supplied over the rating value. *3 Package Thermal Resistance (between junction and ambient) The junction temperature (Tj) expressed by the equation indicated below should not exceed 125C under the operating conditions. Tj = P x Rj-a + Ta (P: Maximum power consumption) 5/16 FEDL9261A-01 OKI Semiconductor ML9261A RECOMMENDED OPERATING CONDITIONS-1 Unit Power Supply: 5.0 V (Typ.) Parameter Symbol Condition Min. Typ. Max. Unit Power Supply (1) VDD -- 4.5 5.0 5.5 V Power Supply (2) VDISP -- 20 -- 60 V "H" Input Voltage VIH Applicable to all inputs 0.7 VDD -- -- V "L" Input Voltage Driver Output Current VIL Applicable to all inputs -- -- 0.3 VDD V lOHVH1 Only 1 output is ON. -- -- -40 mA lOHVH2 All outputs are ON. -- -- -120 mA CLK Frequency fCLK -- -- -- 4.0 MHz Operating Temperature TOP -- -40 -- +85 C RECOMMENDED OPERATING CONDITIONS-2 Unit Power Supply: 3.3 V (Typ.) Symbol Condition Min. Typ. Max. Unit Power Supply (1) Parameter VDD -- 3.0 3.3 3.6 V Power Supply (2) VDISP -- 20 -- 60 V "H" Input Voltage VIH Applicable to all inputs 0.8 VDD -- -- V "L" Input Voltage VIL Applicable to all inputs -- -- 0.2 VDD V lOHVH1 Only 1 output is ON. -- -- -40 mA Driver Output Current lOHVH2 All outputs are ON. -- -- -120 mA CLK Frequency fCLK -- -- -- 4.0 MHz Operating Temperature TOP -- -40 -- +85 C 6/16 FEDL9261A-01 OKI Semiconductor ML9261A ELECTRICAL CHARACTERISTICS DC Characteristics-1 (VDD = 4.5 to 5.5 V, VDISP = 20 to 60 V, Ta = -40 to +85C) Parameter Symbol Applicable pin Condition Min. Typ. Max. Unit "H" Input Voltage VIH All inputs -- 0.7 VDD -- -- V "L" Input Voltage VIL All inputs -- -- -- 0.3 VDD V lIH1 DIN, CLK, LS VDD = VIN = 5.5 V -1.0 -- +1.0 A IIH2 CL, CHG VDD = VIN = 5.5 V 5.0 -- 80 A IIL All inputs VDD = 5.5 V, VIN = 0 V -1.0 -- +1.0 A "H" Input Current "L" Input Current Input Capacitance "H" Output Voltage "L" Output Voltage Supply Current CIN All inputs Ta = 25C -- 15 -- pF VOH1 DOUT IOH = -0.1 mA VDD-1 -- -- V VOH2 HVO1 to 60 VDISP-4 -- -- V VOL1 DOUT -- -- 1.1 V VOL2 HVO1 to 60 -- -- 3.0 V IDD1 VDD All inputs: "L" -- -- 10.0 A All inputs: "H" -- -- 10.0 A All inputs: "L" -- -- 70.0 A All inputs: "H" -- -- 70.0 A IDD2 VDD IDISP1 VDISP IDISP2 VDISP VDISP = 40 V IOH = -40 mA IOL = 0.1 mA VDISP = 40 V IOL = 1 mA No load DC Characteristics-2 (VDD = 3.0 to 3.6 V, VDISP = 20 to 60 V, Ta = -40 to +85C) Symbol Applicable pin Condition Min. Typ. Max. Unit "H" Input Voltage Parameter VIH All inputs -- 0.8 VDD -- -- V "L" Input Voltage VIL All inputs -- -- -- 0.2 VDD V "H" Input Current "L" Input Current Input Capacitance "H" Output Voltage "L" Output Voltage Supply Current lIH1 DIN, CLK, LS VDD = VIN = 3.3 V -1.0 -- +1.0 A IIH2 CL, CHG VDD = VIN = 3.3 V 2.0 -- 50 A IIL All inputs VDD = 3.3 V, VIN = 0 V -1.0 -- +1.0 A CIN All inputs Ta = 25C -- 15 -- pF VOH1 DOUT IOH = -0.1 mA VDD-1 -- -- V VOH2 HVO1 to 60 VDISP-4 -- -- V VOL1 DOUT -- -- 1.1 V VOL2 HVO1 to 60 -- -- 3.0 V IDD1 VDD All inputs: "L" -- -- 10.0 A IDD2 VDD All inputs: "H" -- -- 10.0 A IDISP1 VDISP All inputs: "L" -- -- 70.0 A IDISP2 VDISP All inputs: "H" -- -- 70.0 A VDISP = 40 V IOH = -40 mA IOL = 0.1 mA VDISP = 40 V IOL = 1 mA No load 7/16 FEDL9261A-01 OKI Semiconductor ML9261A AC Characteristics-1 (VDD = 4.5 to 5.5 V, VDISP = 20 to 60 V, Ta = -40 to +85C) Symbol Condition Min. Max. Unit CLK Pulse Width Parameter tW (CLK) -- 80 150 ns DIN Setup Time tSU (D-CLK) -- 50 -- ns DIN Hold Time tH (CLK-D) -- 50 -- ns tSU (CLK-LS) -- 50 -- ns tSU (LS-CLK) During normal operation 50 -- ns tSU (L-CLK) At display data reset 50 -- ns tH (CLK-L) At display data reset 50 -- ns tSU (LS-CHG) -- 50 -- ns tSU (LS-CL) -- 50 -- ns CLK-LS Setup Time LS-CLK Setup Time CLK-LS Hold Time LS-CHG Setup Time LS-CL Setup Time LS Pulse Width tW (LS) -- 80 -- ns tW (CHG) -- 10 -- s CL Pulse Width tW (CL) -- 10 -- s DOUT Delay time tPD, tPRD CHG Pulse Width Driver Output Delay Time Driver Output Slew Rate Load: 30 pF -- 50 ns tDLH VDISP = 40 V -- 2.0 s tDHL -- 2.0 s tDRHL Load: 1.0 k resistance in parallel with 20 pF capacitance -- 2.0 s tTLH VDISP = 40 V -- 5.0 s tTHL Load: 1.0 k resistance in parallel with 20 pF capacitance -- 5.0 s AC Characteristics-2 (VDD = 3.0 to 3.6 V, VDISP = 20 to 60 V, Ta = -40 to +85C) Symbol Condition Min. Max. Unit CLK Pulse Width Parameter tW (CLK) -- 80 150 ns DIN Setup Time tSU (D-CLK) -- 50 -- ns DIN Hold Time CLK-LS Setup Time LS-CLK Setup Time CLK-LS Hold Time LS-CHG Setup Time LS-CL Setup Time LS Pulse Width tH (CLK-D) -- 50 -- ns tSU (CLK-LS) -- 50 -- ns tSU (LS-CLK) During normal operation 50 -- ns tSU (L-CLK) At display data reset 50 -- ns tH (CLK-L) At display data reset 50 -- ns tSU (LS-CHG) -- 50 -- ns tSU (LS-CL) -- 50 -- ns tW (LS) -- 80 -- ns tW (CHG) -- 10 -- s CL Pulse Width tW (CL) -- 10 -- s DOUT Delay time tPD, tPRD CHG Pulse Width Driver Output Delay Time Driver Output Slew Rate Load: 30 pF -- 50 ns tDLH VDISP = 40 V -- 3.0 s tDHL -- 3.0 s tDRHL Load: 1.0 k resistance in parallel with 20 pF capacitance -- 3.0 s tTLH VDISP = 40 V -- 5.0 s tTHL Load: 1.0 k resistance in parallel with 20 pF capacitance -- 5.0 s 8/16 tSU(D-CLK) HVO (OTHERS) HVO (1, 2, 59, 60) CL CHG LS DOUT DIN CLK tH(CLK-D) T1/2 1/fCLK T3/4 tDLH tSU(LS-CL) tSU(CLK-LS) tPD T1/2 tPD tTLH tDLH tTLH tDHL tSU(LS-CHG) tW(CHG) tW(CHG) tW(LS) tSU(LS-CLK) T59/60 tW(CLK) T3/4 tTHL tTHL tDHL tW(CL) tW(CL) FEDL9261A-01 OKI Semiconductor ML9261A TIMING DIAGRAMS Normal Display Operation 9/16 HVO (OTHERS) HVO (1, 2, 59, 60) CL CHG LS DOUT DIN CLK T1/2 T3/4 T59/60 tSU(L-CLK) tDRHL tH(CLK-L) tPRD T1/2 FEDL9261A-01 OKI Semiconductor ML9261A Display Data Reset Operation 10/16 FEDL9261A-01 OKI Semiconductor ML9261A FUNCTIONAL DESCRIPTION Display Data Reset When the power is turned on, the shift register outputs (PO1 to PO60) and register outputs (O1 to O60) are indeterminate. Consequently the display of a VFD tube may flicker because unnecessary driver outputs go high. To prevent such flicker, it is required to perform the following operations. 1. Turn on the logic power supply while the CL input is kept low. 2. Set the LS input high. 3. Switch the CLK input from a low level to a high level at least once. By performing the above operations, all of the shift register outputs (PO1 to PO60) and register outputs (O1 to O60) are set low. 4. Enter display data. 5. Set the CL input high. Data Transfer Write display data by using a serial transfer. Serial data is input in the shift register at the rising edge of a CLK input pulse. When the LS input rises, display data is written in the latch. Driver Output Control 1. To turn on or off driver outputs by using display data transferred into the shift register, set the CL input high and set the CHG input low. 2. To set all the driver outputs low, set the CL input low. 3. To set all the driver outputs high, set the CL input and CHG input high at a time. 11/16 FEDL9261A-01 OKI Semiconductor ML9261A Function Table Shift register Input CLK Shift Register Parallel Out Output DIN LS PO1 PO2 **** PO59 PO60 DOUT H L H PO1n **** PO58n PO59n PO59n L L L PO1n **** PO58n PO59n PO59n X L PO1n PO2n **** PO59n PO60n PO60n X H L L **** L L L X: Don't Care PO1n to PO59n: PO1 to PO59 data just before CLOCK rises. Register Input CLK Shift Register Parallel Out Latch Output POm Om H H LS X X L L X X No Change L L H X: Don't Care, m: 1 to 60 Driver output Input CL CHG CLK Latch Output Output LS Om HVOm H L X X H H H L X X L L H H X X X H L X X X X L X X H L L X: Don't Care, m: 1 to 60 12/16 FEDL9261A-01 OKI Semiconductor ML9261A TEST CIRCUIT 20 pF VDISP HVO1 VDD 1.0 k 20 pF HVO2 1.0 k 20 pF HVO60 1.0 k 30 pF DOUT DIN CLK LS CL CHG L-GND D-GND NOTES ON POWER APPLICATION Connect L-GND and G-GND pins externally to provide the equal potential. To prevent IC erroneous operation, turn on VDD before turning on VDISP, and turn off VDISP before turning off VDD. Voltage VDISP voltage VDD voltage Time 13/16 FEDL9261A-01 OKI Semiconductor ML9261A PACKAGE DIMENSIONS (Unit: mm) SSOP70-P-500-0.80-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 2.15 TYP. 3/Dec. 5, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/16 FEDL9261A-01 OKI Semiconductor ML9261A REVISION HISTORY Document No. PEDL9261A-01 Date Jan. 22, 2002 Page Previous Current Edition Edition - - Description Preliminary first edition Removed Preliminary classification. 1 5 1 5 The following contents of "FEATURES" have been revised: * "Logic Supply Voltage (VCC)" to "Logic Supply Voltage (VDD)". * "Drive Supply Voltage (VHV): +60 V" to "Drive Supply Voltage (VDISP): +20 to +60 V". Rating and Unit of Parameter "Power Dissipation" in the table have been revised from 1.9 and mW to 1.47 and W, respectively. Partially changed the content of Note *3. FEDL9261A-01 Mar. 28, 2002 7 7 Removed (Design Goal) from "Supply Current" in the two tables. 12 12 Symbol "PO2n" has been changed to Symbol "PO1n" in Column "PO2" of Column "Shift Register Parallel Out". 13 13 Parameter The test circuit has been partially changed. "The logic power supply" and "the driver power supply" have been changed to VDD and VDISP in the sentence of "NOTES ON POWER APPLICATIONS". Changed "VDISP pin voltage" and "VDD pin voltage" to "VDISP voltage" and VDD voltage" in the bottom figure. 15/16 FEDL9261A-01 OKI Semiconductor ML9261A NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 16/16