Preliminary Data Sheet Integrator Series FPGAs - 40MX and 42MX Families Features * Supported by Actel Designer Series development system with interfaces to popular design environments such as Cadence, Exemplar, IST, Mentor Graphics, Synopsys, Synplicity, and Viewlogic * Low power consumption (less than 100A in stand-by mode) * JTAG 1149.1 boundary scan testing High Capacity * * * * 2,000 to 52,000 available logic gates Up to 3 Kbits configurable dual-port SRAM Fast wide-decode circuitry Up to 250 user-programmable I/O Pins High Performance * * * * * 5.0V and 3.3V Programmable PCI-compliant I/O 250 MHz performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-bit Address Decode General Description Actel's new MX family of programmable logic devices provides system logic designers with a high-performance, cost-effective ASIC alternative in a single Actel FPGA. Ease of Integration * Mixed voltage operation (3.3 V or 5 V I/O) * Synthesis-friendly architecture to support ASIC design methodologies * 95-100% resource utilization, using automatic place-and-route tools with up to 100% pin fixing * Deterministic, user-controllable timing via DirectTime software tools The MX family architecture is based on Actel's patented antifuse technology, implemented in a 0.45 triple-metal CMOS process. With capacities ranging from 2,000 to 52,000 gates, the synthesis-friendly MX family of devices provides data paths up to 250 MHz, are live on power-up, and deliver up to five times lower stand-by power consumption than any other FPGA device. With up to 250 I/O the MX FPGAs are available in a wide variety of packages. Integrator Series Product Profile Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 A42MX52 2,000 1,200 N/A 4,000 2,000 N/A 9,000 4,000 N/A 16,000 8,000 N/A 24,000 14,000 N/A 36,000 20,000 2,560 52,000 30,000 3,072 -- 295 -- -- 547 -- 348 336 N/A 624 608 N/A 954 912 24 1230 1184 24 1888 1833 28 SRAM Modules (64x4 or 32x8) NA NA NA NA NA 10 12 Dedicated Flip-Flops -- -- 348 624 954 1,276 1,944 Capacity Gates ASIC Equivalent Gates SRAM Bits Logic Modules Sequential Combinatorial Decode Clocks User I/O (maximum) JTAG Packages S e p t e m b e r 1997 (c) 1997 Actel Corporation 1 1 2 2 2 6 6 57 69 104 140 176 202 250 No No No No Yes Yes Yes PL44 PL68 PQ100 VQ80 PL44 PL68 PL68 PQ100 VQ80 PL84 PQ100 PQ160 TQ176 PL84 PQ160 PQ208 TQ176 PL84 PQ160 PQ208 TQ176 PQ208 RQ208 RQ240 RQ208 RQ240 1-91 The MX Integrator family is comprised of the 40MX and the 42MX FPGAs. The 42MX devices also feature Actel's I/O which supports mixed voltage systems. I/Os can operate with either 0V to 5.0V swing, for 5.0V input tolerance, for 3.3V and mixed 5.0V/3.3V system operation. The logic core can be operated at 5.0V for maximum performance; or at 3.3V for minimum power consumption. The 42MX FPGA devices include system-level features such as JTAG, dual-port SRAM, fast wide-decode modules, and a programmable PCI interface. The 42MX FPGAs were designed to integrate system logic that is typically implemented in multiple CPLDs, PALs and FPGAs. The 42MX family offers the industry's fastest dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The large number of storage elements can efficiently address applications requiring wide data-path manipulation and can transformation functions such as telecommunications, networking, and DSP. Power consumption can be reduced to 100A, providing an excellent solution for low-power systems. MultiPlex I/O includes selectable PCI output drives in certain 42MX devices, enabling 100% PCI compliance for both 5.0V and 3.3V systems. Ordering Information A42MX16 - PQ 100 Application (Temperature Range) Blank = Commercial (0 to +70C) I = Industrial (-40 to +85C) Package Lead Count Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flatpack RQ = Plastic Power Quad Flatpack TQ = Thin (1.4 mm) Quad Flatpack VQ = Very Thin (1.0 mm) Quad Flatpack Speed Grade Blank = Standard Speed 1 = Approximately 15% faster than Standard 2 = Approximately 25% faster than Standard 3 = Approximately 35% faster than Standard F = Approximately 40% slower than Standard Part Number A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 A42MX52 1-92 = = = = = = = 2,000 Gates 4,000 Gates 9,000 Gates 16,000 Gates 24,000 Gates 36,000 Gates 52,000 Gates In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Product Plan Speed Grade Application Std -1* -2* -3* -F* C I M B 44-pin Plastic Leaded Chip Carrier (PLCC) -- -- 68-pin Plastic Leaded Chip Carrier (PLCC) -- -- 100-pin Plastic Quad Flatpack (PQFP) -- -- 80-pin Very Thin Plastic Quad Flatpack (VQFP) -- -- 44-pin Plastic Leaded Chip Carrier (PLCC) -- -- 68-pin Plastic Leaded Chip Carrier (PLCC) -- -- 84-pin Plastic Leaded Chip Carrier (PLCC) -- -- 100-pin Plastic Quad Flatpack (PQFP) -- -- 80-pin Very Thin Plastic Quad Flatpack (VQFP) -- -- 84-pin Plastic Leaded Chip Carrier (PLCC) -- -- -- 100-pin Plastic Quad Flatpack (PQFP) -- -- -- 160-pin Plastic Quad Flatpack (PQFP) -- -- -- 176-pin Thin Plastic Quad Flatpack (TQFP) -- -- -- 84-pin Plastic Leaded Chip Carrier (PLCC) -- -- -- 100-pin Plastic Quad Flatpack (PQFP) -- -- -- 160-pin Plastic Quad Flatpack (PQFP) -- -- -- 208-pin Plastic Quad Flatpack (PQFP) -- -- -- 176-pin Thin Plastic Quad Flatpack (TQFP) -- -- -- 84-pin Plastic Leaded Chip Carrier (PLCC) -- -- -- 160-pin Plastic Quad Flatpack (PQFP) -- -- -- 208-pin Plastic Quad Flatpack (PQFP) -- -- -- 176-pin Thin Plastic Quad Flatpack (TQFP) -- -- -- 208-pin Plastic Quad Flatpack (PQFP) -- -- -- 208-pin Plastic Power Quad Flatpack (RQFP) -- -- -- 240-pin Plastic Power Quad Flatpack (RQFP) -- -- -- 208-pin Plastic Power Quad Flatpack (RQFP) P P P -- P P P -- -- 240-pin Plastic Power Quad Flatpack (RQFP) P P P -- P P P -- -- A40MX02 Device A40MX04 Device A42MX09 Device A42MX16 Device A42MX24 Device A42MX36 Device A42MX52 Device Applications: C I M B = = = = Commercial Industrial Military MIL-STD-883 Availability: = Available P = Planned -- = Not Planned * Speed Grade: -1 -2 -3 -F = = = = Approx. 15% faster than Standard Approx. 25% faster than Standard Approx. 35% faster than Standard Approx. 40% slower than Standard 1-93 Integrator Series devices are supported by Actel's Designer Series development software, which provides a seamless integration into any ASIC design flow. The Designer Series development tools offer automatic placement and routing (even with preassigned pins), static timing analysis, user programming, and debug and diagnostic probe capabilities. In addition, the DirectTime tool provides deterministic as well as controllable timing. DirectTime allows the designer to specify the performance requirements of individual paths and system clocks. Using these specifications, the software will automatically optimize the placement and routing of the logic to meet the constraints. Included with the Designer Series tools is Actel's ACTgenTM Macro Builder. ACTgen allows the designer quickly to build fast, efficient logic functions such as counters, adders, FIFOs, and RAM. The Designer Series tools provide designers with the capability to move up to high-level description languages, such as VHDL and Verilog, or to use schematic design entry with interfaces to most EDA tools. Designer Series is supported on 486 and Pentium PCs and on Sun(R) and HP(R) workstations. The software provides CAE interfaces to Cadence, Mentor Graphics(R), Escalade, OrCADTM and Viewlogic(R) design environments. Additional development tools are supported through Actel's Industry Alliance Program, including DATA I/O (ABEL FPGA) and MINC. Actel's FPGAs are an ideal solution for shortening the system design and development cycle, and they offer a cost-effective alternative for low-volume production runs. The 40MX and 42MX devices are an excellent choices for integrating logic that is currently implemented in multiple PALs, CPLDs, and FPGAs. Some example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and coprocessor functions. Plastic Device Resources User I/Os PLCC 44-pin PLCC 68-pin PLCC 84-pin VQFP 80-pin PQFP 100-pin PQFP 160-pin PQFP 208-pin RQFP 208-pin RQFP 240-pin TQFP 176-pin A40MX02 34 57 -- 57 57 -- -- -- -- -- A40MX04 34 57 69 69 69 -- -- -- -- -- A42MX09 -- -- 72 -- 83 104 -- -- -- 103 A42MX16 -- -- 72 -- 83 125 140 -- -- 140 A42MX24 -- -- 72 -- -- 125 176 -- -- 150 A42MX36 -- -- -- -- -- -- 176 176 202 -- A42MX52 -- -- -- -- -- -- -- 176 202 -- Device Package Definitions (Consult your local Actel sales representative for product availability.) PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, RQFP = Plastic Power Quad Flat Pack 1-94 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Pin Description QCLKA/B,C,D Quadrant Clock (Input/Output) CLK, CLKA, CLKB Clock Clock A and Clock B (input) Quadrant clock inputs. When not used as a register control signal, these pins can function as general-purpose I/O. TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) SDI TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. TCK GND TDI Ground (Input) Input LOW supply voltage. I/O Input/Output (Input, Output) Input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the Designer Series software. MODE Mode (Input) Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). When the MODE pin is HIGH, the special functions are active. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. To turn off input/output devices for low-power mode, MODE pin must be HIGH. NC No Connection Not connected to circuitry within the device. PRA/I/O Probe A (Output) Used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB/I/O Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. Test Clock Clock signal to shift the JTAG data into the device. This pin functions as an I/O when the JTAG fuse is not programmed. Test Data In Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. TDO Test Data Out Serial data output for JTAG instructions and test data. This pin functions as an I/O when the JTAG fuse is not programmed. TMS Test Mode Select Serial data input for JTAG test mode. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. V CC Supply Voltage (Input) Input HIGH supply voltage. V CCA Supply Voltage (Input) Input HIGH supply voltage, supplies array core only. V CCI Supply Voltage (Input) Input HIGH supply voltage, supplies I/O cells only. Note: TCK, TDI, TDO, TMS are available only on devices containing JTAG circuitry. Probe B (Output) Used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. 1-95 Connecting V C C on MX Devices 40MX The 40MX FPGAs will operate in 5.0V only systems, or 3.3V only systems. VCC Input Output 3.3V 3.3V 3.3V 5.0V 5.0V 5.0V 42MX The 42MX FPGAs will operate in 5.0V only systems, 3.3V only systems, or mixed 5.0V/3.3V systems. VCCA VCCI Input Output 3.3V 3.3V 3.3V 3.3V 5.0V 3.3V 3.3V, 5.0V 3.3V 5.0V 5.0V 5.0V 5.0V Integrator Series Architectural Overview The 40MX and 42MX devices are composed of fine-grained building blocks that produce fast, efficient logic designs. All devices within the Integrator Series are composed of logic modules, routing resources, clock networks, and I/O modules, which are the building blocks for designing fast logic designs. In addition, a subset of devices contain embedded dual-port SRAM and wide decode modules. The dual-port SRAM modules are optimized for high-speed data-path functions such as FIFOs, LIFOs, and scratchpad memory. The "Integrator Series Product Profile" on page 1-91, lists the specific logic resources contained within each device. Logic Modules The 40MX logic module is an eight-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 1). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different combinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the array, since latches and flip-flops can be constructed from logic modules wherever needed in the application. 1-96 Figure 1 * 40MX Logic Module In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules), and decode (D-modules). A0 B0 S0 The C-module is shown in Figure 2 and implements the following function: D00 Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D01+S1*S0*D11 D00 Y where S0=A0*B0 D10 S1=A1+B1 D11 The S-module shown in Figure 3 is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D flip-flop or a transparent latch. To increase flexibility, the S-module register can be by passed so that it implements purely combinatorial logic. D00 S1 A1 B1 Figure 2 * C-module Implementation D00 D01 Y D10 D Q OUT D11 CLR S1 Y D10 S0 D11 D01 S0 D Q OUT GATE S1 Up to 7-input function plus D-type flip-flop with clear Up to 7-input function plus latch D00 D0 D01 Y D1 S D Q OUT GATE CLR Up to 4-input function plus latch with clear Y OUT D10 D11 S1 S0 Up to 8-input function (same as C-module) Figure 3 * S-module Implementation 1-97 Some of the 42MX devices contain a third type of logic module, D-modules, which are arranged around the peripheries of the devices. D-modules contain wide-decode circuitry, which provides a fast, wide-input AND function similar to that found in product term architectures (Figure 4). The D-module allows 42MX devices to perform wide-decode functions at speeds comparable to CPLDs and PAL devices. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hard-wired to an output pin, or it can be fed back into the array to be incorporated into other logic. 7 inputs Hardwire to I/O Programmable inverter Feedback to array Dual-Port SRAM Modules Several 42MX devices contain dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as 32 x 8 or 64 x 4. (Refer to the "Integrator Series Product Profile" table, on page 1-91, for the number of SRAM blocks within a particular device.) SRAM WD[7:0] Figure 4 * D-Module Implementation modules can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the 42MX dual-port SRAM block is shown in Figure 5. Latches [7:0] [5:0] [5:0] WRAD[5:0] Write Port Logic SRAM Module 32 x 8 or 64 x 4 (256 bits) RDAD[5:0] Latches Read Logic Latches REN RCLK MODE BLKEN WEN Read Port Logic RD[7:0] Write Logic WCLK Routing Tracks Figure 5 * 42MX Dual-Port SRAM Block The 42MX SRAM modules are true dual-port structures containing independent Read and Write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64 x 4 bit blocks. When configured in byte mode, the highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering 1-98 active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]) which are connected to segmented vertical routing tracks. The 42MX dual-port SRAM blocks are ideal for high-speed buffered applications requiring fast FIFO and LIFO queues. Actel's ACTgen Macro Builder provides the capability to design quickly memory functions, such as FIFOs, LIFOs, and In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es RAM arrays. In addition, unused SRAM blocks need not be wasted, since they can be used to implement registers for other logic within the design. MultiPlex I/O Modules The I/O modules provide the interface between the device pins and the logic array. The top of Figure 6 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module. (Refer to the Macro Library Guide for more information.) All 42MX I/O modules contain a tristate buffer, with input and output latches that can be configured for input, output, or bidirectional operation. EN Q D PAD From Array G/CLK* C-module, to register input and output signals. To achieve 5.0V or 3.3V PCI-compliant output drives on A42MX24, A42MX36, and A42MX52, a chip-wide PCI fuse is programmed. When the PCI fuse is not programmed, output drive is standard. (See the bottom portion of Figure 6.) Actel's Designer Series development tools provide a design library of I/O macros. The I/O macro library provides macrofunctions that can implement all I/O configurations supported by the MX FPGAs. Routing Structure The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may be either of continuous length or broken into pieces called segments. Varying segment lengths allows the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends, using antifuses, to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Horizontal Routing Q D To Array G/CLK* * Can be configured as a Latch or D Flip-Flop (using C-module) Schematic Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 7. Nondedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Vertical Routing STD Signal Output PCI Drive PCI Enable Fuse Figure 6 * I/O Module The Integrator Series devices contain flexible I/O structures, in that each output pin has a dedicated output-enable control. The I/O module can be used to latch input or output data, or both, providing a fast setup time. In addition, the Actel Designer software tools can build a D flip-flop, using a Another set of routing tracks run vertically through the module. Vertical tracks are of three types: input, output, and long. Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array, where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 7. Antifuse Structures An antifuse is a "normally open" structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient 1-99 Segmented horizontal routing tracks Logic Modules CLKB CLKINB CLKA CLKINA FROM PADS S0 S1 CLKMOD INTERNAL SIGNAL CLKO(17) Antifuses CLOCK DRIVERS CLKO(16) CLKO(15) Vertical routing tracks Figure 7 * Routing Structure CLKO(2) programming algorithms. The structure is highly testable because there are no preexisting connections; therefore, temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. CLKO(1) Clock Networks The 40MX devices have one global CLK distribution network. Two low-skew, high fanout clock distribution networks are provided in each 42MX device. These networks are referred to as CLK0 and CLK1. Each network has a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows: * Externally from the CLKA pad * Externally from the CLKB pad * Internally from the CLKINA input * Internally from the CLKINB input The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The user controls the clock module by selecting one of two clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLK0 or CLK1 is being used. The clock input pads can also be used as normal I/Os, bypassing the clock networks. (See Figure 8.) The 42MX devices that contain SRAM modules have four additional register control resources, called quadrant clock 1-100 CLOCK TRACKS Figure 8 * Clock Networks networks (Figure 9). Each quadrant clock provides a local, high-fanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. Test Circuitry Both 40MX and 42MX devices provide the means to test and debug a design once it is programmed into a device. The 40MX and 42MX devices contain Actel's Actionprobe(R) test facility. Once a device has been programmed, the Actionprobe test facility allows the designer to probe any internal node during device operation to aid in debugging a design. In addition, 42MX devices contain JTAG 1149.1 Boundary Scan Test. JTAG Boundary Scan Testing (BST) Device pin spacing is decreasing with the advent of fine-pitch packages such as TQFP and BGA, and manufacturers are routinely implementing surface-mount technology with multilayer PC boards. Boundary scan is becoming an attractive tool to help system manufacturers test their PC boards. The Joint Test Action Group (JTAG) developed the IEEE Boundary Scan standard 1149.1 to facilitate board-level testing during manufacturing. IEEE Standard 1149.1 defines a four-pin Test Access Port (TAP) interface for testing integrated circuits in a system. The 42MX family provides four JTAG BST pins: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCLK), and Test Mode Select (TMS). Devices are configured in a JTAG "chain" In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es where by BST data can be transmitted serially between devices via TDO-to-TDI interconnections. The TMS and TCLK signals are shared among all devices in the JTAG chain so that all components operate in the same state. The 42MX family implements a subset of the IEEE 1149.1 BST instruction, in addition to a private instruction, to allow the use of Actel's Actionprobe facility with JTAG BST. Refer to the IEEE 1149.1 specification for detailed information regarding JTAG testing. JTAG Architecture The 42MX JTAG BST circuitry consist of a Test Access Port (TAP) controller, JTAG instruction register, a JPROBE register, a bypass register, and a boundary scan register. Figure 10 is a block diagram of the 42MX JTAG circuitry. QCLKA QCLKB QCLKC Quad Clock Module QCLK1 QCLK3 Quad Clock Module *QCLK1IN QCLKD *QCLK3IN S1 S0 S0 S1 Quad Clock Module QCLK2 QCLK4 Quad Clock Module *QCLK2IN *QCLK4IN S1 S0 S0 S1 *QCLK1IN, QCLK2IN, QCLK3IN, and QCKL4IN are internally generated signals. Figure 9 * Quadrant Clock Network JPROBE Register Boundary Scan Register Output MUX TDO Bypass Register Control Logic TMS TAP Controller TCLK TDI Instruction Decode Instruction Register Figure 10 * JTAG BST Circuitry 1-101 When a device is operating in JTAG BST mode, four I/O pins are used for the TDI, TDO, TMS, and TCLK signals. An active reset (nTRST) pin is not supported. However the 42MX contains power-on reset circuitry that resets the JTAG BST circuitry upon power-up. During normal device operation, the JTAG pins should be held LOW to disable the JTAG circuitry. The following table summarizes the functions of the JTAG BST signals. JTAG Signal Name Function TDI Test Data In Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. TDO Test Data Out Serial data output for JTAG instructions and test data. TMS Test Mode Select Serial data input for JTAG test mode. Data is shifted in on the rising edge of TCLK. TCLK Test Clock Clock signal to shift the JTAG data into the device. JTAG BST Instructions JTAG BST testing within the 42MX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signal to control the JTAG testing of the device. The JTAG test mode is determined by the bit stream entered on the TMS pin. The table in the next column describes the JTAG instructions supported by the 42MX. Actionprobe If a device has been successfully programmed and the security fuse has not been programmed, any internal logic or I/O module output can be observed using the Actionprobe circuitry and the PRA and/or PRB pins. The Actionprobe diagnostic system provides the software and hardware required to perform real-time debugging. Refer to "Using the Actionprobe for System-Level Debug" application note for further information. 1-102 Test Mode Code Description EXTEST 000 Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. SAMPLE/ PRELOAD 001 Allows a snapshot of the signals at the device pins to be captured and examined during device operation. INTEST 010 Refer to the IEEE 1149.1 specification. JPROBE 011 A private instruction allowing the user to connect Actel's Micro Probe registers to the JTAG chain. USER INSTRUCTION 100 Allows the user to build application-specific instructions such as RAM READ and RAM WRITE. HIGH Z 101 Refer to the IEEE 1149.1 specification. CLAMP 110 Refer to the IEEE 1149.1 specification. BYPASS 111 Enables the bypass register between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the JTAG chain. In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 5.0V Operating Conditions Recommended Operating Conditions Absolute Maximum Ratings 1 Parameter Free air temperature range Symbol Parameter VCC DC Supply Voltage Limits Units -0.5 to +7.0 V VI Input Voltage -0.5 to VCC +0.5 V VO Output Voltage -0.5 to VCC +0.5 V IIO I/O Source/Sink Current2 20 mA TSTG Storage Temperature -65 to +150 C Commercial Industrial Units Temperature Range1 0 to +70 -40 to +85 C Power Supply Tolerance 5 10 %VCC Note: 1. Ambient temperature (TA) is used for commercial and industrial. Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND - 0.5 V, the internal protection diode will be forward biased and can draw excessive current. Electrical Specifications Commercial Symbol Commercial -F Industrial Parameter Units Min. VOH1 Max. Min. Max. Max. (IOH = -10 mA) 2 2.4 2.4 V (IOH = -6 mA) 3.84 3.84 V (IOH = -4 mA) VOL1 Min. 3.7 (IOL = 10 mA) 2 0.5 0.5 (IOL = 6 mA) 0.33 0.33 V V 0.40 V VIL -0.3 0.8 -0.3 0.8 -0.3 0.8 V VIH 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V Input Transition Time tR, tF2 500 500 500 ns CIO I/O Capacitance2, 3 10 10 10 pF Standby Current, ICC4 (typical = 1 mA) 1.0 20 10 mA ICC(D) Dynamic VCC Supply Current See "Power Dissipation" on page 1-21. Low Power Mode Standby Current, ICC 0.1 20 10 mA Power Current During Power-Up 1.0 20 10 mA Notes: 1. Only one output tested at a time. VCC = min. 2. 3. 4. Not tested, for information only. Includes worst-case 84-pin CPGA package capacitance. VOUT = 0 V, f = 1 MHz. All outputs unloaded. All inputs = VCC or GND; typical ICC = 0.25 mA. ICC limit includes IPP and ISV during normal operation. 1-103 3.3V Operating Conditions Recommended Operating Conditions Absolute Maximum Ratings 1 Parameter Free air temperature range Symbol Parameter Limits Units -0.5 to +7.0 V VCC DC Supply Voltage VI Input Voltage -0.5 to VCC +0.5 V VO Output Voltage -0.5 to VCC +0.5 V I/O Source Sink 20 mA -65 to +150 C IIO TSTG Current2 Storage Temperature Commercial Industrial Units Temperature Range1 0 to +70 -40 to +85 C Power Supply Tolerance 5 10 %V Note: 1. Ambient temperature (TA) is used for commercial. Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND - 0.5 V, the internal protection diodes will forward bias and can draw excessive current. Electrical Specifications Commercial Industrial Parameter Units Min. VOH1 VOL1 (IOH = -4 mA) 2.15 (IOH = -3.2 mA) 2.4 (IOL = 6 mA) Max. Min. Max. 3.7 V V 0.4 0.48 V VIL -0.3 0.8 -0.3 0.8 V VIH 2.0 VCC + 0.3 2.0 VCC + 0.3 V 500 500 ns 10 10 pF 0.75 0.75 mA Input Transition Time tR, tF2 CIO I/O Capacitance2, 3 Standby Current, ICC4 (typical = 0.3 mA) ICC(D) Dynamic VCC Supply Current See "Power Dissipation" on page 1-21. Low Power Mode Standby Current, ICC 0.1 10 mA Power Current During Power-Up 1.0 10 mA Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND. 1-104 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Package Thermal Characteristics The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package at commercial temperature is as follows: 150C - 70C Max. junction temp. (C) - Max. commercial temp. ----------------------------------------------------------------------------------------------------------------------------- = --------------------------------- = 2.6W ja (C/W) 30C/W ja Maximum Power Dissipation Package Type Pin Count Still Air 300 ft/min Still Air 300 ft/min Plastic Quad Flatpack 100 42 C/W 33 C/W 1.9 W 2.4 W Plastic Quad Flatpack 160 34 C/W 27 C/W 2.4 W 3.0 W Plastic Quad Flatpack 208 25 C/W 16.2 C/W 3.2 W 4.9 W Plastic Leaded Chip Carrier 44 45 C/W 35 C/W 1.8 W 2.3 W Plastic Leaded Chip Carrier 68 38 C/W 29 C/W 2.1 W 2.8 W Plastic Leaded Chip Carrier 84 37 C/W 28 C/W 2.2 W 2.9 W Thin Quad Flatpack 176 32 C/W 25 C/W 2.5 W 3.2 W Power Quad Flatpack 208 16.8 C/W 11.4 C/W 4.8 W 7.0 W Power Quad Flatpack 240 16.1 C/W 10.6 C/W 5.0 W 7.5 W Power Dissipation General Power Equation P = [ICCstandby + ICCactive] * VCC + IOL* VOL* N + IOH * (VCC - VOH) * M where: The power due to standby current is typically a small component of the overall power. Standby power is calculated for commercial, worst-case conditions: ICC 2 mA VCC 5.25 V Power 10.5 mW VOL, VOH are TTL level output voltages. The static power dissipation by TTL loads depends on the number of outputs driving high or low and on the DC load current. Again, this number is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low and 140 mW with all outputs driving high. The actual dissipation will average somewhere between, as I/Os switch states with time. N equals the number of outputs driving TTL loads to VOL. Active Power Component ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematic because their values depend on the family type, on design details, and on the system I/O. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have small static power components that result in power dissipation lower than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. 1-105 Equivalent Capacitance fm = Average logic module switching rate in MHz The power dissipated by a CMOS circuit can be expressed by Equation 1. fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz fq2 = Average second routed array clock rate in MHz Power (W) = CEQ * VCC2 * F (1) where: CEQ is the equivalent capacitance expressed in picofarads (pF). Fixed Capacitance Values for Actel FPGAs (pF) VCC is power supply in volts (V). F is the switching frequency in megahertz (MHz). Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C EQ Values for Actel FPGAs Modules (CEQM) 5.2 Input Buffers (CEQI) 11.6 Output Buffers (CEQO) 23.8 Routed Array Clock Buffer Loads (CEQCR) 3.5 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Device Type A40MX02 A40MX04 A40MX09 A42MX16 A42MX24 A42MX36 A42MX52 r1 routed_Clk1 41.4 68.6 134 168 190 230 285 r2 routed_Clk2 -- -- 134 168 190 230 285 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) Power = VCC2 * [(m x CEQM * fm)Modules + (n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2) = 80% of combinatorial modules Inputs switching (n) = # of inputs/4 Outputs switching (p) = # outputs/4 where: First routed array clock loads (q1) = 40% of sequential modules Second routed array clock loads (q2) = 40% of sequential modules Load capacitance (CL) = 35 pF m = Number of logic modules switching at frequency fm n = Number of input buffers switching at frequency fn p = Number of output buffers switching at frequency fp q1 = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock Average logic module switching rate = F/10 (fm) Average input switching rate (fn) = F/5 = F/10 r1 = Fixed capacitance due to first routed array clock Average output switching rate (fp) r2 = Fixed capacitance due to second routed array clock Average first routed array clock rate = F (fq1) CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL 1-106 = Output load capacitance in pF Average second routed array clock rate (fq2) = F/2 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 40MX Timing Model* Internal Delays Input Delay I/O Module tINYL = 3.1 ns Predicted Routing Delays Output Delay I/O Module Logic Module tIRD2 = 1.4 ns tDLH = 6.7 ns tIRD1 = 0.9 ns tIRD4 = 3.1 ns tIRD8 = 6.6 ns ARRAY CLOCK tCKH = 5.6 ns tPD = 2.9 ns tCO = 2.9 ns tRD1 = 0.9 ns tRD2 = 1.4 ns tRD4 = 3.1 ns tRD8 = 6.6 ns tENHZ = 11.6 ns FO = 128 FMAX = 70 MHz * Values are shown for 40MX `-3 speed' devices at worst-case commercial conditions. 1-107 42MX Timing Model* Input Delays Internal Delays Combinatorial I/O Module Logic Module tINYL = 1.3 ns t IRD2 = 3.2 ns Predicted Routing Delays Output Delays I/O Module tDLH = 3.8 ns D Q tRD1 = 0.8 ns tRD2 = 1.3 ns tRD4 = 2.0 ns tRD8 = 3.2 ns tPD = 2.6 ns G Sequential Logic Module tINH = 0.0 ns tINSU = 0.3 ns tINGL = 2.6 ns Combinatorial Logic included in tSUD ARRAY CLOCKS tCKH = 5.1 ns FMAX = 225 MHz FO = 256 tSUD = 0.4 ns tHD = 0.0 ns D Q Q tRD1 = 0.8 ns tENHZ = 5.4 ns G tCO = 2.6 ns tOUTH = 0.0 ns tOUTSU = 0.3 ns tGLH = 4.2 ns tLCO = 10.7 ns (64 loads, pad-pad) *Values are shown for A42MX09-2 at worst-case commercial conditions 1-108 D I/O Module tDLH = 3.8 ns Input module predicted routing delay In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 42MX Timing Model (Logic Functions using Quadrant Clocks)* Input Delays Internal Delays Predicted Routing Delays I/O Module tINPY = 1.3 ns t IRD1 = 3.2 ns Output Delays I/O Module Combinatorial Module D Q tDLH = 3.7 ns tRD1 = 1.3 ns tRD2 = 1.8 ns tRD4 = 2.6 ns tPD = 2.5 ns G tINH = 0.0 ns tINSU = 0.3 ns tINGO = 2.6 ns Decode Module tRDD = 0.3 ns tPDD = 2.9 ns I/O Module tDLH = 3.7 ns Sequential Logic Module Combinatorial Logic included in tSUD tSUD = 0.3 ns tHD = 0.0 ns QUADRANT CLOCKS D Q tRD1 = 1.3 ns D Q tENHZ = 3.7 ns G tCO = 2.5 ns tLH = 0.0 ns tLSU = 0.3 ns tGHL= 4.6 ns tCKH = 12 ns** FMAX = 100 MHz * Preliminary values are shown for A42MX36-2 at worst-case commercial conditions ** Load dependent 1-109 42MX Timing Model (SRAM Functions)* Input Delays I/O Module tINPY = 1.3 ns t IRD1 = 3.2 ns D Q G tINSU = 0.3 ns tINH = 0.0 ns tINGO = 2.6 ns Predicted Routing Delays WRAD [5:0] ARRAY CLOCKS RD [7:0] WD [7:0] RDAD [5:0] BLKEN REN WEN WCLK RCLK tADSU = 1.8 ns tADH = 0.0 ns tWENSU = 2.9 ns tBENS = 2.9 ns tADSU = 1.8 ns tADH = 0.0 ns tRENSU = 0.8 ns tRCO = 3.8 ns FMAX = 100 MHz *Values are shown for A42MX36-2 at worst-case commercial conditions. 1-110 tRD1 = 2.0 ns I/O Module tDLH = 3.7 ns * * * D Q G tGHL= 4.6 ns tLSU = 0.3 ns tLH = 0.0 ns In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Parameter Measurement Output Buffer Delays E D In 50% PAD VOL 50% VOH E 1.5 V 1.5 V TRIBUFF 50% VCC PAD E 50% 1.5 V PAD To AC test loads (shown below) PAD GND 10% VOL tDHL tDLH tENZL 50% VOH 50% tENHZ tENZH tENLZ 90% 1.5 V AC Test Loads Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 35 pF R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k To the output under test 35 pF Input Buffer Delays Module Delays PAD S A B Y INBUF S, A or B 3V PAD 1.5 V 1.5 V VCC Y GND 0V 50% tINYH 50% 50% Y tINYL 50% 50% tPLH 50% Y tPHL Y 50% tPHL 50% tPLH 1-111 Sequential Module Timing Characteristics Flip-Flops and Latches D E CLK Y PRE CLR (Positive edge triggered) tHD D1 tSUD tA tWCLKA G, CLK tSUENA tWCLKI tHENA E tCO Q tRS PRE, CLR tWASYN Note: 1-112 D represents all data functions involving A, B, and S for multiplexed flip-flops. In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Sequential Timing Characteristics (continued) Input Buffer Latches PAD DATA IBDL G PAD CLK CLKBUF DATA tINH G tINSU tHEXT CLK tSUEXT Output Buffer Latches D PAD OBDLHS G D tOUTSU G tOUTH 1-113 Decode Module Timing A B C D E F G Y H VCC A-G, H 50% VCC Y tPHL tPLH SRAM Timing Characteristics Read Port Write Port WRAD [5:0] BLKEN WEN WCLK WD [7:0] 1-114 RDAD [5:0] RAM Array LEW 32x8 or 64x4 (256 bits) REN RCLK RD [7:0] In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Dual-Port SRAM Timing Waveforms 42MX SRAM Write Operation tRCKHL tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] tADH Valid tWENSU tWENH tBENSU tBENH WEN BLKEN Note: Valid Identical timing for falling-edge clock. 42MX SRAM Synchronous Read Operation tCKHL tRCKHL RCLK tRENSU tRENH tADSU tADH REN RDAD[5:0] Valid tRCO tDOH RD[7:0] Note: Old Data New Data Identical timing for falling-edge clock. 1-115 42MX SRAM Asynchronous Read Operation--Type 1 (Read Address Controlled) tRDADV RDAD[5:0] ADDR1 ADDR2 tRPD tDOH Data 1 RD[7:0] Data 2 42MX SRAM Asynchronous Read Operation--Type 2 (Write Address Controlled) WEN WD[7:0] WRAD[5:0] BLKEN tWENSU tWENH Valid tADSU WCLK tADH tRPD tDOH RD[7:0] 1-116 Old Data New Data In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Predictable Performance: Tight Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The MX FPGAs deliver a tight fanout delay distribution. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel's patented PLICE antifuse offers an extremely very low resistive/capacitive interconnect. The antifuses, fabricated in 0.45 micron lithography, offer nominal levels of 100 ohms resistance and 7.0 femtofarad (fF) capacitance per antifuse. The Integrator Series fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. Timing Characteristics Timing characteristics for devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all Integrator Series members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design is complete. Delay values may then be determined by using the Designer Series utility or by performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Since the architecture provides deterministic timing and abundant routing resources, Actel's Designer Series development tools offers DirectTime, a timing-driven place-and-route tool. Using DirectTime, the designer can specify timing-critical nets and system clock frequency. Using these timing specifications, the place-and-route software optimizes the layout of the design to meet the user's specifications. Long Tracks Some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6% of nets in a fully utilized device require long tracks. Long tracks add approximately 3 ns to 6 ns delay. This additional delay is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. Timing Derating A best-case timing derating factor of 0.45 is used to reflect best case processing. Note that this factor is relative to the standard-speed timing parameters and must be multiplied by the appropriate voltage and temperature derating factors for a given application. Timing Derating Factor (Tem perature and Voltage) Industrial (Commercial Specification) x Min. Max. 0.69 1.11 Timing Derating Factor for Designs at Typical Temperature (T J = 25C) and Voltage (5.0 V) (Maximum Specification, Worst-Case Condition) x Note: 0.85 This derating factor applies to all routing and propagation delays. 1-117 Temperature and Voltage Deratin g Factors (Normalized to Worst-Case Commercial, T J = 4.75 V, 70C) -55 -40 0 25 70 85 125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, TJ = 4.75 V, 70C) 1.3 Derating Factor 1.2 1.1 125C 1.0 85C 70C 0.9 25C 0.8 0C -40C -55C 0.7 0.6 4.50 4.75 5.00 Voltage (V) Note: 1-118 This derating factor applies to all routing and propagation delays. 5.25 5.50 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tPD1 Single Module 1.54 1.74 2.05 2.87 ns tPD2 Dual Module Macros 3.06 3.47 4.08 5.71 ns tCO Sequential Clk to Q 1.54 1.74 2.05 2.87 ns tGO Latch G to Q 1.54 1.74 2.05 2.87 ns tRS Flip-Flop (Latch) Reset to Q 1.54 1.74 2.05 2.87 ns Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.48 1.67 1.97 2.76 ns tRD2 FO=2 Routing Delay 2.08 2.35 2.77 3.88 ns tRD3 FO=3 Routing Delay 2.69 3.04 3.58 5.01 ns tRD4 FO=4 Routing Delay 3.29 3.72 4.38 6.13 ns tRD8 FO=8 Routing Delay 5.69 6.45 7.59 10.63 ns Sequential Timing Characteristics3 tSUD Flip-Flop (Latch) Data Input Setup 3.38 3.83 4.50 6.30 ns tHD4 Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tSUENA Flip-Flop (Latch) Enable Setup 3.38 3.83 4.50 6.30 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 4.13 4.68 5.50 7.70 ns Flip-Flop (Latch) Asynchronous Pulse Width 4.13 4.68 5.50 7.70 ns tA Flip-Flop Clock Input Period 5.59 6.33 7.45 10.43 ns fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) tWASYN 167.50 154.10 134.00 80.40 MHz Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 2. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. 3. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro. 1-119 A40MX02 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINYH Pad to Y High 1.36 1.54 1.81 2.53 ns tINYL Pad to Y Low 1.36 1.54 1.81 2.53 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 2.84 3.21 3.78 5.29 ns tIRD2 FO=2 Routing Delay 3.44 3.89 4.58 6.41 ns tIRD3 FO=3 Routing Delay 4.04 4.58 5.39 7.55 ns tIRD4 FO=4 Routing Delay 4.64 5.26 6.19 8.67 ns tIRD8 FO=8 Routing Delay 7.05 7.99 9.40 13.16 ns FO = 16 FO = 128 3.92 3.92 4.44 4.44 5.22 5.22 7.31 7.31 ns FO = 16 FO = 128 4.22 4.22 4.79 4.79 5.63 5.63 7.88 7.88 ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 2.58 2.71 2.92 3.07 3.44 3.61 4.82 5.05 ns FO = 16 FO = 128 2.58 2.71 2.92 3.07 3.44 3.61 4.82 5.05 ns FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 0.45 0.62 5.39 5.59 0.51 0.70 6.10 6.33 174.79 167.50 0.60 0.82 7.18 7.45 159.85 154.10 0.84 1.15 10.05 10.43 139.00 134.00 ns ns 83.40 80.40 MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 1-120 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A40MX02 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 3.68 4.17 4.91 6.87 ns tDHL Data to Pad Low 4.61 5.22 6.14 8.60 ns tENZH Enable Pad Z to High 4.38 4.96 5.84 8.18 ns tENZL Enable Pad Z to Low 5.44 6.16 7.25 10.15 ns tENHZ Enable Pad High to Z 7.40 8.39 9.87 13.82 ns tENLZ Enable Pad Low to Z 5.14 5.82 6.85 9.59 ns dTLH Delta Low to High 0.02 0.03 0.03 0.04 ns/pF dTHL Delta High to Low 0.03 0.03 0.04 0.06 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 4.36 4.94 5.81 8.13 ns tDHL Data to Pad Low 3.92 4.45 5.23 7.32 ns tENZH Enable Pad Z to High 4.03 4.56 5.37 7.52 ns tENZL Enable Pad Z to Low 5.66 6.41 7.54 10.56 ns tENHZ Enable Pad High to Z 7.40 8.39 9.87 13.82 ns tENLZ Enable Pad Low to Z 5.14 5.82 6.85 9.59 ns dTLH Delta Low to High 0.04 0.04 0.05 0.07 ns/pF dTHL Delta High to Low 0.02 0.03 0.03 0.04 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneous Switching Output Limits for Actel FPGAs" application note on page 4-125. 1-121 A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) 1 Logic Module Propagation Delays Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tPD1 Single Module 2.15 2.44 2.87 4.02 ns tPD2 Dual Module Macros 4.28 4.86 5.71 8.00 ns tCO Sequential Clk to Q 2.15 2.44 2.87 4.02 ns tGO Latch G to Q 2.15 2.44 2.87 4.02 ns tRS Flip-Flop (Latch) Reset to Q 2.15 2.44 2.87 4.02 ns Predicted Routing Delays2 tRD1 FO=1 Routing Delay 2.07 2.34 2.76 3.86 ns tRD2 FO=2 Routing Delay 2.91 3.30 3.88 5.43 ns tRD3 FO=3 Routing Delay 3.76 4.26 5.01 7.02 ns tRD4 FO=4 Routing Delay 4.60 5.21 6.13 8.58 ns tRD8 FO=8 Routing Delay 7.97 9.03 10.63 14.88 ns Sequential Timing Characteristics3 tSUD Flip-Flop (Latch) Data Input Setup 4.73 5.36 6.30 8.82 ns tHD4 Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tSUENA Flip-Flop (Latch) Enable Setup 4.73 5.36 6.30 8.82 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.78 6.55 7.70 10.78 ns Flip-Flop (Latch) Asynchronous Pulse Width 5.78 6.55 7.70 10.78 ns tA Flip-Flop Clock Input Period 7.82 8.87 10.43 14.60 ns fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) tWASYN 100.50 92.46 80.40 48.24 MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. 4. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro. 1-122 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A40MX02 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINYH Pad to Y High 1.90 2.15 2.53 3.55 ns tINYL Pad to Y Low 1.90 2.15 2.53 3.55 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 3.97 4.50 5.29 7.41 ns tIRD2 FO=2 Routing Delay 4.81 5.45 6.41 8.89 ns tIRD3 FO=3 Routing Delay 5.66 6.41 7.55 10.56 ns tIRD4 FO=4 Routing Delay 6.50 7.37 8.67 12.13 ns tIRD8 FO=8 Routing Delay 9.87 11.19 13.16 18.42 ns FO = 16 FO = 128 5.48 5.48 6.21 6.21 7.31 7.31 10.23 10.23 ns FO = 16 FO = 128 5.91 5.91 6.70 6.70 7.88 7.88 11.03 11.03 ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to High Input High to Low Minimum Pulse Width High FO = 16 FO = 128 3.61 3.79 4.09 4.30 4.82 5.05 6.74 7.08 ns Minimum Pulse Width Low FO = 16 FO = 128 3.61 3.79 4.09 4.30 4.82 5.05 6.74 7.08 ns Maximum Skew FO = 16 FO = 128 Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 0.63 0.86 7.54 7.82 0.71 0.98 8.54 8.87 104.88 100.50 0.84 1.15 10.05 10.43 95.91 92.46 1.18 1.61 14.07 14.60 83.40 80.40 ns ns 50.04 48.24 MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 1-123 A40MX02 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 5.16 5.84 6.87 9.62 ns tDHL Data to Pad Low 6.45 7.31 8.60 12.03 ns tENZH Enable Pad Z to High 6.13 6.95 8.18 11.45 ns tENZL Enable Pad Z to Low 7.61 8.63 10.15 14.21 ns tENHZ Enable Pad High to Z 10.36 11.75 13.82 19.35 ns tENLZ Enable Pad Low to Z 7.19 8.15 9.59 13.43 ns dTLH Delta Low to High 0.03 0.04 0.04 0.06 ns/pF dTHL Delta High to Low 0.04 0.05 0.06 0.08 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 6.10 6.91 8.13 11.39 ns tDHL Data to Pad Low 5.49 6.22 7.32 10.25 ns tENZH Enable Pad Z to High 5.64 6.39 7.52 10.53 ns tENZL Enable Pad Z to Low 7.92 8.97 10.56 14.78 ns tENHZ Enable Pad High to Z 10.36 11.75 13.82 19.35 ns tENLZ Enable Pad Low to Z 7.19 8.15 9.59 13.43 ns dTLH Delta Low to High 0.05 0.06 0.07 0.10 ns/pF dTHL Delta High to Low 0.03 0.04 0.04 0.06 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneous Switching Output Limits for Actel FPGAs" application note on page 4-125. 1-124 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tPD1 Single Module 1.54 1.74 2.05 2.87 ns tPD2 Dual Module Macros 3.06 3.47 4.08 5.71 ns tCO Sequential Clk to Q 1.54 1.74 2.05 2.87 ns tGO Latch G to Q 1.54 1.74 2.05 2.87 ns tRS Flip-Flop (Latch) Reset to Q 1.54 1.74 2.05 2.87 ns Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.48 1.67 1.97 2.76 ns tRD2 FO=2 Routing Delay 2.08 2.35 2.77 3.88 ns tRD3 FO=3 Routing Delay 2.69 3.04 3.58 5.01 ns tRD4 FO=4 Routing Delay 3.29 3.72 4.38 6.13 ns tRD8 FO=8 Routing Delay 5.69 6.45 7.59 10.63 ns Sequential Timing Characteristics3 tSUD Flip-Flop (Latch) Data Input Setup 3.38 3.83 4.50 6.30 ns tHD4 Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tSUENA Flip-Flop (Latch) Enable Setup 3.38 3.83 4.50 6.30 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 4.13 4.68 5.50 7.70 ns Flip-Flop (Latch) Asynchronous Pulse Width 4.13 4.68 5.50 7.70 ns tA Flip-Flop Clock Input Period 5.59 6.33 7.45 10.43 ns fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) tWASYN 167.50 154.10 134.00 80.40 MHz Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 2. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. 3. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro. 1-125 A40MX04 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINYH Pad to Y High 1.36 1.54 1.81 2.53 ns tINYL Pad to Y Low 1.36 1.54 1.81 2.53 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 2.84 3.21 3.78 5.29 ns tIRD2 FO=2 Routing Delay 3.44 3.89 4.58 6.41 ns tIRD3 FO=3 Routing Delay 4.04 4.58 5.39 7.55 ns tIRD4 FO=4 Routing Delay 4.64 5.26 6.19 8.67 ns tIRD8 FO=8 Routing Delay 7.05 7.99 9.40 13.16 ns FO = 16 FO = 128 3.92 3.92 4.44 4.44 5.22 5.22 7.31 7.31 ns FO = 16 FO = 128 4.22 4.22 4.79 4.79 5.63 5.63 7.88 7.88 ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 2.58 2.71 2.92 3.07 3.44 3.61 4.82 5.05 ns FO = 16 FO = 128 2.58 2.71 2.92 3.07 3.44 3.61 4.82 5.05 ns FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 0.45 0.62 5.39 5.59 0.51 0.70 6.10 6.33 174.79 167.50 0.60 0.82 7.18 7.45 159.85 154.10 0.84 1.15 10.05 10.43 139.00 134.00 ns ns 83.40 80.40 MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 1-126 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A40MX04 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 3.68 4.17 4.91 6.87 ns tDHL Data to Pad Low 4.61 5.22 6.14 8.60 ns tENZH Enable Pad Z to High 4.38 4.96 5.84 8.18 ns tENZL Enable Pad Z to Low 5.44 6.16 7.25 10.15 ns tENHZ Enable Pad High to Z 7.40 8.39 9.87 13.82 ns tENLZ Enable Pad Low to Z 5.14 5.82 6.85 9.59 ns dTLH Delta Low to High 0.02 0.03 0.03 0.04 ns/pF dTHL Delta High to Low 0.03 0.03 0.04 0.06 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 4.36 4.94 5.81 8.13 ns tDHL Data to Pad Low 3.92 4.45 5.23 7.32 ns tENZH Enable Pad Z to High 4.03 4.56 5.37 7.52 ns tENZL Enable Pad Z to Low 5.66 6.41 7.54 10.56 ns tENHZ Enable Pad High to Z 7.40 8.39 9.87 13.82 ns tENLZ Enable Pad Low to Z 5.14 5.82 6.85 9.59 ns dTLH Delta Low to High 0.04 0.04 0.05 0.07 ns/pF dTHL Delta High to Low 0.02 0.03 0.03 0.04 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneous Switching Output Limits for Actel FPGAs" application note on page 4-125. 1-127 A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) 1 Logic Module Propagation Delays Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tPD1 Single Module 2.15 2.44 2.87 4.02 ns tPD2 Dual Module Macros 4.28 4.86 5.71 8.00 ns tCO Sequential Clk to Q 2.15 2.44 2.87 4.02 ns tGO Latch G to Q 2.15 2.44 2.87 4.02 ns tRS Flip-Flop (Latch) Reset to Q 2.15 2.44 2.87 4.02 ns Predicted Routing Delays2 tRD1 FO=1 Routing Delay 2.07 2.34 2.76 3.86 ns tRD2 FO=2 Routing Delay 2.91 3.30 3.88 5.43 ns tRD3 FO=3 Routing Delay 3.76 4.26 5.01 7.02 ns tRD4 FO=4 Routing Delay 4.60 5.21 6.13 8.58 ns tRD8 FO=8 Routing Delay 7.97 9.03 10.63 14.88 ns Sequential Timing Characteristics3 tSUD Flip-Flop (Latch) Data Input Setup 4.73 5.36 6.30 8.82 ns tHD4 Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tSUENA Flip-Flop (Latch) Enable Setup 4.73 5.36 6.30 8.82 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.78 6.55 7.70 10.78 ns Flip-Flop (Latch) Asynchronous Pulse Width 5.78 6.55 7.70 10.78 ns tA Flip-Flop Clock Input Period 7.82 8.87 10.43 14.60 ns fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) tWASYN 100.50 92.46 80.40 48.24 MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. 4. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro. 1-128 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A40MX04 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINYH Pad to Y High 1.90 2.15 2.53 3.55 ns tINYL Pad to Y Low 1.90 2.15 2.53 3.55 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 3.97 4.50 5.29 7.41 ns tIRD2 FO=2 Routing Delay 4.81 5.45 6.41 8.89 ns tIRD3 FO=3 Routing Delay 5.66 6.41 7.55 10.56 ns tIRD4 FO=4 Routing Delay 6.50 7.37 8.67 12.13 ns tIRD8 FO=8 Routing Delay 9.87 11.19 13.16 18.42 ns FO = 16 FO = 128 5.48 5.48 6.21 6.21 7.31 7.31 10.23 10.23 ns FO = 16 FO = 128 5.91 5.91 6.70 6.70 7.88 7.88 11.03 11.03 ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to High Input High to Low Minimum Pulse Width High FO = 16 FO = 128 3.61 3.79 4.09 4.30 4.82 5.05 6.74 7.08 ns Minimum Pulse Width Low FO = 16 FO = 128 3.61 3.79 4.09 4.30 4.82 5.05 6.74 7.08 ns Maximum Skew FO = 16 FO = 128 Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 0.63 0.86 7.54 7.82 0.71 0.98 8.54 8.87 104.88 100.50 0.84 1.15 10.05 10.43 95.91 92.46 1.18 1.61 14.07 14.60 83.40 80.40 ns ns 50.04 48.24 MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 1-129 A40MX04 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 5.16 5.84 6.87 9.62 ns tDHL Data to Pad Low 6.45 7.31 8.60 12.03 ns tENZH Enable Pad Z to High 6.13 6.95 8.18 11.45 ns tENZL Enable Pad Z to Low 7.61 8.63 10.15 14.21 ns tENHZ Enable Pad High to Z 10.36 11.75 13.82 19.35 ns tENLZ Enable Pad Low to Z 7.19 8.15 9.59 13.43 ns dTLH Delta Low to High 0.03 0.04 0.04 0.06 ns/pF dTHL Delta High to Low 0.04 0.05 0.06 0.08 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 6.10 6.91 8.13 11.39 ns tDHL Data to Pad Low 5.49 6.22 7.32 10.25 ns tENZH Enable Pad Z to High 5.64 6.39 7.52 10.53 ns tENZL Enable Pad Z to Low 7.92 8.97 10.56 14.78 ns tENHZ Enable Pad High to Z 10.36 11.75 13.82 19.35 ns tENLZ Enable Pad Low to Z 7.19 8.15 9.59 13.43 ns dTLH Delta Low to High 0.05 0.06 0.07 0.10 ns/pF dTHL Delta High to Low 0.03 0.04 0.04 0.06 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneous Switching Output Limits for Actel FPGAs" application note on page 4-125. 1-130 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays1 Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tPD1 Single Module 1.55 1.76 2.07 2.90 ns tCO Sequential Clk to Q 1.37 1.56 1.83 2.56 ns tGO Latch G to Q 1.33 1.50 1.77 2.48 ns tRS Flip-Flop (Latch) Reset to Q 1.37 1.56 1.83 2.56 ns 2 Predicted Routing Delays tRD1 FO=1 Routing Delay 0.70 0.79 0.93 1.30 ns tRD2 FO=2 Routing Delay 0.97 1.10 1.29 1.81 ns tRD3 FO=3 Routing Delay 1.24 1.40 1.65 2.31 ns tRD4 FO=4 Routing Delay 1.51 1.71 2.01 2.81 ns tRD8 FO=8 Routing Delay 2.59 2.93 3.45 4.83 ns 3, 4 Sequential Timing Characteristics tSUD Flip-Flop (Latch) Data Input Setup 0.36 0.41 0.48 0.67 ns tHD Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tSUENA Flip-Flop (Latch) Enable Setup 0.45 0.51 0.60 0.84 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.77 4.27 5.02 7.03 ns Flip-Flop (Latch) Asynchronous Pulse Width 4.94 5.59 6.58 9.21 ns tA Flip-Flop Clock Input Period 4.50 5.10 6.00 8.40 ns tINH Input Buffer Latch Hold 0.00 0.0 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.30 0.4 0.4 0.6 ns tOUTH Output Buffer Latch Hold 0.00 0.0 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.30 0.4 0.4 0.6 ns fMAX Flip-Flop (Latch) Clock Frequency tWASYN 225 207 180 108 MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 1-131 A42MX09 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINYH Pad to Y High 1.16 1.32 1.55 2.17 ns tINYL Pad to Y Low 1.43 1.62 1.91 2.67 ns tINGH G to Y High 0.54 0.61 0.72 1.01 ns tINGL G to Y Low 5.30 6.00 7.06 9.88 ns 1 Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 2.05 2.32 2.73 3.82 ns tIRD2 FO=2 Routing Delay 2.34 2.65 3.12 4.37 ns tIRD3 FO=3 Routing Delay 2.64 2.99 3.52 4.93 ns tIRD4 FO=4 Routing Delay 2.94 3.33 3.92 5.49 ns tIRD8 FO=8 Routing Delay 4.13 4.68 5.50 7.70 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 256 2.75 3.15 3.11 3.57 3.66 4.20 5.12 5.88 ns ns tCKL Input High to Low FO = 32 FO = 256 2.54 2.93 2.88 3.32 3.39 3.90 4.75 5.46 ns ns tPWH Minimum Pulse Width High FO = 32 FO = 256 1.35 1.46 1.53 1.66 1.80 1.95 2.52 2.73 ns ns tPWL Minimum Pulse Width Low FO = 32 FO = 256 1.35 1.46 1.53 1.66 1.80 1.95 2.52 2.73 ns ns tCKSW Maximum Skew tSUEXT Input Latch External Setup FO = 32 FO = 256 0.54 0.54 0.61 0.61 0.72 0.72 1.01 1.01 ns ns tHEXT Input Latch External Hold FO = 32 FO = 256 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns tP Minimum Period FO = 32 FO = 256 4.20 4.50 4.76 5.10 5.60 6.00 7.84 8.40 ns ns fMAX Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 0.34 0.34 250 225 0.38 0.38 230 207 0.45 0.45 200 180 0.63 0.63 120 108 ns ns MHz MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 3 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst case performance 1-132 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX09 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Min. Min. Min. TTL Output Module Timing1 Max. Max. Max. Max. Units tDLH Data to Pad High 2.71 3.07 3.61 5.05 ns tDHL Data to Pad Low 3.19 3.61 4.25 5.95 ns tENZH Enable Pad Z to High 2.93 3.32 3.90 5.46 ns tENZL Enable Pad Z to Low 3.24 3.67 4.32 6.05 ns tENHZ Enable Pad High to Z 5.44 6.16 7.25 10.15 ns tENLZ Enable Pad Low to Z 5.93 6.72 7.90 11.06 ns tGLH G to Pad High 4.61 5.22 6.14 8.60 ns tGHL G to Pad Low 4.61 5.22 6.14 8.60 ns tLSU I/O Latch Setup 0.54 0.61 0.72 1.01 ns tLH I/O Latch Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 6.90 7.82 9.20 12.88 ns Array Clock-Out (pad-to-pad), 64 clock loading 9.68 10.97 12.90 18.06 ns dTLH Capacity Loading, Low to High 0.03 0.03 0.04 0.06 ns/pF dTHL Capacity Loading, High to Low 0.04 0.04 0.07 0.07 ns/pF tACO 1 CMOS Output Module Timing tDLH Data to Pad High 3.44 3.89 4.58 6.41 ns tDHL Data to Pad Low 2.66 3.02 3.55 4.97 ns tENZH Enable Pad Z to High 2.93 3.32 3.90 5.46 ns tENZL Enable Pad Z to Low 3.24 3.67 4.32 6.05 ns tENHZ Enable Pad High to Z 5.44 6.16 7.25 10.15 ns tENLZ Enable Pad Low to Z 5.93 6.72 7.90 11.06 ns tGLH G to Pad High 4.61 5.22 6.14 8.60 ns tGHL G to Pad Low 4.61 5.22 6.14 8.60 ns tLSU I/O Latch Setup 0.54 0.61 0.72 1.01 ns tLH I/O Latch Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 6.90 7.82 9.20 12.88 ns Array Clock-Out (pad-to-pad), 64 clock loading 9.68 10.97 12.90 18.06 ns dTLH Capacity Loading, Low to High 0.03 0.03 0.04 0.06 ns/pF dTHL Capacity Loading, High to Low 0.04 0.04 0.05 0.07 ns/pF tACO Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-133 A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays1 Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tPD1 Single Module 2.17 2.46 2.90 4.06 ns tCO Sequential Clk to Q 1.92 2.18 2.56 3.59 ns tGO Latch G to Q 1.86 2.11 2.48 3.47 ns tRS Flip-Flop (Latch) Reset to Q 1.92 2.18 2.56 3.59 ns 2 Predicted Routing Delays tRD1 FO=1 Routing Delay 0.98 1.11 1.30 1.82 ns tRD2 FO=2 Routing Delay 1.35 1.54 1.81 2.53 ns tRD3 FO=3 Routing Delay 1.73 1.96 2.31 3.23 ns tRD4 FO=4 Routing Delay 2.11 2.39 2.81 3.94 ns tRD8 FO=8 Routing Delay 3.62 4.11 4.83 6.76 ns 3, 4 Sequential Timing Characteristics tSUD Flip-Flop (Latch) Data Input Setup 0.50 0.57 0.67 0.94 ns tHD Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tSUENA Flip-Flop (Latch) Enable Setup 0.63 0.71 0.84 1.18 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.27 5.97 7.03 9.84 ns Flip-Flop (Latch) Asynchronous Pulse Width 6.91 7.83 9.21 12.90 ns tA Flip-Flop Clock Input Period 6.30 7.14 8.40 11.76 ns tINH Input Buffer Latch Hold 0.00 0.0 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.30 0.4 0.4 0.6 ns tOUTH Output Buffer Latch Hold 0.00 0.0 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.30 0.4 0.4 0.6 ns fMAX Flip-Flop (Latch) Clock Frequency tWASYN 135 125 108 65 MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. VCC = 3.0 V for 3.3V specifications. 1-134 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX09 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINYH Pad to Y High 1.63 1.84 2.17 3.04 ns tINYL Pad to Y Low 2.01 2.27 2.67 3.74 ns tINGH G to Y High 0.76 0.86 1.01 1.41 ns tINGL G to Y Low 7.41 8.40 9.88 13.84 ns 1 Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 2.87 3.25 3.82 5.35 ns tIRD2 FO=2 Routing Delay 3.28 3.71 4.37 6.12 ns tIRD3 FO=3 Routing Delay 3.70 4.19 4.93 6.90 ns tIRD4 FO=4 Routing Delay 4.12 4.66 5.49 7.68 ns tIRD8 FO=8 Routing Delay 5.78 6.55 7.70 10.78 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 256 3.84 4.41 4.36 5.00 5.12 5.88 7.17 8.23 ns ns tCKL Input High to Low FO = 32 FO = 256 3.56 4.10 4.03 4.64 4.75 5.46 6.64 7.64 ns ns tPWH Minimum Pulse Width High FO = 32 FO = 256 1.89 2.05 2.14 2.32 2.52 2.73 3.53 3.82 ns ns tPWL Minimum Pulse Width Low FO = 32 FO = 256 1.89 2.05 2.14 2.32 2.52 2.73 3.53 3.82 ns ns tCKSW Maximum Skew tSUEXT Input Latch External Setup FO = 32 FO = 256 0.76 0.76 0.86 0.86 1.01 1.01 1.41 1.41 ns ns tHEXT Input Latch External Hold FO = 32 FO = 256 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns tP Minimum Period FO = 32 FO = 256 5.88 6.30 6.66 7.14 7.84 8.40 10.98 11.76 ns ns fMAX Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 0.47 0.47 150 135 0.54 0.54 140 125 0.63 0.63 120 108 0.88 0.88 72 65 ns ns MHz MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 3 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst case performance 1-135 A42MX09 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 3.79 4.30 5.05 7.08 ns tDHL Data to Pad Low 4.46 5.06 5.95 8.33 ns tENZH Enable Pad Z to High 4.10 4.64 5.46 7.64 ns tENZL Enable Pad Z to Low 4.54 5.14 6.05 8.47 ns tENHZ Enable Pad High to Z 7.61 8.63 10.15 14.21 ns tENLZ Enable Pad Low to Z 8.30 9.40 11.06 15.48 ns tGLH G to Pad High 6.45 7.31 8.60 12.03 ns tGHL G to Pad Low 6.45 7.31 8.60 12.03 ns tLSU I/O Latch Setup 0.76 0.86 1.01 1.41 ns tLH I/O Latch Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 9.66 10.95 12.88 18.03 ns Array Clock-Out (pad-to-pad), 64 clock loading 13.55 15.35 18.06 25.28 ns dTLH Capacity Loading, Low to High 0.04 0.05 0.06 0.08 ns/pF dTHL Capacity Loading, High to Low 0.05 0.06 0.07 0.10 ns/pF tACO 1 CMOS Output Module Timing tDLH Data to Pad High 4.81 5.45 6.41 8.98 ns tDHL Data to Pad Low 3.73 4.22 4.97 6.96 ns tENZH Enable Pad Z to High 4.10 4.64 5.46 7.64 ns tENZL Enable Pad Z to Low 4.54 5.14 6.05 8.47 ns tENHZ Enable Pad High to Z 7.61 8.63 10.15 14.21 ns tENLZ Enable Pad Low to Z 8.30 9.40 11.06 15.48 ns tGLH G to Pad High 6.45 7.31 8.60 12.03 ns tGHL G to Pad Low 6.45 7.31 8.60 12.03 ns tLSU I/O Latch Setup 0.76 0.86 1.01 1.41 ns tLH I/O Latch Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 9.66 10.95 12.88 18.03 ns Array Clock-Out (pad-to-pad), 64 clock loading 13.55 15.35 18.06 25.28 ns dTLH Capacity Loading, Low to High 0.04 0.05 0.06 0.08 ns/pF dTHL Capacity Loading, High to Low 0.05 0.06 0.07 0.10 ns/pF tACO Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-136 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays1 `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Min. Min. Min. tPD1 Single Module 2.0 2.3 tCO Sequential Clk to Q 1.9 tGO Latch G to Q tRS Flip-Flop (Latch) Reset to Q Max. Max. Max. Max. Units 2.7 3.8 ns 2.2 2.6 3.6 ns 2.0 2.3 2.7 3.8 ns 1.8 2.0 2.4 3.3 ns 2 Predicted Routing Delays tRD1 FO=1 Routing Delay 1.0 1.1 1.3 1.8 ns tRD2 FO=2 Routing Delay 1.4 1.5 1.8 2.5 ns tRD3 FO=3 Routing Delay 1.7 1.9 2.2 3.1 ns tRD4 FO=4 Routing Delay 2.0 2.2 2.6 3.6 ns tRD8 FO=8 Routing Delay 3.8 4.3 5.0 7.0 ns 3,4 Sequential Timing Characteristics tSUD Flip-Flop (Latch) Data Input Setup 0.4 0.4 0.5 0.7 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 1.4 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.8 4.3 5.0 7.0 ns Flip-Flop (Latch) Asynchronous Pulse Width 4.9 5.6 6.6 9.2 ns tA Flip-Flop Clock Input Period 7.5 8.5 10.0 14.0 ns tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.5 0.6 0.7 1.0 ns tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.5 0.6 0.7 1.0 ns fMAX Flip-Flop (Latch) Clock Frequency tWASYN 216 180 156 94 MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 1-137 A42MX16 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Min. Min. Min. tINYH Pad to Y High 1.3 1.4 tINYL Pad to Y Low 1.0 tINGH G to Y High tINGL G to Y Low Max. Max. Max. Max. Units 1.7 2.4 ns 1.1 1.3 1.8 ns 2.1 2.3 2.7 3.8 ns 2.5 2.8 3.4 4.7 ns 1 Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 3.2 3.7 4.3 6.0 ns tIRD2 FO=2 Routing Delay 3.7 4.2 4.9 6.9 ns tIRD3 FO=3 Routing Delay 4.0 4.5 5.3 7.4 ns tIRD4 FO=4 Routing Delay 4.6 5.2 6.1 8.5 ns tIRD8 FO=8 Routing Delay 6.6 7.5 8.8 12.3 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 384 2.6 3.0 3.0 3.4 3.5 4.0 4.9 5.6 ns ns tCKL Input High to Low FO = 32 FO = 384 2.5 2.9 2.8 3.2 3.3 3.8 4.6 5.3 ns ns tPWH Minimum Pulse Width High FO = 32 FO = 384 3.5 4.1 4.0 4.6 4.7 5.4 6.5 7.6 ns ns tPWL Minimum Pulse Width Low FO = 32 FO = 384 3.5 4.1 4.0 4.6 4.7 5.4 6.6 7.6 ns ns tCKSW Maximum Skew tSUEXT Input Latch External Setup FO = 32 FO = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 384 4.9 7.4 5.5 8.3 6.5 9.8 9.1 13.7 ns ns tP Minimum Period FO = 32 FO = 384 6.7 7.4 7.6 8.4 8.9 9.9 12.5 13.9 ns ns fMAX Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 0.4 1.7 215 195 0.4 2.0 200 180 0.5 2.3 172 156 0.7 3.2 103 94 ns ns MHz MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 1-138 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX16 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Min. Min. Min. TTL Output Module Timing1 Max. Max. Max. Max. Units tDLH Data to Pad High 2.7 3.1 3.6 5.1 ns tDHL Data to Pad Low 3.3 3.7 4.4 6.2 ns tENZH Enable Pad Z to High 3.0 3.4 4.0 5.6 ns tENZL Enable Pad Z to Low 3.3 3.8 4.5 6.2 ns tENHZ Enable Pad High to Z 6.3 7.1 8.4 11.7 ns tENLZ Enable Pad Low to Z 5.8 6.5 7.7 10.8 ns tGLH G to Pad High 5.9 6.6 7.8 10.9 ns tGHL G to Pad Low 6.4 7.3 8.6 12.0 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 6.9 9.2 12.9 ns Array Clock-Out (pad-to-pad), 64 clock loading 9.7 11.0 12.9 18.1 ns dTLH Capacitive Loading, Low to High 0.03 0.03 0.04 0.06 ns/pF dTHL Capacitive Loading, High to Low 0.04 0.04 0.05 0.07 ns/pF tACO 7.8 1 CMOS Output Module Timing tDLH Data to Pad High 3.1 3.5 4.2 5.8 ns tDHL Data to Pad Low 3.8 4.3 5.1 7.1 ns tENZH Enable Pad Z to High 4.0 4.5 5.3 7.5 ns tENZL Enable Pad Z to Low 4.3 4.9 5.8 8.1 ns tENHZ Enable Pad High to Z 7.0 7.9 9.3 13.0 ns tENLZ Enable Pad Low to Z 6.9 7.9 9.2 12.9 ns tGLH G to Pad High 6.9 7.9 9.3 13.0 ns tGHL G to Pad Low 7.5 8.5 10.0 14.0 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 6.9 7.8 9.2 12.9 ns Array Clock-Out (pad-to-pad), 64 clock loading 9.7 11.0 12.9 18.1 ns dTLH Capacitive Loading, Low to High 0.03 0.03 0.04 0.06 ns/pF dTHL Capacitive Loading, High to Low 0.04 0.04 0.05 0.07 ns/pF tACO Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-139 A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70C) Logic Module Propagation Delays1 `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Min. Min. Min. tPD1 Single Module 2.8 3.2 tCO Sequential Clk to Q 2.7 tGO Latch G to Q tRS Flip-Flop (Latch) Reset to Q Max. Max. Max. Max. Units 3.8 5.3 ns 3.1 3.6 5.0 ns 2.8 3.2 3.8 5.3 ns 2.5 2.8 3.3 4.7 ns 2 Predicted Routing Delays tRD1 FO=1 Routing Delay 1.4 1.5 1.8 2.5 ns tRD2 FO=2 Routing Delay 1.9 2.1 2.5 3.5 ns tRD3 FO=3 Routing Delay 2.3 2.6 3.1 4.3 ns tRD4 FO=4 Routing Delay 2.7 3.1 3.6 5.1 ns tRD8 FO=8 Routing Delay 5.3 6.0 7.0 9.8 ns 3,4 Sequential Timing Characteristics tSUD Flip-Flop (Latch) Data Input Setup 0.5 0.6 0.7 0.9 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 1.1 1.2 1.4 2.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.3 6.0 7.0 9.8 ns Flip-Flop (Latch) Asynchronous Pulse Width 6.9 7.8 9.2 12.9 ns tA Flip-Flop Clock Input Period 10.5 11.9 14.0 19.6 ns tINH Input Buffer Latch Hold 0.0 0.0 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.8 0.9 1.0 1.4 ns tOUTH Output Buffer Latch Hold 0.0 0.0 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.8 0.9 1.0 1.4 ns fMAX Flip-Flop (Latch) Clock Frequency tWASYN 130 108 94 57 MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. VCC = 3.0 V for 3.3V specifications. 1-140 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX16 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Min. Min. Min. tINYH Pad to Y High 1.8 2.0 tINYL Pad to Y Low 1.4 tINGH G to Y High tINGL G to Y Low Max. Max. Max. Max. Units 2.4 3.3 ns 1.5 1.8 2.5 ns 2.9 3.3 3.8 5.4 ns 3.5 4.0 4.7 6.6 ns 1 Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 4.5 5.1 6.0 8.4 ns tIRD2 FO=2 Routing Delay 5.1 5.8 6.9 9.6 ns tIRD3 FO=3 Routing Delay 5.6 6.3 7.4 10.4 ns tIRD4 FO=4 Routing Delay 6.4 7.3 8.5 12.0 ns tIRD8 FO=8 Routing Delay 9.2 10.5 12.3 17.2 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 384 3.7 4.2 4.2 4.8 4.9 5.6 6.9 7.9 ns ns tCKL Input High to Low FO = 32 FO = 384 3.5 4.0 3.9 4.5 4.6 5.3 6.5 7.4 ns ns tPWH Minimum Pulse Width High FO = 32 FO = 384 4.9 5.7 5.5 6.4 6.5 7.6 9.1 10.6 ns ns tPWL Minimum Pulse Width Low FO = 32 FO = 384 4.9 5.7 5.6 6.4 6.6 7.6 9.2 10.6 ns ns tCKSW Maximum Skew tSUEXT Input Latch External Setup FO = 32 FO = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 384 6.8 10.3 7.7 11.7 9.1 13.7 12.7 19.2 ns ns tP Minimum Period FO = 32 FO = 384 9.3 10.4 10.6 11.8 12.5 13.9 17.4 19.4 ns ns fMAX Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 0.5 2.4 144 130 0.6 2.8 120 108 0.7 3.2 104 94 0.9 4.5 62 57 ns ns MHz MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 1-141 A42MX16 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing `-2' Speed `-1' Speed `Std' Speed `-F' Speed Parameter Description Min. Min. Min. Min. TTL Output Module Timing1 Max. Max. Max. Max. Units tDLH Data to Pad High 3.8 4.3 5.1 7.1 ns tDHL Data to Pad Low 4.6 5.2 6.2 8.6 ns tENZH Enable Pad Z to High 4.2 4.8 5.6 7.9 ns tENZL Enable Pad Z to Low 4.7 5.3 6.2 8.7 ns tENHZ Enable Pad High to Z 8.8 10.0 11.7 16.4 ns tENLZ Enable Pad Low to Z 8.1 9.1 10.8 15.1 ns tGLH G to Pad High 8.2 9.3 10.9 15.3 ns tGHL G to Pad Low 9.0 10.2 12.0 16.8 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 9.7 10.9 12.9 18.0 ns tACO Array Clock-Out (pad-to-pad), 64 clock loading 13.5 15.4 18.1 25.3 ns dTLH Capacitive Loading, Low to High 0.04 0.05 0.06 0.08 ns/pF dTHL Capacitive Loading, High to Low 0.05 0.06 0.07 0.10 ns/pF 1 CMOS Output Module Timing tDLH Data to Pad High 4.4 4.9 5.8 8.1 ns tDHL Data to Pad Low 5.3 6.0 7.1 9.9 ns tENZH Enable Pad Z to High 5.6 6.4 7.5 10.5 ns tENZL Enable Pad Z to Low 6.1 6.9 8.1 11.3 ns tENHZ Enable Pad High to Z 9.8 11.1 13.0 18.2 ns tENLZ Enable Pad Low to Z 9.7 11.0 12.9 18.1 ns tGLH G to Pad High 9.7 11.0 13.0 18.1 ns tGHL G to Pad Low 10.5 11.9 14.0 19.6 ns tLCO I/O Latch Clock-Out (pad-to-pad), 64 clock loading 9.7 10.9 12.9 18.0 ns Array Clock-Out (pad-to-pad), 64 clock loading 13.5 15.4 18.1 25.3 ns dTLH Capacitive Loading, Low to High 0.04 0.05 0.06 0.08 ns/pF dTHL Capacitive Loading, High to Low 0.05 0.06 0.07 0.10 ns/pF tACO Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-142 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Propagation Delays1 Parameter Description `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Combinatorial Functions tPD Internal Array Module Delay 1.55 1.75 2.06 2.88 ns tPDD Internal Decode Module Delay 1.64 1.86 2.19 3.07 ns 2 Predicted Routing Delays tRD1 FO=1 Routing Delay 1.25 1.41 1.66 2.32 ns tRD2 FO=2 Routing Delay 1.52 1.72 2.02 2.83 ns tRD3 FO=3 Routing Delay 1.79 2.02 2.38 3.33 ns tRD4 FO=4 Routing Delay 2.06 2.33 2.74 3.84 ns tRD5 FO=8 Routing Delay 3.14 3.55 4.18 5.85 ns 3, 4 Sequential Timing Characteristics tCO Flip-Flop Clock-to-Output 1.36 1.54 1.81 2.53 ns tGO Latch Gate-to-Output 1.32 1.50 1.76 2.46 ns tSU Flip-Flop (Latch) Setup Time 0.35 0.40 0.47 0.66 ns tH Flip-Flop (Latch) Hold Time 0.00 0.00 0.00 0.00 ns tRO Flip-Flop (Latch) Reset to Output tSUENA Flip-Flop (Latch) Enable Setup 0.45 0.51 0.60 0.84 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.70 4.19 4.93 6.90 ns Flip-Flop (Latch) Asynchronous Pulse Width 3.85 5.49 6.46 9.04 ns tWASYN 1.36 1.54 1.81 2.53 ns Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 1-143 A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINPY Input Data Pad to Y 1.16 1.31 1.54 2.16 ns tINGO Input Latch Gate-to-Output 1.43 1.62 1.91 2.67 ns tINH Input Latch Hold 0.00 0.00 0.00 0.00 ns tINSU Input Latch Setup 0.53 0.60 0.70 0.98 ns tILA Latch Active Pulse Width 5.20 5.89 6.93 9.70 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 2.64 2.99 3.52 4.93 ns tIRD2 FO=2 Routing Delay 2.94 3.33 3.92 5.49 ns tIRD3 FO=3 Routing Delay 3.23 3.66 4.31 6.03 ns tIRD4 FO=4 Routing Delay 3.53 4.00 4.71 6.59 ns tIRD8 FO=8 Routing Delay 4.72 5.35 6.29 8.81 ns Global Clock Network tCKH Input Low to High FO=32 FO=486 2.87 3.64 3.25 4.12 3.82 4.85 5.35 6.79 ns ns tCKL Input High to Low FO=32 FO=486 2.36 3.08 2.67 3.50 3.14 4.12 4.40 5.77 ns ns tPWH Minimum Pulse Width High FO=32 FO=486 2.40 2.63 2.72 2.98 3.20 3.50 4.48 4.90 ns ns tPWL Minimum Pulse Width Low FO=32 FO=486 2.40 2.63 2.72 2.98 3.20 3.50 4.48 4.90 ns ns tCKSW Maximum Skew FO=32 FO=486 tSUEXT Input Latch External Setup FO=32 FO=486 0.53 0.53 0.60 0.60 0.70 0.70 0.98 0.98 ns ns tHEXT Input Latch External Hold FO=32 FO=486 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns tP Minimum Period (1/fmax) FO=32 FO=486 4.88 5.40 5.53 6.12 6.50 7.20 9.10 10.08 ns ns fMAX Maximum Data-Path Frequency FO=32 FO=486 0.60 0.60 191.25 175.00 0.68 0.68 175.95 161.00 0.80 0.80 153.00 140.00 1.12 1.12 91.80 84.00 ns ns MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. 1-144 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Output Module Timing `-2 Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 2.97 3.37 3.96 5.54 ns tDHL Data to Pad Low 3.35 3.80 4.47 6.26 ns tENZH Enable Pad Z to High 2.25 2.55 3.00 4.20 ns tENZL Enable Pad Z to Low 2.68 3.03 3.57 5.00 ns tENHZ Enable Pad High to Z 5.83 6.60 7.77 10.88 ns tENLZ Enable Pad Low to Z 5.39 6.10 7.18 10.05 ns tGLH G to Pad High 4.58 5.19 6.10 8.54 ns tGHL G to Pad Low 4.58 5.19 6.10 8.54 ns tLSU I/O Latch Output Setup 0.53 0.60 0.70 0.98 ns tLH I/O Latch Output Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 8.33 9.44 11.10 15.54 ns tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 11.78 13.35 15.70 21.98 ns dTLH Capacitive Loading, Low to High 0.04 0.04 0.05 0.07 ns/pF dTHL Capacitive Loading, High to Low 0.03 0.03 0.04 0.06 ns/pF 1 CMOS Output Module Timing tDLH Data to Pad High 3.80 4.31 5.07 7.10 ns tDHL Data to Pad Low 2.78 3.15 3.71 5.19 ns tENZH Enable Pad Z to High 2.25 2.55 3.00 4.20 ns tENZL Enable Pad Z to Low 2.68 3.03 3.57 5.00 ns tENHZ Enable Pad High to Z 5.83 6.60 7.77 10.88 ns tENLZ Enable Pad Low to Z 5.39 6.10 7.18 10.05 ns tGLH G to Pad High 4.58 5.19 6.10 8.54 ns tGHL G to Pad Low 4.58 5.19 6.10 8.54 ns tLSU I/O Latch Setup 0.53 0.60 0.70 0.98 ns tLH I/O Latch Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 8.33 9.44 11.10 15.54 ns tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 11.78 13.35 15.70 21.98 ns dTLH Capacitive Loading, Low to High 0.04 0.04 0.05 0.07 ns/pF dTHL Capacitive Loading, High to Low 0.03 0.03 0.04 0.06 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-145 A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Propagation Delays1 Parameter Description `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Combinatorial Functions tPD Internal Array Module Delay 2.16 2.45 2.88 4.04 ns tPDD Internal Decode Module Delay 2.30 2.61 3.07 4.29 ns 2 Predicted Routing Delays tRD1 FO=1 Routing Delay 1.74 1.98 2.32 3.25 ns tRD2 FO=2 Routing Delay 2.12 2.40 2.83 3.96 ns tRD3 FO=3 Routing Delay 2.50 2.83 3.33 4.66 ns tRD4 FO=4 Routing Delay 2.88 3.26 3.84 5.37 ns tRD5 FO=8 Routing Delay 4.39 4.97 5.85 8.19 ns 3, 4 Sequential Timing Characteristics tCO Flip-Flop Clock-to-Output 1.90 2.15 2.53 3.55 ns tGO Latch Gate-to-Output 1.85 2.09 2.46 3.45 ns tSU Flip-Flop (Latch) Setup Time 0.49 0.56 0.66 0.92 ns tH Flip-Flop (Latch) Hold Time 0.00 0.00 0.00 0.00 ns tRO Flip-Flop (Latch) Reset to Output tSUENA Flip-Flop (Latch) Enable Setup 0.63 0.71 0.84 1.18 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.18 5.87 6.90 9.66 ns Flip-Flop (Latch) Asynchronous Pulse Width 6.78 7.69 9.04 12.66 ns tWASYN 1.90 2.15 2.53 3.55 ns Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Postroute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 1-146 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Input Module Propagation Delays `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units tINPY Input Data Pad to Y 1.62 1.83 2.16 3.02 ns tINGO Input Latch Gate-to-Output 2.01 2.27 2.67 3.74 ns tINH Input Latch Hold 0.00 0.00 0.00 0.00 ns tINSU Input Latch Setup 0.74 0.83 0.98 1.37 ns tILA Latch Active Pulse Width 7.28 8.25 9.70 13.58 ns 1 Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 3.70 4.19 4.93 6.90 ns tIRD2 FO=2 Routing Delay 4.12 4.66 5.49 7.68 ns tIRD3 FO=3 Routing Delay 4.53 5.13 6.03 8.45 ns tIRD4 FO=4 Routing Delay 4.95 5.60 6.59 9.23 ns tIRD8 FO=8 Routing Delay 6.60 7.49 8.81 12.33 ns Global Clock Network tCKH Input Low to High FO=32 FO=486 4.01 5.09 4.55 5.77 5.35 6.79 7.49 9.51 ns ns tCKL Input High to Low FO=32 FO=486 3.30 4.33 3.74 4.90 4.40 5.77 6.15 8.08 ns ns tPWH Minimum Pulse Width High FO=32 FO=486 3.36 3.68 3.81 4.17 4.48 4.90 6.27 6.86 ns ns tPWL Minimum Pulse Width Low FO=32 FO=486 3.36 3.68 3.81 4.17 4.48 4.90 6.27 6.86 ns ns tCKSW Maximum Skew FO=32 FO=486 tSUEXT Input Latch External Setup FO=32 FO=486 0.74 0.74 0.83 0.83 0.98 0.98 1.37 1.37 ns ns tHEXT Input Latch External Hold FO=32 FO=486 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ns ns tP Minimum Period (1/fmax) FO=32 FO=486 6.83 7.56 7.74 8.57 9.10 10.08 12.74 14.11 ns ns fMAX Maximum Data-Path Frequency FO=32 FO=486 0.84 0.84 114.75 105.00 0.95 0.95 105.57 96.60 1.12 1.12 91.80 84.00 1.57 1.57 55.08 50.40 ns ns MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. 1-147 A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Output Module Timing `-2 Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 4.16 4.71 5.54 7.76 ns tDHL Data to Pad Low 4.69 5.32 6.26 8.76 ns tENZH Enable Pad Z to High 3.15 3.57 4.20 5.88 ns tENZL Enable Pad Z to Low 3.75 4.25 5.00 7.00 ns tENHZ Enable Pad High to Z 8.16 9.25 10.88 15.23 ns tENLZ Enable Pad Low to Z 7.54 8.54 10.05 14.07 ns tGLH G to Pad High 6.41 7.26 8.54 11.96 ns tGHL G to Pad Low 6.41 7.26 8.54 11.96 ns tLSU I/O Latch Output Setup 0.74 0.83 0.98 1.37 ns tLH I/O Latch Output Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 11.66 13.21 15.54 21.76 ns Array Latch Clock-Out (Pad-to-Pad) 32 I/O 16.49 18.68 21.98 30.77 ns dTLH Capacitive Loading, Low to High 0.05 0.06 0.07 0.10 ns/pF dTHL Capacitive Loading, High to Low 0.04 0.05 0.06 0.08 ns/pF tACO 1 CMOS Output Module Timing tDLH Data to Pad High 5.32 6.03 7.10 9.94 ns tDHL Data to Pad Low 3.90 4.41 5.19 7.27 ns tENZH Enable Pad Z to High 3.15 3.57 4.20 5.88 ns tENZL Enable Pad Z to Low 3.75 4.25 5.00 7.00 ns tENHZ Enable Pad High to Z 8.16 9.25 10.88 15.23 ns tENLZ Enable Pad Low to Z 7.54 8.54 10.05 14.07 ns tGLH G to Pad High 6.41 7.26 8.54 11.96 ns tGHL G to Pad Low 6.41 7.26 8.54 11.96 ns tLSU I/O Latch Setup 0.74 0.83 0.98 1.37 ns tLH I/O Latch Hold 0.00 0.00 0.00 0.00 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 11.66 13.21 15.54 21.76 ns Array Latch Clock-Out (Pad-to-Pad) 32 I/O 16.49 18.68 21.98 30.77 ns dTLH Capacitive Loading, Low to High 0.05 0.06 0.07 0.10 ns/pF dTHL Capacitive Loading, High to Low 0.04 0.05 0.06 0.08 ns/pF tACO Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-148 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Propagation Delays Parameter Description `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Combinatorial Functions tPD Internal Array Module Delay 1.5 1.7 2.0 2.7 ns tPDD Internal Decode Module Delay 1.9 2.1 2.5 3.5 ns Predicted Module Routing Delays tRD1 FO=1 Routing Delay 1.0 1.1 1.3 1.9 ns tRD2 FO=2 Routing Delay 1.1 1.3 1.5 2.1 ns tRD3 FO=3 Routing Delay 1.3 1.5 1.7 2.4 ns tRD4 FO=4 Routing Delay 1.4 1.6 1.9 2.7 ns tRD5 FO=8 Routing Delay 2.1 2.3 2.8 3.9 ns tRDD Decode-to-Output Routing Delay 0.4 0.4 0.5 0.7 ns Sequential Timing Characteristics tCO Flip-Flop Clock-to-Output 1.5 1.7 2.0 2.8 ns tGO Latch Gate-to-Output 1.5 1.7 2.0 2.7 ns tSU Flip-Flop (Latch) Setup Time 0.4 0.4 0.5 0.7 ns tH Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 ns tRO Flip-Flop (Latch) Reset to Output tSUENA Flip-Flop (Latch) Enable Setup 0.8 0.9 1.0 1.4 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.7 4.2 4.9 6.9 ns Flip-Flop (Latch) Asynchronous Pulse Width 4.8 5.5 6.5 9.0 ns tWASYN 1.5 1.7 2.0 2.8 ns 1-149 A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Timing Parameter Description `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Synchronous SRAM Operations tRC Read Cycle Time 7.5 8.5 10.0 14.0 ns tWC Write Cycle Time 7.5 8.5 10.0 14.0 ns tRCKHL Clock High/Low Time 3.8 4.3 5.0 7.0 ns tRCO Data Valid After Clock High/Low tADSU Address/Data Setup Time 1.8 2.0 2.4 3.4 ns tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 ns tRENSU Read Enable Setup 0.7 0.8 0.9 1.3 ns tRENH Read Enable Hold 3.8 4.3 5.0 7.0 ns tWENSU Write Enable Setup 3.0 3.4 4.0 5.6 ns tWENH Write Enable Hold 0.0 0.0 0.0 0.0 ns tBENS Block Enable Setup 3.1 3.5 4.1 5.7 ns tBENH Block Enable Hold 0.0 0.0 0.0 0.0 ns 3.8 4.3 5.0 7.0 ns Asynchronous SRAM Operations tRPD Asynchronous Access Time tRDADV Read Address Valid 9.8 11.1 13.0 18.2 ns tADSU Address/Data Setup Time 1.8 2.0 2.4 3.4 ns tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 ns tRENSUA Read Enable Setup to Address Valid 0.7 0.8 0.9 1.3 ns tRENHA Read Enable Hold 3.8 4.3 5.0 7.0 ns tWENSU Write Enable Setup 3.0 3.4 4.0 5.6 ns tWENH Write Enable Hold 0.0 0.0 0.0 0.0 ns tDOH Data Out Hold Time 1-150 9.0 1.4 10.2 1.5 12.0 1.8 16.8 2.5 ns ns In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Advanced Information Input Module Propagation Delays `-2' Speed Parameter Description tINPY tINGO tINH tINSU tILA Min. Input Data Pad to Y Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units 1.3 1.5 1.7 2.4 ns 1.6 1.8 2.1 3.0 ns Input Latch Gate-to-Output1 Input Latch Hold1 0.0 0.0 0.0 0.0 ns Input Latch Setup1 0.5 0.6 0.7 1.0 ns 5.2 5.9 6.9 9.7 ns Latch Active Pulse Width1 Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 3.2 3.7 4.3 6.0 ns tIRD2 FO=2 Routing Delay 3.7 4.2 4.9 6.9 ns tIRD3 FO=3 Routing Delay 4.0 4.5 5.3 7.4 ns tIRD4 FO=4 Routing Delay 4.6 5.2 6.1 8.5 ns tIRD8 FO=8 Routing Delay 6.6 7.5 8.8 12.3 ns Global Clock Network tCKH Input Low to High FO=32 FO=635 6.7 8.6 7.6 9.8 8.9 11.5 12.5 16.1 ns ns tCKL Input High to Low FO=32 FO=635 6.2 8.0 7.0 9.1 8.2 10.7 11.5 15.0 ns ns tPWH Minimum Pulse Width High FO=32 FO=635 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns tPWL Minimum Pulse Width Low FO=32 FO=635 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns tCKSW Maximum Skew FO=32 FO=635 tSUEXT Input Latch External Setup FO=32 FO=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=635 2.6 3.2 2.9 3.7 3.4 4.3 4.8 6.0 ns ns tP Minimum Period (1/fmax) FO=32 FO=635 6.5 7.2 7.4 8.2 8.7 9.6 12.2 13.4 ns ns fHMAX Maximum Data-Path Frequency FO=32 FO=635 0.8 0.8 164 152 0.9 0.9 151 140 1.0 1.0 131 121 1.4 1.4 79 73 ns ns MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. 1-151 A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Advanced Information Output Module Timing `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 3.1 3.5 4.2 5.8 ns tDHL Data to Pad Low 3.6 4.1 4.8 6.7 ns tENZH Enable Pad Z to High 3.3 3.7 4.4 6.1 ns tENZL Enable Pad Z to Low 3.6 4.0 4.8 6.7 ns tENHZ Enable Pad High to Z 6.6 7.4 8.7 12.2 ns tENLZ Enable Pad Low to Z 6.1 6.9 8.1 11.3 ns tGLH G to Pad High 5.1 5.8 6.8 9.6 ns tGHL G to Pad Low 5.1 5.8 6.8 9.6 ns tLSU I/O Latch Output Setup 0.5 0.6 0.7 1.0 ns tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 9.8 11.1 13.1 18.3 ns Array Latch Clock-Out (Pad-to-Pad) 32 I/O 13.9 15.7 18.5 25.9 ns dTLH Capacitive Loading, Low to High 0.0 0.0 0.1 0.1 ns/pF dTHL Capacitive Loading, High to Low 0.1 0.1 0.1 0.1 ns/pF 8.1 ns tACO 1 CMOS Output Module Timing tDLH Data to Pad High 4.4 4.9 5.8 tDHL Data to Pad Low 5.3 6.0 7.1 9.9 ns tENZH Enable Pad Z to High 5.6 6.4 7.5 10.5 ns tENZL Enable Pad Z to Low 6.1 6.9 8.1 11.3 ns tENHZ Enable Pad High to Z 9.8 11.1 13.0 18.2 ns tENLZ Enable Pad Low to Z 9.8 11.1 13.0 18.2 ns tGLH G to Pad High 9.8 11.1 13.0 18.2 ns tGHL G to Pad Low 10.5 11.9 14.0 19.6 ns tLSU I/O Latch Setup 0.3 0.3 0.4 0.6 ns tLH I/O Latch Hold 0.0 0.0 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 11.6 13.2 15.5 21.7 tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 16.4 18.5 21.8 30.5 ns dTLH Capacitive Loading, Low to High 0.1 0.1 0.1 0.1 ns/pF dTHL Capacitive Loading, High to Low 0.0 0.1 0.1 0.1 ns/pF ns Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-152 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Propagation Delays Parameter Description `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Combinatorial Functions tPD Internal Array Module Delay 2.1 2.3 2.7 3.8 ns tPDD Internal Decode Module Delay 2.6 2.9 3.5 4.8 ns Predicted Module Routing Delays tRD1 FO=1 Routing Delay 1.4 1.6 1.9 2.6 ns tRD2 FO=2 Routing Delay 1.6 1.8 2.1 3.0 ns tRD3 FO=3 Routing Delay 1.8 2.0 2.4 3.4 ns tRD4 FO=4 Routing Delay 2.0 2.3 2.7 3.8 ns tRD5 FO=8 Routing Delay 2.9 3.3 3.9 5.4 ns tRDD Decode-to-Output Routing Delay 0.5 0.6 0.7 1.0 ns Sequential Timing Characteristics tCO Flip-Flop Clock-to-Output 2.1 2.4 2.8 4.0 ns tGO Latch Gate-to-Output 2.1 2.3 2.7 3.8 ns tSU Flip-Flop (Latch) Setup Time 0.5 0.6 0.7 0.9 ns tH Flip-Flop (Latch) Hold Time 0.0 0.0 0.0 0.0 ns tRO Flip-Flop (Latch) Reset to Output tSUENA Flip-Flop (Latch) Enable Setup 1.1 1.2 1.4 2.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.2 5.9 6.9 9.7 ns Flip-Flop (Latch) Asynchronous Pulse Width 6.8 7.7 9.0 12.7 ns tWASYN 2.1 2.4 2.8 4.0 ns 1-153 A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Timing Parameter Description `-2 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units Synchronous SRAM Operations tRC Read Cycle Time 10.5 11.9 14.0 19.6 ns tWC Write Cycle Time 10.5 11.9 14.0 19.6 ns tRCKHL Clock High/Low Time 5.3 6.0 7.0 9.8 ns tRCO Data Valid After Clock High/Low tADSU Address/Data Setup Time 2.5 2.8 3.4 4.8 ns tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 ns tRENSU Read Enable Setup 12.0 1.1 1.3 1.8 ns tRENH Read Enable Hold 5.3 6.0 7.0 9.8 ns tWENSU Write Enable Setup 4.2 4.8 5.6 7.8 ns tWENH Write Enable Hold 0.0 0.0 0.0 0.0 ns tBENS Block Enable Setup 4.3 4.9 5.7 8.0 ns tBENH Block Enable Hold 0.0 0.0 0.0 0.0 ns 5.3 6.0 7.0 9.8 ns Asynchronous SRAM Operations tRPD Asynchronous Access Time tRDADV Read Address Valid 13.7 15.5 18.2 25.5 ns tADSU Address/Data Setup Time 2.5 2.8 3.4 9.5 ns tADH Address/Data Hold Time 0.0 0.0 0.0 0.0 ns tRENSUA Read Enable Setup to Address Valid 1.0 1.1 1.3 1.8 ns tRENHA Read Enable Hold 5.3 6.0 7.0 9.8 ns tWENSU Write Enable Setup 4.2 4.8 5.6 7.8 ns tWENH Write Enable Hold 0.0 0.0 0.0 0.0 ns tDOH Data Out Hold Time 1-154 12.6 2.0 14.3 2.1 16.8 2.5 23.5 3.5 ns ns In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Input Module Propagation Delays `-2' Speed Parameter Description tINPY tINGO tINH tINSU tILA Min. Input Data Pad to Y Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units 1.8 2.1 2.4 3.4 ns 2.2 2.5 3.0 4.2 ns Input Latch Gate-to-Output1 Input Latch Hold1 0.0 0.0 0.0 0.0 ns Input Latch Setup1 0.7 0.8 1.0 1.4 ns 7.3 8.2 9.7 13.6 ns Latch Active Pulse Width1 Input Module Predicted Routing Delays tIRD1 FO=1 Routing Delay 4.5 5.1 6.0 8.4 ns tIRD2 FO=2 Routing Delay 5.1 5.8 6.9 9.6 ns tIRD3 FO=3 Routing Delay 5.6 6.3 7.4 10.4 ns tIRD4 FO=4 Routing Delay 6.4 7.3 8.5 12.0 ns tIRD8 FO=8 Routing Delay 9.2 10.5 12.3 17.2 ns Global Clock Network tCKH Input Low to High FO=32 FO=635 9.3 12.1 10.6 13.7 12.5 16.1 17.4 22.5 ns ns tCKL Input High to Low FO=32 FO=635 8.6 11.2 9.8 12.7 11.5 15.0 16.1 21.0 ns ns tPWH Minimum Pulse Width High FO=32 FO=635 2.7 3.0 3.1 3.5 3.6 4.1 5.1 5.7 ns ns tPWL Minimum Pulse Width Low FO=32 FO=635 2.7 3.0 3.1 3.5 3.6 4.1 5.1 5.7 ns ns tCKSW Maximum Skew FO=32 FO=635 tSUEXT Input Latch External Setup FO=32 FO=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=635 3.6 4.5 4.0 5.1 4.8 6.0 6.7 8.4 ns ns tP Minimum Period (1/fmax) FO=32 FO=635 9.1 10.1 10.4 11.4 12.2 13.4 17.1 18.8 ns ns fHMAX Maximum Data-Path Frequency FO=32 FO=635 1.1 1.1 99 93 1.2 1.2 91 84 1.4 1.4 79 73 2.0 2.0 48 44 ns ns MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. 1-155 A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Preliminary Information Output Module Timing `-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 4.4 5.0 5.8 8.2 ns tDHL Data to Pad Low 5.1 5.7 6.7 9.4 ns tENZH Enable Pad Z to High 4.6 5.2 6.1 8.5 ns tENZL Enable Pad Z to Low 5.0 5.7 6.7 9.3 ns tENHZ Enable Pad High to Z 9.2 10.4 12.2 17.1 ns tENLZ Enable Pad Low to Z 8.5 9.6 11.3 15.8 ns tGLH G to Pad High 7.2 8.1 9.6 13.4 ns tGHL G to Pad Low 7.2 8.1 9.6 13.4 ns tLSU I/O Latch Output Setup 0.7 0.8 1.0 1.4 ns tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 13.8 15.6 18.3 25.7 ns Array Latch Clock-Out (Pad-to-Pad) 32 I/O 19.4 22.0 25.9 36.3 ns dTLH Capacitive Loading, Low to High 0.1 0.1 0.1 0.1 ns/pF dTHL Capacitive Loading, High to Low 0.1 0.1 0.1 0.1 ns/pF 8.1 11.4 ns tACO 1 CMOS Output Module Timing tDLH Data to Pad High 6.1 6.9 tDHL Data to Pad Low 7.5 8.4 9.9 13.9 ns tENZH Enable Pad Z to High 7.9 8.9 10.5 14.7 ns tENZL Enable Pad Z to Low 8.5 9.6 11.3 15.9 ns tENHZ Enable Pad High to Z 13.7 15.5 18.2 25.5 ns tENLZ Enable Pad Low to Z 13.7 15.5 18.2 25.5 ns tGLH G to Pad High 13.7 15.5 18.2 25.5 ns tGHL G to Pad Low 14.7 16.7 19.6 27.4 ns tLSU I/O Latch Setup 0.4 0.5 0.6 0.8 ns tLH I/O Latch Hold 0.0 0.0 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 16.3 18.4 21.7 30.4 tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 22.9 25.9 30.5 42.7 ns dTLH Capacitive Loading, Low to High 0.1 0.1 0.1 0.1 ns/pF dTHL Capacitive Loading, High to Low 0.1 0.1 0.1 0.1 ns/pF ns Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. 2. SSO information can be found in the "Simultaneously Switching Output Limits for Actel FPGAs" application note. 1-156 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Package Pin Assignments 44-Pin PLCC 68-Pin PLCC 1 68 1 44 68-Pin PLCC 44-Pin PLCC A40MX02 Function A40MX04 Function A40MX02 Function A40MX04 Functions 3 VCC VCC 4 VCC VCC 10 GND GND 14 GND GND 14 VCC VCC 15 GND GND 16 VCC VCC 21 VCC VCC 21 GND GND 25 VCC VCC 25 VCC VCC 32 GND GND 32 GND GND 38 VCC VCC 33 CLK, I/O CLK, I/O 49 GND GND 34 MODE MODE 52 CLK, I/O CLK, I/O 35 VCC VCC 54 MODE MODE 36 SDI, I/O SDI, I/O 55 VCC VCC 37 DCLK, I/O DCLK, I/O 56 SDI, I/O SDI, I/O 38 PRA, I/O PRA, I/O 57 DCLK, I/O DCLK, I/O 39 PRB, I/O PRB, I/O 58 PRA, I/O PRA, I/O 43 GND GND 59 PRB, I/O PRB, I/O Signal Signal 1-157 Package Pin Assignments (continued) 84-Pin PLCC 1 84 A40MX04 84-Pin PLCC Signal A40MX04 Function 4 VCC 12 NC 18 GND 19 GND 25 VCC 26 VCC 33 VCC 40 GND 46 VCC 60 GND 61 GND 64 CLK, I/O 66 MODE 67 VCC 68 VCC 72 SDI, I/O 73 DCLK, I/O 74 PRA, I/O 75 PRB, I/O 82 GND Notes: 1. NC: Denotes No Connection. 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-158 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Package Pin Assignments (continued) 100-Pin PQFP 100-Pin PQFP 100 1 Pin A40MX02 Function A40MX04 Function Pin A40MX02 Function A40MX04 Function 1 2 3 4 5 6 13 19 27 28 29 30 31 32 33 36 37 43 44 48 49 50 51 52 NC NC NC NC NC PRB, I/O GND VCC NC NC NC NC NC NC NC GND GND VCC VCC NC NC NC NC NC NC NC NC NC NC PRB, I/O GND VCC NC NC NC NC I/O I/O I/O GND GND VCC VCC I/O I/O I/O NC NC 53 54 55 56 63 69 77 78 79 80 81 82 86 87 90 92 93 94 95 96 97 98 99 100 NC NC NC VCC GND VCC NC NC NC NC NC NC GND GND CLK, I/O MODE VCC VCC NC NC NC SDI, I/O DCLK, I/O PRA, I/O NC NC NC VCC GND VCC NC NC NC I/O I/O I/O GND GND CLK, I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O Notes: 1. NC: Denotes No Connection. 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-159 Package Pin Assignments (continued) 80-Pin VQFP 1 80 80-Pin VQFP A40MX02 Function A40MX04 Function Pin A40MX02 Function A40MX04 Function 2 NC I/O 47 GND GND 3 NC I/O 50 CLK, I/O CLK, I/O 4 NC I/O 52 MODE MODE 7 GND GND 53 VCC VCC 13 VCC VCC 54 NC I/O 17 NC I/O 55 NC I/O 18 NC I/O 56 NC I/O 19 NC I/O 57 SDI, I/O SDI, I/O 20 VCC VCC 58 DCLK, I/O DCLK, I/O 27 GND GND 59 PRA, I/O PRA, I/O 33 VCC VCC 60 NC NC 41 NC I/O 61 PRB, I/O PRB, I/O 42 NC I/O 68 GND GND 43 NC I/O 74 VCC VCC Pin Notes: 1. NC: Denotes No Connection. 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-160 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es Package Pin Assignments (continued) 84-Pin PLCC Package (Top View) 1 84 84-Pin PLCC 1-161 84-Pin PLCC Package Pin Number A42MX09 Function A42MX16 Function A42MX24 Function 2 CLKB,I/O CLKB,I/O CLKB,I/O 4 PRB,I/O PRB,I/O PRB,I/O 5 I/O I/O I/O (WD) 6 GND GND GND 8 I/O I/O I/O (WD) 9 I/O I/O I/O (WD) 10 DCLK,I/O DCLK,I/O DCLK,I/O 12 MODE MODE MODE 22 VCCI VCCI VCCI 23 VCCA VCCA VCCA 28 GND GND GND 34 I/O I/O TMS, I/O 35 I/O I/O TDI, I/O 36 I/O I/O I/O (WD) 38 I/O I/O I/O (WD) 39 I/O I/O I/O (WD) 43 VCCA VCCA VCCA 44 I/O I/O I/O (WD) 45 I/O I/O I/O (WD) 46 I/O I/O I/O (WD) 47 I/O I/O I/O (WD) 49 GND GND GND 50 I/O I/O I/O (WD) 51 I/O I/O I/O (WD) 52 I/O I/O TDO (WD) 62 I/O I/O TCK, I/O 63 GND GND GND 64 VCCA VCCA VCCA 65 VCCI VCCI VCCI 70 GND GND GND 76 SDI,I/O SDI,I/O SDI,I/O 78 I/O I/O I/O (WD) 79 I/O I/O I/O (WD) 80 I/O I/O I/O (WD) 81 PRA,I/O PRA,I/O PRA,I/O 83 CLKA,I/O CLKA,I/O CLKA,I/O 84 VCCA VCCA VCCA Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-decode I/O (WD) can also be general-purpose user I/O. 3. NC: Denotes No Connection. 4. All unlisted pin numbers are user I/Os. 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-162 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 1-163 Package Pin Assignments (continued) 100-pin PQFP Package (Top View) 100-Pin PQFP 100 1 1-164 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 100-pin PQFP Package Pin Number A42MX09 PQ100 Function A42MX16 PQ100 Function A42MX09 PQ100 Function A42MX16 PQ100 Function Pin Number 2 DCLK, I/O DCLK, I/O 64 GND GND 4 MODE MODE 65 VCCA VCCA 7 I/O I/O 66 VCCI VCCI 9 GND GND 67 VCCA VCCA 14 I/O I/O 70 I/O I/O 15 I/O I/O 72 GND GND 16 VCCA VCCA 77 I/O I/O 17 VCC VCC 79 SDI, I/O SDI, I/O 20 I/O I/O 82 I/O I/O 22 GND GND 84 GND GND 32 I/O I/O 85 I/O I/O 34 GND GND 87 PRA, I/O PRA, I/O 38 I/O I/O 88 I/O I/O 40 VCCA VCCA 89 CLKA, I/O CLKA, I/O 44 I/O I/O 90 VCCA VCCA 46 GND GND 92 CLKB, I/O CLKB, I/O 55 I/O I/O 94 PRB, I/O PRB, I/O 57 GND GND 96 GND GND 62 I/O I/O 100 I/O I/O 63 I/O I/O Notes: 1. NC: Denotes No Connection. 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-165 Package Pin Assignments (continued) 160-pin PQFP Package (Top View) 160 1 160-Pin PQFP Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-decode I/O (WD) can also be general-purpose user I/O. 3. NC: Denotes No Connection. 4. All unlisted pin numbers are user I/Os. 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-166 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 160-Pin PQFP Package Pin Number A42MX16 Function A42MX24 Function Pin Number A42MX16 Function A42MX24 Function 2 DCLK,I/O DCLK,I/O 80 GND GND 4 I/O I/O (WD) 82 I/O TDO, I/O 5 I/O I/O (WD) 83 I/O I/O (WD) 6 VCCI VCCI 84 I/O I/O (WD) 7 I/O I/O 86 VCCI VCCI 11 GND GND 87 I/O I/O 13 I/O I/O (WD) 88 I/O I/O (WD) 14 I/O I/O (WD) 89 GND GND 16 PRB,I/O PRB,I/O 92 I/O I/O 18 CLKB,I/O CLKB,I/O 93 I/O I/O 20 VCCA VCCA 96 I/O I/O (WD) 21 CLKA,I/O CLKA,I/O 97 I/O I/O 23 PRA,I/O PRA,I/O 98 VCCA VCCA 24 I/O I/O (WD) 99 GND GND 25 I/O I/O (WD) 106 I/O I/O (WD) 26 I/O I/O 107 I/O I/O (WD) 29 I/O I/O (WD) 109 GND GND 30 GND GND 111 I/O I/O (WD) 31 I/O I/O (WD) 112 I/O I/O (WD) 34 I/O I/O 114 VCCI VCCI 35 VCCI VCCI 115 I/O I/O (WD) 36 I/O I/O (WD) 116 I/O I/O (WD) 37 I/O I/O (WD) 118 I/O TDI, I/O 38 SDI,I/O SDI,I/O 119 I/O TMS, I/O 40 GND GND 120 GND GND 44 GND GND 125 GND GND 49 GND GND 130 GND GND 54 VCCA VCCA 135 VCCA VCCA 57 VCCA VCCA 138 VCCA VCCA 58 VCCI VCCI 139 VCCI VCCI 59 GND GND 140 GND GND 60 VCCA VCCA 145 GND GND 61 GND GND 150 VCCA VCCA 62 I/O TCK, I/O 155 GND GND 64 GND GND 159 MODE MODE 69 GND GND 160 GND GND 1-167 Package Pin Assignments (continued) 208-Pin PQFP Package, 208-pin RQFP Package (Top View) 208 1 208-Pin PQFP 208-Pin RQFP Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-decode I/O (WD) can also be general-purpose user I/O. 3. NC: Denotes No Connection. 4. All unlisted pin numbers are user I/Os. 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 6. RQFP has an exposed circular metal heat sink on the top surface. 1-168 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 208-Pin PQFP Package, 208-pin RQFP Package A42MX16 Pin Number Function 1 2 3 5 6 7 9 10 11 13 15 16 17 19 20 22 24 26 27 28 29 30 32 33 38 40 41 42 43 45 47 48 50 51 52 53 54 55 57 58 59 60 61 62 65 66 67 68 70 71 74 77 78 79 80 81 83 85 86 89 90 91 93 94 95 96 97 98 100 101 103 GND NC MODE I/O I/O I/O NC NC NC I/O I/O NC VCCA I/O I/O GND I/O I/O GND VCCI VCCA I/O VCCA I/O I/O I/O NC NC NC I/O I/O I/O NC NC GND GND I/O I/O I/O I/O I/O VCCI NC NC I/O I/O NC NC I/O I/O I/O I/O GND VCCA NC I/O I/O I/O I/O NC NC I/O I/O I/O NC NC NC VCCI I/O I/O I/O A42MX24 Function A42MX36 PQ208 Function 42MX36 RQ208 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O GND I/O I/O GND VCCI VCCA I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O GND VCCA VCCI I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O (WD) I/O (WD) TDO, I/O GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O GND I/O I/O GND VCCI VCCA I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O QCLKA, I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O GND VCCA VCCI I/O I/O I/O (WD) I/O (WD) I/O I/O QCLKB, I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O (WD) I/O (WD) TDO, I/O I/O DCLK, I/O I/O I/O (WD) I/O (WD) VCC I/O I/O I/O QCLKC, I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) PRB, I/O CLKB, I/O GND VCCA I/O CLKA, I/O PRA, I/O I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) I/O I/O VCCI I/O (WD) I/O (WD) SDI, I/O I/O GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCA VCCI VCCA GND TCK, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA A42MX16 Pin Number Function 104 105 106 107 108 110 112 113 114 115 117 121 122 126 128 129 130 131 132 133 136 137 138 141 142 144 146 147 148 149 150 151 152 154 155 156 157 159 161 162 164 165 166 168 169 171 176 177 178 180 181 182 183 184 186 187 188 190 191 193 194 195 196 197 201 202 203 204 206 207 208 I/O GND NC I/O I/O I/O NC NC NC NC I/O I/O I/O GND I/O GND VCCA GND VCCI VCCA VCCA I/O I/O NC I/O I/O NC NC NC NC GND I/O I/O I/O I/O I/O GND SDI,I/O I/O I/O VCCI NC NC I/O I/O NC I/O I/O PRA,I/O CLKA,I/O NC NC VCCA GND CLKB,I/O I/O PRB,I/O I/O I/O NC NC NC I/O NC NC VCCI I/O I/O I/O DCLK,I/O I/O A42MX24 Function A42MX36 PQ208 Function 42MX36 RQ208 Function I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND TCK, I/O GND VCCA GND VCCI VCCA VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND SDI,I/O I/O (WD) I/O (WD) VCCI I/O I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) PRA,I/O CLKA,I/O I/O VCCI VCCA GND CLKB,I/O I/O PRB,I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O (WD) I/O (WD) I/O DCLK,I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND TCK, I/O GND VCCA GND VCCI VCCA VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND SDI,I/O I/O (WD) I/O (WD) VCCI I/O I/O I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) PRA,I/O CLKA,I/O I/O VCCI VCCA GND CLKB,I/O I/O PRB,I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) QCLKC, I/O I/O I/O VCCI I/O (WD) I/O (WD) I/O DCLK,I/O I/O GND I/O TDO, I/O I/O (WD) I/O (WD) VCC I/O I/O I/O (WD) I/O (WD) QCLKB, I/O I/O (WD) I/O (WD) I/O I/O VCCA GND I/O I/O I/O I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) QCLKA, I/O I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) TDI, I/O TMS, I/O GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O VCCA VCCI I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O MODE VCCA GND 1-169 Package Pin Assignments (continued) * * * 240-Pin RQFP Package (Top View) Exposed Heat Sink 240 1 240-Pin RQFP * * * * * * * * * Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-decode I/O (WD) can also be general-purpose user I/O. 3. NC: Denotes No Connection. 4. All unlisted pin numbers are user I/Os. 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 6. RQFP has an exposed circular metal heat sink on the top surface. 1-170 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 240-Pin RQFP Package Pin Number A42MX36 Function Pin Number A42MX36 Function 2 DCLK, I/O 119 GND 6 I/O (WD) 120 GND 7 I/O (WD) 121 GND 8 VCCI 123 TDO, I/O 15 QCLKC, I/O 125 I/O (WD) 17 I/O (WD) 126 I/O (WD) 18 I/O (WD) 128 VCCI 21 I/O (WD) 132 I/O (WD) 22 I/O (WD) 133 I/O (WD) 24 PRB, I/O 135 QCLKB, I/O 26 CLKB, I/O 142 I/O (WD) 28 GND 143 I/O (WD) 29 VCCA 150 VCCI 30 VCCI 151 VCCA 32 CLKA, I/O 152 GND 34 PRA, I/O 159 I/O (WD) 37 I/O (WD) 160 I/O (WD) 38 I/O (WD) 163 I/O (WD) 45 QCLKD, I/O 164 I/O (WD) 47 I/O (WD) 166 QCLKA, I/O 48 I/O (WD) 172 VCCI 52 VCCI 174 I/O (WD) 54 I/O (WD) 175 I/O (WD) 55 I/O (WD) 178 TDI, I/O 57 SDI, I/O 179 TMS, I/O 59 VCCA 180 GND 60 GND 181 VCC 61 GND 182 GND 71 VCCI 192 VCCI 85 VCCA 206 VCCA 88 VCCA 209 VCCA 89 VCCI 210 VCCI 90 VCCA 219 VCCA 91 GND 227 VCCI 92 TCK, I/O 237 GND 94 GND 238 MODE 108 VCCI 239 VCCA 118 VCCA 240 GND 1-171 Package Pin Assignments (continued) 176-Pin TQFP Package (Top View) 176 1 176-Pin TQFP Notes: 1. I/O (WD): Denotes I/O pin with an associated wide-decode module. 2. Wide-decode I/O (WD) can also be general-purpose user I/O. 3. NC: Denotes No Connection. 4. All unlisted pin numbers are user I/Os. 5. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-172 In te g ra to r S e ri e s F P G A s - 4 0 MX a n d 4 2 M X Fami l i es 176-pin TQFP Package Pin Number 1 2 8 10 11 13 18 19 20 22 23 24 25 26 27 28 29 33 37 38 45 46 47 48 49 50 52 54 55 56 57 59 60 61 64 66 67 68 69 70 73 74 75 77 78 80 81 82 84 85 86 87 89 96 A42MX09 Function A42MX16 Function A42MX24 Function GND MODE NC NC NC NC GND NC NC NC GND NC VCCA NC NC VCCA NC NC NC NC GND I/O I/O I/O I/O I/O NC NC NC I/O NC I/O I/O NC NC NC GND VCCA I/O I/O I/O NC I/O NC NC NC I/O NC I/O I/O NC I/O GND NC GND MODE NC I/O I/O VCCA GND I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O NC I/O NC GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O NC I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O NC I/O I/O I/O VCCI I/O I/O I/O I/O GND I/O GND MODE I/O I/O I/O VCCA GND I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) VCCI I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O I/O GND VCCA I/O (WD) I/O (WD) I/O I/O I/O I/O (WD) I/O (WD) I/O I/O VCCI I/O (WD) I/O (WD) I/O TDO, I/O GND I/O Pin Number A42MX09 Function A42MX16 Function A42MX24 Function 97 101 103 106 107 108 109 110 111 112 113 114 115 116 117 121 124 125 126 133 135 136 137 138 139 140 141 143 144 145 146 147 149 150 151 152 154 155 156 158 160 161 162 163 165 166 168 169 170 171 172 173 175 NC NC NC GND NC NC GND VCC GND VCCI VCCA NC NC NC I/O NC NC NC NC GND SDI,I/O NC I/O I/O I/O NC I/O NC NC NC I/O NC I/O I/O NC PRA,I/O CLKA,I/O VCCA GND CLKB,I/O PRB,I/O NC I/O I/O NC NC NC I/O NC I/O I/O NC DCLK,I/O I/O NC I/O GND I/O I/O GND VCC GND VCCI VCCA I/O I/O VCC I/O NC I/O I/O NC GND SDI,I/O I/O I/O I/O I/O VCCI I/O I/O I/O NC I/O I/O I/O I/O I/O PRA,I/O CLKA,I/O VCCA GND CLKB,I/O PRB,I/O I/O I/O I/O NC I/O I/O I/O VCCI I/O I/O I/O DCLK,I/O I/O I/O I/O GND I/O TCK, I/O GND VCC GND VCCI VCCA I/O I/O VCC I/O I/O I/O I/O I/O GND SDI,I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O (WD) I/O (WD) PRA,I/O CLKA,I/O VCCA GND CLKB,I/O PRB,I/O I/O (WD) I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O VCCI I/O (WD) I/O (WD) I/O DCLK,I/O 1-173 1-174