LM34919C-Q1 Evaluation Board User's Guide User's Guide Literature Number: SNVU196 SEPTEMBER 2013 Contents 1 2 3 4 5 6 7 8 9 10 INTRODUCTION .................................................................................................................. 5 THEORY OF OPERATION ..................................................................................................... 5 BOARD LAYOUT AND PROBING ........................................................................................... 6 BOARD CONNECTION/START-UP ......................................................................................... 6 OUTPUT RIPPLE CONTROL ................................................................................................. 6 MONITOR THE INDUCTOR CURRENT .................................................................................... 8 MINIMUM LOAD CURRENT ................................................................................................... 8 CIRCUIT PERFORMANCE ..................................................................................................... 9 TYPICAL WAVEFORMS ...................................................................................................... 11 PC BOARD LAYOUT .......................................................................................................... 13 2 Table of Contents SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated www.ti.com List of Figures 1 Evaluation Board - Top Side .............................................................................................. 5 2 Lowest Cost Configuration ................................................................................................. 6 3 Intermediate Ripple Configuration ........................................................................................ 7 4 Minimum Output Ripple Configuration ................................................................................... 8 5 Complete Evaluation Board Schematic .................................................................................. 8 6 Efficiency vs Load Current ................................................................................................. 9 7 Efficiency vs Input Voltage ................................................................................................. 9 8 Switching Frequency vs. Input Voltage ................................................................................. 10 9 Load Derating Curve ...................................................................................................... 10 10 Continuous Conduction Mode ........................................................................................... 11 11 Discontinuous Conduction Mode ........................................................................................ 11 12 Enable, Output Voltage, and PGD at Startup .......................................................................... 12 13 Board Silkscreen........................................................................................................... 13 14 Board Top Layer ........................................................................................................... 13 15 Board Bottom Layer (Viewed from Top) ................................................................................ 14 List of Tables 1 Bill of Materials .............................................................................................................. SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback List of Figures Copyright (c) 2013, Texas Instruments Incorporated 8 3 User's Guide SNVU196 - SEPTEMBER 2013 LM34919C-Q1 Evaluation Board The LM34919CQSDEVM evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 3.3 V output over an input range of 4.5 V to 24 V. The circuit delivers load current to 600 mA, with current limit set at a nominal 640 mA (valley current limit). The board is populated with all components except R7, C6, and C7. These components provide options for managing the output ripple as described later in this document. All trademarks are the property of their respective owners. 4 LM34919C-Q1 Evaluation Board SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated INTRODUCTION www.ti.com 1 INTRODUCTION The LM34919CQSDEVM evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 3.3 V output over an input range of 4.5 V to 24 V. The circuit delivers load currents to 600 mA, with valley current limit set at 640 mA. The board is populated with all components except R7, C6 and C7. These components provide options for managing the output ripple as described later in this document. The board's specification are: * Input Voltage: 4.5 V to 24 V * Output Voltage: 3.3 V * Maximum load current: 600 mA * Minimum load current: 0 A * Current Limit: 768 mA to 812 mA * Measured Efficiency: 87% (VIN = 6 V, IOUT = 300 mA) * Nominal Switching Frequency: 1.5 MHz * Size: 1.4 inches x 2.3 inches Figure 1. Evaluation Board - Top Side 2 THEORY OF OPERATION Refer to the evaluation board topside view in Figure 1. At nominal input voltage, VIN = 12 V, the switching frequency can be determined by R2 (RON resistor) and output voltage VO, according to Equation 1: VOUT FSW Hz 35.5 u 1012 u R2 (1) In LM34919C, like other constant on-time regulators, the on-time varies inversely with VIN to maintain a nearly constant switching frequency. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at FB to switch the regulation comparator. The average load current limit threshold is 768 mA at Vin = 4.5 V, and 812 mA at Vin = 24 V. The variation is due to the change in ripple current amplitude as Vin varies. Refer to the LM34919C data sheet for a more detailed block diagram, and a complete description of the various functional blocks. SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback LM34919C-Q1 Evaluation Board Copyright (c) 2013, Texas Instruments Incorporated 5 BOARD LAYOUT AND PROBING 3 www.ti.com BOARD LAYOUT AND PROBING The picture in Figure 1 also shows the placement of the circuit components. The following should be kept in mind when the board is powered: 1) The LM34919C, and diode D1 may be hot to touch when operating at high input voltage and high load current. 2) Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. 3) At maximum load current (0.6 A), the wire size and length used to connect the load becomes important. Ensure there is not a significant drop in the wires between this evaluation board and the load. 4 BOARD CONNECTION/START-UP The input connections are made to the J1 connector. The load is connected to the J3 (OUT) and J4 (GND) connectors. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 4.5 V and load current be set at 0 A, at which time the output voltage should be 3.3 V. If the output voltage is correct, then increase the input voltage as desired and proceed loading the evaluation board as shown in Figure 8. DO NOT EXCEED 40 V AT VIN. 5 OUTPUT RIPPLE CONTROL The LM34919C requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW pin, for proper operation. The required ripple can be supplied from ripple at VOUT, through the feedback resistors as described in Options A and B below, or the ripple can be generated separately (using R7, C6, and C7) in order to keep the ripple at VOUT at a minimum (Option C). Option A) Lowest Cost Configuration: This evaluation board is supplied with R6 installed in series with the output capacitance (C8, C9). R6 is chosen to generate 25 mVp-p at VOUT. Using 0.47 for R6, the ripple at VOUT ranges from 38 mVp-p to 158 mVp-p over the input voltage range. If the application can accept this ripple level, this is the most economical solution. The circuit is shown in Figure 2. 4.5V to 24V VIN IN C3 C4 1 F 1 F R3 100k C4 0.1 F C1 R2 61.9k 0.1F GND VCC LM34919C On Timer Minimum Off Timer VIN BST C5 0.022 F RON EN 2.52V SS C10 0.022 F FB 0.92VREF R1 10k R4 0 3.3V VOUT D1 Regulation Comparator VOUT L1 8.2 H SW Logic ISEN Current Limit Detect SGND PGD 1.2VREF R5 787 R6 0.47 C8 R8 2.49k C9 10 F 10 F GND RTN Figure 2. Lowest Cost Configuration Option B) Intermediate Ripple Configuration: This configuration generates less ripple at VOUT than option A above by the addition of one capacitor (Cff) across R5, as shown in Figure 3. 6 LM34919C-Q1 Evaluation Board SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated OUTPUT RIPPLE CONTROL www.ti.com 4.5V to 24V VIN IN C3 C4 1 F 1 F R3 100k C2 0.1 F C1 R2 61.9k 0.1F GND VCC LM34919C On Timer Minimum Off Timer VIN BST C5 0.022 F RON EN 2.52V SS C10 0.022 F FB 0.92VREF R1 10k R1 0 3.3V VOUT D1 Regulation Comparator VOUT L1 8.2 H SW Logic ISEN Current Limit Detect R5 787 Cff 2200 pF SGND R6 0.4 C8 R8 2.49k PGD 1.2VREF C9 10 F 10 F GND RTN Figure 3. Intermediate Ripple Configuration Since the output ripple is passed by Cff to the FB pin with little or no attenuation, R6 can be reduced so the minimum ripple at VOUT is 25 mVp-p. The minimum value for Cff is calculated from: Cff t tON (max) x 3 (R5//R8) (2) where tON(max) is the maximum on-time (at minimum VIN), and R5//R8 is the parallel equivalent of the feedback resistors. See Figure 3. Option C) Minimum Ripple Configuration: To obtain minimum ripple at VOUT, R6 is set to 0, and R7, C6, and C7 are added to generate the required ripple for the FB pin. In this configuration, the output ripple is determined primarily by the ESR of the output capacitance and the inductor's ripple current. The ripple voltage required by the FB pin is generated by R7, C6, and C7 since the SW pin switches from -1 V to VIN, and the right end of C6 is a virtual ground. The values for R7 and C6 are chosen to generate a 50-100 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through C7. The following procedure is used to calculate values for R7, C6 and C7: 1) Calculate the voltage VA: VA = VOUT - (VSW x (1 - (VOUT/VIN))) (3) where VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1 V), and VIN is the minimum input voltage. For this circuit, VA calculates to 3.03 V. This is the approximate DC voltage at the R7/C6 junction, and is used in the next equation. 2) Calculate the R7 x C6 product: R7 x C6 = (VIN VA) x tON (4) 'V where tON is the maximum on-time, VIN is the minimum input voltage, and V is the desired ripple amplitude at the R7/C6 junction, 50 mVp-p for this example. R7 and C6 are then chosen from standard value components to satisfy the above product. Typically C6 is 3000 to 5000 pF, and R7 chosen close to 10 k. C7 is chosen large compared to C6, typically 0.1 F. See Figure 4. SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback LM34919C-Q1 Evaluation Board Copyright (c) 2013, Texas Instruments Incorporated 7 MONITOR THE INDUCTOR CURRENT www.ti.com 4.5V to 24V VIN IN C3 C4 1 F 1 F R3 100k C2 0.1 F C1 R2 61.9k 0.1F GND VCC LM34919C Minimum Off Timer On Timer VIN BST C5 0.022 F RON EN 2.52V L1 8.2 H SW Logic SS R7 C10 0.022 F FB R4 0 3.3V VOUT C6 D1 Regulation Comparator VOUT ISEN 0.92VREF Current Limit Detect R1 10k 7.87 k 3300 pF R5 787 C10 0.1 F R6 0 C8 SGND R8 2.49k C9 10 F 10 F PGD 1.2VREF GND RTN Figure 4. Minimum Output Ripple Configuration 6 MONITOR THE INDUCTOR CURRENT The inductor's current can be monitored or viewed on a scope with a current probe. Remove R4, and install an appropriate current loop across the two large pads where R4 was located. In this way the inductor's ripple current and peak current can be accurately determined. 7 MINIMUM LOAD CURRENT The LM34919C requires a minimum load current of 1 mA to ensure the boost capacitor (C5) is recharged sufficiently during each off-time. In this evaluation board, the minimum load current is provided by the feedback resistors allowing the board's minimum load current at VOUT to be specified at zero. 4.5V to 24V VIN IN C3 C4 1 F 1 F R3 100k C2 0.1 F C1 R2 61.9k 0.1F GND VCC LM34919C Minimum Off Timer On Timer VIN RON TP2 BST C5 0.022 F EN TP4 2.52V SS L1 8.2 H SW Logic R7 C10 0.022 F FB R4 0 3.3V VOUT C6 D1 Regulation Comparator VOUT 0.92VREF R1 10k ISEN Current Limit Detect SGND R5 787 C7 R6 0.47 C8 R8 2.49k C9 10 F 10 F PGD 1.2VREF GND TP3 TP1 RTN Figure 5. Complete Evaluation Board Schematic Table 1. Bill of Materials 8 ITEM DESCRIPTION MFG. PART NUMBER PACKAGE VALUE C1,C2 Ceramic Capacitor TDK C1005X7R1H104K050BB 0402 0.1 F,50 V C3,C4 Ceramic Capacitor Murata GRM21BR71H105KA12L 0805 1 F,50 V C5,C10 Ceramic Capacitor Murata GRM155R71H223KA12D 0402 0.022 F,50 V C6 Ceramic Capacitor Unpopulated 0402 C7 Ceramic Capacitor Unpopulated 0402 LM34919C-Q1 Evaluation Board SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated CIRCUIT PERFORMANCE www.ti.com Table 1. Bill of Materials (continued) 8 ITEM DESCRIPTION MFG. PART NUMBER PACKAGE VALUE C8,C9 Ceramic Capacitor Murata GRM21BR71A106KE51L 0805 10 F,10 V D1 Schottky Diode Zetex ZLLS2000TA SOT-23-6 40 V, 2.2 A L1 Power Inductor Wurth Elektronik 744053008 5.8mm x 5.8mm 8.2 H, 2.1 A R1 Resistor Vishay-Dale CRCW040210K0FKED 0402 10 k R2 Resistor Vishay-Dale CRCW040261K9FKED 0402 61.9 k R3 Resistor Vishay-Dale CRCW0402100KFKED 0402 100 k R4 Resistor Vishay-Dale CRCW08050000Z0EA 0805 0 Jumper R5 Resistor Vishay-Dale CRCW0402787RFKED 0402 787 R6 Resistor Vishay-Dale RCWE0805R470FKEA 0805 0.47 R7 Resistor Unpopulated 0402 R8 Resistor Vishay-Dale CRCW04022K49FKED 0402 U1 Switching Regulator Texas Instruments LM34919CQSD 12 Pin WSON 2.49 k CIRCUIT PERFORMANCE 95 90 85 Efficiency (%) 80 75 70 65 Vin = 4.5V Vin = 6V Vin = 9V Vin = 12V Vin = 18V Vin = 24V 60 55 Vout = 3.3V Fsw = 1.5 MHz 50 45 0.2 0.3 0.4 0.5 0.6 Load Current (A) C001 Figure 6. Efficiency vs Load Current 95 90 85 Efficiency (%) 80 75 70 65 Load = 200mA Load = 300mA Load = 400mA Load = 500mA Load = 600mA 60 55 50 45 0 5 Vout = 3.3V Fsw = 1.5 MHz 10 15 20 Input Voltage (V) 25 C002 Figure 7. Efficiency vs Input Voltage SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback LM34919C-Q1 Evaluation Board Copyright (c) 2013, Texas Instruments Incorporated 9 CIRCUIT PERFORMANCE www.ti.com Switching Frequency (MHz) 3.0 2.5 2.0 1.5 1.0 Vout = 3.3V 5RQ N 0.5 4 8 12 16 20 Input Voltage (V) 24 C003 Figure 8. Switching Frequency vs. Input Voltage 0.6 LOAD CURRENT (A) 0.5 0.4 OUTPUT VOLTAGE REGULATION 0.3 0.2 0.1 0 4.5 4.6 4.7 4.8 4.9 5 24 INPUT VOLTAGE (V) Figure 9. Load Derating Curve 10 LM34919C-Q1 Evaluation Board SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated TYPICAL WAVEFORMS www.ti.com 9 TYPICAL WAVEFORMS Trace 2 = VOUT ripple (ac coupled) Trace 4 = inductor Current Trace 1 = SW Pin Vin = 12 V, IOUT = 400 mA Figure 10. Continuous Conduction Mode Trace 2 = VOUT ripple (ac coupled) Trace 4 = inductor Current Trace 1 = SW Pin Vin = 12 V, IOUT = 20 mA Figure 11. Discontinuous Conduction Mode SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback LM34919C-Q1 Evaluation Board Copyright (c) 2013, Texas Instruments Incorporated 11 TYPICAL WAVEFORMS www.ti.com Trace 3 = VOUT Trace 2 = EN Trace 4 = Power Good Trace 1 = VIN = 12 V IOUT = 300 mA Figure 12. Enable, Output Voltage, and PGD at Startup 12 LM34919C-Q1 Evaluation Board SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated PC BOARD LAYOUT www.ti.com 10 PC BOARD LAYOUT Figure 13. Board Silkscreen Figure 14. Board Top Layer SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback LM34919C-Q1 Evaluation Board Copyright (c) 2013, Texas Instruments Incorporated 13 PC BOARD LAYOUT www.ti.com Figure 15. Board Bottom Layer (Viewed from Top) 14 LM34919C-Q1 Evaluation Board SNVU196 - SEPTEMBER 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Should this evaluation board/kit not meet the specifications indicated in the User's Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. 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