MC100LVEL12DG - ON Semiconductor - searchdatasheet.com

August, 2008 − Rev. 4

1Publication Order Number:

MC100LVEL12/D

MC100LVEL12

3.3V ECL Low Impedance

Driver

Description

The MC100LVEL12 is a low impedance drive buffer. With two

pairs of OR/NOR outputs the device is ideally suited for high drive

applications such as memory addressing. The device is functionally

equivalent to the EL12 device and operates from a 3.3 V power supply.

With propagation delays equivalent to the EL12, the LVEL12 is

ideally suited for those applications which require the ultimate in

AC performance in a low voltage environment.

Features

•445 ps Propagation Delay

•Dual Outputs for 25  Drive Applications

•ESD Protection: >4 kV Human Body Model,

> 200 V Machine Model

•The 100 Series Contains Temperature Compensation

•PECL Mode Operating Range:VCC = 3.0 V to 3.8 V

with VEE = 0 V

•NECL Mode Operating Range: VCC= 0 V

with VEE = −3.0 V to −3.8 V

•Internal Input Pulldown Resistors

•Q Output will Default LOW with All Inputs Open or at VEE

•Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

•Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

•Flammability Rating: UL−94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

•Transistor Count = 83 devices

•Pb−Free Packages are Available

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAMS*

KV12

ALYWG

SOIC−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

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KVL12

ALYW

DFN8

MN SUFFIX

CASE 506AA

4A M G

(Note: Microdot may be in either location)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M= Date Code

G= Pb−Free Package

MC100LVEL12

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Figure 1. Logic Diagram and Pinout Assignment

VEE

VCC

D0, D1 ECL Data Inputs

Qa, Qa; Qb, Qb ECL Data Outputs

VCC Positive Supply

VEE Negative Supply

Table 1. PIN DESCRIPTION

PIN FUNCTION

EP (DFN8 only) Thermal exposed pad

must be connected to a sufficient

thermal conduit. Electrically connect

to the most negative supply (GND)

or leave unconnected, floating open.

Table 2. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Units

VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V

VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI  VCC

VI  VEE

6 to 0

−6 to 0

Iout Output Current Continuous

Surge

100

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

JA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 SOIC

190

130

°C/W

JC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 ± 5% °C/W

JA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 TSSOP

185

140

°C/W

JC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W

JA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

JC Thermal Resistance (Junction−to−Case) (Note 1) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

MC100LVEL12

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Table 3. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 17 24 17 24 18 25 mA

VOH Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV

VOL Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV

VIH Input HIGH Voltage 2135 2420 2135 2420 2135 2420 mV

VIL Input LOW Voltage 1490 1825 1490 1825 1490 1825 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.

3. Outputs are terminated through a 50  resistor to VCC − 2.0 V.

Table 4. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 4)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 17 24 17 24 18 25 mA

VOH Output HIGH Voltage (Note 5) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV

VOL Output LOW Voltage (Note 5) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV

VIH Input HIGH Voltage −1165 −880 −1165 −880 −1165 −880 mV

VIL Input LOW Voltage −1810 −1475 −1810 −1475 −1810 −1475 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

4. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.

5. Outputs are terminated through a 50  resistor to VCC − 2.0 V.

Table 5. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 6)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

fmax Maximum Toggle Frequency TBD TBD TBD GHz

tPLH

tPHL

Propagation Delay to

Output 310 580 310 445 580 320 590 ps

tJITTER Cycle−to−Cycle Jitter TBD TBD TBD ps

Output Rise/Fall Times Q

(20% − 80%) 230 400 550 230 400 550 230 400 550 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

6. VEE can vary ±0.3 V.

MC100LVEL12

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Figure 2. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 

50 50 

VTT

VTT = VCC − 3.0 V

ORDERING INFORMATION

Device Package Shipping†

MC100LVEL12D SOIC−898 Units / Rail

MC100LVEL12DG SOIC−8

(Pb−Free)

98 Units / Rail

MC100LVEL12DR2 SOIC−82500 / Tape & Reel

MC100LVEL12DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

MC100LVEL12DT TSSOP−8100 Units / Rail

MC100LVEL12DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC100LVEL12DTR2 TSSOP−82500 / Tape & Reel

MC100LVEL12DTR2G TSSOP−8

(Pb−Free)

2500 / Tape & Reel

MC100LVEL12MNR4 DFN8 1000 / Tape & Reel

MC100LVEL12MNR4G DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC100LVEL12

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC100LVEL12

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PACKAGE DIMENSIONS

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

MC100LVEL12

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PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇÇ

C0.10

PIN ONE

2 X

REFERENCE

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

8 X

SEATING

PLANE

e/2 e

8 X

NOTE 3

8 X 0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

K0.20 −−−

L0.25 0.35

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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Phone: 81−3−5773−3850

MC100LVEL12/D

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