LTC3412
1
3412fb
The LTC
®
3412 is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.625V to 5.5V and provides an
adjustable regulated output voltage from 0.8V to 5V while
delivering up to 2.5A of output current. The internal
synchronous power switch with 85mΩ on-resistance
increases efficiency and eliminates the need for an exter-
nal Schottky diode. Switching frequency is set by an
external resistor or can be sychronized to an external
clock. 100% duty cycle provides low dropout operation
extending battery life in portable systems. OPTI-LOOP
®
compensation allows the transient response to be opti-
mized over a wide range of loads and output capacitors.
The LTC3412 can be configured for either Burst Mode
®
operation or forced continuous operation. Forced con-
tinuous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reduc-
ing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
requirements of the application. To further maximize
battery life, the P-channel MOSFET is turned on continu-
ously in dropout (100% duty cycle).
■
Portable Instruments
■
Battery-Powered Equipment
■
Notebook Computers
■
Distributed Power Systems
■
Cellular Telephones
■
Digital Cameras
■
High Efficiency: Up to 95%
■
2.5A Output Current
■
Low Quiescent Current: 62μA
■
Low R
DS(ON)
Internal Switches: 85mΩ
■
Programmable Frequency: 300kHz to 4MHz
■
No Schottky Diode Required
■
±2% Output Voltage Accuracy
■
0.8V Reference Allows Low Output Voltage
■
Selectable Forced Continuous/Burst Mode Operation
with Adjustable Burst Clamp
■
Synchronizable Switching Frequency
■
Low Dropout Operation: 100% Duty Cycle
■
Power Good Output Voltage Monitor
■
Overtemperature Protection
■
Available in 16-Lead Thermally Enhanced TSSOP
and QFN Packages
2.5A, 4MHz, Monolithic
Synchronous Step-Down Regulator
Figure 1. 2.5V, 2.5A Step-Down Regulator
Efficiency vs Load Current
SVIN PVIN
PGOOD
SW
LTC3412
PGND
SGND
RUN/SS
309k
VIN
2.7V TO 5.5V
1000pF
RT
ITH
VFB
SYNC/MODE
1μH
4.7M
470pF
75k
100pF
100μF
VOUT
2.5V
2.5A
15k
110k 392k
22μF
3412 F01
LOAD CURRENT (A)
0.001
EFFICIENCY (%)
100
80
60
40
20
0
10
3412 G01
VIN = 3.3V
VOUT = 2.5V
Burst Mode OPERATION
FORCED CONTINUOUS
0.1 10.01
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC3412
2
3412fb
Input Supply Voltage ...................................–0.3V to 6V
I
TH
, RUN, V
FB
Voltages ............................... – 0.3V to V
IN
SYNC/MODE Voltages ................................ – 0.3V to V
IN
SW Voltage ................................... – 0.3V to (V
IN
+ 0.3V)
Peak SW Sink and Source Current ......................... 6.5A
ORDER PART NUMBER
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC3412EFE
LTC3412IFE
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
1
2
3
4
5
6
7
8
TOP VIEW
FE PACKAGE
16-LEAD PLASTIC TSSOP
16
15
14
13
12
11
10
9
SV
IN
PGOOD
I
TH
V
FB
R
T
SYNC/MODE
RUN/SS
SGND
PV
IN
SW
SW
PGND
PGND
SW
SW
PV
IN
17
FE PART MARKING
3412EFE
3412IFE
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
T
JMAX
= 125°C, θ
JA
= 37.6°C/W, θ
JC
= 10°C/W
Operating Temperature
Range (Note 2) ....................................... – 40°C to 85°C
Junction Temperature (Note 5)............................. 125°C
Lead Temperature (Soldering, 10 sec)
TSSOP .............................................................. 300°C
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
ORDER PART NUMBER
LTC3412EUF
UF PART MARKING
3412
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
T
JMAX
= 125°C, θ
JA
= 34°C/W, θ
JC
= 1°C/W
16 15 14 13
5678
TOP VIEW
17
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
9
10
11
12
4
3
2
1RUN/SS
SGND
PVIN
SW
PGOOD
SVIN
PVIN
SW
SYNC/MODE
RT
VFB
ITH
SW
PGND
PGND
SW
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SV
IN
Signal Input Voltage Range 2.625 5.5 V
V
FB
Regulated Feedback Voltage (Note 3) ●0.784 0.800 0.816 V
I
FB
Voltage Feedback Leakage Current 0.1 0.4 μA
ΔV
FB
Reference Voltage Line Regulation V
IN
= 2.7V to 5.5V (Note 3) ●0.04 0.2 %/V
V
LOADREG
Output Voltage Load Regulation Measured in Servo Loop, V
ITH
= 0.36V ●0.02 0.2 %
Measured in Servo Loop, V
ITH
= 0.84V ●– 0.02 – 0.2 %
ΔV
PGOOD
Power Good Range ±7.5 ±9%
R
PGOOD
Power Good Pull-Down Resistance 120 200 Ω
I
Q
Input DC Bias Current (Note 4)
Active Current V
FB
= 0.78V, V
ITH
= 1V 250 330 μA
Sleep V
FB
= 1V, V
ITH
= 0V 62 80 μA
Shutdown V
RUN
= 0V, V
MODE
= 0V 0.02 1 μA
LTC3412
3
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency vs Load CurrentEfficiency vs Load Current Efficiency vs Load Current
LOAD CURRENT (A)
0.001
EFFICIENCY (%)
100
80
60
40
20
0
10
3412 G01
VIN = 3.3V
VOUT = 2.5V
Burst Mode OPERATION
FORCED CONTINUOUS
0.1 10.01
100
90
80
70
60
50
40
30
20
10
0
LOAD CURRENT (A)
0.001
EFFICIENCY (%)
10
3412 G02
V
OUT
= 2.5V
1MHz
Burst Mode OPERATION
0.1 10.01
V
IN
= 3.3V V
IN
= 5V
LOAD CURRENT (A)
0.001
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
010
3412 G03
VOUT = 2.5V
1MHz
FORCED CONTINUOUS
0.1 10.01
VIN = 3.3V VIN = 5V
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
OSC
Switching Frequency R
OSC
= 309kΩ0.88 0.95 1.1 MHz
Switching Frequency Range (Note 6) 0.3 4 MHz
f
SYNC
SYNC Capture Range (Note 6) 0.3 4 MHz
R
PFET
R
DS(ON)
of P-Channel FET I
SW
= 1A (Note 7) 85 110 mΩ
R
NFET
R
DS(ON)
of N-Channel FET I
SW
= –1A (Note 7) 65 90 mΩ
I
LIMIT
Peak Current Limit 4 5.4 A
V
UVLO
Undervoltage Lockout Threshold 2.375 2.500 2.625 V
I
LSW
SW Leakage Current V
RUN
= 0V, V
IN
= 5.5V 0.1 1 μA
V
RUN
RUN Threshold 0.5 0.65 0.8 V
I
RUN
RUN/SS Leakage Current 1μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3412E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3412I is guaranteed to meet
specified performance over the –40°C to 85°C temperature range.
Note 3: The LTC3412 is tested in a feedback loop that adjusts V
FB
to
achieve a specified error amplifier output voltage (I
TH
).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
J
is calculated from the ambient temperature T
A
and power
dissipation as follows: LTC3412: T
J
= T
A
+ P
D
(37.6°C/W).
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test correlation
in the UF package and by production test in the FE package.
LTC3412
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INPUT VOLTAGE (V)
2.55 3.05 3.55 4.05 4.55 5.05
EFFICIENCY (%)
98
96
94
92
90
88
86
3412 G04
V
OUT
= 2.5V
1MHz
Burst Mode OPERATION
LOAD = 100mA
LOAD = 1A
LOAD = 2.5A
FREQUENCY (kHz)
300 800 1300 1800 2300 2800 3300 3800
EFFICIENCY (%)
97
96
95
94
93
92
91
3412 G05
V
IN
= 3.3V
V
OUT
= 2.5V
LOAD = 1A
Burst Mode OPERATION
1μH
0.47μH
2.2μH
LOAD CURRENT (A)
00.5 1 1.5 2 2.5
%ΔVOUT/VOUT
0.02
0.00
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
3412 G06
VIN = 3.3V
VOUT = 2.5V
4μs/DIV
V
OUT
20mV/DIV
I
L
200mA/DIV
3412 G07 20μs/DIV 3412 G08
V
OUT
100mV/DIV
I
L
1A/DIV
20μs/DIV
3412 G09
V
OUT
100mV/DIV
I
L
1A/DIV
Efficiency vs FrequencyEfficiency vs Input Voltage Load Regulation
Load Step Transient Forced
ContinuousBurst Mode Operation
Load Step Transient Burst Mode
Operation
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD = 50mA
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD STEP = NO LOAD TO 2.5A
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD STEP = 50mA TO 2.5A
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–45 –25 –5 15 35 55 75 95 115 120
REFERENCE VOLTAGE (V)
3412 G11
0.7960
0.7955
0.7950
0.7945
0.7940
0.7935
0.7930
0.7925
0.7920
V
IN
= 3.3V
INPUT VOLTAGE (V)
2.5 3 3.5 4 4.5 5
ON-RESISTANCE (mΩ)
3412 G12
120
100
80
60
40
20
0
PFET ON-RESISTANCE
NFET ON-RESISTANCE
Start-Up, Burst Mode Operation
Reference Voltage
vs Temperature
Switch On-Resistance
vs Input Voltage
1ms/DIV 3412 G10
V
OUT
1V/DIV
V
RUN
1V/DIV
I
L
1A/DIV
V
IN
= 3.3V, V
OUT
= 2.5V
LOAD = 1Ω
LTC3412
5
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TEMPERATURE (°C)
–40
–20 020 40 60 80 100 120
ON-RESISTANCE (mΩ)
3412 G13
120
110
100
90
80
70
60
50
40
30
20
V
IN
= 3.3V
PFET ON-RESISTANCE
NFET ON-RESISTANCE
INPUT VOLTAGE (V)
2.5 3 3.5 4 4.5 5 5.5
LEAKAGE CURRENT (nA)
3412 G14
2.5
2.0
1.5
1.0
0.5
0
MAIN SWITCH
SYNCHRONOUS SWITCH
R
OSC
(kΩ)
50 150 250 350 450 550 650 750 850 950
FREQUENCY (kHz)
3412 G15
4500
4000
3500
3000
2500
2000
1500
1000
500
0
V
IN
= 3.3V
INPUT VOLTAGE (V)
2.5 3 3.5 4 4.5 5 5.5
FREQUENCY (kHz)
3412 G16
1050
1040
1030
1020
1010
1000
990
R = 309k
TEMPERATURE (°C)
–40
–20 0 20 40 60 80 100 120
FREQUENCY (kHz)
3412 G17
1010
1008
1006
1004
1002
1000
998
996
994
992
990
V
IN
= 3.3V
INPUT VOLTAGE (V)
2.5 3 3.5 4 4.5 5 5.5
DC SUPPLY CURRENT (μA)
3412 G18
350
300
250
200
150
100
50
SLEEP
ACTIVE
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Switch On-Resistance
vs Temperature Switch Leakage vs Input Voltage Frequency vs ROSC
Frequency vs Input Voltage
Switching Frequency
vs Temperature
DC Supply Current
vs Input Voltage
SUPPLY CURRENT (μA)
350
300
250
200
150
100
50
0
TEMPERATURE (°C)
–40
–20 020 40 60 80 100 120
3412 G19
V
IN
= 3.3V
ACTIVE
SLEEP
BURST CLAMP VOLTAGE (V)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
MINIMUM PEAK INDUCTOR CURRENT (mA)
3412 G20
4000
3500
3000
2500
2000
1500
1000
500
0
V
IN
= 3.3V
DC Supply Current vs Temperature
Minimum Peak Inductor Current
vs Burst Clamp Voltage
INPUT VOLTAGE (V)
2.75
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4 4.25 5.25
3412 G21
3.25 3.75 4.75
CURRENT LIMIT (A)
Current Limit vs Input Voltage
LTC3412
6
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PI FU CTIO S
UUU
SV
IN
(Pin 1/Pin 11): Signal Input Supply. Decouple this
pin to SGND with a capacitor. Normally SV
IN
is equal to
PV
IN
. SV
IN
can be greater than PV
IN
but keep the voltage
difference between SV
IN
and PV
IN
less than 0.5V.
PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain
logic output that is pulled to ground when the output
voltage is not within ±7.5% of regulation point.
I
TH
(Pin 3/Pin 13): Error Amplifier Compensation Point.
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.2V to 1.4V with 0.2V corresponding to the zero-sense
voltage (zero current).
V
FB
(Pin 4/Pin 14): Feedback Pin. Receives the feedback
voltage from a resistive divider connected across the
output.
R
T
(Pin 5/Pin 15): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the switching fre-
quency.
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
Clock Synchronization Input. To select forced continuous,
tie to SV
IN
. Connecting this pin to a voltage between 0V and
1V selects Burst Mode operation with the burst clamp set
to the pin voltage.
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5V shuts down the LTC3412. In
shutdown all functions are disabled drawing < 1μA of
supply current. A capacitor to ground from this pin sets the
ramp time to full output current.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal
components, compensation components and the exposed
pad on the bottom side of the IC should connect to this
ground, which in turn connects to PGND at one point.
PV
IN
(Pins 9, 16/Pins 3, 10): Power Input Supply. Decouple
this pin to PGND with a capacitor.
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
Connection to the Inductor. This pin connects to the drains
of the internal main and synchronous power MOSFET
switches.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the (–) terminal of C
IN
and C
OUT
.
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
soldered to PCB for electrical connection and thermal
performance.
(FE/UH Package)
LTC3412
7
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–
+
2
7
4–
+
+
–
–
+
0.74V
ERROR
AMPLIFIER
SYNC/MODE BURST
COMPARATOR
BCLAMP
NMOS
CURRENT
COMPARATOR
PMOS CURRENT
COMPARATOR
REVERSE
CURRENT
COMPARATOR
0.86V
RUNRUN/SS
15
13
12
14
11
SW
P-CH
N-CH
10
PGOOD
3
ITH
VFB
0.8V
5
RT
6
SYNC/MODE
3412 FBD
16
PVIN
98
SGND
1
SVIN
SLOPE
COMPENSATION
VOLTAGE
REFERENCE
OSCILLATOR
LOGIC
SLOPE
COMPENSATION
RECOVERY
–
+
–
+
+
–
PGND
+
–
FU CTIO AL BLOCK DIAGRA
UU
W
OPERATIO
U
Main Control Loop
The LTC3412 is a monolithic, constant-frequency, current
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the I
TH
pin.
The error amplifier adjusts the voltage on the I
TH
pin by
comparing the feedback signal from a resistor divider on
the V
FB
pin with an internal 0.8V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the I
TH
voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –2A for forced continuous mode and 0A for
Burst Mode operation.
The operating frequency is set by an external resistor
connected between the R
T
pin and ground. The practical
switching frequency can range from 300kHz to 4MHz.
LTC3412
8
3412fb
OPERATIO
U
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOS-
FET is switched on until either the overvoltage condition
clears or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SV
IN
will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation but may be desirable
in some applications where it is necessary to keep switch-
ing harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage between 0V
to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the I
TH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the I
TH
pin drops. As the I
TH
voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top MOSFET is held
off and the I
TH
pin is disconnected from the output of the
error amplifier. The majority of the internal circuitry is also
turned off to reduce the quiescent current to 62μA while
the load current is solely supplied by the output capacitor.
When the output voltage drops, the I
TH
pin is reconnected
to the output of the error amplifier and the top power
MOSFET along with all the internal circuitry is switched
back on. This process repeats at a rate that is dependent
on the load demand.
Pulse skipping operation can be implemented by connect-
ing the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage on
the I
TH
pin until the I
TH
voltage drops below 200mV. At this
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
The internal oscillator of the LTC3412 can be synchronized
to an external clock connected to the SYNC/MODE pin. The
frequency of the external clock can be in the range of
300kHz to 4MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
During synchronization, the burst clamp is set to 0V and
each switching cycle begins at the falling edge of the
external clock signal.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3412 is designed to operate down to an input
supply voltage of 2.625V. One important consideration at
low input supply voltages is that the R
DS(ON)
of the P-
channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
LTC3412
9
3412fb
OPERATIO
U
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.8A, the top
power MOSFET will be held off and switching cycles will be
skipped until the inductor current falls to a safe level.
APPLICATIO S I FOR ATIO
WUUU
The basic LTC3412 application circuit is shown in Fig-
ure 1. External component selection is determined by the
maximum load current and begins with the selection of the
inductor value and operating frequency followed by C
IN
and C
OUT
.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance values and/or capacitance to
maintain low output ripple voltage.
The operating frequency of the LTC3412 is determined by
an external resistor that is connected between the R
T
pin
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
RfHz k
OSC
=Ω− Ω
323 10 10
11
.•
() ()
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns. Therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔI
L
increases with higher V
IN
and decreases
with higher inductance.
Δ=⎡
⎣
⎢⎤
⎦
⎥−
⎡
⎣
⎢⎤
⎦
⎥
IV
fL
V
V
LOUT OUT
IN
1
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. High-
est efficiency operation is achieved at low frequency with
small ripple current. This, however, requires a large
inductor.
A reasonable starting point for selecting the ripple current
is ΔI
L
= 0.4(I
MAX
). The largest ripple current occurs at the
highest V
IN
. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
LV
fI
V
V
OUT
LMAX
OUT
IN MAX
=Δ
⎛
⎝
⎜
⎞
⎠
⎟−
⎛
⎝
⎜
⎞
⎠
⎟
() ()
1
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation begins
when the peak inductor current falls below a level set by the
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower induc-
tance values will cause the burst frequency to increase.
LTC3412
10
3412fb
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, mollypermalloy,
or Kool Mμ
®
cores. Actual core loss is independent of core
size for a fixed inductor value but it is very dependent on
the inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate energy but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the trapezoi-
dal current at the source of the top MOSFET. To prevent
large ripple voltage, a low ESR input capacitor sized for the
maximum RMS current should be used. RMS current is
given by:
II V
V
V
V
RMS OUT MAX OUT
IN
IN
OUT
=−
() 1
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
APPLICATIO S I FOR ATIO
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offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher tempera-
ture than required. Several capacitors may also be paral-
leled to meet size or height requirements in the design.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients, as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ΔV
OUT
, is determined by:
Δ≤Δ +
⎛
⎝
⎜⎞
⎠
⎟
V I ESR fC
OUT L OUT
1
8
The output ripple is highest at maximum input voltage
since ΔI
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special poly-
mer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
LTC3412
11
3412fb
current to remain equal to I
BURST
regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the I
TH
pin will decrease. When the I
TH
voltage drops to
150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
I
BURST
is determined by the desired amount of output
voltage ripple. As the value of I
BURST
increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, V
BURST
, can be set by a
resistor divider from the V
FB
pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low out-
put voltage ripple and efficiency, can be implemented by
connecting the SYNC/MODE pin to ground. This sets I
BURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator, and
the lowest output voltage ripple is achieved while still op-
erating discontinuously. During very light output loads,
pulse skipping allows only a few switching cycles to be
skipped while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3412’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external fre-
quency should be set 25% higher than the frequency set
by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412 in a low
quiescent current shutdown state (I
Q
< 1μA).
APPLICATIO S I FOR ATIO
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the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
V
IN
. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
VV
R
R
OUT =+
⎛
⎝
⎜⎞
⎠
⎟
08 1 2
1
.
The resistive divider allows the V
FB
pin to sense a fraction
of the output voltage as shown in Figure 2.
Figure 2. Setting the Output Voltage
LTC3412
VFB
VOUT
SGND
3412 F02
R2
R1
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than V
IN
by 1V,
Burst Mode operation is enabled. During Burst Mode
operation, the voltage on the SYNC/MODE pin determines
the burst clamp level which sets the minimum peak
inductor current, I
BURST
, for each switching cycle accord-
ing to the following equation:
IV V
A
V
BURST BURST
=−
()
⎛
⎝
⎜⎞
⎠
⎟
02 375
08
..
.
V
BURST
is the voltage on the SYNC/MODE pin. I
BURST
can
be programmed in the range of 0A to 3.75A. For values of
V
BURST
greater than 1V, I
BURST
is set at 3.75A. For values
of V
BURST
less than 0.2V, I
BURST
is set at 0A. As the output
load current drops, the peak inductor current decreases to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I
BURST
, the burst clamp will force the peak inductor
LTC3412
12
3412fb
The LTC3412 contains an internal soft-start clamp that
gradually raises the clamp on I
TH
after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on I
TH
after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on I
TH
can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
tRC V
VV
Seconds
SS SS SS IN
IN
=−
⎛
⎝
⎜⎞
⎠
⎟
()
ln .18
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current out
of V
IN
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
=f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
and external inductor R
L
. In con-
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3412 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3412 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3412 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
APPLICATIO S I FOR ATIO
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LTC3412
13
3412fb
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3412 in dropout at an
input voltage of 3.3V, a load current of 2.5A and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the P-
channel switch at 70°C is approximately 97mΩ. There-
fore, power dissipated by the part is:
P
D
= (I
LOAD2
)(R
DS(ON)
) = (2.5A)
2
(97mΩ) = 0.61W
For the TSSOP package, the θ
JA
is 37.6°C/W. Thus the
junction temperature of the regulator is:
T
J
= 70°C + (0.61W)(37.6°C/W) = 93°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3412 in an
application with the following specifications: V
IN
= 2.7V to
4.2V, V
OUT
= 2.5V, I
OUT(MAX)
= 2.5A, I
OUT(MIN)
= 10mA, f
= 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
Rkk
OSC =−=
323 10
110 10 313
11
6
.•
•
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current at maximum V
IN
:
LV
MHz A
V
VH=⎛
⎝
⎜⎞
⎠
⎟−
⎛
⎝
⎜⎞
⎠
⎟=μ
25
11
125
42 101
.
()()
.
..
Using a 1μH inductor, results in a maximum ripple current
of:
Δ=μ
⎛
⎝
⎜⎞
⎠
⎟−
⎛
⎝
⎜⎞
⎠
⎟=IV
MHz H
V
VA
L
25
11 125
42 101
.
()()
.
..
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. In this application,
two tantalum capacitors will be used to provide the bulk
capacitance and a ceramic capacitor in parallel to lower the
total effective ESR. For this design, two 100μF tantalum
capacitors in parallel with a 10μF ceramic capacitor will be
used. C
IN
should be sized for a maximum current rating of:
IA
V
V
V
VA
RMS RMS
=
()
⎛
⎝
⎜⎞
⎠
⎟−=25 25
42
42
25 1123..
.
.
..
Decoupling the PV
IN
and SV
IN
pins with a 22μF ceramic
capacitor and a 220μF tantalum capacitor is adequate for
most applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2 and R3. The
voltage on the MODE pin will be set to 0.32V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
0.32V will set the minimum inductor current, I
BURST
, as
follows:
IVV
V
VmA
BURST=−
()
⎛
⎝
⎜⎞
⎠
⎟=032 02 375
08 563..
.
.
APPLICATIO S I FOR ATIO
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LTC3412
14
3412fb
APPLICATIO S I FOR ATIO
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If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
RR k
R
R
V
V
2 3 185
12
3
08
032
+=
+=
.
.
The last two equations shown result in the following
values for R2 and R3: R2 = 110k , R3 = 75k. The value of
R1 can now be determined by solving the equation shown
below:
11
185
25
08
1 393
+=
=
R
k
V
V
Rk
.
.
A value of 392k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3412. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3412. The exposed pad should
be connected to SGND.
2. Connect the (+) terminal of the input capacitor(s), C
IN
,
as close as possible to the PV
IN
pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PV
IN
, SV
IN
, V
OUT
, PGND, SGND, or any other DC rail
in your system).
5. Connect the V
FB
pin directly to the feedback resistors.
The resistor divider must be connected between V
OUT
and
SGND.
Figure 3. LTC3412 Layout Diagram
Top Side Bottom Side
LTC3412
15
3412fb
APPLICATIO S I FOR ATIO
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Figure 4. Single Lithium-Ion to 2.5V, 2.5A Regulator at 1MHz, Burst Mode Operation Using POSCAPs
8SGND
C
SS
470pF X7R
C
C
100pF
*
**
†
††
TOKO D62CB A920CY-1ROM
SANYO POSCAP 4TPB100M
TAIYO YUDEN LMK325BJ106MN
SANYO POSCAP 2R5TPC220M
7
R
SS
4.7M
RUN
6SYNC/MODE
R
OSC
309k
5R
T
R2
110k
4
R3
75k
V
FB
R
ITH
7.15k 3
C
ITH
680pF X7R
I
TH
2PGOODPGOOD
1SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412 13 L1*
1μH
PGND
14
SW
15
SW
16
PV
IN
C
IN2
22μF
X5R 6.3V
C
IN1††
220μF
C
OUT2†
10μF
C
OUT1
**
100μF
×2
V
OUT
2.5V
2.5A
V
IN
2.7V TO 4.2V
GND
3412 F04
R1 392k
+
R
PG
100k
C
FB
22pF X5R
LTC3412
16
3412fb
2.5V, 2.5A Regulator Using All Ceramic Capacitors
8SGND
C
SS
470pF X7R
7
R
SS
4.7M
RUN
6SYNC/MODE
R
OSC
309k
5R
T
R2
110k
4
R3
75k
V
FB
R
ITH
15k 3
C
ITH
1000pF X7R
I
TH
2PGOODPGOOD
1SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412 13 L1*
1μH
PGND
14
SW
15
SW
16
PV
IN
C1
22pF X5R
C
IN2
22μF
X5R 6.3V
C
IN1
22μF
X5R 6.3V
C
OUT
**
100μF
V
OUT
2.5V
2.5A
V
IN
2.7V TO 5.5V
GND
3412 F05
C
IN3
**
100μF
R1 392k
*
**
TOKO D62CB A920CY-1ROM
TDK C4532X5R0J107M
C
C
100pF
R
PG
100k
8SGND
C
SS
470pF X7R
7
R
SS
4.7M RUN
6SYNC/MODE
R
OSC
309k
5R
T
R2
110k
R3
75k
4V
FB
R
ITH
10k 3
C
ITH
560pF X7R
I
TH
2PGOODPGOOD
1SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412 13
PGND
14
SW
15
SW
16
PV
IN
C
IN2
22μF**
C
IN1
**
22μF
C
OUT
**
22μF
×2
V
OUT
1.8V
2A
V
IN
3.3V
GND
R1 232k
3412 TA05
L1
1μH*
*
**
SUMIDA CR431R0
AVX 12066D226MAT
C2
47pF
C1 22pF X5R
R
PG
100k
1.8V, 2.5A Step-Down Regulator at 1MHz, Burst Mode Operation
TYPICAL APPLICATIO S
U
LTC3412
17
3412fb
TYPICAL APPLICATIO S
U
8SGND
C
SS
470pF X7R
7
R
SS
4.7M
RUN
6SYNC/MODE
R
OSC
137k
5R
T
R2
182k
4V
FB
R
ITH
22.1k 3
C
ITH
1000pF X7R
I
TH
2PGOODPGOOD
1SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412 13
PGND
14
SW
15
SW
16
PV
IN
C
IN2
100μF**
C
IN1
**
100μF
C
OUT
**
100μF
×2
V
OUT
2.5V
2.5A
V
IN
3.3V
GND
R1 392k
R
IN
5Ω
3412 TA06
L1
0.47μH*
*
**
VISHAY DALE IHLP-2525CZ-01 0.47
TDK C4532X5R0J107M
C1
56pF
C
FF
22pF X7R
R
PG
100k
C
IN3
0.1μF
X5R
2.5V, 2.5A Low Output Noise Regulator at 2MHz
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1 1 10
3412 TA07
30
20
10
0
90
100
Efficiency vs Load Current
2MHz, Low Noise
LTC3412
18
3412fb
8SGND
C
SS
470pF X7R
7
R
SS
4.7M
RUN
6SYNC/MODE
R
OSC
309k
5R
T
R2
200k
4
V
FB
R
ITH
15k 3
C
ITH
1000pF X7R
I
TH
2PGOODPGOOD
1SV
IN
9
PV
IN
10
SW
11
SW
12
PGND
LTC3412 13
PGND
14
SW
15
SW
16
PV
IN
C
IN2
22μF
X5R 6.3V
C
IN1
22μF
X5R 6.3V
C
OUT
**
100μF
V
OUT
3.3V
2.5A
V
IN
5V
GND
R1 634k
3412 TA01
L1*
1μH
*
**
PULSE P1166.162T
TDK C4532X5R0J107M
C
C
100pF
C1 22pF X5R
C
IN3
**
100μF
R
PG
100k
3.3V, 2.5A Step-Down Regulator at 1MHz, Forced Continuous Mode Operation
TYPICAL APPLICATIO S
U
8SGND
CSS
470pF X7R
7
RSS
4.7M
RUN
6SYNC/MODE
ROSC
309k
5RT
R2
110k
4
R3
75k
VFB
RITH
15k 3
CITH 1000pF X7R
ITH
2PGOODPGOOD
1SVIN
9
PVIN
10
SW
11
SW
12
PGND
LTC3412 13 L1*
2μH
M1
SILICONIX
Si2302DS
D1
DIODES, INC.
B320A
PGND
14
SW
15
SW
16
PVIN
C1
22pF
CIN2
22μF
X5R 6.3V
CIN1
22μF
X5R 6.3V
COUT**
100μF
VOUT
3.3V
VIN
2.7V TO 4.2V
GND
GND
3412 F04
CIN3**
100μF
×2
R1 576k
*
**
TOKO D63CB
TDK C4532X5R0J107M
C2
100pF
RPG
100k
VIN MAXIMUM IOUT
2.7V 800mA
3V 900mA
3.5V 1.05A
4.2V 1.2A
Lithium-Ion to 3.3V, Single Inductor Buck-Boost Converter
LTC3412
19
3412fb
PACKAGE DESCRIPTIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
FE16 (BA) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.74
(.108)
2.74
(.108)
0.195 – 0.30
(.0077 – .0118)
TYP
2
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
RECOMMENDED SOLDER PAD LAYOUT
3. DRAWING NOT TO SCALE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.74
(.108)
2.74
(.108)
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.55 ± 0.20
1615
1
2
BOTTOM VIEW—EXPOSED PAD
2.15 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.30 ± 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
(UF16) QFN 1004
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.72 ±0.05
0.30 ±0.05
0.65 BSC
2.15 ± 0.05
(4 SIDES)
2.90 ± 0.05
4.35 ± 0.05
PACKAGE
OUTLINE
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
LTC3412
20
3412fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
LT 0707 REV B • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATIO
U
PART NUMBER DESCRIPTION COMMENTS
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IN
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IN
= 2.5V to 9.8V, 94% Efficiency, 100% Duty Cycle, ThinSOT
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IN
= 2.65V to 8.5V, 95% Efficiency, V
OUT
from 0.8V to V
IN
,
MSOP-10
LTC1875 1.5A (I
OUT
), 500kHz Synchronous Step-Down Converter V
IN
= 2.65V to 6V, 95% Efficiency, PLL, SSOP-16
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OUT
), 500kHz Synchronous Step-Down Converter V
IN
= 2.65V to 10V, 95% Efficiency, MSOP-8
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OUT
), 550kHz Synchronous Step-Down Converter V
IN
= 2.65V to 6V, 95% Efficiency, MSOP-8
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), 550kHz Synchronous Step-Down Converter V
IN
= 2.65V to 10V, 95% Efficiency, SSOP-16
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OUT
), 1.4MHz Synchronous Step-Down Converter V
IN
= 2.65V to 6V, 95% Efficiency, MSOP-8
LTC3405A 300mA (I
OUT
), 1.5MHz Synchronous Step-Down Converter V
IN
= 2.65V to 6V, 96% Efficiency, ThinSOT Package
LTC3406/LTC3406B 600mA (I
OUT
), 1.5MHz Synchronous Step-Down Converter V
IN
= 2.5V to 5.5V, 95% Efficiency, ThinSOT,
B Version: Burst Mode Defeat
LTC3411 1.25A (I
OUT
), 4MHz Synchronous Step-Down Converter V
IN
= 2.5V to 5.5V, 95% Efficiency, MSOP-10
ThinSOT is a trademark of Linear Technology Corporation.
2.5V, 2.5A Step-Down Regulator Synchronized to 1.25MHz
8SGND
CSS
470pF X7R
7
RSS
4.7M
RUN
6SYNC/MODE
1.25MHz
EXT CLOCK
ROSC 309k
5RT
R2 182k
4VFB
RITH
15k
RPG
100k
3
CITH 1000pF X7R
ITH
2PGOODPGOOD
1SVIN
9
PVIN
10
SW
11
SW
12
PGND
LTC3412 13 L1*
1μH
PGND
14
SW
15
SW
16
PVIN
CIN2
22μF
X5R 6.3V
CIN1
22μF
X5R 6.3V
COUT1**
100μF
VOUT
2.5V
2.5A
VIN
2.7V TO 5.5V
GND
R1 392k
3412 TA02
*
**
TOKO D62CB A920CY-1ROM
TDK C4532X5R0J107M
CC 100pF
C1 22pF X5R
CIN3**
100μF
