K61P256M120SF3
K61 Sub-Family
Supports the following:
MK61FX512VMJ12,
MK61FN1M0VMJ12
Key features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 120 MHz ARM® Cortex®-M4 core with
DSP instructions delivering 1.25 Dhrystone
MIPS per MHz
• Memories and memory interfaces
– Up to 1024 KB program flash memory on non-
FlexMemory devices
– Up to 512 KB program flash memory on
FlexMemory devices
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– DDR controller interface
– NAND flash controller interface
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to
128 request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Tamper detect and secure storage
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES,
AES, MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per
chip
• Human-machine interface
– Low-power hardware touch sensor interface
(TSI)
– General-purpose input/output
• Analog modules
– Four 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Four analog comparators (CMP) containing a 6-
bit DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Two 8-channel motor control/general
purpose/PWM timers
– Two 2-channel quadrature decoder/general
purpose timers
– IEEE 1588 timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
Freescale Semiconductor Document Number K61P256M120SF3
Data Sheet: Technical Data Rev. 6, 09/2015
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2015 Freescale Semiconductor, Inc.
• Communication interfaces
– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
– USB high-/full-/low-speed On-the-Go controller with ULPI interface
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital Host Controller (SDHC)
– Two I2S modules
K61 Sub-Family, Rev.6, 09/2015.
2 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts........................................................................... 5
1.1 Determining valid orderable parts......................................5
2 Part identification...................................................................... 5
2.1 Description.........................................................................5
2.2 Format............................................................................... 5
2.3 Fields.................................................................................5
2.4 Example............................................................................ 6
3 Terminology and guidelines...................................................... 6
3.1 Definitions..........................................................................6
3.2 Examples...........................................................................6
3.3 Typical-value conditions.................................................... 7
3.4 Relationship between ratings and operating
requirements......................................................................7
3.5 Guidelines for ratings and operating requirements............8
4 Ratings......................................................................................8
4.1 Thermal handling ratings...................................................8
4.2 Moisture handling ratings.................................................. 9
4.3 ESD handling ratings.........................................................9
4.4 Voltage and current operating ratings............................... 9
5 General..................................................................................... 10
5.1 AC electrical characteristics.............................................. 10
5.2 Nonswitching electrical specifications............................... 10
5.2.1 Voltage and current operating requirements...... 10
5.2.2 LVD and POR operating requirements...............12
5.2.3 Voltage and current operating behaviors............13
5.2.4 Power mode transition operating behaviors....... 16
5.2.5 Power consumption operating behaviors............17
5.2.6 EMC radiated emissions operating behaviors.... 20
5.2.7 Designing with radiated emissions in mind.........21
5.2.8 Capacitance attributes........................................21
5.3 Switching specifications.....................................................21
5.3.1 Device clock specifications.................................21
5.3.2 General switching specifications.........................22
5.4 Thermal specifications.......................................................24
5.4.1 Thermal operating requirements.........................24
5.4.2 Thermal attributes...............................................24
5.5 Power sequencing.............................................................25
6 Peripheral operating requirements and behaviors.................... 26
6.1 Core modules.................................................................... 26
6.1.1 Debug trace timing specifications.......................26
6.1.2 JTAG electricals..................................................26
6.2 System modules................................................................29
6.3 Clock modules...................................................................29
6.3.1 MCG specifications.............................................29
6.3.2 Oscillator electrical specifications.......................32
6.3.3 32 kHz oscillator electrical characteristics.......... 34
6.4 Memories and memory interfaces..................................... 34
6.4.1 Flash (FTFE) electrical specifications.................34
6.4.2 EzPort switching specifications...........................39
6.4.3 NFC specifications..............................................40
6.4.4 DDR controller specifications..............................43
6.4.5 Flexbus switching specifications.........................46
6.5 Security and integrity modules.......................................... 48
6.5.1 DryIce Tamper Electrical Specifications............. 48
6.6 Analog............................................................................... 49
6.6.1 ADC electrical specifications.............................. 49
6.6.2 CMP and 6-bit DAC electrical specifications...... 56
6.6.3 12-bit DAC electrical characteristics...................58
6.6.4 Voltage reference electrical specifications..........61
6.7 Timers................................................................................62
6.8 Communication interfaces.................................................62
6.8.1 Ethernet switching specifications........................62
6.8.2 USB electrical specifications...............................64
6.8.3 USB DCD electrical specifications......................65
6.8.4 USB VREG electrical specifications................... 65
6.8.5 ULPI timing specifications...................................66
6.8.6 CAN switching specifications..............................67
6.8.7 DSPI switching specifications (limited voltage
range)................................................................. 67
6.8.8 DSPI switching specifications (full voltage
range)................................................................. 68
6.8.9 Inter-Integrated Circuit Interface (I2C) timing..... 70
6.8.10 UART switching specifications............................71
6.8.11 SDHC specifications...........................................71
6.8.12 I2S/SAI switching specifications......................... 72
6.9 Human-machine interfaces (HMI)......................................79
6.9.1 TSI electrical specifications................................ 79
7 Dimensions............................................................................... 80
7.1 Obtaining package dimensions......................................... 80
8 Pinout........................................................................................80
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 3
8.1 Pins with active pull control after reset.............................. 80
8.2 K61 Signal Multiplexing and Pin Assignments.................. 81
8.3 K61 Pinouts....................................................................... 90
9 Revision History........................................................................ 91
K61 Sub-Family, Rev.6, 09/2015.
4 Freescale Semiconductor, Inc.
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK61 and MK61
2Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
K## Kinetis family • K61
A Key attribute • F = Cortex-M4 w/ DSP and FPU
M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory
FFF Program flash memory size • 512 = 512 KB
• 1M0 = 1 MB
Table continues on the next page...
Ordering parts
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 5
Field Description Values
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • MJ = 256 MAPBGA (17 mm x 17 mm)
CC Maximum CPU frequency (MHz) • 12 = 120 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK61FN1M0VMJ12
3Terminology and guidelines
3.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent
chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
K61 Sub-Family, Rev.6, 09/2015.
6 Freescale Semiconductor, Inc.
3.2 Examples
Operating rating:
Operating requirement:
Operating behavior that includes a typical value:
EXAMPLE
EXAMPLEEXAMPLE
EXAMPLE
3.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
Terminology and guidelines
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 7
3.4 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
3.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
4Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Ratings
K61 Sub-Family, Rev.6, 09/2015.
8 Freescale Semiconductor, Inc.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage1–0.3 3.8 V
VDD_INT Core supply voltage –0.3 3.8 V
VDD_DDR DDR I/O supply voltage –0.3 3.8 V
IDD Digital supply current — 300 mA
IDD_INT Core supply current — 185 mA
IDD_DDR DDR supply current — 220 mA
VDIO Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2–0.3 5.5 V
VDDDR DDR input voltage –0.3 VDD_DDR + 0.3 V
VAIO Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
–0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB1_DP USB1_DP input voltage –0.3 3.63 V
Table continues on the next page...
Ratings
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 9
Symbol Description Min. Max. Unit
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VUSB1_DM USB1_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. It applies for all port pins except Tamper pins.
2. It covers digital pins except Tamper pins and DDR pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
General
K61 Sub-Family, Rev.6, 09/2015.
10 Freescale Semiconductor, Inc.
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage max [VDD_DDR, 1.71 V] 3.6 V
VDD_INT Core supply voltage 1.71 VDD V
VDD_DDR DDR voltage — memory I/O buffers
• DDR1
• DDR2/LPDDR1
2.3
1.71
2.7
1.9
V
V
VREF_DDR Input reference voltage (DDR1/DDR2/
LPDDR1)
0.49 × VDD_DDR VDD_DDR V1
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage (digital pins except
Tamper pins and DDR pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage (digital pins except Tamper
pins and DDR pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VIH_DDR Input high voltage (DDR pins)
• DDR1
• DDR2
• LPDDR1
VREF_DDR + 0.15
VREF_DDR + 0.125
0.7 × VDD_DDR
—
—
—
V
V
V
VIL_DDR Input low voltage (DDR pins)
• DDR1
• DDR2
• LPDDR1
—
—
—
VREF_DDR – 0.15
VREF_DDR – 0.125
0.3 × VDD_DDR
V
V
V
VHYS Input hysteresis (digital pins except Tamper
pins and DDR pins)
0.06 × VDD — V
IICDIO Digital pin (except Tamper pins) negative DC
injection current — single pin
• VIN < VSS-0.3V
-5 — mA
2
IICAIO Analog3, EXTAL0/XTAL0, and EXTAL1/
XTAL1 pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current
injection)
• VIN > VDD+0.3V (Positive current
injection)
-5
—
—
+5
mA
4
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General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 11
Table 1. Voltage and current operating requirements (continued)
Symbol Description Min. Max. Unit Notes
IICcont Contiguous pin DC injection current —
regional limit, includes sum of negative
injection currents or sum of positive injection
currents of 16 contiguous pins
• Negative current injection
• Positive current injection
-25
—
—
+25
mA
VODPU Open drain pullup voltage level VDD VDD V5
VRAM VDD (VDD_INT) voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT
register file
VPOR_VBAT — V
1. For DDR1/DDR2, connect VREF_DDR to the same reference voltage used for the memory. For LPDDR1, connect VREF_DDR
to the VDD_DDR voltage.
2. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection
current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
4. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
5. Open drain outputs must be pulled to VDD.
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±80 — mV
VLVDL Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1.74
1.84
1.80
1.90
1.86
1.96
V
V
1
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General
K61 Sub-Family, Rev.6, 09/2015.
12 Freescale Semiconductor, Inc.
Table 2. LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW3L
VLVW4L
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.94
2.04
2.00
2.10
2.06
2.16
V
V
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period
factory trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
VOH Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT Output high current total for all ports — — 100 mA
IOHT_io60 Output high current total for fast digital ports — — 100 mA
VOH_DDR Output high voltage for DDR pins
• DDR1 (IOH = -16.2 mA)
• DDR2 half strength (IOH = -5.36 mA)
• DDR2 full strength (IOH = -13.4 mA)
• LPDDR1 half strength (IOH = -0.1 mA)
• LPDDR1 full strength (IOH = -0.1 mA)
VDD_DDR -
0.36
VDD_DDR -
0.28
VDD_DDR -
0.28
0.9 x
VDD_DDR
0.9 x
VDD_DDR
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
Table continues on the next page...
General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 13
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IOHT_DDR Output high current total for DDR pins
• DDR1
• DDR2
• LPDDR1
—
—
—
—
—
—
100
56
39
mA
mA
mA
VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
VBAT – 0.5
VBAT – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
VBAT – 0.5
VBAT – 0.5
—
—
—
—
V
V
IOH_Tamper Output high current total for Tamper pins — — 100 mA
VOL Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1 mA
—
—
—
—
0.5
0.5
V
V
IOLT Output low current total for all ports — — 100 mA
IOLT_io60 Output low current total for fast digital ports — — 100 mA
VOL_DDR Output low voltage for DDR pins
• DDR1 (IOL = 16.2 mA)
• DDR2 half strength (IOL = 5.36 mA)
• DDR2 full strength (IOL = 13.4 mA)
• LPDDR1 half strength (IOL = 0.1 mA)
• LPDDR1 full strength (IOL = 0.1 mA)
—
—
—
—
—
—
—
—
—
—
0.37
0.28
0.28
0.1 x
VDD_DDR
0.1 x
VDD_DDR
V
V
V
V
V
IOLT_DDR Output low current total for DDR pins
• DDR1
• DDR2
• LPDDR1
— — 100
56
39
mA
mA
mA
VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
—
—
—
—
0.5
0.5
V
V
Table continues on the next page...
General
K61 Sub-Family, Rev.6, 09/2015.
14 Freescale Semiconductor, Inc.
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IOL_Tamper Output low current total for Tamper pins — — 100 mA
IINA Input leakage current, analog pins and digital
pins configured as analog inputs
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
—
—
—
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
1, 2
IIND Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
• All digital pins
• VIN = VDD
• All digital pins except PTD7
• PTD7
—
—
—
0.002
0.002
0.004
0.5
0.5
1
μA
μA
μA
2, 3
IIND Input leakage current, digital pins
• VIL < VIN < VDD
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
18
12
8
3
26
19
13
6
μA
μA
μA
μA
2, 3, 4
IIND Input leakage current, digital pins
• VDD < VIN < 5.5 V
—
1
50
μA
2, 3
ZIND Input impedance examples, digital pins
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
2, 5
IIN_DDR Input leakage current (per DDR pin) for full
temperature range
— — 1 μA
IIN_DDR Input leakage current (per DDR pin) at 25°C — — 0.025 μA
IIN_Tamper Input leakage current (per Tamper pin) for full
temperature range
— — 1 μA
IIN_Tamper Input leakage current (per Tamper pin) at 25°C — — 0.025 μA
RPU Internal pullup resistors (except Tamper pins) 20 — 50 kΩ 6
RPD Internal pulldown resistors (except Tamper pins) 20 — 50 kΩ 7
RODT On-die termination (ODT) resistance for DDR2
• Rtt1(eff) - 75 Ω
• Rtt2(eff) - 150 Ω
60
120
—
—
90
180
Ω
Ω
General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 15
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
3. Internal pull-up/pull-down resistors disabled.
4. Characterized, not tested in production.
5. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See
Figure 2.
6. Measured at VDD supply voltage = VDD min and Vinput = VSS
7. Measured at VDD supply voltage = VDD min and Vinput = VDD
Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
—
—
300
1.7 V / (VDD
slew rate)
μs
1
• VLLS1 → RUN — 160 μs
• VLLS2 → RUN — 114 μs
Table continues on the next page...
General
K61 Sub-Family, Rev.6, 09/2015.
16 Freescale Semiconductor, Inc.
Table 5. Power mode transition operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
• VLLS3 → RUN — 114 μs
• LLS → RUN — 5.0 μs
• VLPS → RUN — 5 μs
• STOP → RUN — 4.8 μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
49.28
49.08
73.85
73.93
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
74.43
74.28
99.97
100.41
mA
mA
3
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 34.67 58.5 mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
— 18.03 41.91 mA 4
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
1.25
2.93
7.08
1.62
4.39
10.74
mA
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 1.03 4.48 mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 1.58 4.96 mA 5
IDD_VLPW Very-low-power wait mode current at 3.0 V — 0.64 4.29 mA 5
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C —
—
0.22
0.78
0.38
1.33
mA
mA
Table continues on the next page...
General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 17
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• @ 70°C
• @ 105°C
— 2.18 3.56 mA
IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.22
0.78
2.16
0.37
1.33
3.52
mA
mA
mA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
4.09
20.98
84.95
5.58
28.93
111.15
μA
μA
μA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.68
8.8
37.28
4.22
10.74
43.61
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.46
7.04
30.68
4.02
8.99
37.04
μA
μA
μA
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.89
1.28
3.10
1.10
1.85
4.30
μA
μA
μA
6
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled, but peripherals are not in active operation.
4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode at greater than 100 MHz frequencies.
General
K61 Sub-Family, Rev.6, 09/2015.
18 Freescale Semiconductor, Inc.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 19
Figure 4. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol Description Frequency
band (MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 21 dBμV 1, 2, 3
VRE2 Radiated emissions voltage, band 2 50–150 24 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 29 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 28 dBμV
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 72 MHz, fBUS = 72 MHz
3. Determined according to IEC Standard JESD78, IC Latch-Up Test
General
K61 Sub-Family, Rev.6, 09/2015.
20 Freescale Semiconductor, Inc.
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
CIN_D_io60 Input capacitance: fast digital pins — 9 pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock — 120 MHz
fSYS_USBFS System and core clock when Full Speed USB in
operation
20 — MHz
fSYS_USBHS System and core clock when High Speed USB in
operation
60 — MHz
fENET System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
5
50
—
—
MHz
fBUS Bus clock — 60 MHz
FB_CLK FlexBus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fDDR DDR clock — 150 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
Table continues on the next page...
General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 21
Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
FB_CLK FlexBus clock — 4 MHz
fFLASH Flash clock — 0.5 MHz
fLPTMR LPTMR clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
14
8
36
24
ns
ns
ns
ns
4
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
—
—
—
14
8
36
ns
ns
ns
5
Table continues on the next page...
General
K61 Sub-Family, Rev.6, 09/2015.
22 Freescale Semiconductor, Inc.
Table 10. General switching specifications (continued)
Symbol Description Min. Max. Unit Notes
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
— 24 ns
tio50 Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
7
3
28
14
ns
ns
ns
ns
6
—
—
—
—
tio50 Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
18
9
48
24
ns
ns
ns
ns
7
—
—
—
—
tio60 Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
6
3
28
14
ns
ns
ns
ns
6
—
—
—
—
tio60 Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
18
6
48
24
ns
ns
ns
ns
7
—
—
—
—
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
6. 25 pF load
General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 23
7. 15 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature1–40 105 °C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
5.4.2 Thermal attributes
Board type Symbol Description 256 MAPBGA Unit Notes
Single-layer (1s) RθJA Thermal
resistance, junction
to ambient (natural
convection)
43 °C/W 1, 2
Four-layer (2s2p) RθJA Thermal
resistance, junction
to ambient (natural
convection)
28 °C/W 1,2, 3
Single-layer (1s) RθJMA Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
36 °C/W 1,3
Four-layer (2s2p) RθJMA Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
25 °C/W 1,3
— RθJB Thermal
resistance, junction
to board
17 °C/W 4
— RθJC Thermal
resistance, junction
to case
8 °C/W 5
—ΨJT Thermal
characterization
parameter, junction
to package top
outside center
2 °C/W 6
General
K61 Sub-Family, Rev.6, 09/2015.
24 Freescale Semiconductor, Inc.
Board type Symbol Description 256 MAPBGA Unit Notes
(natural
convection)
NOTES:
1. Junction temperature is a function of die size, on-chip power dissipation, package
thermal resistance, mounting site (board) temperature, ambient temperature, air flow,
power dissipation of other components on the board, and board thermal resistance.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air) with the
single layer board horizontal. Board meets JESD51-9 specification.
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuit Thermal
Test Method Environmental Conditions—Forced Convection (Moving Air) with the
board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board. Board temperature is
measured on the top surface of the board near the package.
5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of the
package and the cold plate.
6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air).
5.5 Power sequencing
Voltage supplies must be sequenced in the proper order to avoid damaging internal
diodes. There is no limit on how long after one supply powers up before the next supply
must power up. Note that VDD and VDD_INT can use the same power source.
The power-up sequence is:
1. VDD/VDDA
2. VDD_INT
3. VDD_DDR
The power-down sequence is the reverse:
1. VDD_DDR
2. VDD_INT
3. VDD/VDDA
General
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 25
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol Description Min. Max. Unit
Tcyc Clock period Frequency dependent MHz
Twl Low pulse width 2 — ns
Twh High pulse width 2 — ns
TrClock and data rise time — 3 ns
TfClock and data fall time — 3 ns
TsData setup 3 — ns
ThData hold 2 — ns
TRACECLK
Tr
Twh
Tf
Tcyc
Twl
Figure 5. TRACE_CLKOUT specifications
Th
Ts Ts Th
TRACE_CLKOUT
TRACE_D[3:0]
Figure 6. Trace data specifications
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
26 Freescale Semiconductor, Inc.
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
0
0
0
10
25
50
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
50
20
10
—
—
—
ns
ns
ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 2.4 — ns
J7 TCLK low to boundary scan output data valid — 25 ns
J8 TCLK low to boundary scan output high-Z — 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1 — ns
J11 TCLK low to TDO data valid — 17 ns
J12 TCLK low to TDO high-Z — 17 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
Table 14. JTAG full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
0
0
0
10
20
40
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
50
25
12.5
—
—
—
ns
ns
ns
J4 TCLK rise and fall times — 3 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 27
Table 14. JTAG full voltage range electricals (continued)
Symbol Description Min. Max. Unit
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 2.4 — ns
J7 TCLK low to boundary scan output data valid — 25 ns
J8 TCLK low to boundary scan output high-Z — 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns
J11 TCLK low to TDO data valid — 22.1 ns
J12 TCLK low to TDO high-Z — 22.1 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
J2
J3 J3
J4 J4
TCLK (input)
Figure 7. Test clock input timing
J7
J8
J7
J5 J6
Input data valid
Output data valid
Output data valid
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Figure 8. Boundary scan (JTAG) timing
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
28 Freescale Semiconductor, Inc.
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
TCLK
TDI/TMS
TDO
TDO
TDO
Figure 9. Test Access Port timing
J14
J13
TCLK
TRST
Figure 10. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 29
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
fints_t Internal reference frequency (slow clock) — user
trimmed
31.25 — 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
— ± 0.3 ± 0.6 %fdco 1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
— ± 0.2 ± 0.5 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
— ± 4.5 — %fdco 1
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
— 4 — MHz
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— — kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— — kHz
FLL
ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20 20.97 25 MHz 2, 3
Mid range (DRS=01)
1280 × ffll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × ffll_ref
80 83.89 100 MHz
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
— 23.99 — MHz 4, 5
Mid range (DRS=01)
1464 × ffll_ref
— 47.97 — MHz
Mid-high range (DRS=10)
2197 × ffll_ref
— 71.99 — MHz
High range (DRS=11)
2929 × ffll_ref
— 95.98 — MHz
Jcyc_fll FLL period jitter — 180 — ps
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
30 Freescale Semiconductor, Inc.
Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
• fVCO = 48 MHz
• fVCO = 98 MHz
— 150 —
tfll_acquire FLL target frequency acquisition time — — 1 ms 6
PLL0,1
fpll_ref PLL reference frequency range 8 — 16 MHz
fvcoclk_2x VCO output frequency 180 —360 MHz
fvcoclk PLL output frequency 90 —180 MHz
fvcoclk_90 PLL quadrature output frequency 90 —180 MHz
Ipll PLL0 operating current
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 23)
— 2.8 — mA
Ipll PLL0 operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
— 4.7 — mA 7
Ipll PLL1 operating current
• VCO @ 184 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 23)
— 2.3 — mA 7
Ipll PLL1 operating current
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz, fpll_ref
= 8 MHz, VDIV multiplier = 45)
— 3.6 — mA 7
tpll_lock Lock detector detection time — — 100 × 10-6
+ 1075(1/
fpll_ref)
s8
Jcyc_pll PLL period jitter (RMS)
• fvco = 180 MHz
• fvco = 360 MHz
—
—
100
75
—
—
ps
ps
9
Jacc_pll PLL accumulated jitter over 1µs (RMS)
• fvco = 180 MHz
• fvco = 360 MHz
—
—
600
300
—
—
ps
ps
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. Accumulated jitter depends on VCO frequency and VDIV.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 31
6.3.2 Oscillator electrical specifications
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
1.5
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high-gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
500
2.5
3
4
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Table continues on the next page...
Peripheral operating requirements and behaviors
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32 Freescale Semiconductor, Inc.
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz 1
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 60 MHz 2, 3
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 1000 — ms 4, 5
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 500 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
3. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 33
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz oscillator electrical characteristics
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit
VBAT Supply voltage 1.71 — 3.6 V
RFInternal feedback resistor — 100 — MΩ
Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF
Vpp1Peak-to-peak amplitude of oscillation — 0.6 — V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2 32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal — 32.768 — kHz
tstart Crystal start-up time — 1000 — ms 1
vec_extal32 Externally provided input clock amplitude 700 — VBAT mV 2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
34 Freescale Semiconductor, Inc.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm8 Program Phrase high-voltage time — 7.5 18 μs
thversscr Erase Flash Sector high-voltage time — 13 113 ms 1
thversblk128k Erase Flash Block high-voltage time for 128 KB — 104 1808 ms 1
thversblk256k Erase Flash Block high-voltage time for 256 KB — 208 3616 ms 1
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1blk128k
trd1blk256k
Read 1s Block execution time
• 128 KB data flash
• 256 KB program flash
256 KB data flash
—
—
—
—
0.5
1.0
ms
ms
trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1
tpgmchk Program Check execution time — — 80 μs 1
trdrsrc Read Resource execution time — — 40 μs 1
tpgm8 Program Phrase execution time — 70 150 μs
tersblk128k
tersblk256k
Erase Flash Block execution time
• 128 KB data flash
• 256 KB program flash
256 KB data flash
—
—
110
220
925
1850
ms
ms
2
tersscr Erase Flash Sector execution time — 15 115 ms 2
tpgmsec4k Program Section execution time (4KB flash) — 20 — ms
trd1allx
trd1alln
Read 1s All Blocks execution time
• FlexNVM devices
• Program flash only devices
—
—
—
—
3.4
3.4
ms
ms
trdonce Read Once execution time — — 30 μs 1
tpgmonce Program Once execution time — 70 — μs
tersall Erase All Blocks execution time — 650 5600 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
Swap Control execution time
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 35
Table 21. Flash command timing specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
tswapx01
tswapx02
tswapx04
tswapx08
• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08
—
—
—
—
200
70
70
—
—
150
150
30
μs
μs
μs
μs
tpgmpart64k
tpgmpart256k
Program Partition for EEPROM execution time
• 64 KB EEPROM backup
• 256 KB EEPROM backup
—
—
235
240
—
—
ms
ms
tsetramff
tsetram64k
tsetram128k
tsetram256k
Set FlexRAM Function execution time:
• Control Code 0xFF
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
205
1.6
2.7
4.8
—
2.5
3.8
6.2
μs
ms
ms
ms
t eewr8bers Byte-write to erased FlexRAM location execution
time
— 140 225 μs 3
teewr8b64k
teewr8b128k
teewr8b256k
Byte-write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
400
450
525
1700
1800
2000
μs
μs
μs
t eewr16bers 16-bit write to erased FlexRAM location
execution time
— 140 225 μs
teewr16b64k
teewr16b128k
teewr16b256k
16-bit write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
400
450
525
1700
1800
2000
μs
μs
μs
teewr32bers 32-bit write to erased FlexRAM location
execution time
— 180 275 μs
teewr32b64k
teewr32b128k
teewr32b256k
32-bit write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
475
525
600
1850
2000
2200
μs
μs
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
36 Freescale Semiconductor, Inc.
6.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current
adder during high
voltage flash
programming
operation
— 3.5 7.5 mA
IDD_ERS Average current
adder during high
voltage flash erase
operation
— 1.5 4.0 mA
6.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles 5 50 — years
tnvmretd1k Data retention after up to 1 K cycles 20 100 — years
nnvmcycd Cycling endurance 10 K 50 K — cycles 2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance 5 50 — years
tnvmretee10 Data retention up to 10% of write endurance 20 100 — years
nnvmcycee Cycling endurance for EEPROM backup 20 K 50 K — cycles 2
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
Write endurance
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
70 K
630 K
2.5 M
10 M
175 K
1.6 M
6.4 M
25 M
—
—
—
—
writes
writes
writes
writes
3
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16-
bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 37
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_subsystem = × Write_efficiency × n
EEPROM – 2 × EEESPLIT × EEESIZE
EEESPLIT × EEESIZE nvmcycee
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
38 Freescale Semiconductor, Inc.
Figure 11. EEPROM backup writes to FlexRAM
6.4.2 EzPort switching specifications
Table 24. EzPort switching specifications
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
EP1 EZP_CK frequency of operation (all commands except
READ)
— fSYS/2 MHz
EP1a EZP_CK frequency of operation (READ command) — fSYS/8 MHz
EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns
EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns
EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns
EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns
EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns
EP7 EZP_CK low to EZP_Q output valid — 16 ns
EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns
EP9 EZP_CS negation to EZP_Q tri-state — 12 ns
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 39
EP2
EP3 EP4
EP5 EP6
EP7 EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 12. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
which are defined as:
input clock
T
SCALER
=
NFC
T=H
T
L
T+
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SCALER =SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means TH = TL. In case the reciprocal of SCALER is not an integer:
(1 + SCALER / 2) x
=
L
TNFC
T
2
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
40 Freescale Semiconductor, Inc.
(1 – SCALER / 2) x
=
H
TNFC
T
2
For example, if SCALER is 0.2, then TH = TL = TNFC/2.
TNFC
THTL
However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC.
TNFC
THTL
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
Table 25. NFC specifications
Num Description Min. Max. Unit
tCLS NFC_CLE setup time 2TH + TL – 1 — ns
tCLH NFC_CLE hold time TH + TL – 1 — ns
tCS NFC_CEn setup time 2TH + TL – 1 — ns
tCH NFC_CEn hold time TH + TL— ns
tWP NFC_WP pulse width TL – 1 — ns
tALS NFC_ALE setup time 2TH + TL— ns
tALH NFC_ALE hold time TH + TL— ns
tDS Data setup time TL – 1 — ns
tDH Data hold time TH – 1 — ns
tWC Write cycle time TH + TL – 1 — ns
tWH NFC_WE hold time TH – 1 — ns
tRR Ready to NFC_RE low 4TH + 3TL + 90 — ns
tRP NFC_RE pulse width TL + 1 — ns
tRC Read cycle time TL + TH – 1 — ns
tREH NFC_RE high hold time TH – 1 — ns
tIS Data input setup time 11 — ns
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 41
tCS tCHtWP
tDS tDH
tCLS tCLH
NFC_CLE
NFC_CEn
NFC_WE
NFC_IOn
Figure 13. Command latch cycle timing
tCS tCHtWP
tDS tDH
tALS tALH
address
NFC_ALE
NFC_CEn
NFC_WE
NFC_IOn
Figure 14. Address latch cycle timing
tCS tCH
tWP
tDS tDH
data data data
tWC
tWH
NFC_CEn
NFC_WE
NFC_IOn
Figure 15. Write data latch cycle timing
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
42 Freescale Semiconductor, Inc.
tCH
tRP
data data data
tRC
tREH
tIS
tRR
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
Figure 16. Read data latch cycle timing in non-fast mode
tCH
tRP
data data data
tRC
tREH
tIS
tRR
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
Figure 17. Read data latch cycle timing in fast mode
6.4.4 DDR controller specifications
The following timing numbers must be followed to properly latch or drive data onto the
DDR memory bus. All timing numbers are relative to the DQS byte lanes.
Table 26. DDR controller — AC timing specifications
Symbol Description Min. Max. Unit Notes
Frequency of operation
• DDR1
• DDR2
• LPDDR
83.3
1251
50
150
150
150
MHz
MHz
MHz
2
tDDRCK Clock period
• DDR1
6.6
6.6
12
8
ns
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 43
Table 26. DDR controller — AC timing specifications (continued)
Symbol Description Min. Max. Unit Notes
• DDR2
• LPDDR
6.6 20 ns
VOX-AC DDRCK AC differential cross point voltage
• DDR1
• DDR2
• LPDDR
0.5 x VDD_DDR
– 0.2 V
0.5 x VDD_DDR
– 0.125 V
0.4 x VDD_DDR
0.5 x VDD_DDR
+ 0.2 V
0.5 x VDD_DDR
+ 0.125 V
0.4 x VDD_DDR
V
V
V
tDDRCKH Pulse width high 0.45 0.55 tDDRCK 3
tDDRCKL Pulse width low 0.45 0.55 tDDRCK 3
tCMV Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output setup
0.5 x tDDRCK –
1
— ns 4
tCMH Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output hold
0.5 x tDDRCK –
1
— ns
tDQSS DQS rising edge to CK rising edge -0.2 x tDDRCK 0.2 x tDDRCK ns
tQS Data and data mask output setup (DQ→DQS)
relative to DQS (DDR write mode)
0.25 x tDDRCK –
1
— ns 5, 6
tQH Data and data mask output hold (DQS→DQ)
relative to DQS (DDR write mode)
0.25 x tDDRCK –
1
— ns 7
tDQSQ DQS-DQ skew for DQS and associated DQ
signals
– (0.25 x
tDDRCK – 1)
0.25 x tDDRCK –
1
ns 8
1. This is minimum frequency of operation according to JEDEC DDR2 specification.
2. DDR data rate = 2 x DDR clock frequency
3. Pulse width high plus pulse width low cannot exceed min and max clock period.
4. Command output setup should be 1/2 the memory bus clock (tDDRCK) plus some minor adjustments for process,
temperature, and voltage variations.
5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be
larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0].
6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1];
DDR_DQ[7:0] is relative to DDR_DQS[0]
8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
44 Freescale Semiconductor, Inc.
12345678910
CMD CMD
COLROW
WD1 WD2 WD3 WD4
tDDRCK tDDRCKH tDDRCKL
tCMV tCMH
tQH
tQS
tDQSS
DDR_CLK
DDR__CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
DDR_DQSn
DDR_DMn
DDR_DQn
Figure 18. DDR write timing
123456789101112
RD3RD4
RD1
RD2RD3RD4
tDDRCK tDDRCHH tDDRCKL
CL=3.0
tCMV
CL=2.5
tCMH
DDR_CLK
DDR__CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
DDR_DQS
DDR_DQn
DDR_DQS
DDR_DQn
RD4
123456789101112
RD1 RD2 RD3
CMD
ROW COL
CMD
DQS read preamble
DQS read preamble
RD3
RD4RD1 RD2 RD3
(CL=3.0 )
(CL=2.5 )
Figure 19. DDR read timing
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 45
Figure 20. DDR read timing, DQ vs. DQS
6.4.5 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 27. Flexbus limited voltage range switching specifications
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — FB_CLK MHz
FB1 Clock period 20 — ns
FB2 Address, data, and control output valid — 11.5 ns 1
FB3 Address, data, and control output hold 0.5 — ns 1
FB4 Data and FB_TA input setup 8.5 — ns 2
FB5 Data and FB_TA input hold 0.5 — ns 2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 28. Flexbus full voltage range switching specifications
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V
Frequency of operation — FB_CLK MHz
FB1 Clock period 1/FB_CLK — ns
FB2 Address, data, and control output valid — 13.5 ns 1
FB3 Address, data, and control output hold 0 — ns 1
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
46 Freescale Semiconductor, Inc.
Table 28. Flexbus full voltage range switching specifications (continued)
Num Description Min. Max. Unit Notes
FB4 Data and FB_TA input setup 13.7 — ns 2
FB5 Data and FB_TA input hold 0.5 — ns 2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB1
FB3
FB5
FB4
FB4
FB5
FB2
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
FB_TSIZ[1:0]
Figure 21. FlexBus read timing diagram
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 47
Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB1
FB3
FB4
FB5
FB2
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
FB_TSIZ[1:0]
Figure 22. FlexBus write timing diagram
6.5 Security and integrity modules
6.5.1 DryIce Tamper Electrical Specifications
Information about security-related modules is not included in this document and is
available only after a nondisclosure agreement (NDA) has been signed. To request an
NDA, please contact your local Freescale sales representative.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
48 Freescale Semiconductor, Inc.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 29 and Table 30 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 31 and
Table 32.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 29. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 ×
VREFH
VREFH
V
CADIN Input capacitance • 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF
RADIN Input series
resistance
— 2 5 kΩ
RAS Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 18.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes 5
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 49
Table 29. 16-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000 — 818.330 ksps
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037
—
461.467
ksps
5
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 23. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
50 Freescale Semiconductor, Inc.
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to
0.5
LSB45
INL Integral non-linearity • 12-bit modes
• <12-bit modes
—
—
±1.0
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN = VDDA5
EQQuantization error • 16-bit modes
• ≤13-bit modes
—
—
–1 to 0
—
—
±0.5
LSB4
ENOB Effective number of
bits
16-bit differential mode
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
—
—
—
—
bits
bits
bits
bits
6
SINAD Signal-to-noise plus
distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
—
—
-94
-85
—
—
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
16-bit single-ended mode
82
78
95
90
—
—
dB
dB
7
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 51
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
• Avg = 32
EIL Input leakage error IIn × RAS mV IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 8
VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
12.30
12.00
1 2 3 4 5 6 7 8 9 10 1211
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
Figure 24. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
52 Freescale Semiconductor, Inc.
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
14.00
13.75
13.25
13.00
12.75
12.50
12.00
11.75
11.50
11.25
11.00
1 2 3 4 5 6 7 8 9 10 1211
Averaging of 4 samples
Averaging of 32 samples
13.50
12.25
Figure 25. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 31. 16-bit ADC with PGA operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
VREFPGA PGA ref voltage VREF_OU
T
VREF_OU
T
VREF_OU
T
V2, 3
VADIN Input voltage VSSA — VDDA V
VCM Input Common
Mode range
VSSA — VDDA V
RPGAD Differential input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
—
—
—
128
64
32
—
—
—
kΩ IN+ to IN-4
RAS Analog source
resistance
— 100 — Ω 5
TSADC sampling
time
1.25 — — µs 6
Crate ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
18.484 — 450 Ksps 7
16 bit modes 37.037 — 250 Ksps 8
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 53
Table 31. 16-bit ADC with PGA operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics
Table 32. 16-bit ADC with PGA characteristics
Symbol Description Conditions Min. Typ.1Max. Unit Notes
IDDA_PGA Supply current Low power
(ADC_PGA[PGALPb]=0)
— 420 644 μA 2
IDC_PGA Input DC current A 3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
— 1.54 — μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
— 0.57 — μA
G Gain4• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
0.95
1.9
3.8
7.6
15.2
30.0
58.8
1
2
4
8
16
31.6
63.3
1.05
2.1
4.2
8.4
16.6
33.2
67.8
RAS < 100Ω
BW Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
4
40
kHz
kHz
PSRR Power supply
rejection ratio
Gain=1 — -84 — dB VDDA= 3V
±100mV,
Table continues on the next page...
Peripheral operating requirements and behaviors
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54 Freescale Semiconductor, Inc.
Table 32. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
fVDDA= 50Hz,
60Hz
CMRR Common mode
rejection ratio
• Gain=1
• Gain=64
—
—
-84
-85
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
VOFS Input offset
voltage
• Chopping disabled
(ADC_PGA[PGACHPb]
=1)
• Chopping enabled
(ADC_PGA[PGACHPb]
=0)
—
—
2.4
0.2
—
—
mV
mV
Output offset =
VOFS*(Gain+1)
TGSW Gain switching
settling time
— — 10 µs 5
dG/dT Gain drift over full
temperature range
• Gain=1
• Gain=64
—
—
6
31
10
42
ppm/°C
ppm/°C
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
—
—
0.07
0.14
0.21
0.31
%/V
%/V
VDDA from 1.71
to 3.6V
EIL Input leakage
error
All modes IIn × RAS mV IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF Maximum
differential input
signal swing where VX = VREFPGA × 0.583
V6
SNR Signal-to-noise
ratio
• Gain=1
• Gain=64
80
52
90
66
—
—
dB
dB
16-bit
differential
mode,
Average=32
THD Total harmonic
distortion
• Gain=1
• Gain=64
85
49
100
95
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
SFDR Spurious free
dynamic range
• Gain=1
• Gain=64
85
53
105
88
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
ENOB Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
11.6
8.0
7.2
6.3
12.8
13.4
13.6
9.6
9.6
14.5
—
—
—
—
—
bits
bits
bits
bits
bits
16-bit
differential
mode,fin=100Hz
Table continues on the next page...
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 55
Table 32. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
11.0
7.9
7.3
6.8
6.8
7.5
14.3
13.8
13.1
12.5
11.5
10.6
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
SINAD Signal-to-noise
plus distortion
ratio
See ENOB 6.02 × ENOB + 1.76 dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
Table continues on the next page...
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56 Freescale Semiconductor, Inc.
Table 33. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
00
01
10
HYSTCTR
Setting
0.1
10
11
Vin level (V)
CMP Hystereris (V)
3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.05
0
0.01
0.02
0.03
0.08
0.07
0.06
0.04
Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 57
00
01
10
HYSTCTR
Setting
10
11
0.1 3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.1
0
0.02
0.04
0.06
0.18
0.14
0.12
0.08
0.16
Vin level (V)
CMP Hysteresis (V)
Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
58 Freescale Semiconductor, Inc.
6.6.3.2 12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 150 μA
IDDA_DACH
P
Supply current — high-speed mode — — 700 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ) — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
V/μs
CT Channel to channel cross talk — — -80 dB
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 59
Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 28. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
60 Freescale Semiconductor, Inc.
Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 29. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 36. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 61
Table 37. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915 1.195 1.1977 V 1
Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1
Vout Voltage reference output — user trim 1.193 — 1.197 V 1
Vstep Voltage reference trim step — 0.5 — mV 1
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range)
— — 80 mV 1
Ibg Bandgap only current — — 80 µA 1
Ihp High-power buffer current — — 1 mA 1
ΔVLOAD Load regulation
• current = + 1.0 mA
• current = - 1.0 mA
—
—
2
5
—
—
mV 1, 2
Tstup Buffer startup time — — 100 µs
Vvdrift Voltage drift (Vmax -Vmin across the full voltage
range)
— 2 — mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 38. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 50 °C
Table 39. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vout Voltage reference output with factory trim 1.173 1.225 V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
62 Freescale Semiconductor, Inc.
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 40. MII signal switching specifications
Symbol Description Min. Max. Unit
— RXCLK frequency — 25 MHz
MII1 RXCLK pulse width high 35% 65% RXCLK
period
MII2 RXCLK pulse width low 35% 65% RXCLK
period
MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns
MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns
— TXCLK frequency — 25 MHz
MII5 TXCLK pulse width high 35% 65% TXCLK
period
MII6 TXCLK pulse width low 35% 65% TXCLK
period
MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 — ns
MII8 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns
MII7MII8
Valid data
Valid data
Valid data
MII6 MII5
TXCLK (input)
TXD[n:0]
TXEN
TXER
Figure 30. RMII/MII transmit signal timing diagram
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 63
MII2 MII1
MII4MII3
Valid data
Valid data
Valid data
RXCLK (input)
RXD[n:0]
RXDV
RXER
Figure 31. RMII/MII receive signal timing diagram
6.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 41. RMII signal switching specifications
Num Description Min. Max. Unit
— EXTAL frequency (RMII input clock RMII_CLK) — 50 MHz
RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK
period
RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK
period
RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 — ns
RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 — ns
RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 — ns
RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15 ns
6.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit usb.org.
NOTE
The MCGPLLCLK meets the USB jitter specifications for
certification with the use of an external clock/crystal for both
Device and Host modes.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
64 Freescale Semiconductor, Inc.
The MCGFLLCLK does not meet the USB jitter specifications
for certification.
6.8.3 USB DCD electrical specifications
Table 42. USB0 DCD electrical specifications
Symbol Description Min. Typ. Max. Unit
VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V
VLGC Threshold voltage for logic high 0.8 — 2.0 V
IDP_SRC USB_DP source current 7 10 13 μA
IDM_SINK USB_DM sink current 50 100 150 μA
RDM_DWN D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ
VDAT_REF Data detect voltage 0.25 0.325 0.4 V
6.8.4 USB VREG electrical specifications
Table 43. USB VREG electrical specifications
Symbol Description Min. Typ.1Max. Unit Notes
VREGIN Input supply voltage 2.7 — 5.5 V
IDDon Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
— 125 186 μA
IDDstby Quiescent current — Standby mode, load current
equal zero
— 1.1 10 μA
IDDoff Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
—
—
650
—
—
4
nA
μA
ILOADrun Maximum load current — Run mode — — 120 mA
ILOADstby Maximum load current — Standby mode — — 1 mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
• Standby mode
3
2.1
3.3
2.8
3.6
3.6
V
V
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1 — 3.6 V 2
COUT External output capacitor 1.76 2.2 8.16 μF
ESR External output capacitor equivalent series
resistance
1 — 100 mΩ
ILIM Short circuit current — 290 — mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 65
6.8.5 ULPI timing specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin
Interface. Control and data timing requirements for the ULPI pins are given in the
following table. These timings apply to synchronous mode only. All timings are
measured with respect to the clock as seen at the USB_CLKIN pin.
Table 44. ULPI timing specifications
Num Description Min. Typ. Max. Unit
USB_CLKIN
operating
frequency
— 60 — MHz
USB_CLKIN duty
cycle
— 50 — %
U1 USB_CLKIN clock
period
— 16.67 — ns
U2 Input setup (control
and data)
5 — — ns
U3 Input hold (control
and data)
1 — — ns
U4 Output valid
(control and data)
— — 9.5 ns
U5 Output hold (control
and data)
1 — — ns
U1
U2 U3
U4 U5
USB_CLKIN
ULPI_DIR/ULPI_NXT
(control input)
ULPI_DATAn (input)
ULPI_STP
(control output)
ULPI_DATAn (output)
Figure 32. ULPI timing diagram
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
66 Freescale Semiconductor, Inc.
6.8.6 CAN switching specifications
See General switching specifications.
6.8.7 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 45. Master mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — 30 MHz
DS1 DSPI_SCK output cycle time 2 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
2
— ns 1
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
2
— ns 2
DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns
DS6 DSPI_SCK to DSPI_SOUT invalid −2 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 15 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 33. DSPI classic SPI timing — master mode
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 67
Table 46. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Frequency of operation 15 MHz
DS9 DSPI_SCK input cycle time 4 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 10 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 34. DSPI classic SPI timing — slave mode
6.8.8 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 47. Master mode DSPI timing (full voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V 1
Frequency of operation — 15 MHz
DS1 DSPI_SCK output cycle time 4 x tBUS — ns
Table continues on the next page...
Peripheral operating requirements and behaviors
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68 Freescale Semiconductor, Inc.
Table 47. Master mode DSPI timing (full voltage range) (continued)
Num Description Min. Max. Unit Notes
DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 20.5 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 35. DSPI classic SPI timing — master mode
Table 48. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Frequency of operation — 7.5 MHz
DS9 DSPI_SCK input cycle time 8 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 69
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 36. DSPI classic SPI timing — slave mode
6.8.9 Inter-Integrated Circuit Interface (I2C) timing
Table 49. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 400 1kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Data hold time for I2C bus devices tHD; DAT 023.453040.92µs
Data set-up time tSU; DAT 2505— 1003,6— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb7300 ns
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb6300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using a pin
configured for high drive across the full voltage range and when using the a pin configured for low drive with VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
70 Freescale Semiconductor, Inc.
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
SDA
HD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
SCL
Figure 37. Timing definition for fast and standard mode devices on the I2C bus
6.8.10 UART switching specifications
See General switching specifications.
6.8.11 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 50. SDHC switching specifications over a limited operating voltage
range
Num Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Card input clock
SD1 fpp Clock frequency (low speed) 0 400 kHz
fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz
fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz
fOD Clock frequency (identification mode) 0 400 kHz
SD2 tWL Clock low time 7 — ns
SD3 tWH Clock high time 7 — ns
SD4 tTLH Clock rise time — 3 ns
SD5 tTHL Clock fall time — 3 ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 tOD SDHC output delay (output valid) -5 6.5 ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 tISU SDHC input setup time 5 — ns
SD8 tIH SDHC input hold time 0 — ns
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 71
Table 51. SDHC switching specifications over the full operating voltage
range
Num Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Card input clock
SD1 fpp Clock frequency (low speed) 0 400 kHz
fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz
fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz
fOD Clock frequency (identification mode) 0 400 kHz
SD2 tWL Clock low time 7 — ns
SD3 tWH Clock high time 7 — ns
SD4 tTLH Clock rise time — 3 ns
SD5 tTHL Clock fall time — 3 ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 tOD SDHC output delay (output valid) -5 6.5 ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 tISU SDHC input setup time 5 — ns
SD8 tIH SDHC input hold time 1.3 — ns
SD2SD3 SD1
SD6
SD8
SD7
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 38. SDHC timing
6.8.12 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
Peripheral operating requirements and behaviors
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72 Freescale Semiconductor, Inc.
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.12.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 52. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 2.7 3.6 V
S1 I2S_MCLK cycle time 40 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 15 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15 — ns
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns
Peripheral operating requirements and behaviors
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Freescale Semiconductor, Inc. 73
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 39. I2S/SAI timing — master modes
Table 53. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 2.7 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
• Multiple SAI Synchronous mode
• All other modes
—
—
21
15
ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 25 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
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S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 40. I2S/SAI timing — slave modes
6.8.12.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 54. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 40 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 15 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5 — ns
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns
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S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 41. I2S/SAI timing — master modes
Table 55. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
• Multiple SAI Synchronous mode
• All other modes
—
—
24
20.6
ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 5.8 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 25 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
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76 Freescale Semiconductor, Inc.
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 42. I2S/SAI timing — slave modes
6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 56. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 62.5 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 45 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns
S8 I2S_TX_BCLK to I2S_TXD invalid -1.6 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45 — ns
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 77
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 43. I2S/SAI timing — master modes
Table 57. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
3 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 63 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
78 Freescale Semiconductor, Inc.
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 44. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 58. TSI electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDDTSI Operating voltage 1.71 — 3.6 V
CELE Target electrode capacitance range 1 20 500 pF 1
fREFmax Reference oscillator frequency — 8 15 MHz 2, 3
fELEmax Electrode oscillator frequency — 1 1.8 MHz 2, 4
CREF Internal reference capacitor — 1 — pF
VDELTA Oscillator delta voltage — 600 — mV 2, 5
IREF Reference oscillator current source base current
• 2 μA setting (REFCHRG = 0)
• 32 μA setting (REFCHRG = 15)
—
—
2
36
3
50
μA 2, 6
IELE Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
• 32 μA setting (EXTCHRG = 15)
—
—
2
36
3
50
μA 2, 7
Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8
Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9
Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10
MaxSens Maximum sensitivity 0.008 1.46 — fF/count 11
Res Resolution — — 16 bits
TCon20 Response time @ 20 pF 8 15 25 μs 12
ITSI_RUN Current added in run mode — 55 — μA
ITSI_LP Low power mode current adder — 1.3 2.5 μA 13
Peripheral operating requirements and behaviors
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 79
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. VDD = 3.0 V.
6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN)
The typical value is calculated with the following configuration:
Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF
The minimum value is calculated with the following configuration:
Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
256-pin MAPBGA 98ASA00346D
8 Pinout
8.1 Pins with active pull control after reset
The following pins are actively pulled up or down after reset:
Dimensions
K61 Sub-Family, Rev.6, 09/2015.
80 Freescale Semiconductor, Inc.
Table 59. Pins with active pull control after reset
Pin Active pull direction after reset
PTA0 pulldown
PTA1 pullup
PTA3 pullup
PTA4 pullup
RESET_b pullup
8.2 K61 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E2 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_
CLKOUT
F2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN
F3 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_
b
SDHC0_DCLK
G2 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_
b
SDHC0_CMD SPI1_SOUT
G7 VDD VDD VDD
H7 VDDINT VDDINT VDDINT
H8 VSS VSS VSS
F1 PTF17 DISABLED PTF17 SPI2_SCK FTM0_CH4 UART0_RX
G1 PTF18 DISABLED PTF18 SPI2_SOUT FTM1_CH0 UART0_TX
G3 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
G4 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 FTM3_CH0
H2 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_
b
I2S0_MCLK FTM3_CH1 USB_SOF_
OUT
H1 PTF19 DISABLED PTF19 SPI2_SIN FTM1_CH1 UART5_RX
H5 PTF20 DISABLED PTF20 SPI2_PCS1 FTM2_CH0 UART5_TX
H3 PTE7 DISABLED PTE7 UART3_RTS_
b
I2S0_RXD0 FTM3_CH2
H4 PTE8 ADC2_SE16 ADC2_SE16 PTE8 I2S0_RXD1 UART5_TX I2S0_RX_FS FTM3_CH3
J1 PTE9 ADC2_SE17 ADC2_SE17 PTE9 I2S0_TXD1 UART5_RX I2S0_RX_
BCLK
FTM3_CH4
J2 PTE10 DISABLED PTE10 UART5_CTS_
b
I2S0_TXD0 FTM3_CH5
Pinout
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 81
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
K1 PTE11 ADC3_SE16 ADC3_SE16 PTE11 UART5_RTS_
b
I2S0_TX_FS FTM3_CH6
K3 PTE12 ADC3_SE17 ADC3_SE17 PTE12 I2S0_TX_
BCLK
FTM3_CH7
G8 VDD VDD VDD
H9 VSS VSS VSS
J3 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3
K2 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_
ALT3
L4 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_
b
I2C0_SDA
M3 PTE19 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_RTS_
b
I2C0_SCL CMP3_OUT
L2 VSS VSS VSS
M1 USB0_DP USB0_DP USB0_DP
M2 USB0_DM USB0_DM USB0_DM
L1 VOUT33 VOUT33 VOUT33
L3 VREGIN VREGIN VREGIN
N1 PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
N2 PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
P1 PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
P2 PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
R1 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
R2 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
T1 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
T2 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
N5 VDDA VDDA VDDA
P4 VREFH VREFH VREFH
Pinout
K61 Sub-Family, Rev.6, 09/2015.
82 Freescale Semiconductor, Inc.
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
M4 VREFL VREFL VREFL
N4 VSSA VSSA VSSA
P3 ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
N3 ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
T3 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
R3 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
R4 DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
M5 TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
TAMPER0/
RTC_
WAKEUP_B
L5 TAMPER1 TAMPER1 TAMPER1
L6 TAMPER2 TAMPER2 TAMPER2
R5 TAMPER3 TAMPER3 TAMPER3
P6 TAMPER4 TAMPER4 TAMPER4
R6 TAMPER5 TAMPER5 TAMPER5
T6 XTAL32 XTAL32 XTAL32
T5 EXTAL32 EXTAL32 EXTAL32
P5 VBAT VBAT VBAT
N6 TAMPER6 TAMPER6 TAMPER6
M6 TAMPER7 TAMPER7 TAMPER7
G9 VDD VDD VDD
H10 VDDINT VDDINT VDDINT
J8 VSS VSS VSS
P7 PTE24 ADC0_SE17/
EXTAL1
ADC0_SE17/
EXTAL1
PTE24 CAN1_TX UART4_TX I2S1_TX_FS EWM_OUT_b I2S1_RXD1
R7 PTE25 ADC0_SE18/
XTAL1
ADC0_SE18/
XTAL1
PTE25 CAN1_RX UART4_RX I2S1_TX_
BCLK
EWM_IN I2S1_TXD1
M7 PTE26 ADC3_SE5b ADC3_SE5b PTE26 ENET_1588_
CLKIN
UART4_CTS_
b
I2S1_TXD0 RTC_
CLKOUT
USB_CLKIN
K7 PTE27 ADC3_SE4b ADC3_SE4b PTE27 UART4_RTS_
b
I2S1_MCLK
L7 PTE28 ADC3_SE7a ADC3_SE7a PTE28
Pinout
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 83
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
T7 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
N8 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
T8 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
P8 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_
b
FTM0_CH0 JTAG_TMS/
SWD_DIO
R8 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
T12 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 RMII0_RXER/
MII0_RXER
CMP2_OUT I2S0_TX_
BCLK
JTAG_TRST_
b
G10 VDD VDD VDD
J9 VSS VSS VSS
P9 PTF21 ADC3_SE6b ADC3_SE6b PTF21 FTM2_CH1 UART5_RTS_
b
N9 PTF22 ADC3_SE7b ADC3_SE7b PTF22 I2C0_SCL FTM1_CH0 UART5_CTS_
b
R12 PTA6 ADC3_SE6a ADC3_SE6a PTA6 ULPI_CLK FTM0_CH3 I2S1_RXD0 TRACE_
CLKOUT
P12 PTA7 ADC0_SE10 ADC0_SE10 PTA7 ULPI_DIR FTM0_CH4 I2S1_RX_
BCLK
TRACE_D3
N12 PTA8 ADC0_SE11 ADC0_SE11 PTA8 ULPI_NXT FTM1_CH0 I2S1_RX_FS FTM1_QD_
PHA
TRACE_D2
T13 PTA9 ADC3_SE5a ADC3_SE5a PTA9 ULPI_STP FTM1_CH1 MII0_RXD3 FTM1_QD_
PHB
TRACE_D1
P13 PTA10 ADC3_SE4a ADC3_SE4a PTA10 ULPI_DATA0 FTM2_CH0 MII0_RXD2 FTM2_QD_
PHA
TRACE_D0
R13 PTA11 ADC3_SE15 ADC3_SE15 PTA11 ULPI_DATA1 FTM2_CH1 MII0_RXCLK FTM2_QD_
PHB
M10 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/
MII0_RXD1
I2S0_TXD0 FTM1_QD_
PHA
N10 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 RMII0_RXD0/
MII0_RXD0
I2S0_TX_FS FTM1_QD_
PHB
R11 PTA14 CMP3_IN0 CMP3_IN0 PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_
DV/
MII0_RXDV
I2S0_RX_
BCLK
I2S0_TXD1
P11 PTA15 CMP3_IN1 CMP3_IN1 PTA15 SPI0_SCK UART0_RX RMII0_TXEN/
MII0_TXEN
I2S0_RXD0
T14 VSS VSS VSS
N11 PTA16 CMP3_IN2 CMP3_IN2 PTA16 SPI0_SOUT UART0_CTS_
b/
UART0_COL_
b
RMII0_TXD0/
MII0_TXD0
I2S0_RX_FS I2S0_RXD1
Pinout
K61 Sub-Family, Rev.6, 09/2015.
84 Freescale Semiconductor, Inc.
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
T11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_
b
RMII0_TXD1/
MII0_TXD1
I2S0_MCLK
P10 PTF23 ADC3_SE10 ADC3_SE10 PTF23 I2C0_SDA FTM1_CH1 TRACE_
CLKOUT
R10 PTF24 ADC3_SE11 ADC3_SE11 PTF24 CAN1_RX FTM1_QD_
PHA
TRACE_D3
R9 PTF25 ADC3_SE12 ADC3_SE12 PTF25 CAN1_TX FTM1_QD_
PHB
TRACE_D2
T9 PTF26 ADC3_SE13 ADC3_SE13 PTF26 FTM2_QD_
PHA
TRACE_D1
T10 PTF27 ADC3_SE14 ADC3_SE14 PTF27 FTM2_QD_
PHB
TRACE_D0
J7 VDD VDD VDD
K8 VSS VSS VSS
T15 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0
T16 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_
ALT1
R16 RESET_b RESET_b RESET_b
N13 PTA24 CMP3_IN4 CMP3_IN4 PTA24 ULPI_DATA2 MII0_TXD2 FB_A29
R14 PTA25 CMP3_IN5 CMP3_IN5 PTA25 ULPI_DATA3 MII0_TXCLK FB_A28
M13 PTA26 ADC2_SE15 ADC2_SE15 PTA26 ULPI_DATA4 MII0_TXD3 FB_A27
R15 PTA27 ADC2_SE14 ADC2_SE14 PTA27 ULPI_DATA5 MII0_CRS FB_A26
P14 PTA28 ADC2_SE13 ADC2_SE13 PTA28 ULPI_DATA6 MII0_TXER FB_A25
N14 PTA29 ADC2_SE12 ADC2_SE12 PTA29 ULPI_DATA7 MII0_COL FB_A24
P16 PTF0 ADC2_SE11 ADC2_SE11 PTF0 CAN0_TX FTM3_CH0 I2S1_RXD1
L13 PTF1 ADC2_SE10 ADC2_SE10 PTF1 CAN0_RX FTM3_CH1 I2S1_RX_
BCLK
M12 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 RMII0_MDIO/
MII0_MDIO
FTM1_QD_
PHA
M11 PTB1 ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC/
MII0_MDC
FTM1_QD_
PHB
P15 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_
b
ENET0_1588_
TMR0
FTM0_FLT3
M14 PTB3 ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA UART0_CTS_
b/
UART0_COL_
b
ENET0_1588_
TMR1
FTM0_FLT0
N15 PTB4 ADC1_SE10 ADC1_SE10 PTB4 ENET0_1588_
TMR2
FTM1_FLT0
M15 PTB5 ADC1_SE11 ADC1_SE11 PTB5 ENET0_1588_
TMR3
FTM2_FLT0
Pinout
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 85
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
L14 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23
L15 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22
K14 PTB8 DISABLED PTB8 UART3_RTS_
b
FB_AD21
K15 PTB9 DISABLED PTB9 SPI1_PCS1 UART3_CTS_
b
FB_AD20
J13 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX I2S1_TX_
BCLK
FB_AD19 FTM0_FLT1
J14 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX I2S1_TX_FS FB_AD18 FTM0_FLT2
K9 VSS VSS VSS
J10 VDD VDD VDD
N16 PTF2 ADC2_SE6a ADC2_SE6a PTF2 I2C1_SCL FTM3_CH2 I2S1_RX_FS
M16 PTF3 ADC2_SE7a ADC2_SE7a PTF3 I2C1_SDA FTM3_CH3 I2S1_RXD0
L16 PTF4 ADC2_SE4b ADC2_SE4b PTF4 FTM3_CH4 I2S1_TXD0
J15 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX I2S1_TXD0 FB_AD17 EWM_IN
H13 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX I2S1_TXD1 FB_AD16 EWM_OUT_b
H14 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_
BCLK
FB_AD15 FTM2_QD_
PHA
K16 PTF5 ADC2_SE5b ADC2_SE5b PTF5 FTM3_CH5 I2S1_TX_FS
J16 PTF6 ADC2_SE6b ADC2_SE6b PTF6 FTM3_CH6 I2S1_TX_
BCLK
H15 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_
PHB
G13 PTB20 ADC2_SE4a ADC2_SE4a PTB20 SPI2_PCS0 FB_AD31/
NFC_DATA15
CMP0_OUT
G14 PTB21 ADC2_SE5a ADC2_SE5a PTB21 SPI2_SCK FB_AD30/
NFC_DATA14
CMP1_OUT
G15 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29/
NFC_DATA13
CMP2_OUT
H16 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28/
NFC_DATA12
CMP3_OUT
G16 PTC0 ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXTRG FB_AD14/
NFC_DATA11
I2S0_TXD1
F13 PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RTS_
b
FTM0_CH0 FB_AD13/
NFC_DATA10
I2S0_TXD0
F14 PTC2 ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CTS_
b
FTM0_CH1 FB_AD12/
NFC_DATA9
I2S0_TX_FS
E13 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_
BCLK
F15 PTF7 ADC2_SE7b ADC2_SE7b PTF7 FTM3_CH7 UART3_RX I2S1_TXD1
L9 VSS VSS VSS
K10 VDD VDD VDD
F16 PTF8 DISABLED PTF8 FTM3_FLT0 UART3_TX I2S1_MCLK
Pinout
K61 Sub-Family, Rev.6, 09/2015.
86 Freescale Semiconductor, Inc.
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E14 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11/
NFC_DATA8
CMP1_OUT I2S1_TX_
BCLK
E15 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_RXD0 FB_AD10/
NFC_DATA7
CMP0_OUT I2S1_TX_FS
F12 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT PDB0_EXTRG I2S0_RX_
BCLK
FB_AD9/
NFC_DATA6
I2S0_MCLK
G12 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_
OUT
I2S0_RX_FS FB_AD8/
NFC_DATA5
H12 PTC8 ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
PTC8 FTM3_CH4 I2S0_MCLK FB_AD7/
NFC_DATA4
F11 PTC9 ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
PTC9 FTM3_CH5 I2S0_RX_
BCLK
FB_AD6/
NFC_DATA3
FTM2_FLT0
G11 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL FTM3_CH6 I2S0_RX_FS FB_AD5/
NFC_DATA2
I2S1_MCLK
H11 PTC11/
LLWU_P11
ADC1_SE7b ADC1_SE7b PTC11/
LLWU_P11
I2C1_SDA FTM3_CH7 I2S0_RXD1 FB_RW_b/
NFC_WE
J12 PTC12 DISABLED PTC12 UART4_RTS_
b
FB_AD27 FTM3_FLT0
K13 PTC13 DISABLED PTC13 UART4_CTS_
b
FB_AD26
J11 PTC14 DISABLED PTC14 UART4_RX FB_AD25
K12 PTF9 CMP2_IN4 CMP2_IN4 PTF9 UART3_RTS_
b
L12 PTF10 CMP2_IN5 CMP2_IN5 PTF10 UART3_CTS_
b
F10 PTC15 DISABLED PTC15 UART4_TX FB_AD24
N7 VSS VSS VSS
L10 VDD VDD VDD
K11 PTF11 DISABLED PTF11 UART2_RTS_
b
L11 PTF12 DISABLED PTF12 UART2_CTS_
b
F9 PTC16 DISABLED PTC16 CAN1_RX UART3_RX ENET0_1588_
TMR0
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_
b
NFC_RB
E9 PTC17 DISABLED PTC17 CAN1_TX UART3_TX ENET0_1588_
TMR1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_
b
NFC_CE0_b
M9 PTC18 DISABLED PTC18 UART3_RTS_
b
ENET0_1588_
TMR2
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
NFC_CE1_b
M8 PTC19 DISABLED PTC19 UART3_CTS_
b
ENET0_1588_
TMR3
FB_CS3_b/
FB_BE7_0_b
FB_TA_b
L8 PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0 UART2_RTS_
b
FTM3_CH0 FB_ALE/
FB_CS1_b/
FB_TS_b
I2S1_RXD1
Pinout
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 87
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
F8 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_
b
FTM3_CH1 FB_CS0_b I2S1_RXD0
K6 PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOUT UART2_RX FTM3_CH2 FB_AD4 I2S1_RX_FS
J6 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FTM3_CH3 FB_AD3 I2S1_RX_
BCLK
K5 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_
b
FTM0_CH4 FB_AD2/
NFC_DATA1
EWM_IN
J5 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5 FB_AD1/
NFC_DATA0
EWM_OUT_b
K4 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
H6 PTF13 DISABLED PTF13 UART2_RX
G6 PTF14 DISABLED PTF14 UART2_TX
T4 VSS VSS VSS
E7 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
J4 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/
NFC_CLE
F7 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17/
NFC_ALE
E6 PTD10 DISABLED PTD10 UART5_RTS_
b
FB_A18/
NFC_RE
G5 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_
b
SDHC0_
CLKIN
FB_A19
F5 PTD12 DISABLED PTD12 SPI2_SCK FTM3_FLT0 SDHC0_D4 FB_A20
F4 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21
E5 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22
E4 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23
F6 PTF15 DISABLED PTF15 UART0_RTS_
b
E1 PTF16 DISABLED PTF16 SPI2_PCS0 FTM0_CH3 UART0_CTS_
b/
UART0_COL_
b
B1 DDR_VDD DDR_VDD DDR_VDD
A1 DDR_VSS DDR_VSS DDR_VSS
D3 DDR_DQS1 DISABLED DDR_DQS1
D1 DDR_DQ8 DISABLED DDR_DQ8
C1 DDR_DQ9 DISABLED DDR_DQ9
B5 DDR_VDD DDR_VDD DDR_VDD
A5 DDR_VSS DDR_VSS DDR_VSS
D5 DDR_VSS DDR_VSS DDR_VSS
C2 DDR_DQ10 DISABLED DDR_DQ10
Pinout
K61 Sub-Family, Rev.6, 09/2015.
88 Freescale Semiconductor, Inc.
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
B2 DDR_DQ11 DISABLED DDR_DQ11
C3 DDR_DQ12 DISABLED DDR_DQ12
B8 DDR_VDD DDR_VDD DDR_VDD
A12 DDR_VSS DDR_VSS DDR_VSS
C4 DDR_DQ13 DISABLED DDR_DQ13
B3 DDR_DQ14 DISABLED DDR_DQ14
A2 DDR_DQ15 DISABLED DDR_DQ15
A3 DDR_DM1 DISABLED DDR_DM1
E8 DDR_VSS DDR_VSS DDR_VSS
B12 DDR_VDD DDR_VDD DDR_VDD
A16 DDR_VSS DDR_VSS DDR_VSS
C6 DDR_VREF DDR_VREF DDR_VREF
C5 DDR_DQ0 DISABLED DDR_DQ0
B4 DDR_DQ1 DISABLED DDR_DQ1
A4 DDR_DQ2 DISABLED DDR_DQ2
C16 DDR_VDD DDR_VDD DDR_VDD
C7 DDR_VSS DDR_VSS DDR_VSS
B6 DDR_DQ3 DISABLED DDR_DQ3
D6 DDR_DQ4 DISABLED DDR_DQ4
A6 DDR_DQ5 DISABLED DDR_DQ5
A7 DDR_ODT DISABLED DDR_ODT
E11 DDR_VSS DDR_VSS DDR_VSS
D2 DDR_VDD DDR_VDD DDR_VDD
C9 DDR_VSS DDR_VSS DDR_VSS
B7 DDR_DQ6 DISABLED DDR_DQ6
A8 DDR_DQ7 DISABLED DDR_DQ7
C8 DDR_DQS0 DISABLED DDR_DQS0
D9 DDR_DM0 DISABLED DDR_DM0
D4 DDR_VDD DDR_VDD DDR_VDD
C14 DDR_VSS DDR_VSS DDR_VSS
A9 DDR_BA0 DISABLED DDR_BA0
B10 DDR_BA1 DISABLED DDR_BA1
B9 DDR_BA2 DISABLED DDR_BA2
A10 DDR_CKB DISABLED DDR_CKB
A11 DDR_CK DISABLED DDR_CK
D7 DDR_VDD DDR_VDD DDR_VDD
D8 DDR_VSS DDR_VSS DDR_VSS
D10 DDR_A0 DISABLED DDR_A0
C11 DDR_A1 DISABLED DDR_A1
B11 DDR_A2 DISABLED DDR_A2
Pinout
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 89
256
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
C12 DDR_A3 DISABLED DDR_A3
E10 DDR_VDD DDR_VDD DDR_VDD
D12 DDR_VSS DDR_VSS DDR_VSS
C10 DDR_A4 DISABLED DDR_A4
A13 DDR_A5 DISABLED DDR_A5
A14 DDR_A6 DISABLED DDR_A6
D11 DDR_A7 DISABLED DDR_A7
A15 DDR_A8 DISABLED DDR_A8
E12 DDR_VDD DDR_VDD DDR_VDD
E3 DDR_VSS DDR_VSS DDR_VSS
B16 DDR_CKE DISABLED DDR_CKE
B15 DDR_A9 DISABLED DDR_A9
B13 DDR_A10 DISABLED DDR_A10
B14 DDR_A11 DISABLED DDR_A11
C15 DDR_A12 DISABLED DDR_A12
D16 DDR_A13 DISABLED DDR_A13
D15 DDR_A14 DISABLED DDR_A14
E16 DDR_RAS_B DISABLED DDR_RAS_B
C13 DDR_CAS_B DISABLED DDR_CAS_B
D14 DDR_CS_B DISABLED DDR_CS_B
D13 DDR_WE_B DISABLED DDR_WE_B
8.3 K61 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
K61 Sub-Family, Rev.6, 09/2015.
90 Freescale Semiconductor, Inc.
1
A DDR_VSS
B DDR_VDD
C DDR_DQ9
D DDR_DQ8
E PTF16
F PTF17
G PTF18
H PTF19
J PTE9
K PTE11
L VOUT33
M USB0_DP
N
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
P
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
RPGA0_DP/
ADC0_DP0/
ADC1_DP3
1
TPGA1_DP/
ADC1_DP0/
ADC0_DP3
2
DDR_DQ15
DDR_DQ11
DDR_DQ10
DDR_VDD
PTE0
PTE1/
LLWU_P0
PTE3
PTE6
PTE10
PTE17
VSS
USB0_DM
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA0_DM/
ADC0_DM0/
ADC1_DM3
2
PGA1_DM/
ADC1_DM0/
ADC0_DM3
3
DDR_DM1
DDR_DQ14
DDR_DQ12
DDR_DQS1
DDR_VSS
PTE2/
LLWU_P1
PTE4/
LLWU_P2
PTE7
PTE16
PTE12
VREGIN
PTE19
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
4
DDR_DQ2
DDR_DQ1
DDR_DQ13
DDR_VDD
PTD15
PTD13
PTE5
PTE8
PTD8
PTD6/
LLWU_P15
PTE18
VREFL
VSSA
VREFH
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
4
VSS
5
DDR_VSS
DDR_VDD
DDR_DQ0
DDR_VSS
PTD14
PTD12
PTD11
PTF20
PTD5
PTD4/
LLWU_P14
TAMPER1
TAMPER0/
RTC_
WAKEUP_B
VDDA
VBAT
TAMPER3
5
EXTAL32
6
DDR_DQ5
DDR_DQ3
DDR_VREF
DDR_DQ4
PTD10
PTF15
PTF14
PTF13
PTD3
PTD2/
LLWU_P13
TAMPER2
TAMPER7
TAMPER6
TAMPER4
TAMPER5
6
XTAL32
7
DDR_ODT
DDR_DQ6
DDR_VSS
DDR_VDD
PTD7
PTD9
VDD
VDDINT
VDD
PTE27
PTE28
PTE26
VSS
PTE24
PTE25
7
PTA0
8
DDR_DQ7
DDR_VDD
DDR_DQS0
DDR_VSS
DDR_VSS
PTD1
VDD
VSS
VSS
VSS
PTD0/
LLWU_P12
PTC19
PTA1
PTA3
PTA4/
LLWU_P3
8
PTA2
9
DDR_BA0
DDR_BA2
DDR_VSS
DDR_DM0
PTC17
PTC16
VDD
VSS
VSS
VSS
VSS
PTC18
PTF22
PTF21
PTF25
9
PTF26
10
DDR_CKB
DDR_BA1
DDR_A4
DDR_A0
DDR_VDD
PTC15
VDD
VDDINT
VDD
VDD
VDD
PTA12
PTA13/
LLWU_P4
PTF23
PTF24
10
PTF27
11
DDR_CK
DDR_A2
DDR_A1
DDR_A7
DDR_VSS
PTC9
PTC10
PTC11/
LLWU_P11
PTC14
PTF11
PTF12
PTB1
PTA16
PTA15
PTA14
11
PTA17
12
DDR_VSS
DDR_VDD
DDR_A3
DDR_VSS
DDR_VDD
PTC6/
LLWU_P10
PTC7
PTC8
PTC12
PTF9
PTF10
PTB0/
LLWU_P5
PTA8
PTA7
PTA6
12
PTA5
13
DDR_A5
DDR_A10
DDR_CAS_B
DDR_WE_B
PTC3/
LLWU_P7
PTC1/
LLWU_P6
PTB20
PTB17
PTB10
PTC13
PTF1
PTA26
PTA24
PTA10
PTA11
13
PTA9
14
DDR_A6
DDR_A11
DDR_VSS
DDR_CS_B
PTC4/
LLWU_P8
PTC2
PTB21
PTB18
PTB11
PTB8
PTB6
PTB3
PTA29
PTA28
PTA25
14
VSS
15
DDR_A8
DDR_A9
DDR_A12
DDR_A14
PTC5/
LLWU_P9
PTF7
PTB22
PTB19
PTB16
PTB9
PTB7
PTB5
PTB4
PTB2
PTA27
15
PTA18
16
ADDR_VSS
BDDR_CKE
CDDR_VDD
DDDR_A13
E
DDR_
RAS_B
FPTF8
GPTC0
HPTB23
JPTF6
KPTF5
LPTF4
MPTF3
NPTF2
PPTF0
RRESET_b
16
TPTA19
Figure 45. K61 256 MAPBGA Pinout Diagram
9Revision History
The following table provides a revision history for this document.
Revision History
K61 Sub-Family, Rev.6, 09/2015.
Freescale Semiconductor, Inc. 91
Table 60. Revision History
Rev. No. Date Substantial Changes
3 3/2012 Initial public release
4 10/2012 Replaced TBDs throughout.
5 10/2013 Changes for 4N96B mask set:
• Min VDD operating requirement specification updated to support operation down to
1.71V.
New specifications:
• Updated Vdd_ddr min specification.
• Added Vodpu specification.
• Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specfications. They have been
replaced by new Iina, Iind, and Zind specifications.
• Fpll_ref_acc specification has been added.
• I2C module was previously covered by the general switching specifications. To provide
more detail on I2C operation a dedicated Inter-Integrated Circuit Interface (I2C) timing
section has been added.
Modified specifications:
• Vref_ddr max spec has been updated.
• Tpor spec has been split into two specifications based on VDD slew rate.
• Trd1allx and Trd1alln max have been updated.
• 16-bit ADC Temp sensor slope and Temp sensor voltage (Vtemp25) have been
modified. The typical values that were listed previously have been updated, and min
and max specifications have been added.
Corrections:
• Some versions of the datasheets listed incorrect clock mode information in the
"Diagram: Typical IDD_RUN operating behavior section." These errors have been
corrected.
• Fintf_ft specification was previously shown as a max value. It has been corrected to be
shown as a typical value as originally intended.
• Corrected DDR write and read timing diagrams to show the correct location of the Tcmv
specification.
• SDHC peripheral 50MHz high speed mode options were left out of the last datasheet.
These have been added to the SDHC specifications section.
609/2015 • Updated Power Sequencing section
• Added footnote to ambient temperature specification of Thermal Operating
requirements
• Updated the data and DQS waveforms in DDR read timing diagram
• Removed "USB HS/LS/FS on-the-go controller with on-chip high speed transceiver"
from features section
• Updated Terminology and guidelines section
• Updated the footnotes and the values of Power consumption operating behaviors table
• Added Notes in USB electrical specification section
• Updated I2C timing table
Revision History
K61 Sub-Family, Rev.6, 09/2015.
92 Freescale Semiconductor, Inc.
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Document Number K61P256M120SF3
Revision 6, 09/2015
