Data Sheet VT6212 / VT6212L PCI USB 2.0 Controller Revision 1.10 March 16, 2007 VIA TECHNOLOGIES, INC. Copyright Notice: Copyright (c) 2002-2007 VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users. Trademark Notices: is a registered trademark of VIA Technologies, Incorporated. VT6202, VT6212 and VT6212L may only be used to identify products of VIA Technologies, Incorporated. Windows XPTM, Windows 2000TM, Windows METM and Windows 98SETM are registered trademarks of Microsoft Corporation. PCITM is a registered trademark of the PCI Special Interest Group. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. Offices: VIA Technologies Incorporated Taiwan Office: st 1 Floor, No. 531 Chung-Cheng Road, Hsin-Tien Taipei, Taiwan ROC Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453 Home page: http ://www.via.com.tw VIA Technologies Incorporated USA Office: 940 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 or (510) 687-4654 Home Page: http ://www.viatech.com VT6212 / VT6212L PCI USB2.0 Controller REVISION HISTORY Document Release 1.0 1.01 Date 6/5/03 2/27/04 1.02 1.03 1.04 10/21/04 12/21/04 4/19/05 1.05 11/16/05 1.06 1.07 12/7/05 8/18/06 1.08 1.09 9/21/06 11/17/06 1.10 3/16/07 Revision 1.10, March 16, 2007 Revision Initial external release Updated cover page Updated copyright page Changed pins 104, 103, 57, 58, 59, 97 to NC Updated pin-out diagram Updated pin list Updated pin descriptions Added figure 4, lead-free mechanical specification diagram Specified PCI 2.2 bus support Registers updated f0rx41[4], f0rx42[1-0], f0rx48[5], f0rx4B[0], f2rx41[4], f2rx48[5], f2rx49[7-5], f2rx4A, f2rx4B[5, 3-0], f2rx51 Modified legal page Changed pins 60, 63, 64 and 102 to NC Updated pin-out diagram Updated pin list Updated pin descriptions Updated pin information Updated Figure 3, Figure 4, Figure 5 and Figure 6 in package mechanical specifications Updated legal page Updated Revision ID Code Updated Revision ID Code Modified power specifications in Table 5 Updated mechanical specification diagram -i- Initials EY JW JW JW JW SV SV TL TL TL JY Revision History VT6212 / VT6212L PCI USB2.0 Controller TABLE OF CONTENTS REVISION HISTORY .......................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES .........................................................................................................................................................................III LIST OF TABLES ...........................................................................................................................................................................IV PRODUCT FEATURES ................................................................................................................................................................... 1 OVERVIEW....................................................................................................................................................................................... 2 PINOUTS............................................................................................................................................................................................ 3 PIN DIAGRAM ................................................................................................................................................................................ 3 PIN LIST ......................................................................................................................................................................................... 4 PIN DESCRIPTIONS......................................................................................................................................................................... 5 REGISTERS....................................................................................................................................................................................... 8 REGISTER OVERVIEW ................................................................................................................................................................... 8 REGISTER SUMMARY TABLES ....................................................................................................................................................... 8 Function 0-1 UHCI Universal Host Controller Interface ................................................................................................... 8 Function 0-1 UHCI PCI Configuration Header ....................................................................................................................................... 8 Function 0-1 UHCI Device Specific Registers........................................................................................................................................ 8 Function 0-1 USB UHCI I/O Registers................................................................................................................................. 8 Function 2 EHCI Enhanced Host Controller Interface ...................................................................................................... 9 Function 2 EHCI PCI Configuration Header........................................................................................................................................... 9 Function 2 EHCI Device Specific Registers ........................................................................................................................................... 9 Function 2 USB EHCI Memory-Mapped I/O Registers ................................................................................................... 10 EHCI Memory Mapped I/O Capability Registers ................................................................................................................................. 10 EHCI Memory Mapped I/O Operational Registers ............................................................................................................................... 10 REGISTER DESCRIPTIONS............................................................................................................................................................ 11 Function 0-1 UHCI Universal Host Controller Interface ................................................................................................. 11 Function 0-1 Configuration Space Header ............................................................................................................................................ 11 Function 0-1 Device Specific Registers ................................................................................................................................................ 12 Function 2 EHCI Enhanced Host Controller Interface .................................................................................................... 14 Function 2 Configuration Space Header................................................................................................................................................ 14 Function 2 Device-Specific Registers ................................................................................................................................................... 15 Function 2 EHCI Compliant USB Memory-Mapped I/O Registers ...................................................................................................... 16 EHCI Capability Registers .................................................................................................................................................................... 16 EHCI Operational Registers .................................................................................................................................................................. 16 ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 17 PACKAGE MECHANICAL SPECIFICATIONS........................................................................................................................ 19 Revision 1.10, March 16, 2007 -ii- Table of Contents VT6212 / VT6212L PCI USB2.0 Controller LIST OF FIGURES FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. VT6212 / VT6212L CHIP BLOCK DIAGRAM........................................................................................................ 2 VT6212 (PQFP) / VT6212L (LQFP) PIN DIAGRAM (TOP VIEW) ...................................................................... 3 VT6212 MECHANICAL SPECIFICATIONS - 128 PIN PQFP PACKAGE ...................................................... 19 VT6212 LEAD-FREE MECHANICAL SPECIFICATIONS - 128 PIN PQFP PACKAGE .............................. 20 VT6212L MECHANICAL SPECIFICATIONS - 128 PIN LQFP PACKAGE ................................................... 21 VT6212L LEAD-FREE MECHANICAL SPECIFICATIONS - 128 PIN LQFP PACKAGE ........................... 22 Revision 1.10, March 16, 2007 -iii- List of Figures VT6212 / VT6212L PCI USB2.0 Controller LIST OF TABLES TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. VT6212 / VT6212L PIN LIST (ALPHABETICAL ORDER) .................................................................................... 4 VT6212 / VT6212L PIN DESCRIPTIONS .................................................................................................................. 5 ABSOLUTE MAXIMUM RATINGS......................................................................................................................... 17 DC CHARACTERISTICS .......................................................................................................................................... 17 POWER SPECIFICATIONS ...................................................................................................................................... 18 Revision 1.10, March 16, 2007 -iv- List of Tables VT6212 / VT6212L PCI USB2.0 Controller VT6212 / VT6212L PCI USB 2.0 4-Port Host Controller USB 2.0 UHCI / EHCI Host Controller for the PCI 2.2 Bus PRODUCT FEATURES * USB 2.0 - - - - - - - - - Compliant with Universal Serial Bus Specification Revision 2.0 Compliant with Enhanced Host Controller Interface Specification Revision 1.0 Compliant with Universal Host Controller Interface Specification Revision 1.1 PCI multi-function device consists of two UHCI Host Controllers for full/low-speed signaling and one EHCI Host Controller core for high-speed signaling 4 downstream facing ports in the root hub with integrated physical layer transceivers shared by UHCI and EHCI Host Controllers Supports PCI-Bus Power Management Interface Specification release 1.1 Legacy support for all downstream facing ports 4 DMA engines with pipelined control for USB data transfer bandwidth improvement Dynamic clock stop control for power consumption reduction * Serial EEPROM Support for Boot Register Update * Cardbus Mode Support * 2.5V Power Supply with 5V Tolerant Inputs * 0.22m, Low Power CMOS Process * 128-Pin PQFP (VT6212) and 128-Pin LQFP (VT6212L) Packages Available * Schematics and PCB Reference Designs Available * System Clock Using 24 MHz Crystal * Support for PCI Mobile Design Guide Revision 1.10, March 16, 2007 -1- Product Features VT6212 / VT6212L PCI USB2.0 Controller OVERVIEW The VT6212 / VT6212L USB 2.0 UHCI and EHCI Host Controller for the PCI 2.2 Bus provides higher bandwidth (480 Mbps) and is backward compatible with USB 1.1. It implements Universal Serial Bus Specification Revision 2.0 and is compliant with UHCI 1.1 and EHCI 1.0 with a 32-bit PCI host bus interface. The VT6212 / VT6212L adopts 4 DMA engines with pipelined control for USB data transfer bandwidth improvement and dynamic clock stop control for power consumption reduction. The VT6212 / VT6212L supports 4 downstream facing ports with 1.5 (low-speed), 12 (full-speed) and 480 (high-speed) Mbps transaction capability. The Root Hub is integrated with physical-layer transceivers shared by UHCI (for full/low-speed) and EHCI (for high-speed) Host Controllers. The VT6212 / VT6212L also supports PCI-Bus Power Management Interface Specification 1.1 and has legacy support for all downstream facing ports. The VT6212 / VT6212L is ready to provide a PCI 4-port USB2.0 peripheral-interface to satisfy the needs of desktops, mobile systems, and other host platforms. Support for the VT6212 / VT6212L is built into Microsoft Windows XP and Windows 2000. Win98SE and WinME drivers are provided by VIA. PCI Bus INTA# SMI# INTB# PME# INTC# WakeUp_Event WakeUp_Event WakeUp_Event PCI Bus Interface UHCI Host Controller #2 EHCI Host Controller Arbiter UHCI Host Controller #1 Root Hub USB Port 1 USB Port 2 PHY USB Port 3 USB Port 4 Figure 1. VT6212 / VT6212L Chip Block Diagram Revision 1.10, March 16, 2007 -2- Overview AD22 AD21 CBE3# VCC25 GND IDSEL AD20 AD19 GND VCC33 AD18 AD17 AD16 AD15 AD14 AD13 GND VCC33 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# GND VCC33 PAR CBE1# AD12 AD11 AD10 AD9 GND VCC33 VCC25 GND AD8 AD7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 IO IO IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 102 - 101 - 100 IO 99 IO 98 - 97 - 96 O 95 I 94 - 93 - 92 - 91 - 90 - 89 A 88 - 87 IO 86 IO 85 - 84 - 83 IO 82 IO 81 - 80 - 79 IO 78 IO 77 - 76 - 75 IO 74 IO 73 - 72 I 71 - 70 - 69 I 68 O 67 I 66 I 65 TEST2 VCC33 GND TEST3 WAKEUP_EN NC VCCOSC XOUT XIN GNDOSC GNDPLL VCCPLL GNDPLLA VCCPLLA REXT GNDUSB1 USBP1+ USBP1VCCUSB1 GNDUSB2 USBP2+ USBP2VCCUSB2 GNDUSB3 USBP3+ USBP3VCCUSB3 GNDUSB4 USBP4+ USBP4VCCUSB4 USBOC1# VCCSUS GNDSUS USBOC2# PME# USBOC3# USBOC4# VT6212 / VT6212L PCI USB2.0 Controller PINOUTS Pin Diagram NC NC INTA# INTB# INTC# GND PCICLK VCC33 PCIRST# GNT# REQ# GND VCC25 AD31 AD30 AD29 GND VCC33 AD28 AD27 AD26 AD25 AD24 AD23 GND VCC33 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 O O O I I I O IO IO IO IO IO IO IO IO IO - Revision 1.10, March 16, 2007 VT6212 PCI 4-Port USB2 Host Controller PQFP-128 -3I I O O O O I IO IO IO IO IO IO IO IO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 TESTMODE ATPG_EN VCC33 GND SMI# NC NC NC EECS EECK GND VCC25 VCC33 GND EEDI EEDO AD0 AD1 AD2 AD3 VCC33 GND AD4 CBE0# AD5 AD6 Figure 2. VT6212 (PQFP) / VT6212L (LQFP) Pin Diagram (Top View) Pin Diagram VT6212 / VT6212L PCI USB2.0 Controller Pin List Table 1. VT6212 / VT6212L Pin List (Alphabetical Order) Pin 48 47 46 45 42 40 39 38 37 32 31 30 29 16 15 14 13 12 11 8 7 2 1 126 125 124 123 122 121 118 117 116 Typ PU Pin Name IO AD0 IO AD1 IO AD2 IO AD3 IO AD4 IO AD5 IO AD6 IO AD7 IO AD8 IO AD9 IO AD10 IO AD11 IO AD12 IO AD13 IO AD14 IO AD15 IO AD16 IO AD17 IO AD18 IO AD19 IO AD20 IO AD21 IO AD22 IO AD23 IO AD24 IO AD25 IO AD26 IO AD27 IO AD28 IO AD29 IO AD30 IO AD31 Revision 1.10, March 16, 2007 Pin 63 41 28 19 3 23 55 56 50 49 104 103 58 97 57 59 20 5 9 17 25 33 36 43 51 54 61 100 108 114 119 127 Typ I IO IO IO IO IO O O O I IO P P P P P P P P P P P P P P P PU Pin Name PD ATPG_EN CBE0# CBE1# CBE2# CBE3# DEVSEL# PD EECK EECS EEDI PU EEDO NC NC NC NC NC NC FRAME# GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin 93 92 90 69 87 83 79 75 112 6 105 106 107 21 27 109 111 67 113 88 60 24 102 99 98 64 22 71 68 66 65 85 -4- Typ P P P P P P P P I I O O O IO IO P I O O A O IO IO IO IO I IO I I I I IO PU Pin Name GNDOSC GNDPLL GNDPLLA GNDSUS GNDUSB1 GNDUSB2 GNDUSB3 GNDUSB4 GNT# IDSEL INTA# INTB# INTC# IRDY# PAR PCICLK PCIRST# PME# REQ# REXT SMI# STOP# TEST2 TEST3 WAKEUP_EN PD TESTMODE TRDY# PU USBOC1# PU USBOC2# PU USBOC3# PU USBOC4# USBP1- Pin 86 81 82 77 78 73 74 4 35 53 115 10 18 26 34 44 52 62 101 110 120 128 96 91 89 70 84 80 76 72 94 95 Typ PU Pin Name IO USBP1+ IO USBP2- IO USBP2+ IO USBP3- IO USBP3+ IO USBP4- IO USBP4+ P VCC25 P VCC25 P VCC25 P VCC25 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCC33 P VCCOSC P VCCPLL P VCCPLLA P VCCSUS P VCCUSB1 P VCCUSB2 P VCCUSB3 P VCCUSB4 I XIN O XOUT Alphabetical-Order Pin List VT6212 / VT6212L PCI USB2.0 Controller Pin Descriptions Table 2. VT6212 / VT6212L Pin Descriptions PCI Interface Signal Name Pin # I/O Power (see pin list) 3, 19, 28, 41 IO PAR 27 IO IDSEL 6 I DEVSEL# 23 IO FRAME# 20 IO STOP# 24 IO IRDY# TRDY# PCIRST# 21 22 111 IO IO I PCICLK INTA# INTB# INTC# REQ# GNT# 109 105 106 107 113 112 I O O O O I VCC33 Address and Data. Addresses are passed during the first clock cycle. Data is passed in subsequent cycles. VCC33 Command / Byte Enables. The command for the current cycle is driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are then driven on following clocks. VCC33 Parity. A single parity bit is provided over AD[31:0] and CBE[3:0]# to check that the data has been transferred accurately.. VCC33 Initialization Device Select. Used as a chip select during configuration read and write cycles. VCC33 Device Select. As an output, this signal is asserted to claim PCI transactions through positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT6212-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle. VCC33 Cycle Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. VCC33 PCI Stop. Asserted by the target (the VT6212 / VT6212L chip) to request the master (PCI device) to stop the current transaction. VCC33 Initiator Ready. Asserted when the initiator is ready for data transfer. VCC33 Target Ready. Asserted when the target is ready for data transfer. VCC33 PCI Reset. When detected low, an internal hardware reset is performed. PCIRST# assertion or deassertion may be asynchronous to PCICLK, however, it is recommended that deassertion be synchronous to guarantee a clean and bounce free edge. VCC33 PCI Clock. 33 MHz. Used to clock all PCI bus transactions. VCC33 PCI Interrupt A. Asynchronous signal used to request an interrupt. VCC33 PCI Interrupt B. Asynchronous signal used to request an interrupt. VCC33 PCI Interrupt C. Asynchronous signal used to request an interrupt. VCC33 PCI Bus Request. Asserted by the VT6212 / VT6212L to request bus use. VCC33 PCI Bus Grant. Asserted by the bus arbiter to grant permission to the VT6212 / VT6212L for access to the PCI bus for bus master operations. AD[31:0] CBE[3 :0]# IO Signal Description Serial EEPROM Interface Signal Name EECS EECK EEDI EEDO Pin # I/O Power Signal Description 56 55 50 49 O O O I VCC33 VCC33 VCC33 VCC33 EEPROM Chip Select. Connect to EEPROM EECS pin. EEPROM Clock. Connect to EEPROM EECK pin. EEPROM Data In. Connect to EEPROM EEDI pin. EEPROM Data Output. Connect to EEPROM EEDO pin. Chipset South Bridge Interface Signal Name SMI# PME# Pin # I/O Power 60 67 O O VCC33 VCCSUS Revision 1.10, March 16, 2007 Signal Description System Management Interrupt. Power Management Event Interrupt. -5- Pin Descriptions VT6212 / VT6212L PCI USB2.0 Controller No Connection Signal Name NC Pin # I/O 57-59, 97, 103-104 - Power Signal Description No connection. USB Ports Signal Name USBP1+ USBP1- USBP2+ USBP2- USBP3+ USBP3- USBP4+ USBP4- USBOC1# Pin # I/O Power 86 85 82 81 78 77 74 73 71 IO IO IO IO IO IO IO IO I VCCUSB1 VCCUSB1 VCCUSB2 VCCUSB2 VCCUSB3 VCCUSB3 VCCUSB4 VCCUSB4 VCCSUS Signal Description USB Port 1 Differential Data Plus. Asserted high (> 2.8V) USB Port 1 Differential Data Minus. Asserted low (< 0.3V) USB Port 2 Differential Data Plus. Asserted high (> 2.8V) USB Port 2 Differential Data Minus. Asserted low (< 0.3V) USB Port 3 Differential Data Plus. Asserted high (> 2.8V) USB Port 3 Differential Data Minus. Asserted low (< 0.3V) USB Port 4 Differential Data Plus. Asserted high (> 2.8V) USB Port 4 Differential Data Minus. Asserted low (< 0.3V) USB Over-Current Input Port 1. When the supplied current exceeds 500 mA on a USB port, USBOC# should be asserted. If this input is asserted low, the host controller will disable USB port 1. The port will remain disabled as long as the condition persists. See Design Guide and evaluation board schematics for overcurrent detection scheme. 68 I USBOC2# VCCSUS USB Over-Current Input Port 2. Same as above but for port 2. 66 I USBOC3# VCCSUS USB Over-Current Input Port 3. Same as above but for port 2. 65 I USBOC4# VCCSUS USB Over-Current Input Port 4. Same as above but for port 2. 94 I XIN VCCOSC Crystal Input. May be connected to a 24 MHz parallel resonant fundamental mode crystal (see Design Guide for specific connection details). 95 O XOUT VCCOSC Crystal Output. Must be connected to a 24 MHz parallel resonant fundamental mode crystal (see Design Guide for specific connection details). 88 A REXT VCCPLL External Resistor. Typical 6.12k 1% pull down to analog ground (see Design Guide for specific connection details). Data encoding is NRZI (Non Return to Zero Inverted) so at times the reverse may be true (i.e., the plus pin may be asserted low and the minus pin asserted high.) Test Pins and Reserved Pins Signal Name Pin # I/O Power Signal Description ATPG_EN 63 I VCC25 TESTMODE TEST2 TEST3 WAKEUP_EN 64 102 99 98 I IO IO IO VCC25 VCC25 VCC25 VCC25 Automatic Test Program Generator Enable. Do not connect for normal operation. Internal pulldown. Test Mode Enable. Do not connect for normal operation. Internal pulldown. Test Signal 2. Leave unconnected for normal operation. Test Signal 3. Pull down 4.7K-ohm for normal operation. WAKEUP_EN. Enable wakeup function Revision 1.10, March 16, 2007 -6- Pin Descriptions VT6212 / VT6212L PCI USB2.0 Controller Power and Ground Signal Name Pin # Power Digital I/O VCCSUS 10, 18, 26, 34, 44, 52, 62, 101, 110, 120, 128 4, 35, 53, 115 5, 9, 17, 25, 33, 36, 43, 51, 54, 61, 100, 108, 114, 119, 127 70 GNDSUS 69 Suspend VCCUSB[4-1] 72, 76, 80, 84 USB Ports GNDUSB[4-1] 75, 79, 83, 87 USB Ports VCCPLL GNDPLL 91 92 PLL PLL VCCPLLA GNDPLLA 89 90 PLL PLL VCCOSC GNDOSC 96 93 OSC OSC VCC33 VCC25 GND Revision 1.10, March 16, 2007 Signal Description Digital I/O Power. 3.3V 100mV Internal Ground Internal Logic Power. 2.5V 5% Ground. Connect to primary PCB ground plane. Suspend Suspend I/O Power. Connect to system 3.3V 5% suspend power for support of wakeup on USB incoming port activity. Suspend I/O Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. USB Port Power. Connect to system 3.3V 5% suspend power for support of wakeup on USB incoming port activity. USB Port 1-4 Analog Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. PLL Digital Power. Connect to quiet 2.5V 5% power source. PLL Digital Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. PLL Analog Power. Connect to quiet 2.5V 5% power source. PLL Analog Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. Oscillator Power. Connect to quiet 2.5V 5% power source. Oscillator Analog Ground. Connect to analog ground plane (connected to primary PCB ground plane through ferrite beads for isolation from digital switching noise). See Design Guide for details. -7- Pin Descriptions VT6212 / VT6212L PCI USB2.0 Controller ELECTRICAL SPECIFICATIONS Table 3. Absolute Maximum Ratings Symbol Parameter TSTG Storage temperature Min Max Unit -55 125 C 0 85 C TC Case operating temperature VCC Power supply voltages -0.5 4.0 V VI Input voltage -0.5 5.5 V VO Output voltage at any output -0.5 VCC + 0.5 V 2 kV VESD Electrostatic discharge Comment Human Body Model Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions. Table 4. DC Characteristics TC = 0-55oC, VCCPCI = VCCSUS = VCCUSBN = 3.3V+/-5%, VCC25 = VCCOSC = VCCPLL = VCCPLLA =2.5V+/-5%, GND = 0V Symbol Parameter Min Max Unit Condition VIL Input Low Voltage -0.50 0.8 V VIH Input High Voltage 2.0 VCC+0.5 V VOL Output Low Voltage - 0.45 V IOL=4.0mA VOH Output High Voltage 2.4 - V IOH=-1.0mA IIL Input Leakage Current - +/-10 A 0<VIN<VCC IOZ Tristate Leakage Current - +/-20 A 0.45<VOUT<VCC Revision 1.10, March 16, 2007 -17- Electrical Specifications VT6212 / VT6212L PCI USB2.0 Controller Table 5. Power Specifications TC = 0-55oC, VCC33 = VCCSUS = VCCUSB = 3.3V+/-5%, VCC25 = VCCOSC = VCCPLL = VCCPLLA =2.5V+/-5%, GND = 0V Symbol Typ Max Unit ICC25-PD Parameter Power Supply Current - 2.5V 0 - mA Condition Power down or suspend ICC33-PD Power Supply Current - 3.3V 0 - mA Power down or suspend ICC25 Power Supply Current - VCC25 (2.5V) 14.5 - mA Idle with no port activity ICC33 Power Supply Current - VCC33 (3.3V) 0.05 - mA Idle with no port activity ICC25A Power Supply Current - Analog (2.5V) 61.5 - mA Idle with no port activity ICC0USB Power Supply Current - USB (3.3V) 32.9 - mA Idle with no port activity ICC1USB Power Supply Current - USB (3.3V) 71 - mA One port transmitting ICC2USB Power Supply Current - USB (3.3V) 108.9 - mA Two ports transmitting ICC3USB Power Supply Current - USB (3.3V) 159 - mA Three ports transmitting ICC4USB Power Supply Current - USB (3.3V) 200 - mA Four ports transmitting PD-PD Overall Chip Power Dissipation 3.35 - mW Power down or suspend PD-IDLE Overall Chip Power Dissipation 298 - mW Idle with no port activity PD-4USB Overall Chip Power Dissipation 943 - mW Four ports transmitting "Analog 2.5V" power includes VCCPLL, VCCPLLA, and VCCOSC "USB 3.3V" power includes VCCUSB and VCCSUS Revision 1.10, March 16, 2007 -18- Electrical Specifications VT6212 / VT6212L PCI USB2.0 Controller PACKAGE MECHANICAL SPECIFICATIONS D D1 D2 A A2 65 103 64 Product Name VT6212 E E1 E2 -A- A1 0.05 s 102 -D- -B- YYWWVV TAIWAN LLLLLLLLLL C M Y: Date Code Year W: Date Code Week V: Chip Version L: Lot Code 128 e b 4X 4X D 38 D 39 1 aaa C A-B D bbb H A-B D ddd M C A-B s D s L1 c SEE DETAIL "F" 0- 1 0- D -C- SEATING PLANE ccc C 0- 2 CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL R1 MIN. NOM. MAX. MIN. NOM. MAX. A 3.40 0.134 R2 A1 0.25 0.010 A2 2.50 2.72 2.90 0.098 0.107 0.114 D 23.20 BASIC 0.913 BASIC GAGE PLANE E 17.20 BASIC 0.677 BASIC S L D1 20.00 BASIC 0.787 BASIC 0.25 mm -03 E1 14.00 BASIC 0.551 BASIC L1 D2 18.50 BASIC 0.728 BASIC E2 12.50 BASIC 0.492 BASIC DETAIL "F" 0.30 0.005 0.012 R1 0.13 R2 0.13 0.005 NOTES : 0 7 0 7 00- 1 0 0 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE 0- 2 15 REF 15 REF PROTRUSION IS 0.25 mm PER SIDE. D1 AND 0- 3 15 REF 15 REF E1 ARE MAXIMUM PLASTIC BODY SIZE c 0.11 0.15 0.23 0.004 0.006 0.009 DIMENSIONS INCLUDING MOLD MISMATCH. L 0.73 0.88 1.03 0.029 0.035 0.041 L1 1.60 REF 0.063 REF 2. DIMENSION b DOES NOT INCLUDE DAMBAR S 0.20 0.008 PROTRUSION. ALLOWABLE DAMBAR b 0.17 0.20 0.27 0.007 0.008 0.011 PROTRUSION SHALL NOT CAUSE THE LEAD e 0.50 BASIC 0.020 BASIC WIDTH TO EXCEED THE MAXIMUM b TOLERANCES OF FORM AND POSITION DIMENSION BY MORE THAN 0.08mm. aaa 0.20 0.008 DAMBAR CAN NOT BE LOCATED ON THE bbb 0.20 0.008 LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ccc 0.08 0.003 ADJACENT LEAD IS 0.07mm. ddd 0.08 0.003 Figure 3. VT6212 Mechanical Specifications - 128 Pin PQFP Package Revision 1.10, March 16, 2007 -19- Mechanical Specifications VT6212 / VT6212L PCI USB2.0 Controller D D1 D2 A A2 65 103 64 Lead-Free Package Product Name VT6212 G E E1 E2 -A- A1 0.05 s 102 -D- -B- YYWWVV TAIWAN LLLLLLLLLL C M 128 e b 38 4X 4X D 39 1 D Y: Date Code Year W: Date Code Week V: Chip Version L: Lot Code aaa C A-B D bbb H A-B D ddd M C A-B s D s L1 c SEE DETAIL "F" 0- 1 0- D -C- SEATING PLANE ccc C 0- 2 CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL R1 MIN. NOM. MAX. MIN. NOM. MAX. A 3.40 0.134 R2 A1 0.25 0.010 A2 2.50 2.72 2.90 0.098 0.107 0.114 D 23.20 BASIC 0.913 BASIC GAGE PLANE E 17.20 BASIC 0.677 BASIC S L D1 20.00 BASIC 0.787 BASIC 0.25 mm -03 E1 14.00 BASIC 0.551 BASIC L1 D2 18.50 BASIC 0.728 BASIC E2 12.50 BASIC 0.492 BASIC DETAIL "F" 0.30 0.005 0.012 R1 0.13 R2 0.13 0.005 NOTES : 0 7 0 7 00- 1 0 0 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE 0- 2 15 REF 15 REF PROTRUSION IS 0.25 mm PER SIDE. D1 AND 0- 3 15 REF 15 REF E1 ARE MAXIMUM PLASTIC BODY SIZE c 0.11 0.15 0.23 0.004 0.006 0.009 DIMENSIONS INCLUDING MOLD MISMATCH. L 0.73 0.88 1.03 0.029 0.035 0.041 L1 1.60 REF 0.063 REF 2. DIMENSION b DOES NOT INCLUDE DAMBAR S 0.20 0.008 PROTRUSION. ALLOWABLE DAMBAR b 0.17 0.20 0.27 0.007 0.008 0.011 PROTRUSION SHALL NOT CAUSE THE LEAD e 0.50 BASIC 0.020 BASIC WIDTH TO EXCEED THE MAXIMUM b TOLERANCES OF FORM AND POSITION DIMENSION BY MORE THAN 0.08mm. aaa 0.20 0.008 DAMBAR CAN NOT BE LOCATED ON THE bbb 0.20 0.008 LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ccc 0.08 0.003 ADJACENT LEAD IS 0.07mm. ddd 0.08 0.003 Figure 4. VT6212 Lead-free Mechanical Specifications - 128 Pin PQFP Package Revision 1.10, March 16, 2007 -20- Mechanical Specifications VT6212 / VT6212L PCI USB2.0 Controller D D1 D2 A A2 65 103 64 Product Name VT6212L E E1 E2 -A- A1 0.05 s 102 -D- -B- YYWWVV TAIWAN C M LLLLLLLLLL Y: Date Code Year W: Date Code Week V: Chip Version L: Lot Code 128 e b 4X 4X D 38 D 39 1 aaa C A-B D bbb H A-B D L1 c ddd M C A-B s D s SEE DETAIL "F" 0- 1 0D -C- SEATING PLANE ccc C 0- 2 CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL R1 MIN. NOM. MAX. MIN. NOM. MAX. A 1.60 0.063 R2 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 22.00 BASIC 0.866 BASIC GAGE PLANE E 16.00 BASIC 0.630 BASIC S L D1 20.00 BASIC 0.787 BASIC 0.25 mm -03 E1 14.00 BASIC 0.551 BASIC L1 D2 18.50 BASIC 0.728 BASIC E2 12.50 BASIC 0.492 BASIC DETAIL "F" R1 0.08 0.003 R2 0.08 0.20 0.003 0.008 NOTES : 0 3.5 7 0 3.5 7 00- 1 0 0 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE 0- 2 11 12 13 11 12 13 PROTRUSION IS 0.25 mm PER SIDE. D1 AND 0- 3 11 12 13 11 12 13 E1 ARE MAXIMUM PLASTIC BODY SIZE c 0.09 0.20 0.004 0.008 DIMENSIONS INCLUDING MOLD MISMATCH. L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF 2. DIMENSION b DOES NOT INCLUDE DAMBAR S 0.20 0.008 PROTRUSION. ALLOWABLE DAMBAR b 0.17 0.20 0.27 0.007 0.008 0.011 PROTRUSION SHALL NOT CAUSE THE LEAD e 0.50 BASIC 0.020 BASIC WIDTH TO EXCEED THE MAXIMUM b TOLERANCES OF FORM AND POSITION DIMENSION BY MORE THAN 0.08mm. aaa 0.20 0.008 DAMBAR CAN NOT BE LOCATED ON THE bbb 0.20 0.008 LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ccc 0.08 0.003 ADJACENT LEAD IS 0.07mm. ddd 0.08 0.003 Figure 5. VT6212L Mechanical Specifications - 128 Pin LQFP Package Revision 1.10, March 16, 2007 -21- Mechanical Specifications VT6212 / VT6212L PCI USB2.0 Controller D D1 D2 A A2 102 65 64 103 Lead-Free Package VT6212L G -A- E E1 E2 -B- YYWWVV TAIWAN C M LLLLLLLLLL Y: Date Code Year W: Date Code Week V: Chip Version L: Lot Code 128 39 e b aaa C A-B D 38 4X D 1 4X bbb H A-B D ddd M C A-B s D s D Product Name A1 0.05 s -D- L1 c SEE DETAIL "F" 0- 1 D 0 ccc C -C- SEATING PLANE 0- 2 CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL R1 MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 A R2 0.006 0.05 0.15 0.002 A1 1.35 1.40 1.45 0.053 0.055 0.057 A2 22.00 BASIC 0.866 BASIC D GAGE PLANE 16.00 BASIC 0.630 BASIC E S L 20.00 BASIC 0.787 BASIC D1 0.25 mm 0- 3 14.00 BASIC 0.551 BASIC E1 L1 D2 18.50 BASIC 0.728 BASIC E2 12.50 BASIC 0.492 BASIC DETAIL "F" R1 0.08 0.003 0.08 0.20 0.003 0.008 R2 NOTES : 0 3.5 7 0 3.5 7 00 0 0- 1 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE 0- 2 11 12 13 11 12 13 PROTRUSION IS 0.25 mm PER SIDE. D1 AND 0- 3 11 12 13 11 12 13 E1 ARE MAXIMUM PLASTIC BODY SIZE c 0.008 0.09 0.20 0.004 DIMENSIONS INCLUDING MOLD MISMATCH. L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF 2. DIMENSION b DOES NOT INCLUDE DAMBAR S 0.008 0.20 PROTRUSION. ALLOWABLE DAMBAR b 0.17 0.20 0.27 0.007 0.008 0.011 PROTRUSION SHALL NOT CAUSE THE LEAD e 0.50 BASIC 0.020 BASIC WIDTH TO EXCEED THE MAXIMUM b TOLERANCES OF FORM AND POSITION DIMENSION BY MORE THAN 0.08mm. aaa 0.20 0.008 DAMBAR CAN NOT BE LOCATED ON THE bbb 0.20 0.008 LOWER RADIUS OR THE FOOT. MINIMUM ccc 0.08 0.003 SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. ddd 0.08 0.003 Figure 6. VT6212L Lead-free Mechanical Specifications - 128 Pin LQFP Package Revision 1.10, March 16, 2007 -22- Mechanical Specifications