TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 4.5-V TO 18-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN THREE BUCK SWITCHER WITH INTEGRATED FET Check for Samples: TPS65251 FEATURES 1 * * * * * * * * * Wide Input Supply Voltage Range (4.5 V - 18 V) 0.8 V, 1% Accuracy Reference Continuous Loading: 3 A (Buck 1), 2 A (Buck 2 and 3) Maximum Current: 3.5 A (Buck 1), 2.5 A (Buck 2 and 3) Adjustable Switching Frequency 300 kHz - 2.2 MHz Set By External Resistor Dedicated Enable for Each Buck External Synchronization Pin for Oscillator External Enable/Sequencing and Soft Start Pins Adjustable Current Limit Set By External Resistor * * * * * Soft Start Pins Current-Mode Control With Simple Compensation Circuit Power Good Optional Low Power Mode Operation for Light Loads QFN Package, 40-Pin 6 mm x 6 mm RHA APPLICATIONS * * * * * * Set Top Boxes Blu-ray DVD DVR DTV Car Audio/Video Security Camera DESCRIPTION/ORDERING INFORMATION The TPS65251 features three synchronous wide input range high efficiency buck converters. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- or 15-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and close to the input supply. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The current mode control allows a simple RC compensation. The switching frequency of the converters can either be set with an external resistor connected to ROSC pin or can be synchronized to an external clock connected to SYNC pin if needed. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. 180 out of phase operation between Buck 1 and Buck 2, 3 (Buck 2 and 3 run in phase) minimizes the input filter requirements. TPS65251 features a supervisor circuit that monitors each converter output. The PGOOD pin is asserted once sequencing is done, all PG signals are reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high. TPS65251 also features a light load pulse skipping mode (PSM) by allowing the LOW_P pin tied to V3V. The PSM mode allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2011, Texas Instruments Incorporated TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com CMP2 SS2 RLIM2 GND LOW_P FB2 V7V PGOOD AGND V3V FB2 GND FB2 EN2 BST2 VIN VIN VIN2 LX2 LX2 LX1 LX1 VIN1 BST1 VIN VIN SS1 RLIM1 V2 V1 VIN1 EN1 FB1 FB1 FB3 FB3 SYNC ROSC FB1 CMP1 VIN3 BST3 EN3 SS3 CMP3 FB3 VIN3 TPS65251 RLIM3 V3 GND LX3 LX3 VIN2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM AGND ROSC V3V V7V OSC INTERNAL VOLTAGE RAILS SYNC 12V DC Supply BST1 VIN1 LX1 Vout BUCK1 LX1 SS1 BUCK1 FB1 from enable logic EN1 COMP1 Rlim1 BST2 LX2 VIN2 Vout BUCK2 LX2 SS2 BUCK2 FB2 from enable logic EN2 COMP2 Rlim2 BST3 VIN3 LX3 SS3 from enable logic Vout BUCK3 LX3 BUCK3 EN3 FB3 COMP3 Rlim3 VIN PFM mode PGOOD LOW_P PG Generator GND 2 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 ORDERING INFORMATION (1) PACKAGE (2) TA -40C to 125C (1) (2) ORDERABLE PART NUMBER 40-pin (QFN) - RHA Reel of 2500 TPS65251RHAR Reel of 250 TPS65251RHAT TOP-SIDE MARKING TPS65251 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. PIN OUT AGND V3V V7V PGOOD GND LOW_P FB2 COMP2 SS2 RLIM2 30 29 28 27 26 25 24 23 22 21 GND 31 20 EN2 VIN 32 19 BST2 VIN 33 18 VIN2 VIN 34 17 LX2 GND 35 16 LX2 LX3 36 15 LX1 LX3 37 14 LX1 VIN3 38 13 VIN1 BST3 39 12 BST1 EN3 40 11 EN1 2 3 4 5 6 7 8 9 SS3 CMP3 FB3 SYNC ROSC FB1 CMP1 SS1 10 RLIM1 1 RLIM3 QFN RHA40 (power pad connected to ground) Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 3 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com TERMINAL FUNCTIONS (DCA) NAME NO. I/O DESCRIPTION RLIM3 1 I Current limit setting for Buck 3. Fit a resistor from this pin to ground to set the peak current limit on the output inductor. SS3 2 I Soft start pin for Buck 3. Fit a small ceramic capacitor to this pin to set the converter soft start time. COMP3 3 O Compensation for Buck 3. Fit a series RC circuit to this pin to complete the compensation circuit of this converter. FB3 4 I Feedback input for Buck 3. Connect a divider set to 0.8V from the output of the converter to ground. SYNC 5 I Synchronous clock input. If there is a sync clock in the system, connect to the pin. When not used connect to GND. ROSC 6 I Oscillator set. This resistor sets the frequency of internal autonomous clock. If external synchronization is used resistor should be fitted and set to ~70% of external clock frequency. FB1 7 I Feedback pin for Buck 1. Connect a divider set to 0.8 V from the output of the converter to ground. COMP1 8 O Compensation pin for Buck 1. Fit a series RC circuit to this pin to complete the compensation circuit of this converter. SS1 9 I Soft start pin for Buck 1. Fit a small ceramic capacitor to this pin to set the converter soft start time. RLIM1 10 I Current limit setting pin for Buck 1. Fit a resistor from this pin to ground to set the peak current limit on the output inductor. EN1 11 I Enable pin for Buck 1. A low level signal on this pin disables it. If pin is left open a weak internal pull-up to V3V will allow for automatic enable. For a delayed start-up add a small ceramic capacitor from this pin to ground. BST1 12 I Bootstrap capacitor for Buck 1. Fit a 47-nF ceramic capacitor from this pin to the switching node. VIN1 13 I Input supply for Buck 1. Fit a 10-F ceramic capacitor close to this pin. LX1 14, 15 O Switching node for Buck 1 LX2 16, 17 O Switching node for Buck 2 VIN2 18 I Input supply for Buck 2. Fit a 10-F ceramic capacitor close to this pin. BST2 19 I Bootstrap capacitor for Buck 2. Fit a 47-nF ceramic capacitor from this pin to the switching node. EN2 20 I Enable pin for Buck 2. A low level signal on this pin disables it. If pin is left open a weak internal pull-up to V3V will allow for automatic enable. For a delayed start-up add a small ceramic capacitor from this pin to ground. RLIM2 21 I Current limit setting for Buck 2. Fit a resistor from this pin to ground to set the peak current limit on the output inductor. SS2 22 I Soft start pin for Buck 2. Fit a small ceramic capacitor to this pin to set the converter soft start time. COMP2 23 O Compensation pin for Buck 2. Fit a series RC circuit to this pin to complete the compensation circuit of this converter FB2 24 I Feedback input for Buck 2. Connect a divider set to 0.8 V from the output of the converter to ground. LOW_P 25 I Low power operation mode(active high) input for TPS65251 GND 26 PGOOD 27 O Power good. Open drain output asserted after all converters are sequenced and within regulation. Polarity is factory selectable (active high default). V7V 28 O Internal supply. Connect a 10-F ceramic capacitor from this pin to ground. V3V 29 O Internal supply. Connect a 10-F ceramic capacitor from this pin to ground. AGND 30 Analog ground. Connect all GND pins and the power pad together. GND 31 Ground pin 4 Ground pin Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 TERMINAL FUNCTIONS (DCA) (continued) NO. I/O VIN NAME 32 I Input supply DESCRIPTION VIN 33 I Input supply VIN 34 I Input supply GND 35 LX3 36, 37 VIN3 38 BST3 39 I Bootstrap capacitor for Buck 3. Fit a 47-nF ceramic capacitor from this pin to the switching node. EN3 40 I Enable pin for Buck 3. A low level signal on this pin disables it. If pin is left open a weak internal pull-up to V3V will allow for automatic enable. For a delayed start-up add a small ceramic capacitor from this pin to ground. Ground pin O Switching node for Buck 3 Input supply for Buck 3. Fit a 10-F ceramic capacitor close to this pin. PAD Power pad. Connect to ground. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Voltage range at VIN1,VIN2, VIN3, LX1, LX2, LX3 -0.3 to 18 V Voltage range at LX1, LX2, LX3 (maximum withstand voltage transient < 10 ns) -1 to 18 V Voltage at BST1, BST2, BST3, referenced to Lx pin -0.3 to 7 V Voltage at V7V, COMP1, COMP2, COMP3 -0.3 to 7 V Voltage at V3V, RLIM1, RLIM2, RLIM3, EN1,EN2,EN3, SS1, SS2,SS3, FB1, FB2, FB3, PGOOD, SYNC, ROSC, LOW_P -0.3 to 3.6 V Voltage at AGND, GND -0.3 to 0.3 V TJ Operating virtual junction temperature range -40 to 125 C TSTG Storage temperature range -55 to 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 4.5 18 V TJ Junction temperature -40 125 C ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN Human body model (HBM) Charge device model (CDM) MAX UNIT 2000 V 500 V Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 5 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com PACKAGE DISSIPATION RATINGS (1) (1) PACKAGE qJA (C/W) TA = 25C POWER RATING (W) TA = 55C POWER RATING (W) TA = 85C POWER RATING (W) RHA 30 3.33 2.3 1.3 Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x .6-mm board with the following layer arrangement: (a) Top layer: 2 Oz Cu, 6.7% coverage (b) Layer 2: 1 Oz Cu, 90% coverage (c) Layer 3: 1 Oz Cu, 90% coverage (d) Bottom layer: 2 Oz Cu, 20% coverage ELECTRICAL CHARACTERISTICS TJ = -40C to 125C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE VIN Input Voltage range 4.5 IDDSDN Shutdown EN pin = low for all converters 1.3 mA IDDQ Quiescent, low power disabled (Lo) Converters enabled, no load Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V 20 mA IDDQ_LOW_P Quiescent, low power enabled (Hi) Converters enabled, no load Buck 1 = 3.3 V, Buck 2 = 2.5 V, Buck 3 = 7.5 V 1.5 mA UVLOVIN VIN under voltage lockout UVLODEGLITCH V3V Internal biasing supply V7V Internal biasing supply V7VUVLO UVLO for internal V7V rail V7VUVLO_DEGLITCH 18 V Rising VIN 4.22 Falling VIN 4.1 Both edges 110 s 3.3 V 6.25 V Rising V7V 3.8 Falling V7V 3.6 Falling edge 110 V V s BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW POWER MODE) VIH Enable threshold high V3p3 = 3.2 V - 3.4 V 1.55 V VIL Enable treshold Low V3p3 = 3.2 V - 3.4 V ICHEN Pull up current enable pin tD Discharge time enable pins ISS Soft start pin current source FSW_BK Converter switching frequency range Set externally with resistor 0.3 2.2 MHz RFSW Frequency setting resistor Depending on set frequency 50 600 k fSW_TOL Internal oscillator accuracy fSW = 800 kHz -10 10 % VSYNCH External clock threshold high V3p3 = 3.3 V 1.55 VSYNCL External clock treshold Low V3p3 = 3.3 V SYNCRANGE Synchronization range 0.2 SYNCCLK_MIN Sync signal minimum duty cycle 40 SYNCCLK_MAX Sync signal maximum duty cycle VIHLOW_P Low power mode threshold high V3p3 = 3.3 V VILLOW_P Low power mode treshold Low V3p3 = 3.3 V 1.24 Power-up V 1.1 A 10 ms 5 A V 1.24 V 2.2 MHz % 60 1.55 % V 1.24 V FEEDBACK, REGULATION, OUTPUT STAGE VFB Feedback voltage tON_MIN Minimum on time (current sense blanking) 6 VIN = 12V TJ = 25C -1% 0.8 1% VIN = 4.5 to 18V -2% 0.8 2% 80 120 Submit Documentation Feedback V ns Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS (continued) TJ = -40C to 125C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLINEREG Line regulation - DC VOUT/VINB VINB = 4.5 V to 18 V, IOUT = 1000 mA 0.5 % VOUT VLOADREG Load regulation - DC VOUT/IOUT IOUT = 10 % - 90% IOUT,MAX 0.5 % VOUT/A ILIMIT1 Peak inductor current limit range 1 4 A ILIMIT2 Peak inductor current limit range 1 3 A ILIMIT3 Peak inductor current limit range 1 3 A MOSFET (BUCK 1) H.S. Switch Turn-On resistance high side FET on VIN = 12 V, TJ = 25C CH1 95 m L.S. Switch Turn-On resistance low side FET on CH1 VIN = 12 V, TJ = 25C 50 m H.S. Switch Turn-On resistance high side FET on VIN = 12 V, TJ = 25C CH2 120 m L.S. Switch Turn-On resistance low side FET on CH2 VIN = 12 V, TJ = 25C 80 m H.S. Switch Turn-On resistance high side FET on VIN = 12 V, TJ = 25C CH3 120 m L.S. Switch Turn-On resistance low side FET on CH3 VIN = 12 V, TJ = 25C 80 m gM Error amplifier transconductance -2 A < ICOMP < 2 A 130 mhos gmPS COMP to ILX gM ILX = 0.5 A 10 A/V Output falling (device will be disabled after tON_HICCUP ) 85 Output rising (PG will be asserted) 90 MOSFET (BUCK 2) MOSFET (BUCK 3) ERROR AMPLIFIER POWER GOOD RESET GENERATOR VUVBUCKX Threshold voltage for buck under voltage % tUV_deglitch Deglitch time (both edges) Each buck 11 ms tON_HICCUP Hiccup mode ON time VUVBUCKX asserted 12 ms tOFF_HICCUP Hiccup mode OFF time before re-start is attempted All converters disabled. Once tOFF_HICCUP elapses, all converters will go through sequencing again. 15 ms Output rising (high side fet will be forced off) 109 VOVBUCKX Threshold voltage for buck over voltage Output falling (high side fet will be allowed to switch ) 107 Measured after minimum reset period of all bucks power-up successfully 1 tRP minimum reset period % s THERMAL SHUTDOWN TTRIP Thermal shut down trip point Rising temperature THYST Thermal shut down hysteresis Device re-starts TTRIP_DEGLITCH Thermal shut down deglitch 160 C 110 s Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 C 20 7 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS Buck 1 TA = 25C, VIN = 12 V, fSW = 1.1 MHz (unless otherwise noted) 8 Figure 1. Start-Up VOUT = 3.3 V, 2 A Figure 2. Ripple VOUT = 3.3 V, 1.5 A, fSW = 800 kHz, 20 mV/div Figure 3. Transient Load Response VOUT = 3.3 V, I = 1 A to 1.5 A, 100 mV/div Figure 4. Transient Supply Response VOUT = 3.3 V, VIN = 8 V to 16.5 V, 20 mV/div Figure 5. Efficiency VOUT = 3.3 V, L= 4.7 H, DCR = 28 m Figure 6. Efficiency VOUT = 1.2 V, L = 4.7 H, DCR = 28 m Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) Buck 1 TA = 25C, VIN = 12 V, fSW = 1.1 MHz (unless otherwise noted) Figure 7. Efficiency Low Power Enabled VOUT = 3.3 V, L = 4.7 H Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 9 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS Buck 2 TA = 25C, VIN = 12 V, fSW = 1.14 MHz (unless otherwise noted) 10 Figure 8. Start-Up VOUT = 2.5 V, 1.5 A Figure 9. Ripple VOUT = 2.5 V, 1.5 A, fSW = 800 kHz, 5 mV/div Figure 10. Transient Load Response VOUT = 2.5 V, I = 1 A to 1.5 A Figure 11. Transient Supply Response VOUT = 2.5 V, VIN = 9 V to 8 V Figure 12. Efficiency VOUT = 3.3 V, L = 4.7 H, DCR = 28 m (Also Applies to Buck 3) Figure 13. Efficiency VOUT = 1.8 V, L = 4.7 H, DCR = 28 m (Also Applies to Buck 3) Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) Buck 2 TA = 25C, VIN = 12 V, fSW = 1.14 MHz (unless otherwise noted) Figure 14. Efficiency Low Power Enabled VOUT = 2.5 V, L = 4.7 F Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 11 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS Buck 3 TA = 25C, VIN = 12 V, fSW = 1.14 MHz (unless otherwise noted) 12 Figure 15. Start-Up VOUT = 7.5 V, 0.7 A Figure 16. Ripple VOUT = 7.5 V, 0.5 A, fSW = 800 kHz 5 mV/div Figure 17. Transient Load Response VOUT = 7.5 V, I = 1 A to 1.5 A Figure 18. Transient Supply Response VOUT = 2.5 V, VIN = 9 V to 8 V Figure 19. Efficiency VOUT = 2.5 V, L = 4.7 H, DCR = 28 m (Also Applies to Buck 2) Figure 20. Efficiency Low Power Enabled VOUT = 2.5 V, L = 4.7 F Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 TYPICAL APPLICATION CIRCUIT 1.8V 2A V2 R22 C1 20K C24 4700pF C21 22uF 10uF C2 PG LP FB2 3.3uF C25 C26 100pF 4.7nF R23 R20 47nF C37 R30 40.2K 4.7nF C33 R33 4.7nF 120K 12.7K VIN2 CMP2 SS2 RLIM2 GND LOW_P FB2 R21 C20 L2 47nF 32K 4.7uH L1 1.2V 3A V1 4.7uH VIN1 C11 22uF C10 47nF EN1 C17 4.7nF R13 C13 100K R1 R31 4.7nF EN2 BST2 LX1 VIN1 BST1 SS1 RLIM1 VIN3 BST3 EN3 SYNC ROSC FB1 CMP1 VIN3 TPS65251 SS3 CMP3 FB3 C31 22uF C30 GND LX3 LX3 RLIM3 L3 C34 R32 4700pF 20K C36 FB2 C27 VIN2 LX2 LX2 LX1 VIN VIN 4.7uH 40.2K C23 4.7nF VIN VIN V3 3.3V 2A V7V PGOOD GND AGND V3V 150K 383K 4.7nF R12 C14 20K 4700pF 4.7nF R10 40.2K C16 4.7nF R11 80.6K C15 100pF C35 100pF OVERVIEW TPS65251 is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65251 can support 4.5-V to 18-V input supply, high load current, 300-kHz to 2.2-MHz clocking. The buck converters have an optional PSM mode, which can improve power dissipation during light loads. Alternatively, the device implements a constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency of 300 kHz to 2.2 MHz allows for efficiency and size optimization. The switching frequency is adjustable by selecting a resistor to ground on the ROSC pin. The SYNC pin also provides a means to synchronize the power converter to an external signal. Input ripple is reduced by 180 degree out-of-phase operation between Buck 1 and Buck 2. Buck 3 operates in phase with Buck 2. All three buck converters have peak current mode control which simplifies external frequency compensation. A traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the crossover frequency over 100 kHz. Each buck converter has an individual current limit, which can be set up by a resistor to ground from the RLIM pin. The adjustable current limiting enables high efficiency design with smaller and less expensive inductors. The device has two built-in LDO regulators. During a standby mode, the 3.3-V LDO and the 6.5-V LDO can be used to drive MCU and other active loads. By this, the system is able to turn off the three buck converters and improve the standby efficiency. The device has a power good comparator monitoring the output voltage. Each converter has its own soft start and enable pins, which provide independent control and programmable soft start. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 13 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com DETAILED DESCRIPTION Adjustable Switching Frequency To select the internal switching frequency connect a resistor from ROSC to ground. Figure 21 shows the required resistance for a given switching frequency. Figure 21. ROSC vs Switching Frequency ROSC(kW) = 174 * f -1.122 (1) For operation at 800 kHz a 230-k resistor is required. Synchronization The status of the SYNC pin will be ignored during start-up and the TPS65251's control will only synchronize to an external signal after the PGOOD signal is asserted. The status of the SYNC pin will be ignored during start-up and the TPS65251 will only synchronize to an external clock if the PGOOD signal is asserted. When synchronization is applied, the PWM oscillator frequency must be lower than the sync pulse frequency to allow the external signal trumping the oscillator pulse reliably. When synchronization is not applied, the SYNC pin should be connected to ground. Out-of-Phase Operation Buck 1 has a low conduction resistance compared to Buck 2 and 3. Normally Buck 1 is used to drive higher system loads. Buck 2 and 3 are used to drive some peripheral loads like I/O and line drivers . The combination of Buck 2 and 3's loads may be on par with Buck 1's. In order to reduce input ripple current, Buck 2 operates in phase with Buck 3; Buck 1 and Buck 2 operate 180 degrees out-of-phase. This enables the system, having less input ripple, to lower component cost, save board space and reduce EMI. Delayed Start-Up If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay added is ~1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1-M pull-up to the 3V3 rail. 14 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 Soft Start Time The device has an internal pull-up current source of 5 A that charges an external slow start capacitor to implement a slow start time. Equation 2 shows how to select a slow start capacitor based on an expected slow start time. The voltage reference (VREF) is 0.8 V and the slow start charge current (Iss) is 5 A. The soft start circuit requires 1 nF per 200 S to be connected at the SS pin. A 1-ms soft-start time is implemented for all converters fitting 4.7 nF to the relevant pins. ( ) Css(nF) Tss(ms) = VREF(V) * Iss(A) (2) Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1% tolerance or better divider resistors. In order to improve efficiency at light load, start with 40.2 k for the R1 resistor and use the Equation 3 to calculate R2. ae 0.8V o R 2 = R1 x c / e VO - 0.8V o (3) Vo TPS65251 R1 FB R2 0.8V + Figure 22. Voltage Divider Circuit Input Capacitor Use 10-F X7R/X5R ceramic capacitors at the input of the converter inputs. These capacitors should be connected as close as physically possible to the input pins of the converters. Bootstrap Capacitor The device has three integrated boot regulators and requires a small ceramic capacitor between the BST and LX pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be 0.047 F. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. Error Amplifier The device has a transconductance error amplifier. The transconductance of the error amplifier is 130 A/V during normal operation. The frequency compensation network is connected between the COMP pin and ground. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 15 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com Loop Compensation TPS65251 is a current mode control dc/dc converter. The error amplifier is a transconductance amplifier with a of 130 A/V. A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60 and 90 degrees, or type III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to attenuate high-frequency noise when needed. . It may also prevent noise coupling from other rails if there is possibility of cross coupling in between rails when layout is very compact. Vo iL Co RL Gm=10A/V RESR Cff R1 Current Sense I/V Gain FBx g M = 130 u Vref = 0.8V COMPx R2 Rc CRoll Cc Figure 23. Loop Compensation 16 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 To calculate the external compensation components follow the following steps: TYPE II CIRCUIT Select switching frequency that is appropriate for application depending on L, C sizes, output ripple, EMI concerns and etc. Switching frequencies between 500 kHz and 1 MHz give best trade off between performance and cost. When using smaller L and Cs, switching frequency can be increased. To optimize efficiency, switching frequency can be lowered. Use type III circuit for switching frequencies higher than 500 kHz. Select cross over frequency (fc) to be less than 1/5 to 1/10 of switching frequency. Suggested fc = fs/10 RC = Set and calculate Rc. 2p x fc x Vo x Co g M x Vref x gm ps Calculate Cc by placing a compensation zero at or before the converter dominant pole Cc = 1 fp = CO x RL x 2p TYPE III CIRCUIT RL x Co Rc Suggested fc = fs/10 RC = 2p x fc x Co g M x gm ps Cc = RL x Co Rc Add CRoll if needed to remove large signal coupling to high impedance COMP node. Make sure that fpRoll = 1 2 x p x RC x CRoll CRoll = Re sr x Co RC CRoll = Re sr x Co RC is at least twice the cross over frequency. Calculate Cff compensation zero at low frequency to boost the phase margin at the crossover frequency. Make sure that the zero frequency (fzff is smaller than soft start equivalent frequency (1/Tss). NA C ff = 1 2 x p x fz ff x R1 Slope Compensation The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic oscillations in peak current mode control. Power Good The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all three buck converters' outputs are more than 90% of its nominal output voltage and reset time of 1 second elapses. The polarity of the PGOOD is active high. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 17 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com Current Limit Protection The TPS65251 current limit trip is set by the following formulae: 180 ILIM = R + 1.3 (4) LIM Figure 24. Buck 1 150 ILIM = R + 1.12 (5) LIM Figure 25. Buck 2 and 3 All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the converters, all the converters will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed, the converter will ramp up and operate normally. If this is not the case the converter will see another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts for less than 10 ms, only the relevant converter affected will go into and out of under-voltage and no global hiccup mode will occur. The converter will be protected by the cycle-by-cycle current limit during that time. Overvoltage Transient Protection The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops below the lower OVP threshold which is 107%, the high side MOSFET is allowed to turn on the next clock cycle. 18 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20C. Power Dissipation The total power dissipation inside TPS65251 should not to exceed the maximum allowable junction temperature of 125C. The maximum allowable power dissipation is a function of the thermal resistance of the package (RJA) and ambient temperature. To 1. 2. 3. calculate the temperature inside the device under continuous loading use the following procedure. Define the set voltage for each converter. Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading. Determine from the graphs below the expected losses (Y axis) in watts per converter inside the device. The losses depend on the input supply, the selected switching frequency, the output voltage and the converter chosen. 4. To calculate the maximum temperature inside the IC use the following formula: THOT_SPOT = TA + PDIS * qJA (6) Where: TA is the ambient temperature PDIS is the sum of losses in all converters qJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout BUCK 1 LOSSES (W) vs OUTPUT CURRENT VIN = 12 V, fSW = 500 kHz VO (From Top to Bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V BUCK 1 LOSSES (W) vs OUTPUT CURRENT VIN = 12 V, fSW = 1.1 MHz VO (From Top to Bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V Figure 26. Figure 27. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 19 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com BUCK 2 AND 3 LOSSES (W) vs OUTPUT CURRENT VIN = 12 V, fSW = 500 kHz VO (From Top to Bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V BUCK 2 AND 3 LOSSES (W) vs OUTPUT CURRENT VIN = 12 V, fSW = 1.1 MHz VO (From Top to Bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V Figure 28. Figure 29. Low Power Mode Operation By pulling the Low_p pin high all converters will operate in pulse-skipping mode, greatly reducing the overall power consumption at light and no load conditions. Although each buck converter has a skip comparator that makes sure regulation is not lost when a heavy load is applied and low power mode is enabled, system design needs to make sure that the LP pin is pulled low for continuous loading in excess of 100 mA. When low power is implemented, the peak inductor current used to charge the output capacitor is: IN - VOUT ILIMIT = 0.25 * TSLEEP_CLK * V 3/4 L (7) Where TSLEEP_CLK is half of the converter switching period, 2/fSW. The size of the additional ripple added to the output is: 1 * DVOUT = 3/4 C ( VIN L * ILIMIT2 ILOAD - 3/4 3/4* 3/4 2 VOUT * (VIN - VOUT) fSLEEP_CLK ) (8) And the peak output voltage during low power operation is: DVOUT VOUT_PK = VOUT + 3/4 2 (9) VOUT_PK VOUT Figure 30. Peak Output Voltage During Low Power Operation 20 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 APPLICATION INFORMATION Design Guide - Step-By-Step Design Procedure The following example illustrates the design procedure for selecting external components for the three buck converters. The example focuses on Buck 1, but the procedure can be directly applied to Buck 2 and 3 as well. The design goal parameters are given in Table 1. Table 1. Design Parameters Output voltage 1.2 V Transient response 0.5-A to 2-A load step 120 mV Maximum output current 3A Input voltage 12 V nom, 9.6 V to 14.4 V Output voltage ripple < 30 mV p-p Switching frequency 500 kHz Typical Buck 1 Application Schematic The application schematic of Buck 1 is shown in Figure 31. The design procedure is given below. C1 10uF C2 PG LP FB2 GND VIN GND LOW_P FB2 CMP2 SS2 RLIM2 AGND V3V V7V PGOOD 3.3uF VIN VIN VIN GND LX3 LX3 VIN2 LX2 LX2 LX1 LX1 VIN1 BST1 SS1 RLIM1 SS3 CMP3 FB3 SYNC ROSC FB1 CMP1 RLIM3 TPS65251 VIN3 BST3 EN3 EN2 BST2 EN1 L1 1.2V 3A V1 4.7uH VIN1 C11 22uF C10 47nF C17 4.7nF R13 C13 100K R1 383K R12 C14 20K 4700pF 4.7nF R10 40.2K C16 4.7nF R11 80.6K C15 100pF Figure 31. Typical Buck 1 Application Circuit Selecting the Switching Frequency The first step is to decide on a switching frequency for the regulator. Typically, you will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high switching Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 21 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which hurt the converter's performance. The converter is capable of running from 300 kHz to 2.2 MHz. Unless a small solution size is an ultimate goal, a moderate switching frequency of 500 kHz is selected to achieve both a small solution size and a high efficiency operation. Using Figure 21, R1 is determined to be 383 k Output Inductor Selection To calculate the value of the output inductor, use Equation 10. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. In general, KIND is normally from 0.1 to 0.3 for the majority of applications. For this design example, use KIND = 0.2 and the inductor value is calculated to be 3.6 H. For this design, a nearest standard value was chosen: 4.7 H. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 11 and Equation 12. Lo = Vin - Vout Vout x Io x K ind Vin x fsw (10) Vin - Vout Vout x Iripple = Lo Vin x fsw ILrms = Io 2 + (11) 1 ae Vo x (Vin max - Vo) o xc / 12 e Vin maxx Lo x fsw o ILpeak = Iout + 2 Iripple 2 (12) (13) Output Capacitor There are two primary considerations for selecting the value of the output capacitor. The output capacitors are selected to meet load transient and output ripple's requirements. Equation 14 gives the minimum output capacitance to meet the transient specification. For this example, LO = 4.7 H, IOUT = 1.5 A - 0.75 A = 0.75 A and VOUT = 120 mV. Using these numbers gives a minimum capacitance of 18 F. A standard 22-F ceramic capacitor is chose in the design. Co > DI OUT 2 x Lo Vout x DVout (14) Equation 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. From Equation 11, the output current ripple is 0.46 A. From Equation 15, the minimum output capacitance meeting the output voltage ripple requirement is 1.74 F. Co > 1 1 x 8 x fsw Vripple Iripple (15) Additional capacitance de-rating for aging, temperature and DC bias should influence this minimum value. For this example, one 22-F, 6.3-V X7R ceramic capacitor with 3 m of ESR will be used. Input Capacitor A minimum 10-F X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These capacitors should be connected as close as physically possible to the input pins of the converters as they handle the RMS ripple current shown in Equation 16. For this example, IOUT = 3 A, VOUT = 1.2 V, VINmin = 9.6 V, from Equation 16, the input capacitors must support a ripple current of 0.99 A RMS. 22 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 TPS65251 www.ti.com SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 Icirms = Iout x Vout (Vin min - Vout ) x Vin min Vin min (16) The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 17. Using the design example values, IOUTmax = 3 A, CIN = 10 F, fSW = 500 kHz, yields an input voltage ripple of 150 mV. DVin = Iout maxx 0.25 Cin x fsw (17) Soft Start Capacitor The soft start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. This is useful if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The soft start capacitor value can be calculated using Equation 18. In this example, the converter's soft start time is 0.8 ms. In TPS65251, Iss is 5 A and Vref is 0.8 V. From Equation 18, the soft start capacitance is 5 nF. A standard 4.7-nF ceramic capacitor is chosen in this design. In this example, C16 is 4.7nF Css (nF ) = Tss (ms ) x Iss (uA) Vref (V ) (18) Bootstrap Capacitor Selection A 0.047-F ceramic capacitor must be connected between the BST to LX pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or higher voltage rating. Adjustable Current Limiting Resistor Selection The converter uses the voltage drop on the high-side MOSFET to measure the inductor current. The over current protection threshold can be optimized by changing the trip resistor. Equation 19 governs the threshold of over current protection. In this example, the over current threshold is 3.5 A and the equation yields RLIM1 = 80 k. Due to the tolerance of the high-side current sensing, additional 30% is added to cover the upper tolerance. Thus RLIM1 is determined to be 100 k. In this example, R13 is 100 k. RLIM 1(k W) = 180 ILIM 1 - 1.3 (19) Output Voltage and Feedback Resistors Selection For the example design, 40.2 k was selected for R10. Vout is 1.2 V, Vref = 0.8 V. Using Equation 20, R11 is calculated as 80.4 k. A standard 80.6-k resistor is chose in this design. R11 = Vout - Vref R10 Vref (20) Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 23 TPS65251 SLVSAA4B - JUNE 2010 - REVISED JANUARY 2011 www.ti.com Compensation A type-II compensation circuit is adequate for the converter to have a phase margin between 60 and 90 degrees. The following equations show the procedure of designing a peak current mode control dc/dc converter. The compensation design takes the following steps: 1. Set up the anticipated cross-over frequency. In this example, the anticipated cross-over frequency (fc) is 65 kHz. The power stage gain (gmPS ) is 10 A/V and the GM amplifier gain (gM ) is 130 A/V. R12 = 2p x fc x Vo x Co g M x Vref x gm ps (21) 2. Place compensation zero at low frequency to boost the phase margin at the crossover frequency. From the procedures above, the compensation network includes a 20-k resistor (R12) and a 4700-pF capacitor (C1). 3. An additional pole can be added to attenuate high frequency noise. From the procedures above, the compensation network includes a 20-k resistor (R12) and a 4700-pF capacitor (C14). 3.3-V and 6.5-V LDO Regulators The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins: * 10 F for V7V pin 28 * 3.3 F for V3V pin 29 Layout Recommendation Layout is a critical portion of PMIC designs. * Place VOUT, and LX on the top layer and an inner power plane for VIN. * Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with ground. * The top layer ground area sould be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter cpacitor and directly under the TPS65251 device to provide a thermal path from the Powerpad land to ground. * The AGND pin should be tied directly to the power pad under the IC and the power pad. * For operation at full rated load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating area. * There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching node, the output inductor should be located close to the LX pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. * The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. * The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive to noise so the components associated to these pins should be located as close as possible to the IC and routed with minimal lengths of trace. 24 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated Product Folder Link(s): TPS65251 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS65251RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS65251RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65251RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS65251RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 TPS65251RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65251RHAR VQFN RHA 40 2500 367.0 367.0 38.0 TPS65251RHAT VQFN RHA 40 250 210.0 185.0 35.0 TPS65251RHAT VQFN RHA 40 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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