FEDR27T3202F-002-04
Issue Date: Jul. 9, 2004
MR27T3202F
2M–Word × 16–Bit or 4M–Word × 8–Bit P2ROM
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FEATURES
· 2,097,152-word × 16-bit / 4,194,304-word × 8-bit electrically
switchable configuration
· 2.7 V to 3.6 V power supply
· Access time 90 ns MAX
· Operating current 20 mA MAX (5MHz)
· Standby current 10 µA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR27T3202F-xxxMA
44-pin plastic SOP (SOP44-P-600-1.27-K)
· MR27T3202F-xxxTP
44-pin plastic TSOP (TSOP II 44-P-400-0.80-K)
· MR27T3202F-xxxTN
48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor’s technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to f inal production testing. Advancements in this
technology allo ws production costs to be equivalent to
MASKROM an d has many advantages and added bene fits ov er
the other non-vo lati l e technol ogies, which include the
following;
· Short lea d time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are m aintained to prov ide an agg ressiv e lead-tim e
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and
OTP that require additional progra mming and handling
costs, the P2ROM already has the code loaded at the
factory with minimal effect on the production throughput.
The cost is included in the unit price.
· Custom Marking is available at no additional charge.
· Pin Compatible with Ma sk RO M and some FLASH
products.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48TSOP(Type-I)
PIN CONFIGURATION (TOP VIEW)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
D0
D8
D1
D9
D2
D10
D3
D11
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
D15/A–1
D7
D14
D6
D13
D5
D12
D4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44SOP,
44TSOP(Type-II)
A16
BYTE#
VSS
D15/A–1
D7
D14
D6
D13
D5
D12
D4
VCC
D11
D3
D10
D2
D9
D1
D8
D0
OE#
VSS
CE#
A0
FEDR27T3202F-002-04
MR27T3202F / P2ROM
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BLOCK DIAGRAM
PIN DESCRIPTIONS
Pin name Functions
D15 / A–1 Data output / Address input
A0 to A20 Address inputs
D0 to D14 Data outputs
CE# Chip enable input
OE# Output enable input
BYTE# Word / Byte select input
VCC Power supply voltage
VSS Ground
NC No connect
A
0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
CE# BYTE#
OE#
CE OE
× 8/× 16 Switch
D0 D2 D4 D6 D8 D10 D12 D14
D1 D3 D5 D7 D9 D11 D13 D15
Memory Cell Matrix
2M × 16-Bit or 4M × 8-Bit
Multiplexer
Output Buffer
Row Decoder
Column Decoder
Address Buffer
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
A–1
FEDR27T3202F-002-04
MR27T3202F / P2ROM
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FUNCTION TABLE
Mode CE# OE# BYTE# VCC D0 to D7 D8 to D14 D15/A–1
Read (16-Bit) L L H DOUT
Read (8-Bit) L L L DOUT Hi–Z L/H
H
Output disable L H L
Hi–Z
H
Standby H L
3.0 V
Hi–Z
: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Value Unit
Operating temperature under bias Ta 0 to 70 °C
Storage temperature Tstg –55 to 125 °C
Input voltage VI –0.5 to VCC+0.5 V
Output voltage VO –0.5 to VCC+0.5 V
Power supply voltage VCC relative to VSS –0.5 to 5 V
Power dissipation per package PD Ta = 25°C 1.0 W
Output short circuit current IOS 10 mA
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter Symbol Condition Min. Typ. Max. Unit
VCC power supply voltage VCC 2.7 3.6 V
Input “H” level VIH 2.2 VCC+0.5 V
Input “L” level VIL VCC = 2.7 to 3.6 V –0.5∗∗ 0.6 V
Voltage is relative to VSS.
: Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
(VCC = 3.0 V, Ta = 25°C, f = 1 MHz)
Parameter Symbol Condition Min. Typ. Max. Unit
Input CIN18
BYTE# CIN2 VI = 0 V — — 120
Output COUT V
O = 0 V 10 pF
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(VCC = 2.7 V to 3.6 V, Ta = 0 to 70°C)
Parameter Symbol Condition Min. Typ. Max. Unit
Input leakage current ILI V
I = 0 to VCC10 μA
Output leakage current ILO V
O = 0 to VCC10 μA
ICCSC CE# = VCC10 μA VCC power supply current
(Standby) ICCST CE# = VIH1 mΑ
VCC power supply current
(Read) ICCA CE# = VIL, OE# = VIH
f=5MHz — — 20 mA
Input “H” level VIH — 2.2 VCC+0.5 V
Input “L” level VIL–0.5∗∗ 0.6 V
Output “H” level VOH I
OH = –1 mA 2.4 V
Output “L” level VOL I
OL = 2 mA 0.4 V
Voltage is relative to VSS.
: Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
(VCC = 2.7 V to 3.6 V, Ta = 0 to 70°C)
Parameter Symbol Condition Min. Max. Unit
Address cycle tim e tC 90 ns
Address access time tACC CE# = OE# = VIL — 90 ns
CE# access time tCE OE# = VIL 90 ns
OE# access time tOE CE# = VIL 30 ns
tCHZ OE# = VIL 0 30 ns
Output disable time tOHZ CE# = VIL 0 25 ns
Output hold time tOH CE# = OE# = VIL 0 — ns
Measurement conditions
Input signal level --------------------------------------0 V / 3 V
Input timing reference level-------------------------1/2 Vcc
Output load---------------------------------------------50 pF
Output timing reference level ----------------------1/2 Vcc
Output load
Output
50 pF
(Including scope and jig)
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TIMING CHART (READ CYCLE)
8-Bit Read Mode (BYTE# = VIL)
A-1 to A20
CE#
OE#
D0 to D7
tC
tCE
tOE
tOH
tCHZ
tOHZ
Valid Data
Hi-Z Hi-Z
tOH
Valid Data
tACC
tC
tACC
16-Bit Read Mode (BYTE# = VIH)
A0 to A20
CE#
OE#
D0 to D15
tC
tCE
tOE
tOH
tCHZ
tOHZ
Valid Data
Hi-Z Hi-Z
tOH
Valid Data
tACC
tC
tACC
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PACKAGE DIMENSIONS
SOP44-P-600-1.27-K
Mirror finish
Package material Epoxy resin
Lead frame material 42 alloy
Pin treatment Solder plating (5μm)
Package weight (g) 2.10 TYP.
5
Rev. No./Last Revised 4/Dec. 5, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow
method, temperature and times).
(Unit: mm)
FEDR27T3202F-002-04
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TSOP(2)44-P-400-0.80-K
Mirror finish
Package material Epoxy resin
Lead frame material 42 alloy
Pin treatment Solder plating (5μm)
Package weight (g) 0.54 TYP.
5
Rev. No./Last Revised 3/Dec. 10, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow
method, temperature and times).
(Unit: mm)
FEDR27T3202F-002-04
MR27T3202F / P2ROM
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TSOP(1)48-P-1220-0.50-1K
Mirror finish
Package material Epoxy resin
Lead frame material 42 alloy
Pin treatment Solder plating (5μm)
Package weight (g) 0.55 TYP.
5
Rev. No./Last Revised 1/Dec. 2, 1999
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow
method, temperature and times).
(Unit: mm)
FEDR27T3202F-002-04
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REVISION HISTORY
Page
Document
No. Date Previous
Edition Current
Edition
Description
FEDR27T3202F-02-01 Oct., 2000 Final edition 1
Changed tC, tACC, tCE to 90ns
Added ICCA2 at tC = 200ns
Change the symbo l, ICCA to ICCA1
Changed ICCA1 to 30mA
Changed tOE to 30ns
Changed ICCSC to 10uA
Changed IOH, the condition of VOH, to
–1 mA
5 4
Changed IOL, the condit ion of V OL, to
2 mA
FEDR27T3202F-02-02 Mar., 2002
1-4, 7 1-3 Changed the form
1 1 Change 48TSOP(1) package code to –1K
FEDR27T3202F-02-03 Jun. 4, 2003 1, 4 1, 4 Unify ICCA condition into f=5MHz
FEDR27T3202F-02-04 Jul. 9, 2004 3 3 Add PD condition and IOS = 10mA
FEDR27T3202F-002-04
MR27T3202F / P2ROM
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