LTM4622A
1
Rev B
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual Ultrathin 2A or Single 4A
Step-Down DC/DC µModule Regulator
The LT M
®
4622A is a complete dual 2A step-down switching
mode µModule
®
(micromodule) regulator in a tiny ultrathin
6.25mm × 6.25mm × 1.82mm LGA and 2.42mm BGA pack-
ages. Included in the package are the switching controller,
power FETs, inductor and support components. Operating
over an input voltage range of 3.6V to 20V, the LTM4622A
supports an output voltage range of 1.5V to 12V, set by a
single external resistor. Its high efficiency design delivers
dual 2A continuous, 3A peak, output current. Only a few
ceramic input and output capacitors are needed.
The LTM4622A supports selectable Burst Mode operation
and output voltage tracking for supply rail sequencing. Its
high switching frequency and current mode control enable
a very fast transient response to line and load changes
without sacrificing stability.
Fault protection features include input overvoltage, output
overcurrent and overtemperature protection.
The LTM4622A is available with SnPb (BGA) or RoHS
compliant terminal finish.
Product Selection Guide
PART NUMBER VIN RANGE VOUT RANGE IOUT
LTM4622 3.6V to 20V 0.6V to 5.5V Dual 2.5A or Single 5A
LTM4622A 1.5V to 12V Dual 2A or Single 4A
3.3V and 5V Dual Output DC/DC Step-Down µModule Regulator
12V Input, 3.3V and 5V Output,
Efficiency vs Load Current
APPLICATIONS
n Complete Solution in <1cm2
n Wide Input Voltage Range: 3.6V to 20V
n 1.5V to 12V Output Voltage
n Dual 2A (3A Peak) or Single 4A Output Current
n ±1.5% Maximum Total Output Voltage Regulation
Error Over Load, Line and Temperature
n Current Mode Control, Fast Transient Response
n External Frequency Synchronization
n Multiphase Parallelable with Current Sharing
n Output Voltage Tracking and Soft-Start Capability
n Selectable Burst Mode
®
Operation
n Overvoltage Input and Overtemperature Protection
n Power Good Indicators
n 6.25mm × 6.25mm × 1.82mm LGA and
6.25mm × 6.25mm × 2.42mm BGA Packages
n General Purpose Point-of-Load Conversion
n Telecom, Networking and Industrial Equipment
n Medical Diagnostic Equipment
n Test and Debug Systems
All registered trademarks and trademarks are the property of their respective owners.
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
70
75
80
85
90
95
100
EFFICIENCY (%)
4622A TA01b
VOUT = 5V
VOUT = 3.3V
13.3k
4622A TA01a
4.7µF
25V
VIN
8V TO 20V
VOUT1
3.3V, 2A
47µF
VOUT1
V
OUT2
5V, 2A
47µF
VOUT2
FB1
COMP1
COMP2
GND
LTM4622A
PGOOD1 PGOOD2
VIN2
VIN1
RUN1
RUN2
INTVCC
SYNC/MODE
TRACK/SS1
TRACK/SS2
FREQ 8.25k
FB2
LTM4622A
2
Rev B
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN1, VIN2 ................................................... –0.3V to 22V
VOUT ........................................................... –0.3V to 16V
PGOOD1, PGOOD2 ..................................... –0.3V to 18V
RUN1, RUN2 .................................... –0.3V to VIN + 0.3V
INTVCC, TRACK/SS1, TRACK/SS2 ............ –0.3V to 3.6V
SYNC/MODE, COMP1, COMP2,
FB1, FB2 ........................................... –0.3V to INTVCC
Operating Internal Temperature Range
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Body Temperature ................. 260°C
(Note 1)
(See Pin Functions, Pin Configuration Table)
ORDER INFORMATION
PART NUMBER PAD OR BALL FINISH
PART MARKING* PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)DEVICE FINISH CODE
LT M4622AEV#PBF Au (RoHS) LT M4622AV e4 LGA 4 –40°C to 125°C
LT M4622AIV#PBF Au (RoHS) LT M4622AV e4 LGA 4 –40°C to 125°C
LT M4622AEY#PBF SAC305 (RoHS) LT M4622AY e1 BGA 4 –40°C to 125°C
LT M4622AIY#PBF SAC305 (RoHS) LT M4622AY e1 BGA 4 –40°C to 125°C
LT M4622AIY SnPb (63/37) LT M4622AY e0 BGA 4 –40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
LGA PACKAGE
25-LEAD (6.25mm × 6.25mm × 1.82mm)
TOP VIEW
COMP2
SYNC/
MODE
FREQ
VOUT1
FB1
PGOOD1
TRACK/SS1
A
5
1
2
3
4
PGOOD2
FB2
TRACK/SS2
INTVCC
RUN2
B C D E
COMP1GND GND
RUN1
GND
VIN1
VIN1
VIN2
VIN2
VOUT2
TJMAX = 125°C, θJCtop = 17°C/W, θJCbottom = 11°C/ W,
θJB + θBA = 22°C/W, θJA = 22°C/W,
WEIGHT = 0.21g
BGA PACKAGE
25-LEAD (6.25mm × 6.25mm × 2.42mm)
TOP VIEW
COMP2
SYNC/
MODE
FREQ
VOUT1
FB1
PGOOD1
TRACK/SS1
A
5
1
2
3
4
PGOOD2
FB2
TRACK/SS2
INTVCC
RUN2
B C D E
COMP1GND GND
RUN1
GND
VIN1
VIN1
VIN2
VIN2
VOUT2
TJMAX = 125°C, θJCtop = 17°C/W, θJCbottom = 11°C/ W,
θJB + θBA = 22°C/W, θJA = 22°C/W,
WEIGHT = 0.25g
http://www.linear.com/product/LTM4622A#orderinfo
LTM4622A
3
Rev B
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ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C, VIN1 = VIN2 = 12V, unless otherwise
noted per the typical application shown in Figure27.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator Section: per Channel
VIN1 Input DC Voltage Range l3.6 20 V
VIN2 Input DC Voltage Range 3.6V < VIN1 < 20V l1.5 20 V
VOUT(RANGE) Output Voltage Range VIN1 = VIN2 = 3.6V to 20V l1.5 12 V
VOUT(DC) Output Voltage, Total Variation
with Line and Load
CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k,
MODE = INTVCC,VIN1 = VIN2 = 3.6V to 20V, IOUT = 0A to 2A
l1.477 1.50 1.523 V
VRUN RUN Pin On Threshold RUN Threshold Rising
RUN Threshold Falling
1.20
0.97
1.27
1.00
1.35
1.03
V
V
IQ(VIN) Input Supply Bias Current VIN1 = VIN2 = 12V, VOUT = 1.5V, MODE = GND
VIN1 = VIN2 = 12V, VOUT = 1.5V, MODE = INTVCC
Shutdown, RUN1 = RUN2 = 0
7
500
45
mA
µA
µA
IS(VIN) Input Supply Current VIN1 = VIN2 = 12V, VOUT = 1.5V, IOUT = 2A 0.32 A
IOUT(DC) Output Continuous Current Range VIN1 = VIN2 = 12V, VOUT = 1.5V (Note 3) l0 2 A
ΔVOUT(Line)/VOUT Line Regulation Accuracy VOUT = 1.5V, VIN1 = VIN2 = 3.6V to 20V, IOUT = 0A l0.01 0.1 %/V
ΔVOUT(Load)/VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 2A l0.2 1.0 %
VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic, VIN1 = VIN2 = 12V,
VOUT = 1.5V
5 mV
ΔVOUT(START) Turn-On Overshoot IOUT = 0A, COUT = 100µF Ceramic, VIN1 = VIN2 = 12V,
VOUT = 1.5V
30 mV
tSTART Turn-On Time COUT = 100µF Ceramic, No Load, TRACK/SS = 0.01µF,
VIN1 = VIN2 = 12V, VOUT = 1.5V
1.25 ms
ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 100µF
Ceramic, VIN1 = VIN2 = 12V, VOUT = 1.5V
100 mV
tSETTLE Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load, COUT = 100µF
Ceramic, VIN1 = VIN2 = 12V, VOUT = 1.5V
20 µs
IOUTPK Output Current Limit VIN1 = VIN2 = 12V, VOUT = 1.5V 3 4 A
VFB Voltage at FB Pin IOUT = 0A, VOUT = 1.5V l0.592 0.60 0.608 V
IFB Current at FB Pin (Note 4) ±30 nA
RFBHI Resistor Between VOUT and FB Pins 60.00 60.40 60.80 kΩ
ITRACK/SS Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V 1.25 µA
tSS Internal Soft-Start Time 10% to 90% Rise Time (Note 4) 400 700 μs
tON(MIN) Minimum On-Time (Note 4) 20 ns
tOFF(MIN) Minimum Off-Time (Note 4) 45 ns
VPGOOD PGOOD Trip Level VFB With Respect to Set Output
VFB Ramping Negative
VFB Ramping Positive
–8
8
–14
14
%
%
RPGOOD PGOOD Pull-Down Resistance 1mA Load 20 Ω
VINTVCC Internal VCC Voltage VIN1 = VIN2 = 3.6V to 20V 3.1 3.3 3.5 V
LTM4622A
4
Rev B
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4622A is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4622AE is guaranteed to meet performance
specifications over the 0°C to 125°C internal operating temperature
range. Specifications over the full –40°C to 125°C internal operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTM4622AI is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmentalfactors.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VINTVCC Load Reg INTVCC Load Regulation ICC = 0mA to 50mA 1.3 %
fOSC Oscillator Frequency 1 MHz
fSYNC Frequency Sync Range With Respect to Set Frequency ±30 %
IMODE MODE Input Current MODE = INTVCC –1.5 µA
Note 3: See output current derating curves for different VIN, VOUT and TA.
Note 4: 100% tested at wafer level.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C, VIN1 = VIN2 = 12V, unless otherwise
noted per the typical application shown in Figure27.
LTM4622A
5
Rev B
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TYPICAL PERFORMANCE CHARACTERISTICS
1.5V Output Transient Response
8V Output Transient Response
Efficiency vs Load Current
at 5VIN
Efficiency vs Load Current
at 12VIN
Burst Mode Efficiency,
12VIN, 1.5VOUT
5V Output Transient Response
3.3V Output Transient Response
Efficiency vs Load Current
at 16VIN
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
4622A G01
3.3V OUTPUT, 1MHz
1.5V OUTPUT, 1MHz
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
4622A G02
8V OUTPUT, 1.5MHz
5V OUTPUT, 1.5MHz
3.3V OUTPUT, 1MHz
1.5V OUTPUT, 1MHz
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2.0
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
4622A G03
3.3V OUTPUT, 1MHz
1.5V OUTPUT, 1MHz
12V OUTPUT, 1.5MHz
8V OUTPUT, 1.5MHz
5V OUTPUT, 1.5MHz
LOAD CURRENT (mA)
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
4622A G04
Burst Mode OPERATION
CMM
12V Output Transient Response
50µs/DIV
LOAD STEP
1A/DIV
VOUT
AC-COUPLED
50mV/DIV
4622A G05
VIN = 12V, VOUT = 1.5V, fSW = 1MHz
OUTPUT CAPACITOR = 47µF ×1 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
50µs/DIV
LOAD STEP
1A/DIV
VOUT
AC-COUPLED
50mV/DIV
4622A G06
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
OUTPUT CAPACITOR = 47µF ×1 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
50µs/DIV
LOAD STEP
1A/DIV
VOUT
AC-COUPLED
100mV/DIV
4622A G07
VIN = 12V, VOUT = 5V, fSW = 1MHz
OUTPUT CAPACITOR = 47µF ×2 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
50µs/DIV
LOAD STEP
1A/DIV
VOUT
AC-COUPLED
100mV/DIV
4622A G08
VIN = 12V, VOUT = 8V, fSW = 1.5MHz
OUTPUT CAPACITOR = 47µF ×2 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
50µs/DIV
LOAD STEP
1A/DIV
VOUT
AC-COUPLED
100mV/DIV
4622A G09
VIN = 16V, VOUT = 12V, fSW = 1.5MHz
OUTPUT CAPACITOR = 47µF ×2 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
LTM4622A
6
Rev B
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Start-Up with No Load
CurrentApplied
Start-Up with 2A Load
CurrentApplied
Recover from Short-Circuit with
No Load Current Applied
Short-Circuit with No Load
Current Applied
Short-Circuit with 2A Load
Current Applied Steady-State Output Voltage Ripple
TYPICAL PERFORMANCE CHARACTERISTICS
10ms/DIV
VOUT
2V/DIV
RUN
10V/DIV
IIN
0.5A/DIV
4622A G11
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
OUTPUT CAPACITOR = 10µF CERAMIC
+ 47µF POSCAP
SOFT-START CAP = 0.1µF
20µs/DIV
4622A G14
IIN
1A/DIV
VOUT
2V/DIV
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
OUTPUT CAPACITOR = 10µF + 47µF POSCAP
10ms/DIV
VOUT
2V/DIV
RUN
10V/DIV
IIN
1A/DIV
4622A G10
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
OUTPUT CAPACITOR = 10µF CERAMIC
+ 47µF POSCAP
SOFT-START CAP = 0.1µF
20µs/DIV
4622A G12
VOUT
2V/DIV
IIN
1A/DIV
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
OUTPUT CAPACITOR = 10µF CERAMIC
+ 47µF POSCAP
20µs/DIV
4622A G13
VOUT
2V/DIV
IIN
1A/DIV
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
OUTPUT CAPACITOR = 10µF + 47µF POSCAP
20µs/DIV
VOUT
AC-COUPLED
10mV/DIV
4622A G15
VIN = 12V, VOUT = 3.3V, fSW = 1MHz
OUTPUT CAPACITOR = 10µF + 47µF POSCAP
LTM4622A
7
Rev B
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PIN FUNCTIONS
VIN1 (D3, E2), VIN2 (A2, B3): Power Input Pins. Apply
input voltage between these pins and GND pins. Rec-
ommend placing input decoupling capacitance directly
between BOTH VIN1 and VIN2 pins and GND pins. Please
note the module internal control circuity is running off
VIN1. Channel 2 will not work without a voltage higher that
3.6V presents at VIN1.
GND (C1 to C2, B5, D5): Power Ground Pins for Both
Input and Output Returns.
INTVCC (C3): Internal 3.3V Regulator Output. The internal
power drivers and control circuits are powered from this
voltage. This pin is internally decoupled to GND with a
2.2µF low ESR ceramic capacitor. No additional external
decoupling capacitor needed.
SYNC/MODE (C5): Mode Select and External Synchroni-
zation Input. Tie this pin to ground to force continuous
synchronous operation at all output loads. Floating this pin
or tying it to INTVCC enables high efficiency BurstMode
operation at light loads. Drive this pin with a clock to syn-
chronize the LTM4622A switching frequency. An internal
phase-locked loop will force the bottom power NMOS’s
turn on signal to be synchronized with the rising edge
of the clock signal. When this pin is driven with a clock,
forced continuous mode is automatically selected.
VOUT1 (D1, E1), VOUT2 (A1, B1): Power Output Pins of
Each Switching Mode Regulator. Apply output load between
these pins and GND pins. Recommend placing output
decoupling capacitance directly between these pins and
GND pins.
FREQ (C4): Frequency is set internally to 1MHz. An
external resistor can be placed from this pin to GND to
increase frequency, or from this pin to INTVCC to reduce
frequency. See the Applications Information section for
frequency adjustment.
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
RUN1 (D2), RUN2 (B2): Run Control Input of Each Switch-
ing Mode Regulator Channel. Enables chip operation by
tying RUN above 1.27V. Tying this pin below 1V shuts
down the specific regulator channel. Do not float this pin.
PGOOD1 (D4), PGOOD2 (B4): Output Power Good with
Open-Drain Logic of Each Switching Mode Regulator
Channel. PGOOD is pulled to ground when the voltage
on the FB pin is not within ±8% (typical) of the internal
0.6V reference.
TRACK/SS1 (E3), TRACK/SS2 (A3): Output Tracking
and Soft-Start Pin of Each Switching Mode Regulator
Channel. It allows the user to control the rise time of the
output voltage. Putting a voltage below 0.6V on this pin
bypasses the internal reference input to the error ampli-
fier, instead it servos the FB pin to the TRACK voltage.
Above 0.6V, the tracking function stops and the internal
reference resumes control of the error amplifier. There’s
an internal 1.4µA pull-up current from INTVCC on this pin,
so putting a capacitor here provides soft-start function.
A default internal soft-start ramp forces a minimum soft-
start time of 400µs.
FB1 (E4), FB2 (A4): The Negative Input of the Error
Amplifier for Each Switching Mode Regulator Channel.
Internally, this pin is connected to VOUT with a 60.4k preci-
sion resistor. Different output voltages can be programmed
with an additional resistor between FB and GND pins. In
PolyPhase
®
operation, tying the FB pins together allows
for parallel operation. See the Applications Information
section for details.
COMP1 (E5), COMP2 (A5): Current Control Threshold
and Error Amplifier Compensation Point of Each Switch-
ing Mode Regulator Channel. The current comparator’s
trip threshold is linearly proportional to this voltage,
whose normal range is from 0.3V to 1.8V. Tie the COMP
pins together for parallel operation. The device is internal
compensated. Do not drive this pin.
LTM4622A
8
Rev B
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BLOCK DIAGRAM
DECOUPLING REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN External Input Capacitor Requirement
(VIN = 3.6V to 20V, VOUT = 1.5V)
IOUT = 2A 4.7 10 µF
COUT External Output Capacitor Requirement
(VIN = 3.6V to 20V, VOUT = 1.5V)
IOUT = 2A 22 47 µF
Figure1. Simplified LTM4622A Block Diagram
POWER CONTROL
FB2
60.4k
2.2µF
0.1µF
8.25k
0.22µF 10µF
INTVCC
VOUT2
TRACK/SS2
0.1µF
TRACK/SS1
RUN1
RUN2
SYNC/MODE
COMP1
0.1µF
VOUT1
VIN1
VIN2
10k
PGOOD1
VOUT1
3.3V
2A
VIN
8V TO 20V
INTVCC
GND
2.2µH
4622A BD
FREQ
324k
INTERNAL
COMP
COMP2
FB1
60.4k
13.3k
VOUT1
10k
PGOOD2 INTVCC
10µF
47µF
0.22µF
0.1µF
VOUT2 VOUT2
5V
2A
GND
2.2µH
47µF
INTERNAL
COMP
LTM4622A
9
Rev B
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OPERATION
APPLICATIONS INFORMATION
The LTM4622A is a dual output standalone non-isolated
switch mode DC/DC power supply. It can deliver two 2A
DC, 3A peak output current with few external input and
output ceramic capacitors. This module provides dual
precisely regulated output voltage programmable via two
external resistor from 1.5V to 12V over 3.6V to 20V input
voltage range. The typical application schematic is shown
in Figure27.
The LTM4622A contains an integrated controlled on-time
valley current mode regulator, power MOSFETs, inductors,
and other supporting discrete components. The default
switching frequency is 1MHz. For output voltages above
3.3V, an external resistor is required between FREQ and
GND pins to set the operating frequency to 1.5MHz to
2MHz to optimize inductor current ripple. For switching
noise-sensitive applications, the switching frequency can
be adjusted by external resistors and the μModule regulator
can be externally synchronized to a clock within ±30% of
the set frequency. See the Applications Information section.
With current mode control and internal feedback loop
compensation, the LTM4622A module has sufficient
stability margins and good transient performance with
a wide range of output capacitors, even with all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast cur-
rent limiting. An internal overvoltage and undervoltage
comparators pull the open-drain PGOOD output low if the
output feedback voltage exits a ±8% window around the
regulation point. Furthermore, an input overvoltage protec-
tion been utilized by shutting down both power MOSFETs
when VIN rises above 22.5V to protect internal devices.
Multiphase operation can be easily employed by connecting
SYNC pin to an external oscillator. Up to 6 phases can be
paralleled to run simultaneously a good current sharing
guaranteed by current mode control loop.
Pulling the RUN pin below 1V forces the controller into
its shutdown state, turning off both power MOSFETs and
most of the internal control circuitry. At light load currents,
Burst Mode operation can be enabled to achieve higher
efficiency compared to continuous mode (CCM) by set-
ting MODE pin to INTVCC. The TRACK/SS pin is used for
power supply tracking and soft-start programming. See
the Applications Information section.
The typical LTM4622A application circuit is shown in
Figure 27. External component selection is primarily
determined by the input voltage, the output voltage and
the maximum load current. Refer to Table7 for specific
external capacitor requirements for a particular application.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT step
down ratio that can be achieved for a given input voltage
due to the minimum off-time and minimum on-time limits
of the regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
DC(MAX) = 1 – tOFF(MIN) • fSW
where tOFF(MIN) is the minimum off-time, 45ns typical for
LTM4622A, and fSW is the switching frequency. Conversely
the minimum on-time limit imposes a minimum duty cycle
of the converter which can be calculated as:
DC(MIN) = tON(MIN) • fSW
where tON(MIN) is the minimum on-time, 20ns typical for
LTM4622A. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
LTM4622A
10
Rev B
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APPLICATIONS INFORMATION
Output Decoupling Capacitors
With an optimized high frequency, high bandwidth design,
only single piece of 47µF low ESR output ceramic capaci-
tor is required for each LTM4622A output to achieve low
output voltage ripple and very good transient response.
Additional output filtering may be required by the system
designer, if further reduction of output ripples or dynamic
transient spikes is required. Table7 shows a matrix of dif-
ferent output voltages and output capacitors to minimize the
voltage droop and overshoot during a 1A (50%) load step
transient. Multiphase operation will reduce effective output
ripple as a function of the number of phases. Application
Note 77 discusses this noise reduction versus output
ripple current cancellation, but the output capacitance
will be more a function of stability and transient response.
The Linear Technology LTpowerCAD
®
Design Tool is avail-
able to download online for output ripple, stability and
transient response analysis and calculating the output
ripple reduction as the number of phases implemented
increases by N times.
Burst Mode Operation
In applications where high efficiency at intermediate current
are more important than output voltage ripple, Burst Mode
operation could be used by connecting SYNC/MODE pin
to INTVCC to improve light load efficiency. In Burst Mode
operation, a current reversal comparator (IREV) detects
the negative inductor current and shuts off the bottom
power MOSFET, resulting in discontinuous operation and
increased efficiency. Both power MOSFETs will remain
off and the output capacitor will supply the load current
until the COMP voltage rises above the zero current level
to initiate another cycle.
Force Continuous Current Mode (CCM) Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation should
be used. Forced continuous operation can be enabled by
tying the SYNC/MODE pin to GND. In this mode, induc-
tor current is allowed to reverse during low output loads,
the COMP voltage is in control of the current comparator
threshold throughout, and the top MOSFET always turns
Output Voltage Programming
The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 60.4k 0.5% internal
feedback resistor connects VOUT and FB pins together.
Adding a resistor RFB from FB pin to GND programs the
output voltage:
RFB =
0.6V
V
OUT
– 0.6V • 60.4k
Table1. VFB Resistor Table vs Various Output Voltages
(1% Resistor)
VOUT (V) 1.5 1.8 2.5 3.3 5.0 8.0 10.0 12.0
RFB (k) 40.2 30.1 19.1 13.3 8.25 4.87 3.83 3.16
Pease note that for output above 3.3V, a higher operating
frequency is required to optimize inductor current ripple.
See Operating Frequency section.
For parallel operation of N-channels LTM4622A, the fol-
lowing equation can be used to solve for RFB:
RFB =0.6V
V
OUT
– 0.6V •60.4k
N
Input Decoupling Capacitors
The LTM4622A module should be connected to a low AC-
impedance DC source. For each regulator channel, one piece
4.7µF input ceramic capacitor is required for RMS ripple
current decoupling. Bulk input capacitor is only needed
when the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
The bulk capacitor can be an electrolytic aluminum capaci-
tor and polymer capacitor.
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN(RMS) =
I
OUT(MAX)
η%• D • 1– D
( )
where is the estimated efficiency of the power module.
LTM4622A
11
Rev B
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APPLICATIONS INFORMATION
on with each oscillator pulse. During start-up, forced
continuous mode is disabled and inductor current is
prevented from reversing until the LTM4622A’s output
voltage is in regulation.
Operating Frequency
The operating frequency of the LTM4622A is optimized
to achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
The default operating frequency is internally set to 1MHz.
If any operating frequency other than 1MHz is required by
application, the operating frequency can be increased by
adding a resistor, RFSET, between the FREQ pin and GND,
as shown in Figure29. The operating frequency can be
calculated as:
f Hz
( )
=
3.2e11
324k||R
FSET
Ω
( )
Please note a minimum switching frequency is required for
given VIN, VOUT operating conditions to keep a maximum
peak-to-peak inductor ripple current below 1.2A for the
LTM4622A.
The peak-to-peak inductor ripple current can be calculated as:
ΔIP-P = VOUT
2.2 1−VOUT
VIN
⎛
⎝
⎜
⎜
⎜
⎞
⎠
⎟
⎟
⎟ • 1
fSW (MHz)
The maximum 1.2A peak-to-peak inductor ripple current
is enforced due to the nature of the valley current mode
control to maintain output voltage regulation at no load.
To reduce switching current ripple, 1.5MHz to 2MHz op-
erating frequency is suggested for 5V and above output
with RFSET to GND.
VOUT 1.5V to 3.3V 5V, 8V 12V
fSW 1MHz 1.5MHz 1.5MHz to 2MHz
The operating frequency can also be decreased by adding
a resistor between the FREQ pin and INTVCC, calculated as:
f Hz
( )
=1MHz –
5.67e11
RFSET Ω
( )
The programmable operating frequency range is from
800kHz to 4MHz.
Frequency Synchronization
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of the external clock. The
external clock frequency range must be within ±30%
around the set operating frequency. A pulse detection
circuit is used to detect a clock on the SYNC/MODE pin
to turn on the phase-locked loop. The pulse width of the
clock has to be at least 100ns. The clock high level must
be above 2V and clock low level below 0.3V. The presence
of an external clock will place both regulator channels into
forced continuous mode operation. During the start-up of
the regulator, the phase-locked loop function is disabled.
Multiphase Operation
For output loads that demand more than 2A of current, two
outputs in the LTM4622A or even multiple LTM4622As can
be paralleled to run out of phase to provide more output
current without increasing input and output voltage ripples.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage).
The output ripple amplitude is also reduced by the number
of phases used when all of the outputs are tied together
to achieve a single high output current design.
The two switching mode regulator channels inside the
LTM4622A are internally set to operate 180° out of phase.
Multiple LTM4622As could easily operate 90 degrees, 60
degrees or 45 degrees shift which corresponds to 4-phase,
6-phase or 8-phase operation by letting SYNC/MODE of
the LTM4622A synchronize to an external multiphase
oscillator like LTC
®
6902. Figure2 shows a 4-phase design
example for clock phasing.
LTM4622A
12
Rev B
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The LTM4622A device is an inherently current mode
controlled device, so parallel modules will have very
good current sharing. This will balance the thermals on
the design. Please tie RUN, TRACK/SS, FB and COMP pin
of each paralleling channel together. Figure31 shows an
example of parallel operation and pin connection.
INPUT RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved phases.
Figure3 shows this graph.
Soft-Start and Output Voltage Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on the TRACK/SS pin will program the ramp rate
of the output voltage. An internal 1.4µA current source
will charge up the external soft-start capacitor towards
INTVCC voltage. When the TRACK/SS voltage is below
0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time
can be calculated as:
tSS = 0.6 • CSS
1.4µA
where CSS is the capacitance on the TRACK/SS pin. Current
foldback and force continuous mode are disabled during
the soft-start process.
The LTM4622A has internal 400μs soft-start time when
TRACK/SS leave floating.
APPLICATIONS INFORMATION
Figure3. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
Figure2. Example of Clock Phasing for 4-Phase
Operation with LTC6902
4622A F02
V+
3.3V INTVCC
PH
SET
LTC6902
200k
0°
SYNC/MODE VOUT1 8A
180°
VOUT2
DIV
GND
90°
SYNC/MODE VOUT1
270°
0°
90° VOUT2
MOD
OUT1
OUT2
0.75 0.8
4622A F03
0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85
0.9
DUTY FACTOR (VOUT/VIN)
0
DC LOAD CURRENT
RMS INPUT RIPPLE CURRENT
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
LTM4622A
13
Rev B
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Output voltage tracking can also be programmed externally
using the TRACK/SS pin. The output can be tracked up and
down with another regulator. Figure4 and Figure5 show
an example waveform and schematic of a Ratiometric
tracking where the slave regulator’s output slew rate is
proportional to the master’s.
The RFB(SL) is the feedback resistor and the RTR(TOP)/
RTR(BOT) is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure5.
Following the upper equation, the master’s output slew
rate (MR) and the slave’s output slew rate (SR) in Volts/
Time is determined by:
MR
SR =
R
FB(SL)
RFB(SL) + 60.4k
RTR(TOP)
RTR(TOP) +RTR(BOT)
For example, VOUT(MA) = 1.5V, MR = 1.5V/ms and VOUT(SL)
= 3.3V, SR = 3.3V/ms. From the equation, we could solve
out that RTR(TOP) =60.4k and RTR(BOT) = 40.2k is a good
combination for the Ratiometric tracking.
The TRACK pins will have the 1.5µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
The Coincident output tracking can be recognized as a
special Ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), as waveform shown in Figure6.
Figure5. Example Schematic of Ratiometric
Output Voltage Tracking
Figure6. Output Coincident Tracking Waveform
TIME
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT VOLTAGE
4622A F06
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a RTR(TOP)/RTR(BOT) resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should satisfy
the following equation during the start-up.
VOUT(SL) •RFB(SL)
RFB(SL) + 60.4k =
VOUT(MA) •RTR(TOP)
RTR(TOP) +RTR(BOT)
Figure4. Output Ratiometric Tracking Waveform
TIME
SLAVE OUTPUT
MASTER OUTPUT
OUTPUT VOLTAGE
4622A F04
40.2k
4622A F05
10µF
25V
VIN
4V TO 20V
VOUT1
1.5V, 2A
47µF
6.3V
0.1µF
VOUT1
VOUT2
3.3V, 2A
47µF
6.3V
VOUT2
FB1
COMP1
COMP2
FREQ GND
LTM4622A
PGOOD1 PGOOD2
VIN2
VIN1
RUN1
RUN2
INTVCC
SYNC/MODE
TRACK/SS1
TRACK/SS2
13.3k
40.2k
60.4k
FB2
VOUT1
LTM4622A
14
Rev B
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From the equation, we could easily find out that, in the
coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its feedback divider.
R
FB(SL)
RFB(SL) + 60.4k =
R
TR(BOT)
RTR(TOP) +RTR(BOT)
For example, RTR(TOP) = 60.4k and RTR(BOT) = 13.3k is a
good combination for coincident tracking for VOUT(MAX)
= 1.5V and VOUT(SL) = 3.3V application.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a ±8% window around the regulation point. A resistor can
be pulled up to a particular supply voltage for monitoring.
To prevent unwanted PGOOD glitches during transients or
dynamic VOUT changes, the LTM4622A’s PGOOD falling
edge includes a blanking delay of approximately 40µs.
Stability compensation
The LTM4622A module internal compensation loop is
designed and optimized for low ESR ceramic output
capacitors only application. Table7 is provided for most
application requirements. The LTpowerCAD Design Tool
is available to down for control loop optimization.
RUN Enable
Pulling the RUN pin to ground forces the LTM4622A into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Trying the RUN pin
voltage above 1.27V will turn on the entire chip.
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4622A can safely power up into
a pre-biased output without discharging it.
The LTM4622A accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
Overtemperature Protection
The internal overtemperature protection monitors the junc-
tion temperature of the module. If the junction temperature
reaches approximately 160°C, both power switches will be
turned off until the temperature drops about 15°C cooler.
Input Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTM4622A constantly
monitors each VIN pin for an overvoltage condition. When
VIN rises above 22.5V, the regulator suspends operation
by shutting off both power MOSFETs on the correspond-
ing channel. Once VIN drops below 21.5V, the regulator
immediately resumes normal operation. The regulator
executes its soft-start function when exiting an overvolt-
age condition.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parameters defined by JESD51-9 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware test
board—also defined by JESD51-9 (Test Boards for Area
Array Surface Mount Package Thermal Measurements).
The motivation for providing these thermal coefficients in
found in JESD51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plication at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
LTM4622A
15
Rev B
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software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coef-
ficients are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambi-
ent, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as still air although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
2. θJCbottom, the thermal resistance from junction to
ambient, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as still air although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θJCbottom and the thermal re-
sistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure7; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule.
Figure7. Graphical Representation of JESD51-12 Thermal Coefficients
4622A F07
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION
AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
LTM4622A
16
Rev B
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As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal op-
erating conditions of a μModule. For example, in normal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclu-
sively through the top or exclusively through bottom of the
µModule—as the standard defines for θJCtop and θJCbottom,
respectively. In practice, power loss is thermally dissipated
in both directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all of
the correct material coefficients along with accurate power
loss source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
process and due-diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory test have been performed and correlated to the
µModule model, then the θJB and θBA are summed together
to correlate quite well with the µModule model with no
airflow or heat sinking in a properly define chamber. This
θJB + θBA value is shown in the Pin Configuration section
and should accurately equal the θJA value because ap-
proximately 100% of power loss flows from the junction
through the board into ambient with no airflow or top
mounted heat sink.
The 1.5V, 3.3V, 5V, 8V and 12V power loss curves in
Figure8 to Figure12 can be used in coordination with the
load current derating curves in Figure13 to Figure23 for
calculating an approximate θJA thermal resistance for the
LTM4622A (in two-phase single output operation) with no
heat sinking and various airflow conditions. The power loss
curves are taken at room temperature, and are increased
with multiplicative factors of 1.35 assuming junction
temperature at 120°C. The derating curves are plotted
with the output current starting at 4A and the ambient
temperature at 30°C. These output voltages are chosen
to include the lower and higher output voltage ranges
for correlating the thermal resistance. Thermal models
are derived from several temperature measurements in a
controlled temperature chamber along with thermal mod-
eling analysis. The junction temperatures are monitored
while ambient temperature is increased with and without
airflow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature. The
decreased output current will decrease the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operat-
ing temperature specifies how much module temperature
rise can be allowed. As an example in Figure16, the load
current is derated to ~3A at ~100°C with 200LFM air but
not heat sink and the power loss for the 5V to 3.3V at 3A
output is about 1.15W. The 1.15W loss is calculated with
the ~0.85W room temperature loss from the 5V to 3.3V
power loss curve at 3A, and the 1.35 multiplying factor.
If the 100°C ambient temperature is subtracted from the
120°C junction temperature, then the difference of 20°C
divided by 1.15W equals a 17.5°C/W θJA thermal resis-
tance. Table3 specifies a 17°C/W – 18°C/W value which
is very close. Tables 2 to 6 provide equivalent thermal
resistances for 1.5V, 3.3V, 5V, 8V and 12V outputs with
LTM4622A
17
Rev B
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Figure8. 1.5V Output Power Loss Figure9. 3.3V Output Power Loss Figure10. 5V Output Power Loss
APPLICATIONS INFORMATION
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1.0
1.5
2.0
2.5
POWER LOSS (W)
4622A F08
VIN = 16V
VIN = 12V
VIN = 5V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1.0
1.5
2.0
2.5
POWER LOSS (W)
4622A F09
VIN = 16V
VIN = 12V
VIN = 5V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1.0
1.5
2.0
2.5
POWER LOSS (W)
4622A F10
VIN = 16V
VIN = 12V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1.0
1.5
2.0
2.5
POWER LOSS (W)
4622A F11
VIN = 16V
VIN = 12V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1.0
1.5
2.0
2.5
POWER LOSS (W)
4622A F12
VIN = 16V
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F13
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F14
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F15
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F16
0LFM
200LFM
400LFM
Figure11. 8V Output Power Loss Figure12. 12V Output Power Loss Figure13. 5V Input to 1.5V Output
Derating Curve, No Heat Sink
Figure14. 12V Input to to 1.5V Output
Derating Curve, No Heat Sink
Figure15. 16V Input to 1.5V Output
Derating Curve, No Heat Sink
Figure16. 5V Input to 3.3V Output
Derating Curve, No Heat Sink
LTM4622A
18
Rev B
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Figure18. 16V Input to 3.3V Output
Derating Curve, No Heat Sink
Figure19. 12V Input to 5V Output
Derating Curve, No Heat Sink
Figure17. 12V Input to 3.3V Output
Derating Curve, No Heat Sink
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F17
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F18
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F19
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F20
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F21
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F22
0LFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
30
40
50
60
70
80
90
100
110
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CURRENT (A)
4622A F23
0LFM
200LFM
400LFM
Figure20. 16V Input to 5V Output
Derating Curve, No Heat Sink
Figure21. 12V Input to 8V Output
Derating Curve, No Heat Sink
Figure22. 16V Input to 8V Derating
Curve, No Heat Sink
Figure23. 16V Input to 12V Output
Derating Curve, No Heat Sink
LTM4622A
19
Rev B
For more information www.analog.com
Table2. 1.5V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA(°C/W)
Figures 13, 14, 15 5, 12, 16 Figure8 0 None 19–20
Figures 13, 14, 15 5, 12, 16 Figure8 200 None 17–18
Figures 13, 14, 15 5, 12, 16 Figure8 400 None 17–18
Table3. 3.3V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA(°C/W)
Figures 16, 17, 18 5, 12, 16 Figure9 0 None 19–20
Figures 16, 17, 18 5, 12, 16 Figure9 200 None 17–18
Figures 16, 17, 18 5, 12, 16 Figure9 400 None 17–18
Table4. 5V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA(°C/W)
Figures 19, 20 12, 16 Figure10 0 None 19–20
Figures 19, 20 12, 16 Figure10 200 None 17–18
Figures 19, 20 12, 16 Figure10 400 None 17–18
Table5. 8V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA(°C/W)
Figures21, 22 5, 12 Figure11 0 None 19–20
Figures21, 22 5, 12 Figure11 200 None 17–18
Figures21, 22 5, 12 Figure11 400 None 17–18
Table6. 12V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA(°C/W)
Figure23 5, 12 Figure12 0 None 19–20
Figure23 5, 12 Figure12 200 None 17–18
Figure23 5, 12 Figure12 400 None 17–18
APPLICATIONS INFORMATION
LTM4622A
20
Rev B
For more information www.analog.com
APPLICATIONS INFORMATION
Table7. Output Voltage Response for Each Regulator Channel vs Component Matrix (Refer to Figure24)
1.0A Load Step Typical Measured Values
CIN
(CERAMIC) PART NUMBER VALUE
COUT1
(CERAMIC) PART NUMBER VALUE
COUT2
(BULK) PART NUMBER VALUE
Murata GRM188R61E475KE11# 4.7µF, 25V,
0603, X5R
Murata GRM21R60J476ME15# 47µF, 6.3V,
0805, X5R
Panasonic 6TPC150M 150µF, 6.3V 3.5
× 2.8 × 1.4mm
Murata GRM188R61E106MA73# 10µF, 25V,
0603, X5R
Murata GRM188R60J226MEA0# 22µF, 6.3V,
0603, X5R
Taiyo Yuden TMK212BJ475KG-T 4.7µF, 25V,
0805, X5R
Taiyo
Yuden
JMK212BJ476MG-T 47µF, 6.3V,
0805, X5R
VOUT
(V)
CIN
(CERAMIC)
(μF)
CIN
(BULK)
COUT1
(CERAMIC)
(μF)
COUT2
(BULK)
(μF)
CFF
(pF) VIN (V)
DROOP
(mV)
P-P
DERIVATION
(mV)
RECOVERY
TIME (μs)
LOAD
STEP (A)
LOAD STEP
SLEW RATE
(A/μs)
RFB
(kΩ)
1.5 10 0 1 × 47 0 10 5, 12 0 89 10 1.0 10 40.2
1.5 10 0 1 × 4.7 150 0 5, 12 0 75 20 1.0 10 40.2
2.5 10 0 1 × 47 0 10 5, 12 0 112 10 1.0 10 19.1
2.5 10 0 1 × 4.7 150 0 5, 12 0 92 25 1.0 10 19.1
3.3 10 0 1 × 47 0 10 5, 12 0 144 15 1.0 10 13.3
3.3 10 0 1 × 4.7 150 0 5, 12 0 104 30 1.0 10 13.3
5 10 0 2 × 47 0 10 12 0 157 25 1.0 10 8.25
5 10 0 1 × 4.7 150 0 12 0 137 50 1.0 10 8.25
8 10 0 2 × 47 0 10 12 0 234 50 1.0 10 4.87
8 10 0 2 × 4.7 150 0 12 0 149 70 1.0 10 4.87
12 10 0 3 × 47 0 10 16 0 301 50 1.0 10 3.16
12 10 0 3 × 4.7 150 0 16 0 177 80 1.0 10 3.16
LTM4622A
21
Rev B
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 24 and Figure 25 show measured temperature
picture of the LTM4622A with no heat sink from 12V
input down to 3.3V and 5V output with 2A DC current on
each and from 12V down to 5V and 8V output with 2A
DC current on each. Both without heat sink and airflow.
SAFETY CONSIDERATIONS
The LTM4622A modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and over current protection.
and without airflow. The derived thermal resistances in
Tables 2 to 6 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves in
the Typical Performance Characteristics section and ad-
justed with the above ambient temperature multiplicative
factors. The printed circuit board is a 1.6mm thick four
layer board with two ounce copper for the two outer layers
and one ounce copper for the two inner layers. The PCB
dimensions are 95mm × 76mm.
LTM4622A
23
Rev B
For more information www.analog.com
APPLICATIONS INFORMATION
Figure26. Recommended PCB Layout
LAYOUT CHECKLIST/EXAMPLE
The high integration of LTM4622A makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout con-
siderations are still necessary.
• Use large PCB copper areas for high current paths,
including VIN1, VIN2, GND, VOUT1 and VOUT2. It helps
to minimize the PCB conduction loss and thermal
stress.
• Place high frequency ceramic input and output capaci-
tors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath
theunit.
• The two dedicated input decoupling capacitors, one for
each VIN, closely placed on each side of the module.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP pins
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring.
Figure26 gives a good example of the recommended layout.
4622A F26
GND
VOUT2
VOUT1
VIN2
VIN1
LTM4622A
24
Rev B
For more information www.analog.com
Figure27. 8VIN to 20VIN, 3.3V and 5V Output at 2A Design
APPLICATIONS INFORMATION
13.3k
4622A F27
VIN
8V TO 20V
VOUT1
3.3V, 2A
47µF
0.1µF
0.1µF
VOUT1
V
OUT2
5V, 2A
47µF
VOUT2
FB1
COMP1
COMP2
FREQ GND
LTM4622A
PGOOD1 PGOOD2
VIN2
VIN1
RUN2
RUN1
INTVCC
SYNC/MODE
TRACK/SS1
TRACK/SS2
8.25k
FB2
10µF
10µF
6.65k
4622A F28
VOUT
3.3V, 4A
47µF
×2µF
0.1µF
VOUT1
VOUT2
FB1
COMP1
COMP2
FREQ GND
LTM4622A
PGOOD1 PGOOD2
INTVCC
PGOOD
SYNC/MODE
TRACK/SS1
TRACK/SS2 FB2
VIN
4V TO 20V
VIN2
VIN1
RUN2
RUN1
10µF
10µF
3.16k
4622A F29
VOUT1
12V, 2A
47µF
0.1µF
0.1µF
VOUT1
V
OUT2
8V, 2A
47µF
VOUT2
FB1
COMP1
COMP2
FREQ GND
LTM4622A
PGOOD1 PGOOD2
INTVCC
SYNC/MODE
TRACK/SS1
TRACK/SS2
4.87k
FB2
324k
VIN
16V TO 20V
VIN2
VIN1
RUN2
RUN1
10µF
10µF
Figure28. 4VIN to 20VIN, 3.3V Two Phase in Parallel 4A Design
Figure29. 16VIN to 20VIN, 12V and 8V Output at 2A with 2MHz Switching Frequency
LTM4622A
25
Rev B
For more information www.analog.com
APPLICATIONS INFORMATION
Figure30. 4VIN to 20VIN, 1.5V and 3.3V Output at 2A Design with Output Coincident Tracking
0.1µF
13.3k
60.4k
VOUT1
40.2k
4622A F30
VOUT1
1.5V, 2A
47µF
VOUT1
VOUT2
3.3V, 2A
47µF
VOUT2
FB1
COMP1
COMP2
FREQ GND
LTM4622A
PGOOD1 PGOOD2
INTVCC
SYNC/MODE
TRACK/SS1
TRACK/SS2
13.3k
FB2
VIN
4V TO 20V
VIN2
VIN1
RUN2
RUN1
10µF
10µF
10k
10µF
×4
VIN
4V TO 20V
VOUT
1.5V, 8A
1µF
47µF
×4
0.1µF
VOUT1
VOUT2
FB1
COMP1
COMP2
FREQ GND
LTM4622A
PGOOD1 PGOOD2
PGOOD
VIN2
RUN1
VIN1
RUN2
INTVCC
INTV
CC
SYNC/MODE
TRACK/SS1
TRACK/SS2 FB2
4622A F31
VOUT1
VOUT2
FB1
COMP1 COMP
COMP
FB
COMP2
FREQ GND
LTM4622A
PGOOD1 PGOOD2
VIN2
RUN1
VIN1
RUN2
INTVCC
PGOOD
SYNC/MODE
TRACK/SS1
TRACK/SS2 FB2
SET
MOD
OUT3
GND
OUT4
LTC6902
200k
V+
DIV
OUT2
PH
OUT1
FB
Figure31. 4 Phase, 1.5V Output at 8A Design with LTC6902
LTM4622A
26
Rev B
For more information www.analog.com
PACKAGE DESCRIPTION
LTM4622A Component LGA and BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 VOUT2 A2 VIN2 A3 TRACK/SS2 A4 FB2 A5 COMP2
B1 VOUT2 B2 RUN2 B3 VIN2 B4 PGOOD2 B5 GND
C1 GND C2 GND C3 INTVCC C4 FREQ C5 SYNC/MODE
D1 VOUT1 D2 RUN1 D3 VIN1 D4 PGOOD1 D5 GND
E1 VOUT1 E2 VIN1 E3 TRACK/SS1 E4 FB1 E5 COMP1
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4622A
27
Rev B
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4622A#packaging for the most recent package drawings.
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
YX
aaa Z
aaa Z
DETAIL A
PACKAGE BOTTOM VIEW
3
SEE NOTES
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
2.540
1.270
1.270
2.540
2.540
1.270
2.540
1.270
0.3175
0.3175 0.000
E
D
C
B
A
12345
PIN 1
Øb (25 PLACES)
D
E
e
b
F
G
DETAIL A
0.3175
0.3175
LGA 25 0613 REV Ø
LTMXXXXXX
µModule
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
LGA Package
25-Lead (6.25mm × 6.25mm × 1.82mm)
(Reference LTC DWG # 05-08-1949 Rev Ø)
7
SEE NOTES
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
LAND DESIGNATION PER JESD MO-222, SPP-010
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 25
4
3
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
DETAIL B
DETAIL B
SUBSTRATE
MOLD
CAP
// bbb Z
Z
A
SYMBOL
A
b
D
E
e
F
G
H1
H2
aaa
bbb
eee
MIN
1.72
0.60
0.27
1.45
NOM
1.82
0.63
6.25
6.25
1.27
5.08
5.08
0.32
1.50
MAX
1.92
0.66
0.37
1.55
0.15
0.10
0.15
NOTES
DIMENSIONS
TOTAL NUMBER OF LGA PADS: 25
H2
H1
SYXZØ eee
LTM4622A
28
Rev B
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4622A#packaging for the most recent package drawings.
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
YX
aaa Z
aaa Z
DETAIL A
PACKAGE BOTTOM VIEW
3
SEE NOTES
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
2.540
1.270
1.270
2.540 0.630 ±0.025
2.540
1.270
2.540
1.270
0.3175
0.3175 0.000
E
D
C
B
A
12345
PIN 1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
Øb (25 PLACES)
A
DETAIL B
PACKAGE SIDE VIEW
MX YZddd
MZeee
A2
D
E
e
b
F
G
DETAIL A
0.3175
0.3175
BGA 25
0517 REV A
LTMXXXXXX
µModule
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
BGA Package
25-Lead (6.25mm × 6.25mm × 2.42mm)
(Reference LTC DWG # 05-08-1502 Rev A)
6
SEE NOTES
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
2.22
0.50
1.72
0.60
0.60
0.27
1.45
NOM
2.42
0.60
1.82
0.75
0.63
6.25
6.25
1.27
5.08
5.08
0.32
1.50
MAX
2.62
0.70
1.92
0.90
0.66
0.37
1.55
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 25
DIMENSIONS
NOTES
BALL HT
BALL DIMENSION
PAD DIMENSION
SUBSTRATE THK
MOLD CAP HT
Z
5. PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
DETAIL B
SUBSTRATE
A1
ccc Z
Z
// bbb Z
H2
H1
b1
MOLD
CAP
LTM4622A
29
Rev B
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 11/17 Corrected Pin Configuration. Swapped VIN1 and VIN2. 2
B 4/18 Corrected RFSET to GND 9, 11
LTM4622A
30
Rev B
For more information www.analog.com
ANALOG DEVICES, INC. 2017-2018
D16848-0-4/18(B)
www.analog.com
RELATED PARTS
PACKAGE PHOTOS
PART NUMBER DESCRIPTION COMMENTS
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DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
