STK14D88
32Kx8 AutoStore nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-52037 Rev. *A Revised December 01, 2009
Features
■25, 35, 45 ns Read Access and R/W Cycle Time
■Unlimited Read/Write Endurance
■Automatic Nonvolatile STORE on Power Loss
■Nonvolatile STORE Under Hardware or Software Control
■Automatic RECALL to SRAM on Power Up
■Unlimited RECALL Cycles
■200K STORE Cycles
■20-Year Nonvolatil e Data Retention
■Single 3.0V +20%, -10% Power Supply
■Commercial, Industrial Temperatures
■Small Footprint SOIC and SSOP Packages (RoHS-Compliant)
Description
The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.
Data transfers automatically to the nonvolatile storage cells
when power loss is de tected (th e STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatil e memory available.
A
0
A
1
A
2
A
3
A
4
A
10
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
ROW DECODER
INPUT BUFFERS
Quantum Trap
512 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
POWER
CONTROL
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
G
E
W
HSB
V
CCX
V
CAP
A
0
- A
13
Logic Block Diagram
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Document Number: 001-52037 Rev. *A Page 2 of 18
Contents
Features ................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions.................................................................. 3
Absolute Maximum Ratings ............................................... 4
DC Characteristics ....................... ... ... ................................. 4
AC Test Conditions............................................................. 5
Capacitance ......................................................................... 5
SRAM READ Cycles #1 and #2..................................... 6
SRAM WRITE Cycle #1 and #2 ..................................... 7
AutoStore/POWER UP RECALL............. ... ... ...................... 8
Software-Controlled STORE/RECALL Cycle. .................... 9
Hardware STORE Cycle..................................................... 10
Soft Sequence Commands............................................... 10
Mode Selection................................................................... 11
nvSRAM Operation............................................................ 12
nvSRAM....................................................................... 12
SRAM READ................................................................ 12
SRAM WRITE.............................................................. 12
AutoStore Operation... ... ... .............................................12
Hardware STORE (HSB) Operation............................. 12
Software STORE.................... .. ... ................................. 12
Software RECALL............ ............................................ 13
Data Protection............................................................. 13
Best Practices .............................................................. 13
Low Average Active Power .......................................... 13
Noise Considerations................................................... 14
Preventing AutoStore.......... ... .. .................................... 14
Part Numbering Nomenclature......................................... 16
Package Diagrams............................................................. 17
Document History Page.............. .. ..................................... 19
Sales, Solutions, and Legal Information......................... 19
Worldwide Sales and Design Support.......................... 19
Products....................................................................... 19
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Pin Configurations Figure 1. Pin Diagr a m 48 -Pin SSOP/32-SOIC
Pin Descriptions
Pin Name I/O Description
A14-A0Input Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
DQ7-DQ0I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM
EInput Chip Enable: The active low E input selects the device
WInput Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E
GInput Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
VCC Power Supply Power: 3.0V, +20%, -10%
HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin
high if not connected. (Connection Optiona l).
VCAP Power Supply AutoS t o r e Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS Power Supply Ground
NC No Connect Unlabeled pins have no internal connections.
48-Pin SSOP
TOP
VSS
A14
A12
A7
A6
DQ0
DQ1
VCC
DQ2
A3
A2
A1
VCAP
A13
A8
A9
A11
A10
DQ7
DQ6
VSS
A0
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
E
NC
NC 23
24
A5
NC
NC
NC
NC
NC
NC
A4
48
47
46
45
VCC
HSB
NC
NC
W
NC
NC
DQ5
DQ3
DQ4
G
NC NC
32-SOIC
TOP
VSS
A14
A12
A7
A6
DQ0
VCAP
A13
A8
A9
A11
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A5
A4
32
31
30
29
VCC
HSB
W
A3
A2
A1
A0
DQ1
DQ2
A10
DQ7
DQ5
DQ3
DQ4
DQ6
NCNC
E
G
SSOP
Relative PCB Area Usage[1]
Note
1. See “Package Diagrams” on page 16 for detailed package size specifications.
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Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to VSS...........–0.6V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB............ .. ........–0.5V to (VCC + 0.5V)
Temperature under Bias............................... –55°C to 125°C
Storage Temperature.............. ...................... –65°C to 140°C
Power Dissipation................ ... ..........................................1W
DC Output Current (1 output at a time, 1s duration)....15 mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
θjc 5.4 C/W; θja 44.3 [0 fpm], 37.9 [200 fpm], 35.1 C/W [500 fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
θjc 6.2 C/W; θja 51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm].
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only , and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
DC Characteristics
(VCC = 2.7V-3.6V)
Symbol Parameter[2] Commercial Industrial Unit Notes
Min Max Min Max
ICC1A verage VCC Current 65
55
50
70
60
55
mA
mA
mA
tAVAV = 25 ns
tAVAV = 35 ns
tAVAV = 45 ns
Dependent on output loadin g and
cycle rate. Values obtained without
output loads.
ICC2A verage VCC Current during
STORE 3 3 mA All Inputs Don’t Care, VCC = max
Average current for duration of
STORE cycle (tSTORE)
ICC3A verage VCC Current at tAVAV =
200ns
3V, 25°C, Typical
10 10 mA W ≥ (VCC – 0.2V)
All Others Cycling, CMOS Levels
Dependent on output loadin g and
cycle rate. Values obtained without
output loads.
ICC4A verage VCAP Current du ri n g
AutoStore Cycle 3 3 mA All Inputs Don’t Care
Average current for duration of
STORE cycle (tSTORE)
ISB VCC Standby Current
(Standby, Stable CMOS Input
Levels)
33mAE ≥ (VCC
– 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
S tandby current level after nonvolatile
cycle complete
IILK Input Leakage Current ±1±1μAV
CC = max
VIN = VSS to VCC
IOLK Off State Output Leakage Current ±1±1μAV
CC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH Input Logic “1” Voltage 2.0 VCC + .5 2.0 VCC + .5 V All Inputs
VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
VOH Output Logic “1” Voltage 2.4 2.4 V IOUT = –2 mA
VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 4 mA
Note:
2. The HSB pin has IOUT=-10uA for VOH of 2.4V, this parameter is charact erized but not tested
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TAOperating Temperature 0 70 -40 85 °C
VCC Operating Voltage 2.7 3.6 2.7 3.6 V 3.3V +20%, -10%
VCAP Storage Capacitance 17 120 17 120 μFBetween V
CAP pin and VSS, 5V Rated
DATARData Retention 20 20 K
NVCNonvolatile STORE Operations 200 200 Years At 55°C
AC Test Conditions
Figure 2. AC Output Loading
Figure 3. AC Output Loading for Tri-state Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ
Capacitance
Parameter[3] Description Test Conditions Max Unit Conditions
CIN Input Capacitance TA = 2 5°C, f = 1 MHz, 7 pF ΔV = 0 to 3V
COUT Output Capacita nce 7 pF ΔV = 0 to 3V
DC Characteristics (continued)
(VCC = 2.7V-3.6V)
Symbol Parameter[2] Commercial Industrial Unit Notes
Min Max Min Max
Input Pulse Levels. ...................................................0V to 3V
Input Rise and Fall Times ............................................ <5 ns
Input and Output Timing Referenc e Levels.................... 1.5V
Output Load..................................See Figure 2 and Figure 3
577
Ω
30 pF
789
Ω
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
577
Ω
5 pF
789
Ω
3.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
Note
3. These paramet ers are guaranteed but not tested.
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Figure 5. SRAM READ Cycle 2: E Controlled [4, 7]
SRAM READ Cycles #1 and #2
NO. Symbols Parameter STK14D88-25 STK14D88-35 STK14D88-45 Unit
Min Max Min Max Min Max#1 #2 Alt.
1t
ELQV tACS Chip Enable Access Time 25 35 45 ns
2t
AVAV[4] tELEH[4] tRC Read Cycle Time 25 35 45 ns
3t
AVQV[5] tAVQV[5] tAA Address Access Time 25 35 45 ns
4t
GLQV tOE Output Enable to Data Valid 12 15 20 ns
5t
AXQX[5] tAXQX[5] tOH Output Hold after Address Change 3 3 3 ns
6t
ELQX tLZ Address Change or Chip Enable to
Output Active 333ns
7t
EHQZ[6] tHZ Address Change or Chip Disable to
Output Inactive 10 13 15 ns
8t
GLQX tOLZ Output Enable to Output Active 0 0 0 ns
9t
GHQZ[6] tOHZ Output Disable to Output Inactive 10 13 15 ns
10 tELICCH[3] tPA Chip Enable to Power Active 0 0 0 ns
11 tEHICCL[3] tPS Chip Disable to Power Standby 25 35 45 ns
Figure 4. SRAM READ Cycle 1: Address Controlled [4, 5, 6]
Notes
4. W must be high during SRAM READ cycles.
5. Device is continuou sly selected with E and G both low.
6. Measured ± 200 mV from steady state ou tput voltage.
7. HSB must remain high during READ and WRITE cycles.
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
229
11
7
9
10
84
3
61
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SRAM WRITE Cycle #1 and #2
NO. Symbols Parameter STK14D88-25 STK14D88-35 STK14D88-45 Unit
Min Max Min Max Min Max#1 #2 Alt.
12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns
13 tWLWH tWLEH tWP Write Pulse Width 20 2 5 30 ns
14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns
16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns
19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns
20 tWLQZ[6, 8] tWZ Write Enable to Output Disable 10 13 15 ns
21 tWHQX tOW Output Active after End of Writ e 3 3 3 ns
Figure 6. SRAM WRITE Cycle 1: W Controlled [8 , 9]
Figure 7. SRAM WRITE Cycle 2: E Controlled [8, 9]
DATA OUT
E
ADDRESS
W
DAT A IN
PREVIOUS DATA
12
tAVAV
13
tWHDX
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
12
tAVAV
16
tEHDX
13
tWLEH
19
tEHAX
18
tAVEL
17
tAVEH
DATA VALID
15
tDVEH
HIGH IMPEDANCE
14
tELEH
DATA OUT
E
ADDRESS
W
DATA IN
Notes
8. If W is low when E goes low, the outputs remain in the high-impedance state.
9. E or W must be ≥ VIH during address transit i ons.
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AutoS tore/POWER UP RECALL
No. Symbols Alt. Parameter STK14D88 Unit Notes
Min Max
22 tRECALL Po wer up RECALL Duration 20 ms 10
23 tSTORE tHLHZ STORE Cycle Duration 12.5 ms 11, 12
24 VSWITCH Low Voltage Trigger Level 2.65 V
25 VCCRISE Vcc Rise Time 150 μs
Figure 8. AutoStore /POWER UP RECALL
Note: Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH
22
23 23
22 22
Notes
10.tHRECALL starts from the time VCC rises above VSWITCH.
11. If an SRAM WRITE has not taken place since the last nonvolati l e cycle, no STORE will take place.
12.Industrial Grade Devices require 15 ms Max.
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Software-Controlled STORE/RECALL Cycle[13, 14]
No. Symbols Parameter STK14D88-25 STK14D88-35 STK14D88-45 Unit Notes
E Cont Alternate Min Max Min Max Min Max
26 tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 ns 14
27 tAVEL tAS Address Setup Time 0 0 0 ns
28 tELEH tCW Clock Pulse Width 20 25 30 ns
29 tEHAX Address Hold Time 1 1 1 ns
30 tRECALL RECALL Duration 50 50 50 μs
Figure 9. E and G Controlled Software STORE/RECALL Cycle[14]
DATA VALID HIGH IMPEDANCE
ADDRESS #6ADDRESS #1
DATA VALID
26
tAVAV
DATA VALID
DQ (DATA
E
ADDRESS
23 30
tSTORE / tRECALL
26
tAVAV
27
tAVEL 28
tELEH
29
tELAX
Notes
13.The software sequence is clocked on the falling edge of E controlled READs.
14.The six consecutive addresses must be read in the order listed in the soft ware STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles
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Hardware STORE Cycle
NO. Symbols Parameter STK14D88 Unit Notes
Standard Alternate Min Max
31 tDELAY tHLQZ Hardware STORE to SRAM Disabled 1 70 µs 15
32 tHLHX Hardware STORE Pulse Width 15 ns
Figure 10. Hardware STORE Cycle
32
23
31
Soft Sequence Commands
NO. Symbols Parameter STK14D88 Unit Notes
Standard Min Max
33 tSS Soft Sequence Processing Time 70 µs 16, 17
Figure 11. Software Sequence Commands
33 33
Notes
15.Read and Write cycles in progress before HSB is asserted are gi ven this minimum amount of time to complete.
16.This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
17.Commands like Store and Recall lock out I/O until operation is comple te which further increases this time. See specific command.
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Mode Selection
E W G A14–A0Mode IO Power Notes
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active 18, 19, 20
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active 18, 19, 20
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active
18, 19, 20
0x0FC0 Nonvolatile Store Output High Z ICC2
L H L 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active 18, 19, 20
Notes
18.The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
19.While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes
20.I/O state depends on the state of G. The I/O tabl e shown assumes G low.
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nvSRAM Operation
nvSRAM
The STK14D88 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are the SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates like a standard fast static RAM. Data in the
SRAM can be transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architectu re allows a ll cells to be stored
and recalled in parallel. During the STORE and RECALL opera-
tions SRAM READ and WRITE operations are inhibited. The
STK14D88 supports unlimited read and writes like a typical
SRAM. In addition, it provides unlimited RECALL operations
from the nonvolatile cells and up to 200K STORE operations.
SRAM READ
The STK14D88 performs a READ cycle whenever E and G are
low while W and HSB are high. The address specified on pins
A0-16 determine which of the 32,768 data bytes will be accessed.
When the READ is initiated by an address transition, the outputs
will be valid after a delay of tAVQV (READ cycle #1). If the READ
is initiated by E and G, the outputs will be valid at tELQV or at
tGLQV, whichever is later (READ cycle #2). The data outputs
repeatedly respond to address changes within the tAVQV access
time without the need for transitions on any control input pins,
and remain valid u ntil another address change o r until either E
or G is brought high, or W or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E or W goes
high at the end of the cycle. The data on the common I/O pins
DQ0-7 will be written into memory if it is valid tDVWH before the
end of a W controlled WRITE or tDVEH before the end of an E
controlled WR I TE.
It is recommended that G be kept high during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If G is
left low , internal circuitry will turn off the output buffers tWLQZ after
W goes low.
AutoStore Operation
The STK14D88 stores data to nvSRAM using one of three
storage operations. These three operations are Hardware Store
(activated by HSB), Software Store (activated by an address
sequence), and AutoStore (on power down).
AutoStore operation is a unique feature of Cypress Quantum
Trap technology is enabled by default on the STK14D88.
During normal operation, the device will draw current from V CC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH,
the part will automatically disconnect the VCAP pin from VCC. A
STORE operation will be initiated with power provided by the
VCAP capacitor.
Figure 12 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC CHARAC-
TERISTICS table for the size of the capacitor . The voltage on the
VCAP pin is driven to 5V by a charge pump internal to the chip. A
pull up should be placed on W to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whe ther a WRITE o peration has taken
place. The HSB signal can be monitored by the system to detect
an AutoStore cycle is in progress.
Figure 12. AutoStore Mode
Hardware STORE (HSB) Operation
The STK14D88 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin is
driven low, the STK14D88 will conditionally initiate a STORE
operation after tDELAY. An actual STORE cycle will only begin if
a WRITE to the SRAM took place since the last STORE or
RECALL cycle. The HSB pin has a very resistive pull up a nd is
internally driven low to indicate a busy condition while the
STORE (initiated by any means) is in progress. This pin should
be externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operati ons that are in prog ress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low , the
STK14D88 continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low, it will be allowed
a time, tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until HSB returns
high.
If HSB is not used, it should be left unconnected.
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK14D88
software STORE cycle is initiated by executing sequential E
controlled READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data is erased
and then the new data is programmed into the nonvolatile
elements. Once a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
VCC
VCAP
10k Ohm
0.1µF
VCC
VCAP
W
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Document Number: 001-52037 Rev. *A Page 13 of 18
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0FC0, Initiate STORE Cycle
After the sixth address in the sequence has been entered, the
STORE cycle begins and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence.
After the tSTORE cycle time has been fulfilled, the SRAM is again
activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled READ
operations must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0C63, Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is trans-
ferred into the SRAM cells. After the tRECALL cycle time, the
SRAM will once again be ready for READ or WRITE operations.
The RECALL operation in no way alters the da ta in the nonvol-
atile storage elements.
Data Protection
The STK14D88 protects data from corruption during low-voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low-voltage condition i s detected when
VCC<VSWITCH.
If the STK14D88 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE will be
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as be st practices:
■The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality as surance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on, should always program a unique
NV pattern (for example, a complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■Power up boot firmware routines should rewrite the nvSRAM
into the desired state (such as AutoS tore enabled). While the
nvSRAM is shipped in a preset state, best practice is to rewrite
the nvSRAM into the desired state as a safeguard against
events that might flip the bit inadvertently (such as program
bugs, incoming inspection routines, and others).
■If AutoStore has been firmware disabled, it will not reset to
“autostore enabled” on every power down event captured by
the nvSRAM. The application firmware should re-en able or
re-disable AutoSt ore on each reset sequence based on the
behavior desired.
■The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max VCAP value because the
nvSRAM internal algorithm calculates VCAP charge time based
on this max VCAP value. Customers who want to use a larger
VCAP value to make sure there is extra store charge and store
time should discuss their VCAP size selection with Cypress to
understand any impact on the VCAP voltage level at the end of
a tRECALL period.
Low Average Active Power
CMOS technology provides the STK14D88 with the benefit of
power supply current that scales with cycle time. Less current will
be drawn as the memory cycle time becomes longer than 50 ns.
Figure 13 shows the relationship between ICC and
READ/WRITE cycle time. Worst-case current consumption is
shown for commercial temperature range, VCC = 3.6V, and chip
enable at maximum frequency. Only standby current is drawn
when the chip is disabled. The overall average current drawn by
the STK14D88 depends on the following items:
■The duty cycle of chip enable
■The overall cycle rate for operations
■The ratio of READs to WRITEs
■The operating temp erature
■The VCC level
■I/O loading
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Document Number: 001-52037 Rev. *A Page 14 of 18
Figure 13. Current versus Cycle Time
Noise Considerations
The STK14D88 is a high speed memory and so must have a high
frequency bypass capacitor of 0.1 µF connected between both
VCC pins and VSS ground plane with no plane break to chip VSS.
Use leads and traces that are as short as possible. As with all
high speed CMOS ICs, careful routing of power, ground, and
signals will reduce circuit noise.
Preventing AutoStore
The AutoStore function can be disabled by initiating an
AutoStore Disable sequence. A sequence of READ operations
is performed in a manner similar to the software STORE initi-
ation. To initiate the AutoSt ore Disable sequence, the following
sequence of E controlled or G controlled READ operations must
be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x03F8, AutoStore Disable
The AutoStore can be re-enabled by initiating an AutoStore
Enable sequence. A sequence of READ operations is performed
in a manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following sequence of E
controlled or G controlled READ operations must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x07F0, AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) needs to be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
In all cases, make sure the READ sequence is uninterrupted. For
example, an interrupt that occurs in the sequence that reads the
nvSRAM would abort this sequence, resulting in an error.
Average Act iv e Current (mA)
100 150 200 300
0
10
20
30
40
50
Writes
Reads
Cycle Time (ns)
50
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Document Number: 001-52037 Rev. *A Page 15 of 18
Ordering Codes
These parts are not recommended for new designs.
Part Numbering Nomenclature
Packaging Option:
TR = Tape and Reel
Blank = Tube
Speed:
25 - 25 ns
35 - 35 ns
Package:
N =
Plastic 32-pin 300 mil SOIC (5 0 mi l pi tch)
Temperature Range:
Blank - Commercial (0 to 70 °C )
R =
Plastic 48-pin 300 mil SSOP(25 mil pitch)
Lead Finish
F = 100% Sn (Matte Tin) ROHS Compliant 45 - 45 ns
I - Industrial (-4 0 to 85 °C )
STK14D88 - R F 45 I TR
Part Number Description Access Times Temperature
STK14D88-NF25 3V 32Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial
STK14D88-NF35 3V 32Kx8 AutoStore nvSRAM SOP32-300 35 ns Commercial
STK14D88-NF45 3V 32Kx8 AutoStore nvSRAM SOP32-300 45 ns Commercial
STK14D88-NF25TR 3V 32Kx8 AutoStore nvSRAM SOP32-300 25 ns Commercial
STK14D88-NF35TR 3V 32Kx8 AutoStore nvSRAM SOP32-300 35 ns Commercial
STK14D88-NF45TR 3V 32Kx8 AutoStore nvSRAM SOP32-300 45 ns Commercial
STK14D88-RF25 3V 32Kx8 AutoStore nvSRAM SSOP48-300 25 ns Commercial
STK14D88-RF35 3V 32Kx8 AutoStore nvSRAM SSOP48-300 35 ns Commercial
STK14D88-RF45 3V 32Kx8 AutoStore nvSRAM SSOP48-300 45 ns Commercial
STK14D88-RF25TR 3V 32Kx8 AutoStore nvSRAM SSOP48-300 25 ns Commercial
STK14D88-RF35TR 3V 32Kx8 AutoStore nvSRAM SSOP48-300 35 ns Commercial
STK14D88-RF45TR 3V 32Kx8 AutoStore nvSRAM SSOP48-300 45 ns Commercial
STK14D88-NF25I 3V 32Kx8 AutoS t ore nvSRAM SOP32-300 25 ns Industrial
STK14D88-NF35I 3V 32Kx8 AutoS t ore nvSRAM SOP32-300 35 ns Industrial
STK14D88-NF45I 3V 32Kx8 AutoS t ore nvSRAM SOP32-300 45 ns Industrial
STK14D88-NF25ITR 3V 32Kx8 AutoStore nvSRAM SOP32-300 25 ns Industrial
STK14D88-NF35ITR 3V 32Kx8 AutoStore nvSRAM SOP32-300 35 ns Industrial
STK14D88-NF45ITR 3V 32Kx8 AutoStore nvSRAM SOP32-300 45 ns Industrial
STK14D88-RF25I 3V 32Kx8 AutoS t ore nvSRAM SSOP48-300 25 ns Industrial
STK14D88-RF35I 3V 32Kx8 AutoS t ore nvSRAM SSOP48-300 35 ns Industrial
STK14D88-RF45I 3V 32Kx8 AutoS t ore nvSRAM SSOP48-300 45 ns Industrial
STK14D88-RF25ITR 3V 32Kx8 AutoS t ore nvSRAM SSOP48-300 25 ns Industrial
STK14D88-RF35ITR 3V 32Kx8 AutoS t ore nvSRAM SSOP48-300 35 ns Industrial
STK14D88-RF45ITR 3V 32Kx8 AutoS t ore nvSRAM SSOP48-300 45 ns Industrial
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Document Number: 001-52037 Rev. *A Page 16 of 18
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
PIN 1 ID
SEATING PLANE
116
17 32
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.292[7.416]
0.299[7.594]
0.405[10.287]
0.419[10.642]
0.050[1.270]
TYP.
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.0100[0.254]
0.006[0.152]
0.012[0.304]
0.021[0.533]
0.041[1.041]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
0.014[0.355]
0.020[0.508]
0.810[20.574]
0.822[20.878]
51-85127 *B
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Document Number: 001-52037 Rev. *A Revised December 01, 2009 Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
STK14D88
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the us e of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress pro ducts are not warr anted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress do es not aut horize its prod ucts for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent pro tectio n (United States and foreign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s t o license e a pers onal, no n-excl usive , non-tr ansferab le license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this Sour ce Code except a s specified above i s prohibited wi thout
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTAB ILITY AND FITNESS FOR A PA RTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials descr ibed herein. Cy press does n ot
assume any liabil ity arisi ng ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts for use as critical compon ent s in life-suppo rt systems where
a malfuncti on or failure may reasonab ly be expected to resu lt in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Document Title: STK14D88 32Kx8 AutoStore nvSRAM
Document Number: 001-52037
Revision ECN Orig. of
Change Submission
Date Description of Change
** 2668632 GVCH 03/04/2009 New data sheet
*A 2821358 GVCH 12/04/2009 Added Note in Ordering Information mentioning that these parts are not recom-
mended for new desig ns.
Added “Not recommended for New Designs” watermark in the PDF.
Added Contents on page 2.
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