10-Bit Monitor and Control System with ADC, DACs, Temperature Sensor, and GPIOs AD7292 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM /4 1.25V REF BUF AD7292 BUF VIN0 VIN1 10-BIT DAC VOUT0 10-BIT DAC VOUT1 10-BIT DAC VOUT2 10-BIT DAC VOUT3 VIN2 10-BIT SAR ADC VIN3 MUX T/H VIN4 CONTROL LOGIC VIN5 VIN6 VIN7 ALERT AND LIMIT REGISTERS 10660-001 DGND CS AGND DOUT DIN GPIO11 GPIO10 GPIO8 GPIO9 GPIO7 GPIO5 GPIO6/BUSY GPIO3/LDAC GPIO1/ALERT1 SCLK SPI INTERFACE DIGITAL I/Os GPIO4/DAC DISABLE1 Base station power amplifier (PA) monitoring and control RF control loops Optical communication system control General-purpose system monitoring and control REFIN DVDD AVDD VDRIVE TEMPERATURE SENSOR GPIO2/DAC DISABLE0 APPLICATIONS REFOUT GPIO0/ALERT0 10-bit SAR ADC 8 multiplexed analog input channels Single-ended mode of operation Differential mode of operation 5 V analog input range VREF, 2 x VREF, or 4 x VREF input ranges Input measured with respect to AGND or VDD 4 monotonic, 10-bit, 5 V DACs 2 s settling time Power-on reset to 0 V 10 mA sink and source capability Internal temperature sensor 1C accuracy 12 general-purpose digital I/O pins Internal 1.25 V reference Built-in monitoring features Minimum and maximum value register for each channel Programmable alert thresholds Programmable hysteresis SPI interface Temperature range: -40C to +125C Package type: 36-lead LFCSP Figure 1. GENERAL DESCRIPTION The AD7292 contains all the functionality required for generalpurpose monitoring of analog signals and control of external devices, integrated into a single-chip solution. The AD7292 features an 8-channel, 10-bit SAR ADC, four 10-bit DACs, a 1C accurate internal temperature sensor, and 12 GPIOs to aid system monitoring and control. The 10-bit, high speed, low power successive approximation register (SAR) ADC is designed to monitor a variety of singleended input signals. Differential operation is also available by configuring VIN0 and VIN1 to operate as a differential pair. Four 10-bit digital-to-analog converters (DACs) provide outputs from 0 V to 5 V. An internal, high accuracy, 1.25 V reference provides a separately buffered reference source for both the ADC and the DACs. A high accuracy band gap temperature sensor is monitored and digitized by the 10-bit ADC to give a resolution of 0.03125C. The AD7292 also features built-in limit and alarm functions. The AD7292 is a highly integrated solution offered in a 36-lead LFCSP package with an operating temperature range of -40C to +125C. The AD7292 offers a register programmable ADC sequencer, which enables the selection of a programmable sequence of channels for conversion. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7292* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES View a parametric search of comparable parts. * AD7292 Material Declaration * PCN-PDN Information EVALUATION KITS * Quality And Reliability * AD7292 Evaluation Board * Symbols and Footprints DOCUMENTATION DISCUSSIONS Application Notes View all AD7292 EngineerZone Discussions. * AN-1178: AD7292 DAC Disable Function Timing Data Sheet SAMPLE AND BUY * AD7292: 10-Bit Monitor and Control System with ADC, DACs, Temperature Sensor, and GPIOs Data Sheet Visit the product page to see pricing options. User Guides TECHNICAL SUPPORT * UG-449: Evaluating the AD7292 10-Bit Monitor and Control System Submit a technical question or find your regional support number. SOFTWARE AND SYSTEMS REQUIREMENTS DOCUMENT FEEDBACK * AD7292 Evaluation Software Submit feedback for this data sheet. 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AD7292 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Sequence Register (Address 0x03) ................................. 21 Applications ....................................................................................... 1 Configuration Register Bank (Address 0x05) .......................... 21 Functional Block Diagram .............................................................. 1 Alert Limits Register Bank (Address 0x06) ............................ 30 General Description ......................................................................... 1 Alert Flags Register Bank (Address 0x07) .............................. 31 Revision History ............................................................................... 2 Minimum and Maximum Register Bank (Address 0x08) .... 32 Specifications..................................................................................... 3 Offset Register Bank (Address 0x09) ....................................... 32 ADC Specifications ...................................................................... 3 DAC Buffer Enable Register (Address 0x0A) ......................... 33 DAC Specifications....................................................................... 4 GPIO Register (Address 0x0B) ................................................. 33 General Specifications ................................................................. 5 Conversion Command Register (Address 0x0E) ................... 34 Temperature Sensor Specifications ............................................ 5 Timing Specifications .................................................................. 6 ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) ............................................... 34 Absolute Maximum Ratings ............................................................ 7 TSENSE Conversion Result Register (Address 0x20) ................ 34 Thermal Resistance ...................................................................... 7 DAC Channel Registers (Address 0x30 to Address 0x33) .... 34 ESD Caution .................................................................................. 7 ADC Conversion Control ............................................................. 35 Pin Configuration and Function Descriptions ............................. 8 ADC Conversion Command .................................................... 35 Typical Performance Characteristics ........................................... 10 ADC Sequencer .......................................................................... 36 Theory of Operation ...................................................................... 15 DAC Output Control ..................................................................... 37 Analog Inputs .............................................................................. 15 LDAC Operation ........................................................................ 37 ADC Transfer Functions ........................................................... 16 Simultaneous Update of All DAC Outputs ............................. 37 Temperature Sensor ................................................................... 17 Alerts and Limits ............................................................................ 38 DAC Operation ........................................................................... 17 Alert Limit Monitoring Features .............................................. 38 Digital I/O Pins ........................................................................... 17 Hardware Alert Pins................................................................... 38 Serial Port Interface (SPI) .............................................................. 18 Alert Flag Bits in the Conversion Result Registers ................ 38 Interface Protocol ....................................................................... 18 Alert Flags Register Bank .......................................................... 39 Register Structure ........................................................................... 20 Minimum and Maximum Conversion Results ...................... 39 Register Descriptions ..................................................................... 21 Outline Dimensions ....................................................................... 40 Vendor ID Register (Address 0x00) ......................................... 21 Ordering Guide .......................................................................... 40 ADC Data Register (Address 0x01) ......................................... 21 REVISION HISTORY 9/14--Rev. 0 to Rev. A Changes to Figure 2 .......................................................................... 6 Changed t11 from 4 ns max to 4 ns min and Removed Endnote 4; Table 5 .......................................................................... 21 Changes to Figure 35 ...................................................................... 18 Changes to Table 15 ........................................................................ 21 Changes to VIN Filter Subregister (Address 0x13) Section, Conversion Delay Control Subregister (Address 0x14) Section, Table 23, and Table 24 .................................................................... 26 Changes to VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Section, Table 25, and Table 26 .................................................................... 27 Changes to Figure 40 and Figure 41 ............................................ 35 Changes to Figure 42...................................................................... 36 10/12--Revision 0: Initial Version Rev. A | Page 2 of 40 Data Sheet AD7292 SPECIFICATIONS ADC SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = -40C to +125C, unless otherwise noted. Specifications apply to single-ended mode only, unless otherwise noted. Table 1. Parameter DC ACCURACY Resolution Integral Nonlinearity (INL)1 Min Typ Max 0.11 0.5 0.6 0.99 8 12 1 10 0.5 4.17 Bits LSB LSB LSB mV mV mV ppm/C % FS % FS % FS ppm/C 61.5 61.5 dB dB -84 84.5 -80 60 3 dB dB dB MHz MHz Differential Nonlinearity (DNL)1 Offset Error 0.1 3 Offset Error Matching Offset Error Drift Gain Error 0.5 0.22 0.09 Gain Error Matching Gain Error Drift DYNAMIC PERFORMANCE1 Signal-to-Noise Ratio (SNR) Signal-to-Noise-and-Distortion (SINAD) Ratio Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Channel-to-Channel Isolation Full Power Bandwidth With Respect to AVDD Fully Differential Input Range 900 0 0 0 AVDD - 4 x VREF -4 x VREF -2 x VREF -VREF Input Capacitance DC Input Leakage Current INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient 0.25 0.36 Test Conditions/Comments (AVDD - 4 x VREF) to AVDD input range (AVDD - 4 x VREF) to AVDD input range (AVDD - 4 x VREF) to AVDD input range fIN = 10 kHz sine wave CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate ANALOG INPUT Single-Ended Input Range With Respect to AGND Unit 45 625 ns ns kSPS 150 kSPS 4 x VREF 2 x VREF VREF AVDD +4 x VREF +2 x VREF +VREF V V V V V V V pF pF pF A 23 18 15 1 1.245 1.25 13 1.255 Rev. A | Page 3 of 40 V ppm/C fIN = 3 kHz to 1000 kHz At -3 dB (0 V to VREF input range) At -0.1 dB (0 V to VREF input range) See Table 5 ADC only; temperature sensor disabled ADC and temperature sensor VIN0 and VIN1 inputs only 0 V to VREF input range 0 V to 2 x VREF input range 0 V to 4 x VREF input range At 25C AD7292 Parameter EXTERNAL REFERENCE Reference Input Voltage Data Sheet Min 4.75 Input Resistance 1 Typ Max Unit Test Conditions/Comments AVDD V Internal reference used to calibrate temperature sensor 100 k Specifications also apply to differential mode. DAC SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = -40C to +125C, unless otherwise noted. Table 2. Parameter DC ACCURACY Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Zero-Scale Error Full-Scale Error Offset Error Offset Error Drift Gain Error Gain Error Drift DC Power Supply Rejection Ratio (PSRR) DC Crosstalk DAC OUTPUT CHARACTERISTICS Output Voltage Range Short-Circuit Current Load Current Min 0.2 0.1 4.8 0.1 1.62 4.4 0.35 2.6 -50 5 0 Unit 1 0.3 10 0.5 10 Bits LSB LSB mV % FS mV 0.5 4 x VREF 30 10 500 1 9 ppm/C % FS ppm/C dB V V mA mA 1 nF 2 s 1 Overshoot 1 Max 10 Resistive Load to AGND Capacitive Load Stability DC Output Impedance AC CHARACTERISTICS1 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DAC-to-DAC Crosstalk Output Noise Spectral Density Output Noise Output Transient Response During Power-Up Typ 200 mV 12 4 0.4 2 730 28 5 V/s nV-sec nV-sec nV-sec nV/Hz V rms mV The DAC buffer output level is undefined until 30 s after all supplies reach their minimum specified operating voltages. Rev. A | Page 4 of 40 Test Conditions/Comments Guaranteed monotonic All 0s loaded to DAC register All 1s loaded to DAC register Measured in the linear region, TA = -40C to +125C Measured in the linear region, TA = 25C fRIPPLE up to 100 kHz Sink/source current; within 200 mV of supply 1/4 to 3/4 scale step change within 1 LSB, measured from last SCLK edge 1/4 to 3/4 scale step change within 1 LSB, measured from last SCLK edge; CL = 200 pF, RL = 25 k DAC code = midscale, 1 kHz 0.1 Hz to 10 Hz AVDD ramp of 1 ms with 100 k load Data Sheet AD7292 GENERAL SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = -40C to +125C, unless otherwise noted. Table 3. Parameter LOGIC INPUTS Input High Voltage, VIH Min Typ Unit Test Conditions/Comments 0.3 x VDRIVE 0.2 x VDRIVE 1 V V V V A pF V VDRIVE = 2.3 V to 5.25 V VDRIVE = 1.8 V to 1.95 V VDRIVE = 2.3 V to 5.25 V VDRIVE = 1.8 V to 1.95 V 0.7 x VDRIVE 0.8 x VDRIVE Input Low Voltage, VIL Input Leakage Current, IIN Input Capacitance, CIN Input Hysteresis, VHYST GPIO OUTPUTS ISINK/ISOURCE Output High Voltage, VOH Output Low Voltage, VOL POWER REQUIREMENTS AVDD DVDD VDRIVE Static Current IAVDD IDVDD IDRIVE Total Static Current Dynamic Current IAVDD IDVDD IDRIVE Total Dynamic Current Max 3 0.05 x VDRIVE 1.6 0.4 mA V V 5.25 5.25 5.25 V V V 4.2 0.65 0.12 4.97 5.4 1.3 0.35 mA mA mA mA 6.45 0.65 0.12 7.22 8.5 1.3 0.35 26 37.9 34.125 50.925 DVDD - 0.2 4.75 1.8 1.8 Power Dissipation Static Dynamic mA mA mA mA ISINK/ISOURCE = 1.6 mA ISINK/ISOURCE = 1.6 mA AVDD + DVDD + VDRIVE AVDD + DVDD + VDRIVE, DAC outputs loaded and converting at full scale, continuous conversion on ADC inputs mW mW TEMPERATURE SENSOR SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = -40C to +125C, unless otherwise noted. Table 4. Parameter INTERNAL TEMPERATURE SENSOR Operating Range Accuracy Resolution Update Rate Min Typ -40 1 1 0.5 0.03125 1.25 Max Unit Test Conditions/Comments +125 3 2 1.5 C C C C C ms TA = -40C to +125C TA = 0C to +125C TA = 25C Digital filter enabled Rev. A | Page 5 of 40 AD7292 Data Sheet TIMING SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, CL = 27 pF, TA = -40C to +125C, unless otherwise noted.1 Table 5. Parameter tCONVERT Description ADC conversion time/BUSY high time Temperature sensor disabled Temperature sensor enabled ADC acquisition time Frequency of serial read clock2 SCLK period SCLK low SCLK high CS falling edge to SCLK rising edge DIN setup time to SCLK falling edge DIN hold time after SCLK falling edge SCLK falling edge to CS rising edge CS high SCLK to output data valid delay time SCLK to output data valid hold time CS rising edge to SCLK rising edge CS rising edge to DOUT high impedance tACQ fSCLK t1 t2 t3 t4 t5 t63 t7 t8 t9 t10 t114 t12 VDRIVE = 1.8 V Limit at TMIN/TMAX VDRIVE = 2.7 V to 5.25 V 950 5.85 50 15 66 33 33 4 4 2 5 5 30 7 4 15 Unit 950 5.85 50 25 40 20 20 4 4 2 5 5 19 5 4 15 ns max s max ns max MHz max ns min ns min ns min ns min ns min ns max ns min ns min ns max ns min ns min ns max 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE). For VDRIVE = 2.5 V, fSCLK = 22 MHz maximum. 3 Time required for the output to cross 0.2 x VDRIVE and 0.8 x VDRIVE when VDRIVE = 1.8 V; time required for the output to cross 0.3 x VDRIVE and 0.7 x VDRIVE when VDRIVE = 2.7 V to 5.25 V. 4 Guaranteed by design. 2 Timing Diagram BUSY2 t7 t8 t3 CS t2 t4 t11 t1 SCLK t5 DOUT1 X t6 R W D5 D4 D3 D2 D1 D0 X t10 HIGH-Z 1PROVIDED THE READ BIT IS SET. 2IF AN ADC CONVERSION IS REQUESTED. LSB LSB t9 HIGH-Z t12 10660-002 DIN t7 = 5ns IF NO ADC CONVERSION 955ns WITH ADC CONVERSION Figure 2. Serial Interface Timing Diagram Rev. A | Page 6 of 40 Data Sheet AD7292 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 6. Parameter AVDD to AGND DVDD to DGND VDRIVE to DGND VINx to AGND VOUTx to AGND Digital Inputs/Outputs to DGND CS, SCLK, DIN, DOUT to DGND REFOUT to AGND REFIN to AGND DGND to AGND Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) ESD, Human Body Model Reflow Soldering Peak Temperature Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to +6 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to +2.2 V -0.3 V to AVDD + 0.3 V 0.3 V -40C to +125C -65C to +150C 150C 2.5 kV 260C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 7. Thermal Resistance Package Type 36-Lead LFCSP ESD CAUTION Rev. A | Page 7 of 40 JA 54.1 Unit C/W AD7292 Data Sheet 36 35 34 33 32 31 30 29 28 REFIN VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 AD7292 TOP VIEW (Not to Scale) 27 26 25 24 23 22 21 20 19 GPIO0/ALERT0 GPIO1/ALERT1 GPIO2/DAC DISABLE0 GPIO3/LDAC GPIO4/DAC DISABLE1 GPIO5 GPIO6/BUSY GPIO7 REFOUT NOTES 1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND AND CAN BE SOLDERED TO THE GROUND PLANE OF THE SYSTEM. 10660-003 VOUT3 VOUT2 VOUT1 VOUT0 AGND GPIO11 GPIO10 GPIO9 GPIO8 10 11 12 13 14 15 16 17 18 AVDD AGND DGND DVDD VDRIVE CS SCLK DIN DOUT Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2, 14 Mnemonic AVDD AGND 3 DGND 4 5 DVDD VDRIVE 6 7 8 CS SCLK DIN 9 DOUT 10 to 13 VOUT3 to VOUT0 15 to 18 19 GPIO11 to GPIO8 REFOUT 20 21 GPIO7 GPIO6/BUSY 22 23 GPIO5 GPIO4/ DAC DISABLE1 24 GPIO3/LDAC 25 GPIO2/ DAC DISABLE0 Description Supply Pin. This pin should be decoupled to AGND with a 0.1 F decoupling capacitor. Analog Ground. Ground reference point for all analog circuitry on the AD7292. All analog signals should be referred to AGND. Both the AGND and DGND pins should be connected to the ground plane of the system. Digital Ground. Ground reference point for all digital circuitry on the AD7292. All digital signals should be referred to DGND. Both the DGND and AGND pins should be connected to the ground plane of the system. Sets the GPIO voltage level. This pin should be decoupled to DGND with a 0.1 F decoupling capacitor. This pin sets the reference level of the SPI bus from 1.8 V to 5.25 V. This pin should be decoupled to DGND with a 0.1 F decoupling capacitor. Chip Select Signal. This active low logic input signal is used to frame the serial data input. SPI Clock Input. SPI Serial Data Input. Serial data to be loaded into the registers of the AD7292 is provided on this pin. Data is clocked into the serial interface on the falling edge of SCLK. SPI Serial Data Output. Serial data to be read from the registers of the AD7292 is provided on this pin. Data is clocked out on the rising edge of SCLK. DOUT is high impedance when it is not outputting data. Buffered DAC Analog Outputs. Each DAC analog output is driven from an output amplifier and has a maximum output voltage span of 5 V. Each DAC is capable of sourcing and sinking 10 mA and driving a 1 nF load. General-Purpose Input/Output Pins. ADC Internal Reference Output. Decouple the internal ADC reference buffer to AGND with a 0.1 F decoupling capacitor. General-Purpose Input/Output Pin. General-Purpose Input/Output Pin (GPIO6). Busy Output Pin (BUSY). When a conversion starts, this output pin transitions high and remains high until the conversion is completed. General-Purpose Input/Output Pin. General-Purpose Input/Output Pin (GPIO4). DAC Disable Pin 1 (DAC DISABLE1). When this pin is activated, the selected DAC outputs are disabled. Select the DAC channels to be disabled by this pin using the GPIO4/DAC DISABLE1 subregister within the configuration register bank (see Table 30). General-Purpose Input/Output Pin (GPIO3). LDAC Input Pin (LDAC). When this input is taken high, the DAC registers are updated. General-Purpose Input/Output Pin (GPIO2). DAC Disable Pin 0 (DAC DISABLE0). When this pin is activated, the selected DAC outputs are disabled. Select the DAC channels to be disabled by this pin using the GPIO2/DAC DISABLE0 subregister within the configuration register bank (see Table 29). Rev. A | Page 8 of 40 Data Sheet Pin No. 26 Mnemonic GPIO1/ALERT1 27 GPIO0/ALERT0 28 to 35 VIN0 to VIN7 36 REFIN EPAD EPAD AD7292 Description General-Purpose Input/Output Pin (GPIO1). Alert Pin 1 (ALERT1). When configured as an alert, this pin acts as an out-of-range indicator and becomes active when the conversion result violates the high or low limit stored in the alert limits register bank. The polarity of the alert signal is controlled using the general subregister within the configuration register bank. General-Purpose Input/Output Pin (GPIO0). Alert Pin 0 (ALERT0). When configured as an alert, this pin acts as an out-of-range indicator and becomes active when the conversion result violates the high or low limit stored in the alert limits register bank. The polarity of the alert signal is controlled using the general subregister within the configuration register bank. Analog Inputs. The eight single-ended analog inputs of the AD7292 are multiplexed into the on-chip track-and-hold amplifier. Each input channel can accept analog inputs from 0 V to 5 V. Any unused input channels should be connected to AGND to avoid noise pickup. Voltage Reference Input. An external reference for the AD7292 can be applied to this pin. If this pin is unused, connect it to AGND. The exposed pad is internally connected to AGND and can be soldered to the ground plane of the system. Rev. A | Page 9 of 40 AD7292 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AVDD = 5V DVDD = 5V VDRIVE = 3V TA = 25C fSAMPLE = 200kSPS RANGE = 0V TO VREF SINGLE-ENDED MODE SNR = 61.6dB THD = -84.0dB SINAD = 61.49dB SFDR = 79.05dB -40 -60 -80 -60 -80 -100 10 20 30 40 50 60 70 80 90 100 -120 10660-004 0 INPUT FREQUENCY (kHz) 0.3 30 40 50 60 70 80 90 100 AVDD = 4.75V TA = 25C DVDD = 5.25V WCP INL = 0.091LSB VDRIVE = 3.3V WCN INL = -0.093LSB CHANNEL 0 AND CHANNEL 1 INTERNAL REFERENCE DIFFERENTIAL MODE, 0V TO VREF RANGE 0.2 0 -0.1 0.1 0 -0.1 0 128 256 384 512 640 768 896 1024 ADC CODE -0.3 10660-006 -0.3 0 128 256 384 512 640 768 896 1024 ADC CODE Figure 5. Typical ADC INL, Single-Ended Mode 10660-008 -0.2 -0.2 Figure 8. Typical ADC INL, Differential Mode 0.3 0.25 AVDD = DVDD = 5.25V TA = 25C VDRIVE = 1.8V WCP DNL = 0.11LSB CHANNEL 3 WCN DNL = -0.119LSB INTERNAL REFERENCE SINGLE-ENDED MODE, 0V TO 4 x VREF RANGE TA = 25C AVDD = 4.75V WCP INL = 0.067LSB DVDD = 5.25V WCN INL = -0.08LSB VDRIVE = 3.3V CHANNEL 0 AND CHANNEL 1 INTERNAL REFERENCE DIFFERENTIAL MODE, 0V TO VREF RANGE 0.20 0.15 DNL ERROR (LSB) 0.2 0.1 0 -0.1 0.10 0.05 0 -0.05 -0.10 -0.15 -0.2 -0.3 0 128 256 384 512 640 768 896 ADC CODE 1024 Figure 6. Typical ADC DNL, Single-Ended Mode -0.25 0 128 256 384 512 640 768 896 ADC CODE Figure 9. Typical ADC DNL, Differential Mode Rev. A | Page 10 of 40 1024 10660-009 -0.20 10660-007 DNL ERROR (LSB) 20 0.3 INL ERROR (LSB) 0.1 10 Figure 7. ADC FFT, 200 kSPS, fIN = 10 kHz, Differential Mode AVDD = DVDD = 5.25V VDRIVE = 1.8V CHANNEL 3 INTERNAL REFERENCE TA = 25C WCP INL = 0.068LSB WCN INL = -0.255LSB SINGLE-ENDED MODE, 0V TO 4 x VREF RANGE 0.2 0 INPUT FREQUENCY (kHz) Figure 4. ADC FFT, 200 kSPS, fIN = 10 kHz, Single-Ended Mode INL ERROR (LSB) -40 10660-005 -100 -120 AVDD = 5V DVDD = 5.25V VDRIVE = 1.8V TA = 25C fSAMPLE = 200kSPS RANGE = 0V TO 2 x VREF DIFFERENTIAL MODE SNR = 61.798dB THD = -86.602dB SINAD = 61.784dB SFDR = 86.142dB -20 AMPLITUDE (dB) AMPLITUDE (dB) -20 Data Sheet AD7292 0.4 AVDD = 5V DVDD = 3V VDRIVE = 3V fSAMPLE = 225kSPS INTERNAL REFERENCE SINGLE-ENDED MODE 0.4 0.2 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 0V TO 0V TO 0V TO 0V TO 0V TO 0V TO (AVDD (AVDD -20 VREF , -INL VREF , +INL 2 x VREF , -INL 2 x VREF , +INL 4 x VREF , -INL 4 x VREF , +INL - 4 x VREF ) TO AVDD, -INL - 4 x VREF ) TO AVDD, +INL 0 0 -0.1 -0.3 20 40 60 TEMPERATURE (C) 80 100 120 AVDD = 5V DVDD = 3V VDRIVE = 3V fSAMPLE = 225kSPS INTERNAL REFERENCE SINGLE-ENDED MODE 0.1 -0.2 -0.4 -40 10660-010 0V TO 0V TO 0V TO 0V TO 0V TO 0V TO (AVDD (AVDD -20 Figure 10. ADC INL vs. Temperature 20 40 60 TEMPERATURE (C) 80 100 120 5 4 GAIN ERROR (LSB) 3 1 0 -1 -2 -3 -40 -20 VREF 2 x VREF 4 x VREF - 4 x VREF ) TO AVDD 0 80 100 120 -60 0V TO VREF, 0 0V TO VREF, 220 0V TO VREF, 510 0V TO 2 x VREF, 0 0V TO 2 x VREF, 220 0V TO 2 x VREF, 510 -70 -80 AVDD = 5V DVDD = 3V VDRIVE = 3V fSAMPLE = 225kSPS TA = 25C INTERNAL REFERENCE -90 -100 -110 10660-014 90 100 80 70 60 50 40 30 20 10 -120 INPUT FREQUENCY (kHz) 0V TO VREF 0V TO 2 x VREF 0V TO 4 x VREF (AVDD - 4 x VREF) TO AVDD -20 0 20 40 60 80 100 120 Figure 14. ADC Gain Error vs. Temperature, Single-Ended and Differential Modes CHANNEL-TO-CHANNEL ISOLATION (dB) -50 -2 TEMPERATURE (C) -20 -40 0 -1 -5 -40 Figure 11. Offset Error vs. Temperature, Single-Ended and Differential Modes -30 1 -4 20 40 60 TEMPERATURE (C) AVDD - 4 x VREF, 0 AVDD - 4 x VREF, 220 AVDD - 4 x VREF, 510 0V TO 4 x VREF, 0 0V TO 4 x VREF, 220 0V TO 4 x VREF, 430 0V TO 4 x VREF, 510 2 -3 10660-012 0V TO 0V TO 0V TO (AVDD AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V fSAMPLE = 200kSPS INTERNAL REFERENCE 10660-013 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V fSAMPLE = 200kSPS INTERNAL REFERENCE 2 OFFSET ERROR (LSB) 0 Figure 13. ADC DNL vs. Temperature 3 THD (dB) VREF , -DNL VREF , +DNL 2 x VREF , -DNL 2 x VREF , +DNL 4 x VREF , -DNL 4 x VREF , +DNL - 4 x VREF ) TO AVDD, -DNL - 4 x VREF ) TO AVDD, +DNL Figure 12. THD vs. Input Frequency for Various Source Impedances, Single-Ended Mode 120 115 110 105 100 95 90 85 80 75 70 AVDD = 5V DVDD = 3V 65 VDRIVE = 3V 60 fSAMPLE = 250kSPS 55 0V TO VREF TA = 25C 50 0V TO 2 x VREF INTERNAL REFERENCE 0V TO 4 x VREF 45 fIN = 10kHz (AVDD - 4 x VREF ) TO AVDD 40 35 FULL-SCALE SIGNAL ON CHANNEL, 30 VIN0 TO VIN3 AND VIN5 TO VIN7 25 INPUT FREQUENCY RAMPED MEASUREMENTS ON VIN4 20 100 1k 10k 100k 1M 10M 100M INPUT FREQUENCY (Hz) Figure 15. ADC Channel-to-Channel Isolation Rev. A | Page 11 of 40 10660-016 INL ERROR (LSB) 0.6 0.3 DNL ERROR (LSB) 0.8 10660-011 1.0 AD7292 Data Sheet 1.3 900 AVDD = 5V DVDD = 5V VDRIVE = 2.5V TA = 25C OCCURRENCES 700 1.2 REFERENCE VOLTAGE (V) 800 600 500 400 300 1.1 1.0 AVDD = 5V DVDD = VDRIVE = 3V fSAMPLE = 225kSPS ANALOG INPUT RANGE = AVDD - 4 x VREF TA = 25C 0.9 0.8 200 512 0.6 OUTPUT CODE 1k 0.15 DNL ERROR (LSB) 0.3 0.1 -0.1 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V TA = 25C INTERNAL REFERENCE -0.5 256 384 512 640 768 896 0.05 -0.05 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V TA = 25C INTERNAL REFERENCE -0.15 1024 DAC CODE -0.25 10660-019 INL ERROR (LSB) 0.25 128 0 DNL ERROR (LSB) AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE 20 40 60 80 TEMPERATURE (C) 100 120 10660-021 INL ERROR (LSB) INL MIN 0 256 384 512 640 768 896 1024 Figure 20. Typical DAC DNL vs. Output Code INL MAX -20 128 DAC CODE Figure 17. Typical DAC INL vs. Output Code 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 1M Figure 19. Reference Voltage vs. Load Resistance 0.5 0 100k LOAD RESISTANCE () Figure 16. Histogram of Codes -0.3 10k 10660-020 511 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 DNL MAX DNL MIN AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE -20 0 20 40 60 80 TEMPERATURE (C) Figure 21. DAC DNL vs. Temperature Figure 18. DAC INL vs. Temperature Rev. A | Page 12 of 40 100 120 10660-022 510 10660-017 0 10660-018 0.7 100 Data Sheet AD7292 0.4 5.0 4.5 DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE 0.3 4.0 GAIN ERROR (%FSR) OFFSET ERROR (mV) 0.2 3.5 3.0 2.5 AVDD = 5.25V 2.0 1.5 AVDD = 4.75V 0.1 0 -0.1 AVDD = 5.25V -0.2 1.0 DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE -20 0 20 40 60 80 100 120 -0.4 -40 TEMPERATURE (C) -20 0 40 20 120 100 80 60 TEMPERATURE (C) Figure 22. DAC Offset Error vs. Temperature Figure 25. DAC Gain Error vs. Temperature 0.10 4.996 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE CODE = 0x3FF TA = 25C 0.08 4.993 4.992 4.991 0.07 0.06 0.05 0.04 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE CODE = 0x000 TA = 25C 0.03 4.990 0.02 4.989 0.01 0 1 2 3 4 5 6 7 8 9 10 SOURCE CURRENT (mA) 0 10660-026 4.988 0 1 2 3 4 5 6 9 8 7 10 SINK CURRENT (mA) 10660-027 4.994 0.09 OUTPUT VOLTAGE (V) 4.995 OUTPUT VOLTAGE (V) AVDD = 4.75V 10660-024 0 -40 -0.3 10660-023 0.5 Figure 26. DAC Sink Current (Zero Scale) Figure 23. DAC Source Current (Full Scale) 1.255 2.510 1.254 2.508 AVDD = DVDD = VDRIVE = 5V 10 DEVICES REFERENCE VOLTAGE (V) 1.253 2.504 2.502 2.500 AVDD = 5.25V DVDD = 5V VDRIVE = 3.3V INTERNAL REFERENCE CODE = 0x200 2.496 2.494 -10 -8 -6 -4 -2 0 2 4 6 8 LOAD CURRENT (mA) 1.252 1.251 1.250 1.249 1.248 1.247 1.246 10 1.245 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 27. Reference Voltage vs. Temperature Figure 24. DAC Output Voltage vs. Load Current (Midscale) Rev. A | Page 13 of 40 120 10660-028 2.498 10660-025 OUTPUT VOLTAGE (V) 2.506 AD7292 Data Sheet 6.0 1.6 AVDD = DVDD = VDRIVE = 5V 10 DEVICES 1.4 5.8 5.6 ERROR (C) 1.0 0.8 0.6 0.4 0.2 5.2 5.0 4.8 4.6 4.4 -0.2 4.2 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 10660-031 0 -0.4 -40 Figure 28. Temperature Sensor Error vs. Temperature 70 60 50 40 30 10 0V TO VREF 0V TO 2 x VREF 0V TO 4 x VREF 0 1k 10k 100k 1M POWER SUPPLY RIPPLE FREQUENCY (Hz) 10M 10660-032 AVDD = 5V DVDD = 3V VDRIVE = 3V TA = 25C fSAMPLE = 225kSPS INTERNAL REFERENCE 20 AVDD = 5V, DVDD = 3V, VDRIVE = 3V, SCLK VARIED AVDD = 5.25V, DVDD = 5.25V, VDRIVE = 5.25V, SCLK FIXED, 25MHz AVDD = 4.75V, DVDD = 1.8V, VDRIVE = 1.8V, SCLK FIXED, 15 MHz 4.0 0 100 200 300 400 500 SAMPLING FREQUENCY (kHz) Figure 30. Total Supply Current vs. Throughput Rate 80 PSRR (dB) 5.4 Figure 29. PSRR vs. Power Supply Ripple Frequency Rev. A | Page 14 of 40 600 10660-033 TOTAL CURRENT (mA) 1.2 Data Sheet AD7292 THEORY OF OPERATION ANALOG INPUTS VIN+ VREF p-p The analog input range is programmed to one of these values: 0 V to VREF, 0 V to 2 x VREF, or 0 V to 4 x VREF. For information about programming the input range, see the VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) section. In 0 V to 2 x VREF mode, the input is scaled by a factor of 2 before the conversion takes place. In 0 V to 4 x VREF mode, the input is scaled by a factor of 4 before the conversion takes place. Note that the voltage with respect to AGND on the ADC analog input pins cannot exceed AVDD. If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias this signal up so that it is correctly formatted for the ADC. Figure 31 shows a typical connection diagram when operating the ADC in singleended mode with a bipolar 0.625 V input signal. +1.25V R 0V VREF p-p R 0V VIN VIN0 3R -0.625V AD7292 VIN1 Figure 32. Differential Analog Input The amplitude of the differential signal is the difference between the signals applied to the input pins of the differential pair, VIN0 and VIN1. The resulting converted data is stored in straight binary format in the ADC data register. VIN0 and VIN1 should be simultaneously driven by two signals that are 180 out of phase; each signal should be of maximum amplitude VREF, 2 x VREF, or 4 x VREF, depending on the selected range. Therefore, if the 0 V to VREF range is selected, the amplitude of the differential signal is -VREF to +VREF peak-to-peak (2 x VREF), regardless of the common-mode voltage (VCM). The common-mode voltage is the average of the two signals. VCM = (VIN+ + VIN-)/2 The common-mode voltage is, therefore, the voltage on which the two inputs are centered; the resulting span for each input is VCM VREF/2. This voltage must be set up externally. When the inputs are driven with an amplifier, the actual common-mode range is determined by the output voltage swing of the amplifier and the input common-mode range of the AD7292. The commonmode voltage must be in this range to guarantee the functionality of the AD7292 (see Figure 33). When a conversion takes place, the common-mode voltage is rejected, resulting in a virtually noise-free signal of amplitude -VREF to +VREF. R 69 VIN7 REF OUT DIFFERENTIAL MODE AVDD = 5V DVDD = 3V VDRIVE = 3V TA = 25C fSAMPLE = 225kSPS INTERNAL REFERENCE Figure 31. Interfacing to a Bipolar Input Signal Differential Mode 65 SINAD (dB) 10660-037 67 0.47F VIN- The AD7292 can be configured to have one differential analog input pair (VIN0 and VIN1). Differential signals have some benefits over single-ended signals, including noise immunity based on the common-mode rejection of the device and improvements in distortion performance. Figure 32 shows the fully differential analog input of the AD7292. 63 61 1 x VREF 2 x VREF 4 x VREF 59 57 55 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE (V) Figure 33. Common-Mode Voltage (Dependent on Input Range) Rev. A | Page 15 of 40 10660-138 +0.625V AD7292 COMMON-MODE VOLTAGE Single-Ended Mode In applications where the signal source has high impedance, it is recommended that the analog input be buffered before it is applied to the ADC. VIN0 10660-038 The AD7292 has eight analog input channels. By default, these channels are configured as single-ended inputs. Differential operation is also available by configuring VIN0 and VIN1 to operate as a differential pair. AD7292 Data Sheet ADC TRANSFER FUNCTIONS The LSB size depends on the input range selected (see Table 9). The output coding of the AD7292 is 10-bit straight binary for the analog input channels. The designated code transitions occur at successive LSB values. Table 9. Input Range and LSB Size To select the input range, set the appropriate bits in the VIN RANGE1 and VIN RANGE0 subregisters of the configuration register bank (see Table 10). Input Range 0 V to VREF 0 V to 2 x VREF 0 V to 4 x VREF LSB Size VREF/210 2VREF/210 4VREF/210 The ideal transfer function for the AD7292 when operating with an input range of 0 V to VREF is shown in Figure 34. Table 10. Analog Input Range Selection Subregister Bit Settings VIN RANGE1 VIN RANGE0 0 0 0 1 1 0 1 1 1 1 2 Sample with Respect to AGND Single-Ended Input Range Differential Input Range (VIN0 to VIN7) (VIN0 and VIN1 Only) 0 V to 4 x VREF -4 x VREF to +4 x VREF 0 V to 2 x VREF -2 x VREF to +2 x VREF 0 V to 2 x VREF -2 x VREF to +2 x VREF 0 V to VREF -VREF to +VREF Sample with Respect to AVDD2 Single-Ended Input Range (VIN0 to VIN7) (AVDD - 4 x VREF) to AVDD Not applicable Not applicable Not applicable For more information, see the ADC Sampling Mode Subregister (Address 0x12) section. The contents of the VIN RANGE0 and VIN RANGE1 subregisters are ignored when the AD7292 is configured to sample with respect to AVDD; the only input range allowed when sampling with respect to AVDD is from (AVDD - 4 x VREF) to AVDD. 111...111 ADC CODE 111...110 111...000 011...111 1LSB = VREF /1024 000...010 000...001 000...000 0V 1LSB +VREF - 1LSB NOTES 1. VREF IS 1.25V. 2. INPUT RANGE IS 0V TO VREF . 10660-040 ANALOG INPUT Figure 34. Straight Binary Transfer Characteristic Corresponding to Single-Ended Input Range of 0 V to VREF Table 11. Output Codes and Ideal Input Voltages (AVDD = 5 V) Description +FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR 0 V to 4 x VREF 4.995117 V 2.504883 V 2.5 V 2.495117 V 0.004883 V 0V Analog Input Range Single-Ended Mode of Operation Differential Mode of Operation 0 V to (AVDD - 4 x VREF) -4 x VREF to -2 x VREF to 2 x VREF 0 V to VREF -VREF to +VREF to AVDD +4 x VREF +2 x VREF 2.497559 V 1.248779 V 4.995117 V 4.990234 V 2.495117 V 1.247559 V 1.252441 V 0.626221 V 2.504883 V 0.009766 V 0.004883 V 0.002441 V 1.25 V 0.625 V 2.5 V 0V 0V 0V 1.247559 V 0.623779 V 2.495117 V -0.009766 V -0.004883 V -0.002441 V 0.002441 V 0.001221 V 0.004883 V 4.995117 V -2.495117 V -1.247559 V 0V 0V 0V -5 V -2.5 V -1.25 V Rev. A | Page 16 of 40 Digital Output Code (Hex) 0x3FF 0x201 0x200 0x1FF 0x001 0x000 Data Sheet AD7292 TEMPERATURE SENSOR DAC OPERATION The AD7292 contains one local temperature sensor. The on-chip, band gap temperature sensor measures the temperature of the AD7292 die. The temperature sensor input gathers data and computes a value over a period of several hundred microseconds. The temperature measurement takes place continuously in the background, leaving the user free to perform conversions on the other channels. The four DACs of the AD7292 provide digital control with 10 bits of resolution. DAC outputs VOUT0 to VOUT3 feature an output voltage range up to 5 V (LSB of 4.88 mV). After a temperature value is computed, a signal passes to the control logic to initiate a conversion automatically. If an ADC conversion is in progress, the temperature sensor conversion is performed as soon as the ADC conversion is completed. If the ADC is idle, the temperature sensor conversion takes place immediately. The TSENSE conversion result register stores the result of the last conversion on the temperature channel; this result can be read at any time provided that the temperature sensor is enabled via the temperature sensor subregister within the configuration register bank (see the Temperature Sensor Subregister (Address 0x20) section). Temperature readings from the ADC are stored in the TSENSE conversion result register. Results are in 14-bit straight binary format and accommodate both positive and negative temperature measurements. Bit D0 and Bit D1 hold alert flags; Bit D2 stores the LSB, which corresponds to 0.03125C if the digital filter is enabled. Table 12 provides examples of temperature sensor data. An output of all 0s is equal to -256C; this value is output by the AD7292 until the first measurement is completed. Note that when digital filtering is disabled, Bit D3 and Bit D2 of the TSENSE conversion result register are set to 0, producing a 12-bit straight binary result with an LSB of 0.125C. When the TSENSE conversion result is read via the ADC data register (Address 0x01), the temperature sensor result is a 10-bit result with an LSB that equates to 0.5C. Table 12. Temperature Sensor Data Format Temperature (C) -40 -25 -10 -0.03125 0 +0.03125 +10 +25 +50 +75 +100 +125 TSENSE Conversion Result Register, Bits[D15:D2] 01 1011 0000 0000 01 1100 1110 0000 01 1110 1100 0000 01 1111 1111 1111 10 0000 0000 0000 10 0000 0000 0001 10 0001 0100 0000 10 0011 0010 0000 10 0110 0100 0000 10 1001 0110 0000 10 1100 1000 0000 10 1111 1010 0000 The DAC output buffer can be controlled via software using the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 subregisters within the configuration register bank, or via hardware using the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins. DIGITAL I/O PINS To aid in system monitoring, the AD7292 features 12 digital I/O pins. All 12 pins can be configured as GPIO pins. Six of the digital I/O pins can be configured for other functionality; on power-up, the non-GPIO functionality of these six pins is enabled by default. For more information, see the Digital Output Driver Subregister (Address 0x01) section and the Digital I/O Function Subregister (Address 0x02) section. GPIO0/ALERT0 and GPIO1/ALERT1 Pins When Pin 27 and Pin 26 (GPIO0/ALERT0 and GPIO1/ALERT1, respectively) are configured as alert pins, they act as out-of-range indicators that become active when the selected conversion result exceeds the high or low limit stored in the alert limits register bank. The polarity of the alert output pins can be set to active high or active low via the general subregister within the configuration register bank (see the General Subregister (Address 0x08) section). GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins When Pin 25 and Pin 23 (GPIO2/DAC DISABLE0 and GPIO4/ DAC DISABLE1, respectively) are configured as DAC disable pins, they can be used to power down the selected DAC outputs, as determined by the contents of the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 subregisters within the configuration register bank. For more information, see the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) section. GPIO3/LDAC Pin When Pin 24 (GPIO3/LDAC) is configured as an LDAC pin, the DAC registers are updated when this input pin is taken high. GPIO6/BUSY Pin Pin 21 (GPIO6/BUSY) can be configured as a general-purpose input/output or as a busy output pin. When configured as a busy output pin, this pin transitions high when a conversion starts and remains high until the conversion is completed. Rev. A | Page 17 of 40 AD7292 Data Sheet SERIAL PORT INTERFACE (SPI) The AD7292 serial port interface (SPI) allows the user to configure the device for specific functions and operations through an internal structured register space. The interface consists of four signals: CS, SCLK, DIN, and DOUT. The SPI reference level is set by Pin 5 (VDRIVE) to a level in the range of 1.8 V to 5.25 V. Table 13. Address Pointer D7 R D6 W D5 D4 D3 D2 Register select D1 D0 After the address pointer, subsequent data for writing to the part is supplied in bytes (see Figure 36). Some registers are located within register banks and, therefore, require both a pointer address and a subpointer address. The subpointer address is specified in the first byte following the pointer address (see Figure 37). Figure 36 through Figure 38 show the read and write data formats. These figures show read operations; for a write to a register or subregister, the write bit is set and the DOUT line remains high impedance. SCLK is the serial clock input for the device; all data transfers on DIN or DOUT take place with respect to SCLK. The chip select input pin (CS) is an active low control that initiates the data transfer and conversion process. Data is clocked into the AD7292 on the SCLK falling edge. Data is loaded into the device MSB first. The length of each frame can vary and depends on the command being sent. Data is clocked out of the AD7292 on DOUT in the same frame as the read command, on the rising edge of SCLK while CS is low. When CS is high, the SCLK and DIN signals are ignored and the DOUT line becomes high impedance. If neither the read nor write bit is set (Bit D7 and Bit D6 of the address pointer are set to 0), the address pointer is updated but no data is read or written. Note that writing this command also reinitializes the ADC sequencer (see the ADC Conversion Control section). On completion of a read or write, the AD7292 is ready to accept a new pointer address; alternatively, the CS pin can be taken high to terminate the operation. INTERFACE PROTOCOL When reading from or writing to the AD7292, the first byte contains the address pointer (see Table 13). Bit D7 and Bit D6 of the address pointer are the read and write bits, respectively. Bit D5 to Bit D0 of the address pointer specify the register address for the read or write operation. A register can be simultaneously read from and written to by setting both Bit D7 and Bit D6 to 1. BUSY2 t7 t8 t3 CS t2 t4 t11 t1 SCLK t5 X t6 R W D5 D4 D3 D2 D1 D0 LSB HIGH-Z DOUT1 X t10 HIGH-Z LSB t9 t12 10660-041 1PROVIDED THE READ BIT IS SET. 2IF AN ADC CONVERSION IS REQUESTED. t7 = 5ns IF NO ADC CONVERSION 955ns WITH ADC CONVERSION Figure 35. Serial Interface Timing Diagram CS DIN R W POINTER [D5:D0] DIN [D7:D0] DOUT [D15:D0] 1 DOUT 1PROVIDED DIN [D15:D8] THE READ BIT IS SET. Figure 36. Accessing a 16-Bit Register Rev. A | Page 18 of 40 10660-042 DIN Data Sheet AD7292 CS R W POINTER [D5:D0] SUBPOINTER [D7:D0] DIN [D7:D0] DOUT [D7:D0] 1 DOUT 10660-043 DIN 1PROVIDED THE READ BIT IS SET. Figure 37. Accessing an 8-Bit Subregister Within a Register Bank CS R W POINTER [D5:D0] SUBPOINTER [D7:D0] DIN [D15:D8] DOUT [D15:D0] 1 DOUT 1PROVIDED DIN [D7:D0] THE READ BIT IS SET. Figure 38. Accessing a 16-Bit Subregister Within a Register Bank Rev. A | Page 19 of 40 10660-044 DIN AD7292 Data Sheet REGISTER STRUCTURE The AD7292 contains internal registers that store conversion results, high and low conversion limits, and information to configure and control the device (see Figure 39). Each register has an address; the address pointer register points to the address when communicating with the register. Some registers and subregisters contain reserved bits. The AD7292 allows either a 0 or a 1 to be written to these reserved bits. VENDOR ID REGISTER ADC DATA ADC SEQUENCE REGISTER CONFIGURATION REGISTER BANK DATA ALERT FLAGS REGISTER BANK MINIMUM AND MAXIMUM REGISTER BANK Table 14. AD7292 Registers Address 0x00 0x01 0x03 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0E 0x10 ALERT LIMITS REGISTER BANK 0x11 OFFSET REGISTER BANK 0x12 DAC BUFFER ENABLE REGISTER GPIO REGISTER 0x13 CONVERSION COMMAND 0x14 ADC CONVERSION RESULT REGISTERS x 8 0x15 TSENSE CONVERSION RESULT REGISTER 0x16 DAC CHANNEL REGISTERS x 4 SERIAL BUS INTERFACE Figure 39. AD7292 Register Structure 0x17 DIN SCLK DOUT CS 10660-045 ADDRESS POINTER REGISTER Table 14 lists each register and specifies whether the register has read access or read and write access. 0x20 0x30 0x31 0x32 0x33 1 2 Register Name Vendor ID register ADC data register ADC sequence register Configuration register bank Alert limits register bank Alert flags register bank Minimum and maximum register bank Offset register bank DAC buffer enable register GPIO register Conversion command2 ADC conversion result register, Channel 0 ADC conversion result register, Channel 1 ADC conversion result register, Channel 2 ADC conversion result register, Channel 3 ADC conversion result register, Channel 4 ADC conversion result register, Channel 5 ADC conversion result register, Channel 6 ADC conversion result register, Channel 7 TSENSE conversion result register DAC Channel 0 register DAC Channel 1 register DAC Channel 2 register DAC Channel 3 register Access1 R R R/W R/W R/W R/W R/W Data Format Figure 36 Figure 36 Figure 36 Figure 38 Figure 38 Figure 38 Figure 38 R/W R/W R/W N/A R Figure 37 Figure 36 Figure 36 N/A Figure 36 R Figure 36 R Figure 36 R Figure 36 R Figure 36 R Figure 36 R Figure 36 R Figure 36 R R/W R/W R/W R/W Figure 36 Figure 36 Figure 36 Figure 36 Figure 36 R is read only; R/W is read/write. See the ADC Conversion Command section for more information. Rev. A | Page 20 of 40 Data Sheet AD7292 REGISTER DESCRIPTIONS VENDOR ID REGISTER (ADDRESS 0x00) CONFIGURATION REGISTER BANK (ADDRESS 0x05) The 16-bit, read-only vendor ID register stores the Analog Devices vendor ID, 0x0018. The vendor ID register is provided to identify the AD7292 to an SPI master such as a microcontroller. The configuration register bank subregisters are listed in Table 15. On power-up, the subregisters within the configuration register bank contain all 0s by default. ADC DATA REGISTER (ADDRESS 0x01) Table 15. Configuration Register Bank Subregisters The 16-bit, read-only ADC data register provides read access to the most recent ADC conversion result. This register provides 10 bits of conversion data, four channel identifier bits, and two alert bits (see the ADC Conversion Control section). Subaddress (Hex) 0x01 0x02 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x20 0x21 0x30 0x31 ADC SEQUENCE REGISTER (ADDRESS 0x03) The 16-bit, read/write ADC sequence register allows the user to specify a preprogrammed sequence of ADC channels for conversion. The ADC converts on each of the specified ADC channels in turn. For more information, see the ADC Conversion Control section. Table 16 describes the register bit functions. Bit D15 is the first bit in the data stream. On power-up, the ADC sequence register contains all 0s by default. Temperature sensor results can be inserted into the sequence by writing a 1 to Bit D8 of the ADC sequence register, provided that the temperature sensor has been enabled in the temperature sensor subregister within the configuration register bank (see the Temperature Sensor Subregister (Address 0x20) section). 1 All subregisters in the configuration register bank are read/write. Table 16. ADC Sequence Register, Bit Function Descriptions Bits [D15:D9] D8 Bit Name Reserved TSENSE readback enable R/W R/W R/W D7 ADC Channel 7 convert R/W D6 ADC Channel 6 convert R/W D5 ADC Channel 5 convert R/W D4 ADC Channel 4 convert R/W D3 ADC Channel 3 convert R/W D2 ADC Channel 2 convert R/W D1 ADC Channel 1 convert R/W D0 ADC Channel 0 convert R/W Subregister Name1 Digital output driver Digital I/O function General VIN RANGE0 VIN RANGE1 ADC sampling mode VIN filter Conversion delay control VIN ALERT0 routing VIN ALERT1 routing Temperature sensor Temperature sensor alert routing GPIO2/DAC DISABLE0 GPIO4/DAC DISABLE1 Description Reserved 0 = disable TSENSE readback 1 = enable TSENSE readback 0 = disable conversion of Channel 7 1 = enable conversion of Channel 7 0 = disable conversion of Channel 6 1 = enable conversion of Channel 6 0 = disable conversion of Channel 5 1 = enable conversion of Channel 5 0 = disable conversion of Channel 4 1 = enable conversion of Channel 4 0 = disable conversion of Channel 3 1 = enable conversion of Channel 3 0 = disable conversion of Channel 2 1 = enable conversion of Channel 2 0 = disable conversion of Channel 1 1 = enable conversion of Channel 1 0 = disable conversion of Channel 0 1 = enable conversion of Channel 0 Rev. A | Page 21 of 40 AD7292 Data Sheet Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) The 16-bit digital output driver subregister enables the output drivers of the digital I/O pins. Setting Bits[D11:D0] to 1 enables the corresponding digital I/O output driver. Six of the 12 digital I/O pins offer mixed functionality (see Table 18). When a digital I/O pin is configured as a GPIO pin and its output is enabled, its value is controlled by the GPIO register (see the GPIO Register (Address 0x0B) section). Six of the 12 GPIO pins offer dual functionality. To enable standard GPIO functionality, write a 1 to the corresponding bit in the 16-bit digital I/O subregister. To enable the alternative functionality, write a 0 to the appropriate bit (see Table 18). For example, to configure the GPIO6/BUSY pin as an ADC busy pin, write a 0 to Bit D6 of Address 0x02. Table 17. Digital Output Driver Subregister, Bit Function Descriptions Bits [D15:D12] D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Reserved GPIO11 output GPIO10 output GPIO9 output GPIO8 output GPIO7 output GPIO6 output GPIO5 output GPIO4 output GPIO3 output GPIO2 output GPIO1 output GPIO0 output R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved 0 = disable GPIO11 output driver; 1 = enable GPIO11 output driver 0 = disable GPIO10 output driver; 1 = enable GPIO10 output driver 0 = disable GPIO9 output driver; 1 = enable GPIO9 output driver 0 = disable GPIO8 output driver; 1 = enable GPIO8 output driver 0 = disable GPIO7 output driver; 1 = enable GPIO7 output driver 0 = disable GPIO6 output driver; 1 = enable GPIO6/BUSY output driver 0 = disable GPIO5 output driver; 1 = enable GPIO5 output driver 0 = disable GPIO4 output driver; 1 = enable GPIO4/DAC DISABLE1 output driver 0 = disable GPIO3 output driver; 1 = enable GPIO3/LDAC output driver 0 = disable GPIO2 output driver; 1 = enable GPIO4/DAC DISABLE0 output driver 0 = disable GPIO1 output driver; 1 = enable GPIO1/ALERT1 output driver 0 = disable GPIO0 output driver; 1 = enable GPIO1/ALERT0 output driver Table 18. Digital I/O Function Subregister, Bit Function Descriptions Bits [D15:D12] D11 Bit Name Reserved GPIO11 R/W R/W R/W D10 GPIO10 R/W D9 GPIO9 R/W D8 GPIO8 R/W D7 GPIO7 R/W D6 GPIO6/BUSY R/W D5 GPIO5 R/W D4 GPIO4/DAC DISABLE1 R/W D3 GPIO3/LDAC R/W D2 GPIO2/DAC DISABLE0 R/W D1 GPIO1/ALERT1 R/W D0 GPIO0/ALERT0 R/W Description Reserved 0 = reserved 1 = enable the GPIO11 function 0 = reserved 1 = enable the GPIO10 function 0 = reserved 1 = enable the GPIO9 function 0 = reserved 1 = enable the GPIO8 function 0 = reserved 1 = enable the GPIO7 function 0 = enable the ADC busy output function 1 = enable the GPIO6 function 0 = reserved 1 = enable the GPIO5 function 0 = enable the DAC DISABLE1 input function 1 = enable the GPIO4 function 0 = enable the LDAC input function 1 = enable the GPIO3 function 0 = enable the DAC DISABLE0 input function 1 = enable the GPIO2 function 0 = enable the ALERT1 output function 1 = enable the GPIO1 function 0 = enable the ALERT0 output function 1 = enable the GPIO0 function Rev. A | Page 22 of 40 Data Sheet AD7292 General Subregister (Address 0x08) When the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins are configured as DAC disable pins (via the digital I/O function subregister), Bits[D2:D1] of the 16-bit general subregister control the power disable mode of these two pins. Table 19 shows the four power disable modes. The GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 subregisters determine which DAC outputs are controlled by the GPIO2/DAC DISABLE0 and GPIO4/ DAC DISABLE1 pins (see Table 29 and Table 30). Bit D5 and Bit D4 of the general subregister are used to configure the polarity of the ALERT output pins when the GPIO1/ALERT1 and GPIO0/ALERT0 pins are configured as alert outputs (see the Digital Output Driver Subregister (Address 0x01) section and the Digital I/O Function Subregister (Address 0x02) section). Bit D8 is used to select the source of the voltage reference used for the AD7292. When this bit is set to 1, the external reference is used. When this bit is set to 0, the internal reference is used. Table 19. General Subregister, Bit Function Descriptions Bits [D15:D9] D8 Bit Name Reserved Reference mode R/W R/W R/W [D7:D6] D5 Reserved ALERT1 polarity R/W R/W D4 ALERT0 polarity R/W D3 [D2:D1] Reserved DAC disable mode R/W R/W D0 Reserved R/W Description Reserved. This bit specifies whether the internal reference or an external reference is used. 0 = internal reference used (default). 1 = external reference used. Reserved. When the GPIO1/ALERT1 pin is configured to function as an alert, this bit sets the polarity of the ALERT1 pin. 0 = active low (default). 1 = active high. When the GPIO0/ALERT0 pin is configured to function as an alert, this bit sets the polarity of the ALERT0 pin. 0 = active low (default). 1 = active high. Reserved. These bits control the disable mode of the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins when these pins are configured to function as DAC disable pins. 00 = 1 k and 100 k resistors in parallel to ground (default). 01 = 100 k resistor to ground. 10 = 1 k resistor to ground. 11 = high impedance. Reserved. Rev. A | Page 23 of 40 AD7292 Data Sheet VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) The 16-bit VIN RANGE0 and VIN RANGE1 subregisters specify a divide-by-2 factor for each analog input channel, VIN0 to VIN7. A divide-by-2 factor from both the VIN RANGE0 and VIN RANGE1 subregisters can be applied to each channel; that is, setting Bit D0 of VIN RANGE1 and Bit D0 of VIN RANGE0 enables a divide-by-4 factor for the VIN0 input range. The settings of the VIN RANGE0 and VIN RANGE1 bits are ignored if samples are with respect to AVDD (see the ADC Sampling Mode Subregister (Address 0x12) section). Table 20. VIN RANGE0 and VIN RANGE1 Subregisters, Bit Function Descriptions (Default = 0) Bits [D15:D8] D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Reserved VIN7 range VIN6 range VIN5 range VIN4 range VIN3 range VIN2 range VIN1 range VIN0 range R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Analog input range for VIN7 (see Table 21) Analog input range for VIN6 (see Table 21) Analog input range for VIN5 (see Table 21) Analog input range for VIN4 (see Table 21) Analog input range for VIN3 (see Table 21) Analog input range for VIN2 (see Table 21) Analog input range for VIN1 (see Table 21) Analog input range for VIN0 (see Table 21) Table 21. Analog Input Range Selection Subregister Bit Settings VIN RANGE1 VIN RANGE0 0 0 0 1 1 0 1 1 Sample with Respect to AGND Single-Ended Input Range Differential Input Range (VIN0 to VIN7) (VIN0 and VIN1 Only) 0 V to 4 x VREF -4 x VREF to +4 x VREF 0 V to 2 x VREF -2 x VREF to +2 x VREF 0 V to 2 x VREF -2 x VREF to +2 x VREF 0 V to VREF -VREF to +VREF Rev. A | Page 24 of 40 Sample with Respect to AVDD Single-Ended Input Range (VIN0 to VIN7) (AVDD - 4 x VREF) to AVDD Not applicable Not applicable Not applicable Data Sheet AD7292 ADC Sampling Mode Subregister (Address 0x12) Table 22 lists the bit function descriptions for the 16-bit ADC sampling mode subregister. Bit D0 allows the user to enable differential input mode for analog input channels VIN0 and VIN1. When enabled and converting on VIN0, the differential input to the ADC is (VIN0, VIN1). When enabled and converting on VIN1, the differential input to the ADC is (VIN1, VIN0). To use differential mode, Bit D0 must be set to 1. Bits[D15:D8] specify whether the corresponding analog input, VIN7 to VIN0, is measured with respect to AVDD or AGND. Table 22. ADC Sampling Mode Subregister, Bit Function Descriptions (Default = 0) Bits D15 Bit Name VIN7 sampling mode R/W R/W D14 VIN6 sampling mode R/W D13 VIN5 sampling mode R/W D12 VIN4 sampling mode R/W D11 VIN3 sampling mode R/W D10 VIN2 sampling mode R/W D9 VIN1 sampling mode R/W D8 VIN0 sampling mode R/W [D7:D1] D0 Reserved VIN0/VIN1 differential mode R/W R/W Description This bit specifies whether VIN7 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. This bit specifies whether VIN6 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. This bit specifies whether VIN5 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. This bit specifies whether VIN4 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. This bit specifies whether VIN3 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. This bit specifies whether VIN2 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. This bit specifies whether VIN1 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. This bit specifies whether VIN0 is measured with respect to AVDD or AGND. 0 = sample with respect to AVDD. 1 = sample with respect to AGND. Reserved. This bit specifies whether VIN0 and VIN1 function as two single-ended inputs or as a differential pair. 0 = single-ended mode. 1 = differential mode. Rev. A | Page 25 of 40 AD7292 Data Sheet VIN Filter Subregister (Address 0x13) Conversion Delay Control Subregister (Address 0x14) The 16-bit VIN filter subregister enables digital filtering of the analog inputs channels. The digital filter consists of a simple low-pass filter function to help reduce unwanted noise on dc signals. Writing a 1 to Bits[D7:D0] in this subregister enables digital filtering of the corresponding analog input channel (see Table 23). On power-up, the VIN filter subregister contains all 0s by default. The 16-bit conversion delay control subregister is used to delay the start (including the sample point) of a conversion. The delay is a count of internal ADC clocks following the falling SCLK signal that triggers the start of a conversion. For example, if the conversion delay control subregister holds the value 0x0003, three ADC clocks are counted before the ADC enters hold mode and the conversion begins. The ADC clock has a period of 40 ns typically. If the conversion delay control subregister is set to a nonzero value N, the ADC waits for the programmed number of ADC clock periods (N) after a conversion is triggered before sampling the input. If the register holds the default value of 0, there is no delay, and the conversion is started from the falling SCLK that triggers the start of the conversion. When using the conversion delay, the conversion is extended by N + 1 clocks. Table 23. VIN Filter Subregister, Bit Function Descriptions Bits [D15:D8] D7 Bit Name Reserved Enable digital filtering of VIN7 R/W R/W R/W D6 Enable digital filtering of VIN6 R/W D5 Enable digital filtering of VIN5 R/W D4 Enable digital filtering of VIN4 R/W D3 Enable digital filtering of VIN3 R/W D2 Enable digital filtering of VIN2 R/W D1 Enable digital filtering of VIN1 R/W D0 Enable digital filtering of VIN0 R/W Description Reserved 0 = disable digital filtering of VIN7 1 = enable digital filtering of VIN7 0 = disable digital filtering of VIN6 1 = enable digital filtering of VIN6 0 = disable digital filtering of VIN5 1 = enable digital filtering of VIN5 0 = disable digital filtering of VIN4 1 = enable digital filtering of VIN4 0 = disable digital filtering of VIN3 1 = enable digital filtering of VIN3 0 = disable digital filtering of VIN2 1 = enable digital filtering of VIN2 0 = disable digital filtering of VIN1 1 = enable digital filtering of VIN1 0 = disable digital filtering of VIN0 1 = enable digital filtering of VIN0 Table 24. Conversion Delay Control Subregister, Bit Function Descriptions Bits [D15:D0] Bit Name Delay value R/W R/W Description These bits specify the 16-bit delay value (0 to 0xFFFF) before the start of a conversion. The delay is a count of internal ADC clocks following the falling SCLK signal. Rev. A | Page 26 of 40 Data Sheet AD7292 VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) The 16-bit VIN ALERT0 and VIN ALERT1 subregisters enable the routing of alerts from the analog input channels, VIN0 to VIN7, to the GPIO0/ALERT0 and GPIO1/ALERT1 pins (see Table 25 and Table 26. For information about how to configure the GPIO0/ALERT0 and GPIO1/ALERT1 pins as alert pins, see the Digital I/O Function Subregister (Address 0x02) section and the Digital Output Driver Subregister (Address 0x01) section. For information about how to enable routing of the temperature sensor alerts, see the Temperature Sensor Alert Routing Subregister (Address 0x21) section. Table 25. VIN ALERT0 Routing Subregister, Bit Function Descriptions Bits [D15:D8] D7 Bit Name Reserved Route VIN7 alerts to ALERT0 pin R/W R/W R/W D6 Route VIN6 alerts to ALERT0 pin R/W D5 Route VIN5 alerts to ALERT0 pin R/W D4 Route VIN4 alerts to ALERT0 pin R/W D3 Route VIN3 alerts to ALERT0 pin R/W D2 Route VIN2 alerts to ALERT0 pin R/W D1 Route VIN1 alerts to ALERT0 pin R/W D0 Route VIN0 alerts to ALERT0 pin R/W Description Reserved 0 = disable routing of VIN7 alerts to the ALERT0 pin 1 = enable routing of VIN7 alerts to the ALERT0 pin 0 = disable routing of VIN6 alerts to the ALERT0 pin 1 = enable routing of VIN6 alerts to the ALERT0 pin 0 = disable routing of VIN5 alerts to the ALERT0 pin 1 = enable routing of VIN5 alerts to the ALERT0 pin 0 = disable routing of VIN4 alerts to the ALERT0 pin 1 = enable routing of VIN4 alerts to the ALERT0 pin 0 = disable routing of VIN3 alerts to the ALERT0 pin 1 = enable routing of VIN3 alerts to the ALERT0 pin 0 = disable routing of VIN2 alerts to the ALERT0 pin 1 = enable routing of VIN2 alerts to the ALERT0 pin 0 = disable routing of VIN1 alerts to the ALERT0 pin 1 = enable routing of VIN1 alerts to the ALERT0 pin 0 = disable routing of VIN0 alerts to the ALERT0 pin 1 = enable routing of VIN0 alerts to the ALERT0 pin Table 26. VIN ALERT1 Routing Subregister, Bit Function Descriptions Bits [D15:D0] D7 Bit Name Reserved Route VIN7 alerts to ALERT1 pin R/W R/W R/W D6 Route VIN6 alerts to ALERT1 pin R/W D5 Route VIN5 alerts to ALERT1 pin R/W D4 Route VIN4 alerts to ALERT1 pin R/W D3 Route VIN3 alerts to ALERT1 pin R/W D2 Route VIN2 alerts to ALERT1 pin R/W D1 Route VIN1 alerts to ALERT1 pin R/W D0 Route VIN0 alerts to ALERT1 R/W Description Reserved 0 = disable routing of VIN7 alerts to the ALERT1 pin 1 = enable routing of VIN7 alerts to the ALERT1 pin 0 = disable routing of VIN6 alerts to the ALERT1 pin 1 = enable routing of VIN6 alerts to the ALERT1 pin 0 = disable routing of VIN5 alerts to the ALERT1 pin 1 = enable routing of VIN5 alerts to the ALERT1 pin 0 = disable routing of VIN4 alerts to the ALERT1 pin 1 = enable routing of VIN4 alerts to the ALERT1 pin 0 = disable routing of VIN3 alerts to the ALERT1 pin 1 = enable routing of VIN3 alerts to the ALERT1 pin 0 = disable routing of VIN2 alerts to the ALERT1 pin 1 = enable routing of VIN2 alerts to the ALERT1 pin 0 = disable routing of VIN1 alerts to the ALERT1 pin 1 = enable routing of VIN1 alerts to the ALERT1 pin 0 = disable routing of VIN0 alerts to the ALERT1 pin 1 = enable routing of VIN0 alerts to the ALERT1 pin Rev. A | Page 27 of 40 AD7292 Data Sheet Temperature Sensor Subregister (Address 0x20) The 16-bit temperature sensor subregister enables temperature sensor conversions and digital filtering of the temperature sensor channel. To enable temperature sensor conversions or digital filtering, the corresponding bit in the temperature sensor subregister must be set to 1 (see Table 27). On power-up, the temperature sensor subregister contains all 0s by default. Temperature Sensor Alert Routing Subregister (Address 0x21) For information about how to configure the GPIO0/ALERT0 and GPIO1/ALERT1 pins as alert pins, see the Digital I/O Function Subregister (Address 0x02) section and the Digital Output Driver Subregister (Address 0x01) section. For information about how to enable routing of the analog input channel alerts, see the VIN Filter Subregister (Address 0x13) and Conversion Delay Control Subregister (Address 0x14) section. The 16-bit temperature sensor alert routing subregister enables the routing of alerts from the internal temperature sensor to the GPIO0/ALERT0 and GPIO1/ALERT1 pins (see Table 28). Table 27. Temperature Sensor Subregister, Bit Function Descriptions Bits [D15:D9] D8 Bit Name Reserved Enable/disable digital filtering of TSENSE R/W R/W R/W [D7:D1] D0 Reserved Enable/disable TSENSE conversions R/W R/W Description Reserved. This bit specifies whether digital filtering is enabled on the temperature sensor channel. 0 = disable digital filtering of the temperature sensor channel (default). 1 = enable digital filtering of the temperature sensor channel. Reserved. This bit enables or disables conversion of the temperature sensor channel. 0 = disable TSENSE conversions (default). 1 = enable TSENSE conversions. Table 28. Temperature Sensor Alert Routing Subregister, Bit Function Descriptions Bits [D15:D9] D8 Bit Name Reserved Route TSENSE alerts to ALERT1 pin R/W R/W R/W [D7:D1] D0 Reserved Route TSENSE alerts to ALERT0 pin R/W R/W Description Reserved. This bit specifies whether alerts from the internal temperature sensor are routed to the ALERT1 pin. 0 = disable routing of alerts from the temperature sensor to the ALERT1 pin (default). 1 = enable routing of alerts from the temperature sensor to the ALERT1 pin. Reserved. This bit specifies whether alerts from the internal temperature sensor are routed to the ALERT0 pin. 0 = disable routing of alerts from the temperature sensor to the ALERT0 pin (default). 1 = enable routing of alerts from the temperature sensor to the ALERT0 pin. Rev. A | Page 28 of 40 Data Sheet AD7292 GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) The 16-bit, read/write GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 subregisters specify which DAC channels are disabled by the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins. For example, when Bit D0 in the GPIO2/DAC DISABLE0 subregister is set to 1, the GPIO2/DAC DISABLE0 pin disables DAC output VOUT0 when the pin is taken high. On power-up, these subregisters contain all 0s by default. For information about how to enable the DAC disable function on the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins, see the Digital Output Driver Subregister (Address 0x01) section and the Digital I/O Function Subregister (Address 0x02) section. Table 29. GPIO2/DAC DISABLE0 Subregister, Bit Function Descriptions Bits [D15:D4] D3 Bit Name Reserved Disable VOUT3 pin R/W R/W R/W D2 Disable VOUT2 pin R/W D1 Disable VOUT1 pin R/W D0 Disable VOUT0 pin R/W Description Reserved. This bit specifies whether the VOUT3 output is disabled when the GPIO2/DAC DISABLE0 pin is high. 0 = disable control of VOUT3 by the GPIO2/DAC DISABLE0 pin (default). 1 = enable control of VOUT3 by the GPIO2/DAC DISABLE0 pin. This bit specifies whether the VOUT2 output is disabled when the GPIO2/DAC DISABLE0 pin is high. 0 = disable control of VOUT2 by the GPIO2/DAC DISABLE0 pin (default). 1 = enable control of VOUT2 by the GPIO2/DAC DISABLE0 pin. This bit specifies whether the VOUT1 output is disabled when the GPIO2/DAC DISABLE0 pin is high. 0 = disable control of VOUT1 by the GPIO2/DAC DISABLE0 pin (default). 1 = enable control of VOUT1 by the GPIO2/DAC DISABLE0 pin. This bit specifies whether the VOUT0 output is disabled when the GPIO2/DAC DISABLE0 pin is high. 0 = disable control of VOUT0 by the GPIO2/DAC DISABLE0 pin (default). 1 = enable control of VOUT0 by the GPIO2/DAC DISABLE0 pin. Table 30. GPIO4/DAC DISABLE1 Subregister, Bit Function Descriptions Bits [D15:D4] D3 Bit Name Reserved Disable VOUT3 pin R/W R/W R/W D2 Disable VOUT2 pin R/W D1 Disable VOUT1 pin R/W D0 Disable VOUT0 pin R/W Description Reserved. This bit specifies whether the VOUT3 output is disabled when the GPIO4/DAC DISABLE1 pin is high. 0 = disable control of VOUT3 by the GPIO4/DAC DISABLE1 pin (default). 1 = enable control of VOUT3 by the GPIO4/DAC DISABLE1 pin. This bit specifies whether the VOUT2 output is disabled when the GPIO4/DAC DISABLE1 pin is high. 0 = disable control of VOUT2 by the GPIO4/DAC DISABLE1 pin (default). 1 = enable control of VOUT2 by the GPIO4/DAC DISABLE1 pin. This bit specifies whether the VOUT1 output is disabled when the GPIO4/DAC DISABLE1 pin is high. 0 = disable control of VOUT1 by the GPIO4/DAC DISABLE1 pin (default). 1 = enable control of VOUT1 by the GPIO4/DAC DISABLE1 pin. This bit specifies whether the VOUT0 output is disabled when the GPIO4/DAC DISABLE1 pin is high. 0 = disable control of VOUT0 by the GPIO4/DAC DISABLE1 pin (default). 1 = enable control of VOUT0 by the GPIO4/DAC DISABLE1 pin. Rev. A | Page 29 of 40 AD7292 Data Sheet ALERT LIMITS REGISTER BANK (ADDRESS 0x06) Table 31. Alert Limits Register Bank Subregisters The alert limits register bank comprises subregisters that set the high and low alert limits for the eight analog input channels and the temperature sensor channel (see Table 31). Each subregister is 16 bits in length; values are 10-bit, left-justified (padded with 0s as the 6 LSBs). On power-up, the low limit and hysteresis subregisters contain all 0s, whereas the high limit subregisters are set to 0xFFC0. Subaddress (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 to 0x2F 0x30 0x31 0x32 0x33 to 0xFF If a conversion result exceeds the high or low limit set in the alert limits subregister, the AD7292 signals an alert in one or more of the following ways: * * * Via hardware using the GPIO0/ALERT0 and GPIO1/ALERT1 pins (see the Hardware Alert Pins section) Via software using the alert flag bits in the conversion result registers (see the ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) section and the TSENSE Conversion Result Register (Address 0x20) section) Via software using the alert bits in the alert flags register bank (see the Alert Flags Register Bank (Address 0x07) section) Alert High Limit and Alert Low Limit Subregisters The alert high limit subregisters store the upper limit that activates an alert. If the conversion result is greater than the value in the alert high limit subregister, an alert is triggered. The alert low limit subregister stores the lower limit that activates an alert. If the conversion result is less than the value in the alert low limit subregister, an alert is triggered. An alert associated with either the alert high limit or alert low limit subregister is cleared automatically after the monitored signal is back in range, that is, when the conversion result returns between the configured high and low limits. The contents of the alert flags subregisters are updated after each conversion (see the Alert Flags Register Bank (Address 0x07) section). 1 Subregister Name1 VIN0 alert high limit VIN0 alert low limit VIN0 hysteresis VIN1 alert high limit VIN1 alert low limit VIN1 hysteresis VIN2 alert high limit VIN2 alert low limit VIN2 hysteresis VIN3 alert high limit VIN3 alert low limit VIN3 hysteresis VIN4 alert high limit VIN4 alert low limit VIN4 hysteresis VIN5 alert high limit VIN5 alert low limit VIN5 hysteresis VIN6 alert high limit VIN6 alert low limit VIN6 hysteresis VIN7 alert high limit VIN7 alert low limit VIN7 hysteresis Reserved TSENSE alert high limit TSENSE alert low limit TSENSE hysteresis Reserved All subregisters in the alert limits register bank are read/write. Hysteresis Subregisters Each channel has an associated hysteresis subregister that stores the hysteresis value, N (see Table 31). The hysteresis subregisters can be used to avoid flicker on the GPIO0/ALERT0 and GPIO1/ ALERT1 pins. If the hysteresis function is enabled, the conversion result must return to a value of at least N LSB below the alert high limit subregister value, or N LSB above the alert low limit subregister value for the alert output pins and alert flag bits to be reset (see Figure 46). The value of N is taken from the 10 MSBs of the 16-bit, read/write hysteresis subregister. For more information, see the Hysteresis section. Rev. A | Page 30 of 40 Data Sheet AD7292 ALERT FLAGS REGISTER BANK (ADDRESS 0x07) If a conversion result activates an alert (as specified in the alert limits register bank), the alert flags register bank can be read to obtain more information about the alert. This register bank contains the ADC alert flags and TSENSE alert flags subregisters. Both subregisters store flags that are triggered when the minimum or maximum conversion limits, as defined in the alert limits register bank, are exceeded. Table 32. Alert Flags Register Bank Subregisters Subaddress (Hex) 0x00 0x01 0x02 0x03 to 0xFF 1 Subregister Name1 ADC alert flags subregister Reserved TSENSE alert flags subregister Reserved Bits in the alert flags subregisters can be reset by writing 1 to the selected bits. ADC Alert Flags and TSENSE Alert Flags Subregisters (Address 0x00 and Address 0x02) The ADC alert flags subregister stores alerts for the analog voltage conversion channels, VIN0 to VIN7. The TSENSE alert flags subregister stores alerts for the temperature sensor channel. These subregisters contain two status bits per channel: one corresponding to the high limit, and the other corresponding to the low limit. A bit with a status of 1 shows the channel on which the violation occurred and whether the violation occurred on the high or low limit. If additional alert events occur on any other channels after the first alert is triggered but before the alert flags subregister is read, the corresponding bits for the new alert events are also set. For example, if Bit D14 in the ADC alert flags subregister is set to 1, the low limit on Channel 7 has been exceeded, whereas if Bit D3 is set to 1, the high limit on Channel 1 has been exceeded. To find out which channel or channels caused the alert flag, the user must read the ADC alert flags subregister or the TSENSE alert flags subregister. If the ADC alert flags subregister or the TSENSE alert flags subregister is accessed with both the read and write bits of the address pointer set to 1, the stored alert flags can be read and reset in one operation. A blanket reset can be performed by writing 0xFFFF to the ADC alert flags subregister, or 0x0003 to the TSENSE alert flags subregister, thus clearing all alert flags. Table 33. ADC Alert Flags Subregister, Bit Function Descriptions Bits D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name VIN7 high limit flag VIN7 low limit flag VIN6 high limit flag VIN6 low limit flag VIN5 high limit flag VIN5 low limit flag VIN4 high limit flag VIN4 low limit flag VIN3 high limit flag VIN3 low limit flag VIN2 high limit flag VIN2 low limit flag VIN1 high limit flag VIN1 low limit flag VIN0 high limit flag VIN0 low limit flag R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 = VIN7 high limit exceeded 1 = VIN7 low limit exceeded 1 = VIN6 high limit exceeded 1 = VIN6 low limit exceeded 1 = VIN5 high limit exceeded 1 = VIN5 low limit exceeded 1 = VIN4 high limit exceeded 1 = VIN4 low limit exceeded 1 = VIN3 high limit exceeded 1 = VIN3 low limit exceeded 1 = VIN2 high limit exceeded 1 = VIN2 low limit exceeded 1 = VIN1 high limit exceeded 1 = VIN1 low limit exceeded 1 = VIN0 high limit exceeded 1 = VIN0 low limit exceeded Table 34. TSENSE Alert Flags Subregister, Bit Function Descriptions Bits [D15:D2] D1 D0 Bit Name Reserved TSENSE high limit flag TSENSE low limit flag R/W R/W R/W R/W Description Reserved 1 = TSENSE high limit exceeded 1 = TSENSE low limit exceeded Rev. A | Page 31 of 40 AD7292 Data Sheet MINIMUM AND MAXIMUM REGISTER BANK (ADDRESS 0x08) OFFSET REGISTER BANK (ADDRESS 0x09) The minimum and maximum register bank contains the minimum and maximum conversion values for each of the eight analog input channels and the temperature sensor channel. Values are 10-bit, left justified. The minimum and maximum subregisters are cleared when a value is written to them--that is, they return to their power-up values. This means that if a subregister is accessed with both the read and write bits set, the stored minimum or maximum value can be read and reset in one operation. On power-up, the minimum value subregisters contain 0xFFC0, and the maximum value subregisters contain 0x0000. Table 35. Minimum and Maximum Register Bank Subregisters Subaddress (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 to 0x1F 0x20 0x21 0x22 to 0xFF 1 Subregister Name1 VIN0 maximum value VIN0 minimum value VIN1 maximum value VIN1 minimum value VIN2 maximum value VIN2 minimum value VIN3 maximum value VIN3 minimum value VIN4 maximum value VIN4 minimum value VIN5 maximum value VIN5 minimum value VIN6 maximum value VIN6 minimum value VIN7 maximum value VIN7 minimum value Reserved TSENSE maximum value TSENSE minimum value Reserved The offset register bank contains nine subregisters. Each of the eight analog input channels, as well as the temperature sensor channel, has a corresponding offset register (see Table 36). Table 36. Offset Register Bank Subregisters Subaddress (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x10 1 Subregister Name1 VIN0 offset VIN1 offset VIN2 offset VIN3 offset VIN4 offset VIN5 offset VIN6 offset VIN7 offset Temperature sensor offset All subregisters in the offset register bank are read/write. Each 8-bit, read/write offset subregister stores data in twos complement format. Values are added to the ADC conversion results. The offset encoding scheme used for the analog input channels and the temperature sensor are shown in Table 39 and Table 40, respectively. The default value for all subregisters in the offset register bank is 0x00. When bits in these subregisters are set, the offset value is cumulative. Table 37 provides examples of analog input channel values, and Table 38 provides examples of temperature sensor channel values. Table 37. Examples of Analog Input Channel Offset Values Offset Subregister Value 10000000 11000000 00001000 Offset Value (LSB) -32 -16 +2 Table 38. Examples of Temperature Sensor Channel Offset Values Bits in the minimum and maximum subregisters can be reset by writing 1 to the selected bits. Offset Subregister Value 10000000 11000000 00001000 Offset Value (C) -16 -8 +1 Table 39. VIN0 to VIN7 Offset Encoding Scheme D7 -32 LSB D6 +16 LSB D5 +8 LSB D4 +4 LSB D3 +2 LSB D2 +1 LSB D1 +0.5 LSB D0 +0.25 LSB D3 +1C D2 +0.5C D1 +0.25C D0 +0.125C Table 40. Temperature Sensor Offset Encoding Scheme D7 -16C D6 +8C D5 +4C D4 +2C Rev. A | Page 32 of 40 Data Sheet AD7292 DAC BUFFER ENABLE REGISTER (ADDRESS 0x0A) GPIO REGISTER (ADDRESS 0x0B) The 16-bit, read/write DAC buffer enable register enables the DAC output buffers. Setting the appropriate bit to 1 enables the corresponding DAC output buffer (see Table 41). On power-up, the DAC buffer enable register contains all 0s by default. The 16-bit, read/write GPIO register is used to read or write data to the GPIO pins, provided that the GPIO functionality is enabled (see the Digital Output Driver Subregister (Address 0x01) section and the Digital I/O Function Subregister (Address 0x02) section). On power-up, the GPIO register contains all 0s by default. Table 41. DAC Buffer Enable Register, Bit Function Descriptions Bits [D15:D4] D3 Bit Name Reserved Enable DAC 3 R/W R/W R/W D2 Enable DAC 2 R/W D1 Enable DAC 1 R/W D0 Enable DAC 0 R/W Description Reserved 0 = disable DAC 3 output buffer (default) 1 = enable DAC 3 output buffer 0 = disable DAC 2 output buffer (default) 1 = enable DAC 2 output buffer 0 = disable DAC 1 output buffer (default) 1 = enable DAC 1 output buffer 0 = disable DAC 0 output buffer (default) 1 = enable DAC 0 output buffer Table 42. GPIO Register, Bit Function Descriptions Bits [D15:D12] D11 Bit Name Reserved GPIO11 R/W R/W R/W D10 GPIO10 R/W D9 GPIO9 R/W D8 GPIO8 R/W D7 GPIO7 R/W D6 GPIO6 R/W D5 GPIO5 R/W D4 GPIO4 R/W D3 GPIO3 R/W D2 GPIO2 R/W D1 GPIO1 R/W D0 GPIO0 R/W Description Reserved 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read 0 = low output for write; low input for read 1 = high output for write; high input for read Rev. A | Page 33 of 40 AD7292 Data Sheet CONVERSION COMMAND REGISTER (ADDRESS 0x0E) TSENSE CONVERSION RESULT REGISTER (ADDRESS 0x20) The conversion command signals the ADC to begin conversions. See the ADC Conversion Control section for more information. The 16-bit, read-only TSENSE conversion result register stores the ADC data generated from the internal temperature sensor. The temperature data is stored in a 14-bit straight binary format. Bit D2 has a weight of 0.03125C. An output of all 0s is equal to -256C; this value is output by the AD7292 until the first measurement is completed. An output of 10 0000 0000 0000 corresponds to 0C. ADC CONVERSION RESULT REGISTERS, VIN0 TO VIN7 (ADDRESS 0x10 TO ADDRESS 0x17) The 16-bit, read-only ADC conversion result registers store the conversion results of the eight ADC input channels. Bits[D15:D6] store the 10-bit, straight binary result; Bits[D5:D0] contain the channel ID and alert information. Table 43 lists the contents of the two bytes that are read from the ADC conversion result registers. Channel ID numbers 0 to 7 correspond to the analog input channels, VIN0 to VIN7. When digital filtering is disabled, Bit D3 and Bit D2 are set to 0, producing a 12-bit straight binary result with an LSB of 0.125C. See the Temperature Sensor section for more information. DAC CHANNEL REGISTERS (ADDRESS 0x30 TO ADDRESS 0x33) Writing to the DAC channel registers sets the DAC output voltage codes. For more information, see the DAC Output Control section. Table 43. ADC Conversion Result Register Format MSB D15 B9 D14 B8 D13 B7 D12 B6 D11 B5 D10 B4 D9 B3 D8 B2 [D5:D2] 4-bit channel ID (0000 to 0111) D1 TSENSE alert flag LSB D0 ADC alert flag D7 B1 D6 B0 D6 B4 D5 B3 D4 B2 D31 B1 D21 B0 D1 TSENSE alert flag LSB D0 ADC alert flag D6 B0 D5 0 D4 0 D3 0 D2 0 D1 Copy LSB D0 LDAC Table 44. TSENSE Conversion Result Register Format MSB D15 B13 1 D14 B12 D13 B11 D12 B10 D11 B9 D10 B8 D9 B7 D8 B6 D7 B5 When digital filter is enabled (see the Temperature Sensor Subregister (Address 0x20) section). Table 45. DAC Channel Register Format MSB D15 B9 D14 B8 D13 B7 D12 B6 D11 B5 D10 B4 D9 B3 D8 B2 D7 B1 Rev. A | Page 34 of 40 Data Sheet AD7292 ADC CONVERSION CONTROL ADC CONVERSION COMMAND To initiate an ADC conversion on a channel, the conversion command must be written to the AD7292. The special address pointer byte, 0x8E, consists of the conversion command register (Address 0x0E) with the MSB read bit set to 1 to signify an ADC conversion. When the conversion command is received, the AD7292 uses the current value of the address pointer to determine which channel to convert on. In Figure 40, the first byte sets the address pointer with both the read and write bits cleared and sets Bits[D5:D0] to point to the selected channel conversion result register. The second byte contains the conversion command with the read bit set. After receiving the conversion command, the AD7292 stays in conversion mode, performing a new ADC conversion at the end of each read, until the CS (chip select) input signal is taken high. In Figure 41, the address pointer is set to point to the ADC data register (Address 0x01) with both the read and write bits cleared. The conversion command is issued, and the contents of the ADC sequence register specify the sequence of ADC channels for conversion (see the ADC Sequencer section). In this example, the ADC sequence register is programmed to convert on analog input channels VIN0 and VIN1. The AD7292 stays in conversion mode and performs a new ADC conversion at the end of each read until the CS input signal is taken high. In the examples shown in Figure 40 and Figure 41, an SCLK delay is inserted following the conversion command to allow the ADC to perform the conversion before the data is read. If temperature sensor conversions are requested, a longer delay is necessary (see the Temperature Sensor section). In some applications, the SPI bus master may not allow the serial clock to be held low during a read sequence, and it may be necessary to take CS high, as shown in Figure 42. In this case, the CS line must remain low while the ADC conversion is in progress to prevent possible corruption of the ADC result. In the example shown in Figure 42, the address pointer is set to point to the ADC data register (Address 0x01) with both the read and write bits cleared. The conversion command is issued with the read bit set. The CS line is taken high after the conversion on VIN0 is completed. The CS line is then brought low, and the ADC data register is pointed to with the read bit set. The conversion result is clocked out. The conversion command is reissued before the CS line is taken high again, and so on. CS 1 8 16 1 16 1 16 SCLK POINT TO CHANNEL ISSUE CONVERSION FOR CONVERSION COMMAND CONVERSION RESULT FOR SELECTED CHANNEL [D15:D0] DOUT CONVERSION RESULT FOR SELECTED CHANNEL [D15:D0] CONVERT SELECTED CHANNEL BUSY CONVERT SELECTED CHANNEL CONVERT SELECTED CHANNEL NOTES 1. CS CANNOT BE TAKEN HIGH UNTIL AFTER A CHANNEL CONVERSION HAS TAKEN PLACE OR WHEN BUSY IS HIGH. 10660-046 DIN Figure 40. ADC Conversion Command (ADC Sequencer Not Used) CS 1 8 1 16 8 16 1 8 16 SCLK POINT TO ADC DATA REGISTER ISSUE CONVERSION COMMAND VIN0 RESULT [D15:D0] DOUT BUSY CONVERT VIN0 NOTE 2 VIN1 RESULT [D15:D0] CONVERT VIN1 NOTES 1. CS CANNOT BE TAKEN HIGH UNTIL AFTER A CHANNEL CONVERSION HAS TAKEN PLACE OR WHEN BUSY IS HIGH. 2. TEMP SENSOR CONVERSIONS TAKE PLACE EACH 1.25ms AFTER THE NEXT CHANNEL CONVERSION. Figure 41. ADC Conversion Command (ADC Sequencer Used) Rev. A | Page 35 of 40 CONVERT VIN0 10660-047 DIN AD7292 Data Sheet CS 8 1 16 8 1 16 1 32 24 8 16 24 SCLK POINT TO ADC DATA REGISTER POINT TO ADC DATA REGISTER ISSUE CONVERSION COMMAND POINT TO ADC DATA REGISTER ISSUE CONVERSION COMMAND VIN1 RESULT [D15:D0] VIN0 RESULT [D15:D0] DOUT CONVERT VIN0 CONVERT VIN1 10660-048 DIN BUSY Figure 42. ADC Conversion Command (CS Line Taken High After Conversions) CS 1 16 8 24 40 32 1 8 16 SCLK DIN POINT TO ADC SEQUENCE REGISTER WRITE TO ADC SEQUENCE REGISTER [D15:D0] POINT TO ADC DATA REGISTER ISSUE CONVERSION COMMAND CONVERSION RESULT FOR VIN0 [D15:D0] DOUT CONVERT VIN0 BUSY CS 1 16 8 1 8 16 SCLK CONVERSION RESULT FOR VIN1 [D15:D0] DOUT BUSY CONVERT VIN1 CONVERSION RESULT FOR VIN2 [D15:D0] CONVERT VIN2 10660-049 DIN Figure 43. Example of Using the ADC Sequencer ADC SEQUENCER The AD7292 provides an ADC sequencer, which enables the selection of a preprogrammable sequence of channels for conversion. Figure 43 shows the operation of the ADC sequencer. To initiate a write to the ADC sequence register (Address 0x03), point to it in the address pointer register with the write bit set and the read bit cleared. The next two bytes specify the sequence of channels that the ADC converts on (see Table 16). The ADC data register (Address 0x01) is then pointed to and the conversion command is issued. Note that the read bit is set when issuing the conversion command. When the ADC sequencer is used, ADC conversions are triggered based on the contents of the ADC sequence register; the address pointer reverts to its previous value--in this example, the ADC data register--allowing the conversion results to be read back. After the first ADC conversion is complete, the first result is read back, which requires 16 serial clocks. The first 10 bits contain the ADC result, the next four bits are the channel identifier, and the last two bits are alert bits (see Table 43). On the last falling edge of the clock, the next ADC conversion begins. The AD7292 continues converting on the channels specified by the ADC sequence register. On completing the first sequence of conversions, the sequencer loops back and begins the sequence again until CS is taken high. The AD7292 is ready to accept a new address pointer after CS is taken low. It is recommended that the serial clock be kept low during the ADC conversions to ensure that there is no disturbance of the results. Rev. A | Page 36 of 40 Data Sheet AD7292 DAC OUTPUT CONTROL To set the DAC output voltage codes, the user must write to the DAC channel registers (Address 0x30 to Address 0x33). Figure 44 shows an example of how to set the DAC output voltage codes. 1. 2. 3. 4. When the LDAC bit in the DAC channel register is set to 1, the 10-bit DAC value is stored, but the DAC channel output is not updated. When a write to any DAC channel register occurs with the LDAC bit cleared, all DAC channel outputs are updated with the stored values from previous writes. The DAC buffer enable register (Address 0x0A) is pointed to with the write bit set. The following two bytes specify which of the four DAC output buffers are enabled. The DAC channel register (DAC Channel 0 register in Figure 44) is pointed to with the write bit set. The following two bytes contain the value to be written to the DAC channel. When the LDAC bit in the DAC channel register is used to control the updating of the DAC output, the LDAC pin function should be disabled, that is, the GPIO3/LDAC pin should be configured as GPIO3. Note that the process can be reversed--that is, the user can first write a value to the DAC channel register and then enable the DAC output buffer. The GPIO3/LDAC pin can be used to update the DAC outputs with the stored values when the pin is configured as an LDAC pin (see the Digital Output Driver Subregister (Address 0x01) section and the Digital I/O Function Subregister (Address 0x02) section). If the GPIO3/LDAC pin is configured as an LDAC input and is taken high, the DAC output registers are updated; conversely, if this input pin is held low, the DAC value is stored but the channel output is not updated. LDAC OPERATION SIMULTANEOUS UPDATE OF ALL DAC OUTPUTS A write to a DAC channel register (Address 0x30 to Address 0x33) is addressed to the DAC input register; a read from a DAC channel register is addressed to the DAC output register (see Figure 45). The DAC output registers are updated based on the LDAC bit in the DAC channel register or on the polarity of the GPIO3/LDAC pin (if the pin is configured as an LDAC pin). It may be useful to update all four DAC channel registers simultaneously with the same value but not update the DAC outputs (LDAC bit is set to 1; LDAC pin is set to 0). Setting the copy bit (Bit 1) when writing to any DAC channel register instructs the AD7292 to copy the new DAC value to all the DAC input registers. On completion of this write, the DAC channel output is immediately updated to the new value, provided that the LDAC bit in the DAC channel register is not set. CS 1 24 8 48 32 POINT TO DAC BUFFER ENABLE REGISTER DIN WRITE TO DAC BUFFER ENABLE REGISTER [D15:D0] POINT TO DAC CHANNEL 0 REGISTER WRITE TO DAC CHANNEL 0 REGISTER [D15:D0] 10660-050 SCLK Figure 44. Setting the DAC Output Voltage Code READ DAC CHANNEL REGISTER (0x30 TO 0x33) WRITE DAC INPUT REGISTER DAC OUTPUT REGISTER DAC VOUTx 10660-051 SCLK LDAC BIT GPIO3/LDAC PIN1 1PROVIDED THE GPIO3/LDAC PIN IS CONFIGURED AS AN LDAC PIN. Figure 45. DAC Input and Output Registers Rev. A | Page 37 of 40 AD7292 Data Sheet ALERTS AND LIMITS ALERT LIMIT MONITORING FEATURES The alert limits register bank comprises subregisters that set the high and low alert limits for the eight analog input channels and the temperature sensor channel (see Table 31). Each subregister is 16 bits in length; values are 10-bit, left-justified (padded with 0s as the 6 LSBs). On power-up, the low limit and hysteresis subregisters contain all 0s, whereas the high limit subregisters are set to 0xFFC0. The alert high limit subregisters store the upper limit that activates an alert. If the conversion result is greater than the value in the alert high limit subregister, an alert is triggered. The alert low limit subregister stores the lower limit that activates an alert. If the conversion result is less than the value in the alert low limit subregister, an alert is triggered. If a conversion result exceeds the high or low limit set in the alert limits subregister, the AD7292 signals an alert in one or more of the following ways: Via hardware using the GPIO0/ALERT0 and GPIO1/ ALERT1 pins Via software using the alert flag bits in the conversion result registers Via software using the alert bits in the alert flags register bank Hysteresis The hysteresis value determines the reset point for the alert pins and alert flags if a violation of the limits occurs. Each channel has an associated hysteresis subregister that stores the hysteresis value, N (see Table 31). If the hysteresis function is enabled, the conversion result must return to a value of at least N LSB below the alert high limit subregister value, or N LSB above the alert low limit subregister value to reset the alert output pins and the alert flag bits (see Figure 46). HARDWARE ALERT PINS Pin 27 and Pin 26 (GPIO0/ALERT0 and GPIO1/ALERT1, respectively) can be configured as alert pins (see the Digital I/O Function Subregister (Address 0x02) section). When these pins are configured as alert pins, they become active when the selected conversion result exceeds the high or low limit stored in the alert limits register bank. The polarity of the alert output pins can be set to active high or active low via the general subregister within the configuration register bank (see the General Subregister (Address 0x08) section). If an alert pin signals an alert event and the contents of the alert flags subregisters are not read before the next conversion is completed, the contents of the subregister may change if the out-ofrange signal returns to the specified range. In this case, the ALERTx pin no longer signals the occurrence of an alert event. ALERT FLAG BITS IN THE CONVERSION RESULT REGISTERS The TSENSE alert and ADC alert flag bits in the ADC conversion result and TSENSE conversion result registers indicate whether the conversion result being read or any other channel result has violated the limit registers associated with it. If an alert occurs and the alert bit is set in a conversion result register, the master can read the alert flags register bank to obtain more information about where the alert occurred. HIGH LIMIT HIGH LIMIT - HYSTERESIS INPUT SIGNAL LOW LIMIT + HYSTERESIS LOW LIMIT ALERT SIGNAL TIME Figure 46. Limit Checking: Alert High Limit, Alert Low Limit, and Hysteresis Rev. A | Page 38 of 40 10660-052 The advantage of using the hysteresis subregister associated with each limit subregister is that hysteresis prevents chatter on the alert bits associated with each ADC channel and also prevents flicker on the alert output pins. Figure 46 shows the limit checking operation. Data Sheet AD7292 ALERT FLAGS REGISTER BANK The alert flags register bank contains two subregisters: the ADC alert flags subregister and the TSENSE alert flags subregister. The ADC alert flags subregister stores alerts for the analog voltage conversion channels, VIN0 to VIN7. The TSENSE alert flags subregister stores alerts for the temperature sensor channel. These subregisters contain two status bits per channel: one corresponding to the high limit, and the other corresponding to the low limit (see Table 33 and Table 34). A bit with a status of 1 shows the channel on which the violation occurred and whether the violation occurred on the high or low limit. If additional alert events occur on any other channels after the first alert is triggered but before the alert flags subregister is read, the corresponding bits for the new alert events are also set. For example, if Bit D14 in the ADC alert flags subregister is set to 1, the low limit on Channel 7 has been exceeded, whereas if Bit D3 is set to 1, the high limit on Channel 1 has been exceeded. An alert associated with either the alert high limit or alert low limit subregister is cleared automatically after the monitored signal is back in range, that is, when the conversion result returns between the configured high and low limits. The contents of the alert flags subregister are updated after each conversion. To find out which channel or channels caused the alert flag, the user must read the ADC alert flags subregister or the TSENSE alert flags subregister. If the ADC alert flags subregister or the TSENSE alert flags subregister is accessed with both the read and write bits of the address pointer set to 1, the stored alert flags can be read and reset in one operation. A blanket reset can be performed by writing 0xFFFF to the ADC alert flags subregister, or 0x0003 to the TSENSE alert flags subregister, thus clearing all alert flags. MINIMUM AND MAXIMUM CONVERSION RESULTS The read-only minimum/maximum register bank contains the minimum and maximum conversion values for each of the eight analog input channels and the temperature sensor channel. Values are 10-bit, left justified. The minimum and maximum subregisters are cleared when a value is written to them--that is, they return to their power-up values. This means that if a subregister is accessed with both the read and write bits set, the stored minimum or maximum value can be read and reset in one operation. On power-up, the minimum value subregisters contain 0xFFC0, and the maximum value subregisters contain 0x0000. Rev. A | Page 39 of 40 AD7292 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 36 28 27 1 0.50 BSC 4.05 3.90 SQ 3.85 EXPOSED PAD 19 TOP VIEW 0.80 0.75 0.70 0.70 0.60 0.40 SEATING PLANE 9 18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PIN 1 INDICATOR 10 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 03-29-2012-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 47. 36-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm x 6 mm Body, Very Very Thin Quad (CP-36-3) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7292BCPZ AD7292BCPZ-RL EVAL-AD7292SDZ EVAL-SDP-CB1Z 1 Temperature Range -40C to +125C -40C to +125C Package Description 36-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 36-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board System Development Platform Z = RoHS Compliant Part. (c)2012-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10660-0-9/14(A) Rev. A | Page 40 of 40 Package Option CP-36-3 CP-36-3