The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. D D D SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS Quad Bus Buffers 3-State Outputs Separate Control for Each Channel description SN54125, SN54126, SN54LS125A, SN54LS126A . . . J OR W PACKAGE SN74125, SN74126 . . . N PACKAGE SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE (TOP VIEW) 1G, 1G* 1A 1Y 2G, 2G* 2A 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4G, 4G* 4A 4Y 3G, 3G* 3A 3Y *G on '125 and 'LS125A devices; G on 126 and 'LS126A devices SN54LS125A, SN54LS126A . . . FK PACKAGE (TOP VIEW) 1A 1G, 1G* NC VCC 4G, 4G* These bus buffers feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL output with additional drive capability at high logic levels to permit driving heavily loaded bus lines without external pullup resistors. When disabled, both output transistors are turned off, presenting a high-impedance state to the bus so the output will act neither as a significant load nor as a driver. The '125 and 'LS125A devices' outputs are disabled when G is high. The '126 and 'LS126A devices' outputs are disabled when G is low. SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3G, 3G* 2Y GND NC 3Y 3A 1Y NC 2G, 2G* NC 2A *G on '125 and 'LS125A devices; G on 126 and 'LS126A devices NC - No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 ORDERING INFORMATION PDIP - N 0C to 70C SOIC - D SOP - NS CDIP - J -55C 55C to 125C ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING Tube SN74LS125AN SN74LS125AN Tube SN74LS126AN SN74LS126AN Tube SN74LS125AD Tape and reel SN74LS125ADR Tube SN74LS126AD Tape and reel SN74LS126ADR Tape and reel SN74LS125ANSR 74LS125A Tape and reel SN74LS126ANSR 74LS126A Tube SN54LS125AJ SN54LS125AJ LS125A LS126A Tube SNJ54LS125AJ SNJ54LS125AJ CFP - W Tube SNJ54LS125AW SNJ54LS125AW LCCC - FK Tube SNJ54LS125AFK SNJ54LS125AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. logic diagram (each gate) '125, 'LS125A G A Y '126, 'LS126A G A Y Y=A 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 schematics (each gate) '125 CIRCUITS 4 kW 2.5 kW 4 kW 2.5 kW 85 W 1 kW 4 kW CONTROL INPUT G 1.6 kW 1.6 kW VCC OUTPUT Y 625 W GND DATA INPUT A '126 CIRCUITS 4 kW 2.5 kW 4.25 kW 4 kW 2.5 kW 1 kW 85 W 4 kW CONTROL INPUT G 1.6 kW 1.6 kW VCC OUTPUT Y 625 W DATA INPUT A GND absolute maximum ratings over operating free-air temperature (unless otherwise noted) ('125 and '126) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, JA (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package termal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 schematics (each gate) 'LS125A CIRCUITS 10 kW 8 kW 18 kW 6 kW 4 kW 50 W 4 kW 20 kW INPUT G VCC OUTPUT 1.5 kW 750 W 5 kW GND INPUT A 'LS126A CIRCUITS 18 kW 12 kW 8 kW INPUT G 18 kW 6 kW 4 kW 50 W VCC 4 kW 20 kW 750 W OUTPUT 1.5 kW 5 kW GND INPUT A Resistor values shown are nominal. absolute maximum ratings over operating free-air temperature (unless otherwise noted) ('LS125A and 'LS126A) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package termal impedance is calculated in accordance with JESD 51-7. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 recommended operating conditions SN54125 SN54126 SN74125 SN74126 UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current -2 -5.2 mA IOL TA Low-level output current 16 16 mA 70 C High-level input voltage 2 Operating free-air temperature 2 -55 125 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS PARAMETER SN54125 SN54126 SN74125 SN74126 TYP TYP MIN VIK VOH VOL IOZ II IIH VCC = MIN, VCC = MIN, II = -12 mA VIH = 2 V, IOH = -2 mA IOH = -5.2 mA VIH = 2 V, VIL = 0.8 V, IOL = 16 mA VCC = MAX VIH = 2 V, VO = 2.4 V VO = 0.4 V IIL VCC = MAX, VCC = MAX, IOS VCC = MAX ICC VCC = MAX (see Note 3) MIN -1.5 VIL = 0.8 V VCC = MIN, VIL = 0.8 V VCC = MAX, MAX 2.4 UNIT MAX -1.5 3.3 2.4 V 3.1 04 0.4 V 04 0.4 40 40 -40 -40 1 1 V A VI = 6.5 V VI = 2.4 V 40 40 A VI = 0.4 V -1.6 -1.6 mA -70 mA -30 -70 -28 '125 32 54 32 54 '126 36 62 36 62 mA mA For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time. NOTE 3: Data inputs = 0 V; output control = 4.5 V for '125 and 0 V for '126. switching characteristics, VCC = 5 V, TA = 25C (see Figure 1) PARAMETER SN54125 SN74125 TEST CONDITIONS MIN tPLH tPHL tPZH tPZL tPHZ tPLZ RL = 400 , CL = 50 pF F RL = 400 , CL = 50 pF F RL = 400 , CL = 5 pF F POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54126 SN74126 TYP MAX MIN UNIT TYP MAX 8 13 8 13 12 18 12 18 11 17 11 18 16 25 16 25 5 8 10 16 7 12 12 18 ns ns ns 5 SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 recommended operating conditions SN54LS125A SN54LS126A SN74LS125A SN74LS126A UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current -1 -2.6 mA IOL TA Low-level output current 12 24 mA 70 C High-level input voltage 2 Operating free-air temperature 2 -55 125 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS125A SN54LS126A TEST CONDITIONS PARAMETER MIN VIK VOH VOL IOZ VCC = MIN, VCC = MIN, II = -18 mA VIL = 0.7 V, VIH = 2 V VIL = 0.8 V VIL = 0.7 V, VCC = MIN, MIN VIH = 2 V VCC = MAX,, VIH = 2 V, VIL = 0.8 V, VIL = 0.8 V, VIL = 0 0.7 7V VIL = 0 0.8 8V II IIH VCC = MAX, VCC = MAX, VI = 7 V VI = 2.7 V IIL VCC = MAX, VI = 0.4 V IOS VCC = MAX ICC VCC = MAX (see Note 4) TYP SN74LS125A SN74LS126A MAX MIN TYP -1.5 IOH = -1 mA IOH = -2.6 mA UNIT MAX -1.5 2.4 V 2.4 IOL = 12 mA IOL = 12 mA 0.25 V 0.4 IOL = 24 mA VO = 2.4 V 0.25 0.4 0.35 0.5 V 20 VO = 0.4 V VO = 2.4 V -20 20 VO = 0.4 V A -20 0.1 0.1 mA 20 20 A 'LS125A-G inputs -0.2 -0.2 mA 'LS125A-A inputs; 'LS126A All inputs -0.4 -0.4 mA -225 mA -40 -225 -40 'LS125A 11 20 11 20 'LS126A 12 22 12 22 mA For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 4: Data inputs = 0 V; output control = 4.5 V for 'LS125A and 0 V for 'LS126A. switching characteristics, VCC = 5 V, TA = 25C (see Figure 1) PARAMETER SN54LS125A SN74LS125A TEST CONDITIONS MIN tPLH tPHL tPZH tPZL tPHZ tPLZ 6 RL = 667 , CL = 45 pF F RL = 667 , CL = 45 pF F RL = 667 , CL = 5 pF F POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LS126A SN74LS126A TYP MAX 9 7 MIN UNIT TYP MAX 15 9 15 18 8 18 12 20 16 25 15 25 21 35 20 25 20 25 ns ns ns The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 DEVICES VCC Test Point VCC RL From Output Under Test CL (see Note A) CL (see Note A) High-Level Pulse 1.5 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V 1 k Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL (see Note B) RL From Output Under Test VCC From Output Under Test Test Point 1.5 V 0V tw Low-Level Pulse 1.5 V tsu 0V In-Phase Output (see Note D) tPHL VOH 1.5 V Out-of-Phase Output (see Note D) 1.5 V 3V 1.5 V Waveform 1 (see Notes C and D) tPLZ VOH 1.5 V 1.5 V VOL VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 1.5 V tPZH tPLH 1.5 V 0V tPZL VOL tPHL 1.5 V 0V Output Control (low-level enabling) 1.5 V tPLH 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 3V Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS Input th VOL + 0.5 V tPHZ VOH 1.5 V VOH - 0.5 V 1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 ; tr and tf 7 ns for Series 54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126A QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS The SN54125, SN54126, SN74125, SN74126, and SN54LS126A are obsolete and are no longer supplied. SDLS044A - DECEMBER 1983 - REVISED MARCH 2002 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) High-Level Pulse 1.3 V S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.3 V 5 k Test Point LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 1.3 V 0V tw Low-Level Pulse 1.3 V tsu Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 1.3 V Output Control (low-level enabling) 0V tPLH In-Phase Output (see Note D) 1.3 V 0V 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL tPZH tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 3V 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th Waveform 2 (see Notes C and D) VOL + 0.5 V tPHZ VOH 1.3 V VOH - 0.5 V 1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 1.5 ns, tf 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 20 1 TBD JM38510/32301BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type JM38510/32301BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type JM38510/32301SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type JM38510/32301SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type M38510/32301B2A ACTIVE LCCC FK 20 1 TBD M38510/32301BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type M38510/32301BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type M38510/32301SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type M38510/32301SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type TBD Call TI TBD A42 SN54126J OBSOLETE CDIP J 14 SN54LS125AJ ACTIVE CDIP J 14 SN74125N OBSOLETE PDIP N 14 TBD Call TI Call TI SN74125N3 OBSOLETE PDIP N 14 TBD Call TI Call TI SN74126N OBSOLETE PDIP N 14 TBD Call TI Call TI SN74LS125AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Samples (Requires Login) JM38510/32301B2A 1 (3) Call TI N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) SN74LS125ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) SN74LS125AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) TBD Lead/ Ball Finish MSL Peak Temp CU NIPDAU N / A for Pkg Type SN74LS125AN3 OBSOLETE PDIP N 14 SN74LS125ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) SN74LS125ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS125ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126AJ OBSOLETE CDIP J 14 TBD Call TI CU NIPDAU N / A for Pkg Type Call TI Call TI SN74LS126AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LS126ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LS126ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS126ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54126J OBSOLETE CDIP J 14 TBD Call TI Call TI SNJ54126W OBSOLETE CFP W 14 TBD Call TI Call TI SNJ54LS125AFK ACTIVE LCCC FK 20 1 Addendum-Page 2 TBD Samples (Requires Login) CU NIPDAU Level-1-260C-UNLIM Call TI (3) POST-PLATE N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 23-Mar-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SNJ54LS125AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type SNJ54LS125AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54126, SN54LS125A, SN54LS125A-SP, SN74126, SN74LS125A : * Catalog: SN74126, SN74LS125A, SN54LS125A * Military: SN54126, SN54LS125A * Space: SN54LS125A-SP Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2012 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications * Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LS125ADBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DB 14 2000 330.0 16.4 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LS125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LS125ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LS126ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LS126ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS125ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LS125ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LS125ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LS126ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LS126ANSR SO NS 14 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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