SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Quad Bus Buffers
D
3-State Outputs
D
Separate Control for Each Channel
description
These bus buffers feature three-state outputs
that, when enabled, have the low impedance
characteristics of a TTL output with additional
drive capability at high logic levels to permit
driving heavily loaded bus lines without external
pullup resistors. When disabled, both output
transistors are turned off, presenting a
high-impedance state to the bus so the output will
act neither as a significant load nor as a driver. The
’125 and ’LS125A devices’ outputs are disabled
when G is high. The ’126 and ’LS126A devices’
outputs are disabled when G is low.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54125, SN54126, SN54LS125A,
SN54LS126A . . . J OR W PACKAGE
SN74125, SN74126 ...N PACKAGE
SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1G, 1G*
1A
1Y
2G, 2G*
2A
2Y
GND
VCC
4G, 4G*
4A
4Y
3G, 3G*
3A
3Y
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3G, 3G*
1Y
NC
2G, 2G*
NC
2A
1A
1G, 1G*
NC
3Y
3A 4G, 4G*
2Y
GND
NC VCC
SN54LS125A, SN54LS126A . . . FK PACKAGE
(TOP VIEW)
*G on ’125 and ’LS125A devices;
G on 126 and ’LS126A devices
NC – No internal connection
*G on ’125 and ’LS125A devices;
G on 126 and ’LS126A devices
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP N
Tube SN74LS125AN SN74LS125AN
PDIP
–
N
Tube SN74LS126AN SN74LS126AN
Tube SN74LS125AD
LS125A
0°Cto70°C
SOIC D
Tape and reel SN74LS125ADR
LS125A
0°C
to
70°C
SOIC
–
D
Tube SN74LS126AD
LS126A
Tape and reel SN74LS126ADR
LS126A
SOP NS
Tape and reel SN74LS125ANSR 74LS125A
SOP
–
NS
Tape and reel SN74LS126ANSR 74LS126A
CDIP J
Tube SN54LS125AJ SN54LS125AJ
55°Cto125°C
CDIP
–
J
Tube SNJ54LS125AJ SNJ54LS125AJ
–
55°C
to
125°C
CFP – W Tube SNJ54LS125AW SNJ54LS125AW
LCCC – FK Tube SNJ54LS125AFK SNJ54LS125AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
logic diagram (each gate)
AY
Y = A
G
’125, ’LS125A
AY
G’126, ’LS126A
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics (each gate)
’125 CIRCUITS
’126 CIRCUITS
1.6 k
W
OUTPUT Y
OUTPUT Y
1.6 k
W
1.6 k
W
1.6 k
W
625
W
625
W
4 k
W
4 k
W
4 k
W
4 k
W
4.25 k
W
2.5 k
W
2.5 k
W
2.5 k
W
2.5 k
W
1 k
W
1 k
W
4 k
W
85
W
85
W
DATA
INPUT A
CONTROL
INPUT G
GND
GND
VCC
VCC
CONTROL
INPUT G
DATA
INPUT A
4 k
W
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
(’125 and ’126)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2):N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics (each gate)
10 k
W
18 k
W
12 k
W
8 k
W
18 k
W
18 k
W
8 k
W
6 k
W
6 k
W
4 k
W
4 k
W
5 k
W
4 k
W
750
W
750
W
5 k
W
4 k
W
20 k
W
20 k
W
1.5 k
W
1.5 k
W
50
W
50
W
INPUT G
INPUT G
INPUT A
INPUT A
OUTPUT
GND
OUTPUT
GND
VCC
VCC
’LS125A CIRCUITS
’LS126A CIRCUITS
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
(’LS125A and ’LS126A)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2):D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54125
SN54126 SN74125
SN74126 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current –2–5.2 mA
IOL Low-level output current 16 16 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
†
SN54125
SN54126 SN74125
SN74126 UNIT
TEST
CONDITIONS
MIN TYP‡MAX MIN TYP‡MAX
VIK VCC = MIN, II = –12 mA –1.5 –1.5 V
VOH
VCC = MIN, VIH = 2 V, IOH = –2 mA 2.4 3.3
V
V
OH VIL = 0.8 V IOH = –5.2 mA 2.4 3.1
V
VOL
VCC = MIN, VIH = 2 V, VIL = 0.8 V,
04
04
V
V
OL IOL = 16 mA
0
.
4
0
.
4
V
I
VCC = MAX VIH = 2 V, VO = 2.4 V 40 40
µA
I
OZ VIL = 0.8 V VO = 0.4 V –40 –40 µ
A
IIVCC = MAX, VI = 6.5 V 1 1 mA
IIH VCC = MAX, VI = 2.4 V 40 40 µA
IIL VCC = MAX, VI = 0.4 V –1.6 –1.6 mA
IOS§VCC = MAX –30 –70 –28 –70 mA
ICC
VCC = MAX ’125 32 54 32 54
mA
I
CC
(see Note 3) ’126 36 62 36 62
mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time.
NOTE 3: Data inputs = 0 V ; output control = 4.5 V for ’125 and 0 V for ’126.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER TEST CONDITIONS
SN54125
SN74125 SN54126
SN74126 UNIT
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
tPLH
RL= 400 Ω
CL=50
p
F
8 13 8 13
ns
tPHL
RL
=
400
Ω
,
CL
=
50
F
12 18 12 18
ns
tPZH
RL= 400 Ω
CL=50
p
F
11 17 11 18
ns
tPZL
RL
=
400
Ω
,
CL
=
50
F
16 25 16 25
ns
tPHZ
RL= 400 Ω
CL=5
p
F
5 8 10 16
ns
tPLZ
RL
=
400
Ω
,
CL
=
5
F
7 12 12 18
ns
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54LS125A
SN54LS126A SN74LS125A
SN74LS126A UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –1–2.6 mA
IOL Low-level output current 12 24 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
†
SN54LS125A
SN54LS126A SN74LS125A
SN74LS126A UNIT
TEST
CONDITIONS
MIN TYP‡MAX MIN TYP‡MAX
VIK VCC = MIN, II = –18 mA –1.5 –1.5 V
VOH
VCC = MIN, VIL = 0.7 V, IOH = –1 mA 2.4
V
V
OH VIH = 2 V VIL = 0.8 V IOH = –2.6 mA 2.4
V
V MIN
VIL = 0.7 V, IOL = 12 mA 0.25 0.4
VOL VCC = MIN,
VIH =2V
VIL = 0.8 V, IOL = 12 mA 0.25 0.4 V
VIH
=
2
V
VIL = 0.8 V, IOL = 24 mA 0.35 0.5
VIL =07V
VO = 2.4 V 20
I
V
CC
= MAX,
V
IL =
0
.
7
V
VO = 0.4 V –20
µA
I
OZ
CC ,
VIH = 2 V,
VIL =08V
VO = 2.4 V 20 µ
A
V
IL =
0
.
8
V
VO = 0.4 V –20
IIVCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 µA
IIL
VCC = MAX, ’LS125A-G inputs –0.2 –0.2 mA
I
IL VI = 0.4 V ’LS125A-A inputs; ’LS126A All inputs –0.4 –0.4 mA
IOS§VCC = MAX –40 –225 –40 –225 mA
ICC
VCC = MAX ’LS125A 11 20 11 20
mA
I
CC
CC
(see Note 4) ’LS126A 12 22 12 22
mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 4: Data inputs = 0 V ; output control = 4.5 V for ’LS125A and 0 V for ’LS126A.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER TEST CONDITIONS
SN54LS125A
SN74LS125A SN54LS126A
SN74LS126A UNIT
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
tPLH
RL= 667 Ω
CL=45
p
F
9 15 9 15
ns
tPHL
RL
=
667
Ω
,
CL
=
45
F
7 18 8 18
ns
tPZH
RL= 667 Ω
CL=45
p
F
12 20 16 25
ns
tPZL
RL
=
667
Ω
,
CL
=
45
F
15 25 21 35
ns
tPHZ
RL= 667 Ω
CL=5
p
F
20 25
ns
tPLZ
RL
=
667
Ω
,
CL
=
5
F
20 25
ns
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
tw
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOH
VOL
Figure 1. Load Circuits and Voltage Waveforms
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tw
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOL
VOH
Figure 2. Load Circuits and Voltage Waveforms
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied
.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
JM38510/32301B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/32301BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
JM38510/32301BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
JM38510/32301SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type
JM38510/32301SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type
M38510/32301B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
M38510/32301BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
M38510/32301BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
M38510/32301SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type
M38510/32301SDA ACTIVE CFP W 14 25 TBD A42 N / A for Pkg Type
SN54126J OBSOLETE CDIP J 14 TBD Call TI Call TI
SN54LS125AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SN74125N OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74125N3 OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74126N OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74LS125AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ADBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LS125ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS125AN3 OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74LS125ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS125ANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS125ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126AJ OBSOLETE CDIP J 14 TBD Call TI Call TI
SN74LS126AN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS126ANE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS126ANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS126ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54126J OBSOLETE CDIP J 14 TBD Call TI Call TI
SNJ54126W OBSOLETE CFP W 14 TBD Call TI Call TI
SNJ54LS125AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SNJ54LS125AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SNJ54LS125AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54126, SN54LS125A, SN54LS125A-SP, SN74126, SN74LS125A :
•Catalog: SN74126, SN74LS125A, SN54LS125A
•Military: SN54126, SN54LS125A
•Space: SN54LS125A-SP
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 4
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LS125ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LS125ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS125ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LS126ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS126ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS125ADBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LS125ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LS125ANSR SO NS 14 2000 367.0 367.0 38.0
SN74LS126ADR SOIC D 14 2500 367.0 367.0 38.0
SN74LS126ANSR SO NS 14 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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