26185.114F
Description
The merging of low-power CMOS logic and bipolar output
power drivers using the proprietary DABiC-5 fabrication
process permit the A6841 integrated circuits to be used in a
wide variety of peripheral power driver applications. Each
device has an eight-bit CMOS shift register and CMOS
control circuitry, eight CMOS data latches, and eight bipolar
current-sinking Darlington output drivers. The 500 mA,
NPN Darlington outputs, with integral transient-suppression
diodes, are suitable for use with relays, solenoids, and other
inductive loads.
All package variations of the A6841 offer premium performance
with a minimum output-breakdown voltage rating of 50 V (35 V
sustaining). All drivers can be operated with a split supply
where the negative supply is up to –20 V.
The CMOS inputs are compatible with standard CMOS logic
levels. TTL circuits may require the use of appropriate pull-up
resistors. By using the serial data output, drivers can be cascaded
for interface applications requiring additional drive lines.
The A6841 is provided in an 18-pin plastic DIP (suffix A), and
a 20-pin wide-body SOIC (suffix LW) with improved thermal
characteristics compared to the 18-pin SOIC version it replaces
(100% pin-compatible electrically).These devices are lead (Pb)
free, with 100% matte tin plated leadframes.
Applications include:
▪ Relays
▪ Solenoids
▪ Inductive loads
Features and Benefits
▪ 3.3 to 5 V logic supply range
▪ Power-on reset (POR)
▪ To 10 MHz data input rate
▪ CMOS, TTL compatible inputs
▪ –40°C operation available
▪ Low-power CMOS logic and latches
▪ Schmitt trigger inputs for improved noise immunity
▪ High-voltage current-sink outputs
▪ Internal pull-up/pull-down resistors
▪ Output transient-protection diodes
▪ Single or split supply operation
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Packages:
Functional Block Diagram
Not to scale
A6841
MOS
BIPOLAR
GROUND STROBE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
LOGIC
SUPPLY
OUT
1
OUT
2
OUT
3
OUT
6
OUT
7
OUT
8
OUT
4
OUT
5
VEE or POWER GROUND
VEE or POWER GROUND
SUB
K
18-pin DIP (Package A)
20-pin SOICW (package LW)
(drop-in replacement for discon-
tinued 18-pin SOIC variants)
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Units
Logic Supply Voltage VDD 7V
Emitter Supply Voltage VEE –20 V
Input Voltage Range VIN –0.3 to VDD +0.3 V
Output Voltage VCE 50 V
VCE(SUS) For inductive load applications 35 V
Continuous Output Current IOUT Each output 500 mA
Operating Ambient Temperature TA
Range E –40 to 85 ºC
Range S –20 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.
Selection Guide
Part Number Package Packing Ambient
A6841EA-T 18-pin DIP 21 pieces per tube
–40ºC to 85ºCA6841ELW-20-T 20-pin wide body SOIC 37 pieces per tube
A6841ELWTR-20-T 20-pin wide body SOIC 1000 pieces per reel
A6841SA-T 18-pin DIP 21 pieces per tube
–20ºC to 85ºCA6841SLW-20-T 20-pin wide body SOIC 37 pieces per tube
A6841SLWTR-20-T 20-pin wide body SOIC 1000 pieces per reel
Allowable Package Power Dissipation, PD
50 75 100 125 150
2.5
0.5
0
POWER DISSIPATION (W)
AMBIENT TEMPERATURE (º C)
2.0
1.5
1.0
25
20-PIN SOIC, R
Q
JA
= 90
o
C/W
18-PIN DIP, R
Q
JA
= 65
o
C/W
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, VEE = 0 V, logic supply operating
voltage VDD = 3.0 to 5.5 V
Characteristic Symbol Test Conditions
Vdd = 3.3 V Vdd = 5 V
Units
Min. Typ. Max. Min. Typ. Max.
Output Leakage Current ICEX VOUT = 50 V – – 10 – – 10 A
Output Sustaining Voltage VCE(SUS) IOUT = 350 mA, L = 3 mH 35 – – 35 – – V
Collector–Emitter Saturation
Voltage VCE(SAT)
IOUT = 100 mA – – 1.1 – – 1.1 V
IOUT = 200 mA – – 1.3 – – 1.3 V
IOUT = 350 mA – – 1.6 – – 1.6 V
Input Voltage VIN(1) 2.2 – – 3.3 – – V
VIN(0) – – 1.1 – – 1.7 V
Input Resistance RIN 50 – – 50 – – k
Serial Data Output Voltage VOUT(1) IOUT = –200 A 2.8 3.05 – 4.5 4.75 – V
VOUT(0) IOUT = 200 A – 0.15 0.3 – 0.15 0.3 V
Maximum Clock Frequency2fc10 – – 10 – – MHz
Logic Supply Current
IDD(1) One output on, OE = L, ST = H – – 2.0 – – 2.0 mA
IDD(0)
All outputs off, OE = H, ST = H,
P1 through P8 = L – – 100 – – 100 A
Clamp Diode Leakage Current IrVr = 50 V – – 50 – – 50 A
Clamp Diode Forward Voltage VfIf = 350 mA – – 2 – – 2 V
Output Enable-to-Output Delay tdis(BQ) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
ten(BQ) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Strobe-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
tp(STH-QH) VCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Output Fall Time tfVCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Output Rise Time trVCC = 50 V, R1 = 500 , C1 30 pF – – 1.0 – – 1.0 s
Clock-to-Serial Data Out Delay tp(CH-SQX) IOUT = ±200 A – 50 – – 50 – ns
1Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin.
2Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed.
Serial Shift Register Contents Serial Latch Contents Output Output Contents
Data Clock Data Strobe Enable
Input Input I1I2I3... I8Output Input I1I2I3... I8Input I1I2I3... I8
R7
R7
R
1R2R3... R8
R8
XXX...X X
X
L
R1R2... R7
L
L
R1R2R3... R8
P1P2P3... P8P8P1P2P3... P81
P2P3... P8
XXX...X
LP
HH
HH
H
R1R2... R7
H
H
H...
Truth Table
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Timing Requirements and Specifi cations
(Logic Levels are VDD and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT ENABLE
OUT
N
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A B
D E
LOW = ALL OUTP UTS E NABLE D
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
OUTPUT ENABLE
OUT
N
DATA
10%
50%
dis(BQ)
t
en(BQ)
t
HIGH=ALLOUTPUTSBLANKED(DISABLED)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be
attainable; operation at high temperatures will reduce the specifi ed maxi-
mum clock frequency.
Powering-on with the inputs in the low state ensures that the registers and
latches power-on in the low state (POR).
Serial Data present at the input is transferred to the shift register on the logical
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK
pulses, the registers shift data information towards the SERIAL DATA OUT-
PUT. The serial data must appear at the input prior to the rising edge of the
CLOCK input waveform.
Information present at any register is transferred to the respective latch
when the STROBE is high (serial-to-parallel conversion). The latches will
continue to accept new data as long as the STROBE is held high. Applica-
tions where the latches are bypassed (STROBE tied high) will require that
the OUTPUT ENABLE input be high during serial data entry.
When the OUTPUT ENABLE input is high, all of the output buffers are
disabled (OFF). The information stored in the latches or shift register is not
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE
input low, the outputs are controlled by the state of their respective latches.
Key Description Symbol Time (ns)
A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25
B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25
C Clock Pulse Width tw(CH) 50
D Time Between Clock Activation and Strobe tsu(C) 100
E Strobe Pulse Width tw(STH) 50
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Name Description Number
Package A Package L W
VEE Power Ground to substrate 1, 9 1, 9
CLOCK Clock 2 2
SERIAL DATA IN Serial Data In 3 3
GROUND Logic Ground 4 4
VDD Logic Supply 5 5
SERIAL DATA OUT Serial Data Out, for cascading devices 6 6
STROBE Strobe 7 7
OUTPUT ENABLE Output Enable (active low) 8 8
K Common to +VL , for inductive loads 10 12
NC Not internally connected – 10, 11
OUT8 Sink Output 8 11 13
OUT7 Sink Output 7 12 14
OUT6 Sink Output 6 13 15
OUT5 Sink Output 5 14 16
OUT4 Sink Output 4 15 17
OUT3 Sink Output 3 16 18
OUT2 Sink Output 2 17 19
OUT1 Sink Output 1 18 20
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
K
VEE
CLOCK
SERIAL DATA IN
GROUND
LOGIC SUPPLY
SERIAL DATA OUT
STROBE
OUTPUT ENABLE
VEE
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
K
NC
VEE
CLOCK
SERIAL DATA IN
GROUND
LOGIC SUPPLY
SERIAL DATA OUT
STROBE
OUTPUT ENABLE
VEE
NC
Package A Package LW
Pin-out Diagrams
(NC pins, 10 and 11, not present
on discontinued 18-pin LW package)
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Typical Input Circuits Typical Output Driver
CLOCK
SERIAL
DATA IN
VDD
STROBE
OUTPUT
ENABLE
VDD
OUT
SUB
K
VEE
SUB
2
3
4
5
6
7
8
SERIAL
DATA OUT
SERIAL
DATA IN
OUTPUT
ENABLE
STROBE
CLOCK
+5 V –15 V +30 V
CLK
VDD
ST
OE
1
SHIFT REGISTER
LATCHES
14
15
16
17
18
19
20
9
SUB
12
10 11
13
SUB
2
3
4
5
6
7
8
SERIAL
DATA OUT
SERIAL
DATA IN
OUTPUT
ENABLE
STROBE
CLOCK
+5 V –15 V +30 V
CLK
VDD
ST
OE
1
SHIFT REGISTER
LATCHES
12
13
14
15
16
17
18
9
SUB
10
11
Typical Application
Relay/solenoid driver using split supply
Pins 10 and 11 can fl oat; other pins
match discontinued 18-pin SOIC: 1 to 9
same, pins 12 to 20 match pins 10 to 18
18-pin DIP (A Package) 20-pin SOICW (LW Package)
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LW, 20-Pin SOICW
Package A, 18-Pin DIP
5.33 MAX
0.46 ±0.12
22.86 ±0.51
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
7.62
2.54
0.25 +0.10
–0.05
C
SEATING
PLANE
21
18
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
21
20
21
20
A
2.65 MAX
C
SEATING
PLANE
C0.10
20X
ATerminal #1 mark area
GAUGE PLANE
SEATING PLANE B
2.25
0.65
9.50
1.27
PCB Layout Reference View
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
BReference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
1.27
0.25
0.20 ±0.10
0.41 ±0.10
12.80±0.20
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A6841
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2004-2008 Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
