KSZ8864CNX/RMNUB
Integrated 4 -Port 10/100 Managed Switch
with Two MACs MII or RMII Interfaces
Revision 1.4
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March
4, 2015
Revision 1.4
General Description
The KSZ8864CNX/RMNUB is a hig hl y-integrat ed, La yer 2-
managed 4-port switch with optimized design, plentiful
features and smallest pac k age s ize. It is des ign ed f or cost-
sensitive 10/100Mbps 4-port switch systems with on-chip
termination, lowest-power consumption, and small
package to save system cost. It has 1.4Gbps high-
performance memory bandwidth, shared memory-based
switch fabric with full non-blocking configuration. It also
provides an extensive feature set such as the power
management, pr ogram m able rate lim iting and prior it y ratio,
tag/port-based VLAN, packet filtering, quality-of-service
(QoS), four queue prioritization, management interface,
MIB counters . Port 3 and Por t 4 support either MII or RMII
interfaces with SW3-MII/RMII and SW4-MII/RMII (see
Functional Diagram) for KSZ8864CNX/RMNUB data
interface. An industrial temperature-grade version of the
KSZ8864CNXIA and a qualified AEC-Q100 Automotive
version of the KSZ8864RMNUB ar e also available (see the
Ordering Information section).The KSZ8864CNX/RMNUB
provides m ultiple CPU control/da ta interfaces to effectively
address both current and emerging fast Ethernet
applications.
The KSZ8864CNX/RMNUB consists of 10/100 fast
Ethernet PHYs with patented and enhanced mixed-signal
technology, media access control (MAC) units, a high-
speed non-blocking switch fabric, a dedicated address
lookup engine, and an on-chip frame buffer memory.
The KSZ8864CNX/RMNUB contains four MACs and two
PHYs. The two PHYs support the 10/100Base-T/TX.
All registers of MACs and PH Ys units can be managed by
the control interface of SPI or the SMI. MIIM registers of
the PHYs can be accessed through the MDC/MDIO
interface. EEPROM can set all control registers by I2C
controller interface for the unmanaged mode.
Datasheets and support documentation are available on
Micrel’s webs ite at: www.micrel.com.
KSZ8864CNX/RMNUB is a 0.11µm technical device and
adding Mic rel’s L ink MD® feature, KSZ8864CNX/RMNUB is
complete l y pin-compatible with the KSZ8864RMN device.
Functional Diagram
Look Up
Engine
Queue
Management
FIFO, Flow Control, VLAN
Tagging, Priority
SPI
EEPROM
Interface
LED I/F
CONTROL REG SPI
MIB
Counters
P1LED[1:0]
P2LED[1:0] Control
Registers
MDC/MDIO
SMI, MIIM
PORT 4 MAC 4
SW4-MII/RMII
Auto MDI/MDIX
Auto MDI/MDIX
PORT 3 MAC 3
SW3-MII/RMII
10/100
T/TX
PHY2
10/100
T/TX
PHY1
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
Buffer
Management
Frame
Buffers
KSZ8864CNX/RMNUB
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 2 Revision 1.4
Features
Advanced Switch Features
• IEEE 802.1q VLAN support for up to 128 VLAN groups
(full-range 4096 of VLAN IDs).
• Static MAC table supports up to 32 entries.
• VLAN ID tag/untagged options, per port basis.
• IEEE 802.1p/q tag insertion or removal on a per port basis
based on ingress port (egress).
• Programmable rate limiting at the ingress and egress on a
per port basis.
• Jitter-free per packet based rate limiting support.
• Broadcast storm protection with percentage control (global
and per port basis).
• IEEE 802.1d rapid spanning tree protocol RSTP support.
• Tail tag mode (1 byte added before FCS) support at Port 4
to inform the processor which ingress port receives the
packet.
• 1.4Gbps high-performance memory bandwidth and shared
memory based switch fabric with fully non-blocking
configuration.
• Dual MII/RMII with MAC 3 SW3-MII/RMII and MA C 4 SW4-
MII/RMII interfaces.
• Enable/Disable option for huge frame size up to 2000
Bytes per frame.
• IGMP v1/v2 snooping (Ipv4) support for multicast packet
filtering.
• IPv4/IPv6 QoS support.
• Support unknown unicast/multicast address and unknown
VID packet filtering.
• Self-address filtering.
Comprehensive Configuration Register Acce ss
• Serial management interface (MDC/MDIO) to all PHYs
registers and SMI interface (MDC/MDIO) to all registers.
• High-speed SPI (up to 25MHz) and I2C master Interface to
all internal registers.
• I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode.
• Control registers configurable on the fly (port-priority,
802.1p/d/q, AN…).
QoS/CoS Packet Prioritization Support
• Per port, 802.1p and DiffServ-based.
• 1/2/4-queue QoS prioritization selection.
• Programmable weighted fair queuing for ratio control.
• Re-mapping of 802.1p priority field per port basis.
Integrated 4-Port 10/100 Ethernet Switch
• New generation switch with five MACs and five PHYs that
are fully compliant with the IEEE 802.3u standard.
• Non-blocking switch fabric assures fast packet delivery by
utilizing a 1K MAC address lookup table and a store-and-
forward architecture.
• On-chip 64Kbyte memory for frame buffering (not shared
with 1K unicast address table).
• Full-duplex IEEE 802.3x flow control (PAUSE) with force
mode option.
• Half-duplex back pressure flow control.
• HP Auto MDI/MDI-X and IEEE Auto c rossover support.
• LinkMD® TDR-based cable diagnostics to identify faulty
copper cabling.
• MII interface of MAC supports both MAC mode and PHY
mode.
• Per port LED Indicators for link, activity, and 10/100 speed.
• Register port status support for link, activity, full/half duplex
and 10/100 speed.
• On-chip terminations and internal biasing technology for
cost down and lowest power consumption.
Switch Monitoring Feature s
• Port mirroring/monitoring/sniffing: ingress and/or egress
traffic to any port or MII/RMII.
• MIB counters for fully-compliant statistics gathering 34 MIB
counters per port.
• Loop-back support for MAC, PHY, and remote diagnostic
of failure.
• Interrupt for the link change on any ports.
Low-Power Dissipation
• Full-chip software power-down and per port software power
down.
• Energy-detect mode support <0.1W full-chip power
consumption when all ports have no activity.
• Very-low full-chip power consumption (~0.3W), without
extra power consumption on transformers.
• Dynamic clock tree shutdown feature.
• Voltages:
− Analog VDDAT 3.3V only.
− VDDIO support 3.3V, 2.5V, and 1.8V.
− Low 1.2V core power.
− 0.11µm CMOS technology.
• Commercial temperature range: 0°C to +70°C.
• Industrial temperature range: –40°C to +85°C.
• Available in 64-pin QFN, lead-free small package.
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 3 Revision 1.4
Applications
• VoIP phone
• Set-top/game box
• Automoti ve Ether net
• Industrial control
• IPTV POF
• SOHO residential gateway
• Broadband gateway/firewall/VPN
• Integrated DSL/cable modem
• Wireless LAN access point + gateway
• Standalone 10/100 switch
• Embedded system
Ordering Information
For the dev ice marking ( second colum n in the following tab le), the fif th character of line two indicates whether the devic e
has gold wire bonding or silver wire bonding, as follows:
• Gold wire bondin g: The Letter “S” is not present as the fifth character of line 2.
• Silver wire bonding: The Letter “S” is present as the fifth character of line 2.
For line two, the presence or non-presence of the letter “S” is preceded by YY WW, indicating the last two digits of the year
and the two digits work week for the chip date code, and is followed by xxx, indicating the chip revision and assembly site.
Order Part Number Device Marking Temperature
Range Wire
Bonding Description
KSZ8864CNXCA KSZ8864CNXCA
YYWWxxx 0°C to 70°C Gold MII/RMII, Pb-Free, Commercial Temperature,
Gold Wir e Bonding, 64-Pin QFN
SPNZ801152 KSZ8864CNXCA
YYWW
S
xxx 0°C to 70°C Silver MII/RMII, Pb-Free, Commercial Temperature,
Silver Wire Bonding, 64-Pin QFN
KSZ8864CNXIA KSZ8864CNXIA
YYWWxxx -40°C to +85°C Gold MII/RMII, Pb-Free, Industrial Temperature, Gold
Wire Bonding, 64-Pin QFN
SPNY801152 KSZ8864CNXIA
YYWWSxxx -40°C to +85°C Silver MII/RMII, Pb-Free, Industrial Temperature,
Silver Wire Bonding, 64-Pin QFN
KSZ8864RMNUB
(Automotive AEC-Q100
Qualified)
KSZ8864RMNU
YYWWB2x -40°C to +85°C Gold MII/RMII, Pb-Free, Automotive Qualified Device,
Gold Wire Bonding, 64-Pin QFN
KSZ8864CNX-EVAL Evaluation Board for KSZ8864CNX
Revision History
Revision Date Summary of Changes
1.0 02/12/14 In itial document created.
1.1 02/13/14 Minor revision.
1.2 03/19/14 Change Automotive part number from KSZ8864RMNU to KSZ8864RMNUB. Update the description in
Introduction section. Update Register 1 bit [0] description. Correct typos.
1.3 12/8/14
Add missing data in table 22, update description from [20:16] to [11:7] in the port register control 2 bit [6].
Update packag e inform ati on. Added silver wire bonding part numbers to Ordering Information. Updated
Ordering Information to include Ordering Part Number and Device Marking. Add a note for the register
14 bits [4:3].
1.4 03/04/15 Update the ordering information table for KSZ8864RMNUB with device marking. Update the package
information with recommended land pattern.
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 4 Revision 1.4
Contents
List of Figures .......................................................................................................................................................................... 6
List of Tables ........................................................................................................................................................................... 7
Pin Configuration ..................................................................................................................................................................... 8
Pin Description ........................................................................................................................................................................ 9
Pin for Strap-In Options ......................................................................................................................................................... 13
Introduction ............................................................................................................................................................................ 16
Functional Overview: Physical Layer Transceiver ................................................................................................................ 16
100BASE-TX Transmit ...................................................................................................................................................... 16
100BASE-TX Receive ....................................................................................................................................................... 16
PLL Clock Synthesizer ...................................................................................................................................................... 16
Scrambler/De-Scrambler (100BASE-TX only) .................................................................................................................. 16
10BASE-T Transmit ........................................................................................................................................................... 17
10BASE-T Receive ............................................................................................................................................................ 17
MDI/MDI-X Auto Crossover ............................................................................................................................................... 17
Auto-Negotiation ................................................................................................................................................................ 19
LinkMD® Cab le Di agn os tic s ............................................................................................................................................... 21
On-Chip Termination Resistors ......................................................................................................................................... 22
Functional Overview: Power Management ........................................................................................................................... 23
Normal Operation Mode .................................................................................................................................................... 23
Energy Detect Mode .......................................................................................................................................................... 23
Soft Power-Down Mode ..................................................................................................................................................... 24
Power Saving Mod e .......................................................................................................................................................... 24
Port-Bas ed Po wer -Do wn Mode ......................................................................................................................................... 24
Functional Overview: Switch Core ........................................................................................................................................ 24
Address Look-Up ............................................................................................................................................................... 24
Learning ............................................................................................................................................................................. 24
Migration ............................................................................................................................................................................ 24
Aging .................................................................................................................................................................................. 24
Forwarding ......................................................................................................................................................................... 25
Switching Engine ............................................................................................................................................................... 25
Media Access Controller (MAC) Operation ....................................................................................................................... 25
Inter-Packet Gap (IPG) ...................................................................................................................................................... 25
Back-off Algorithm ............................................................................................................................................................. 25
Late Collis ion ..................................................................................................................................................................... 25
Illegal Frames .................................................................................................................................................................... 25
Flow Control ...................................................................................................................................................................... 25
Half-Duplex Back Pressure ............................................................................................................................................... 28
Broadcast Storm Protection............................................................................................................................................... 28
MII Interface Operation ...................................................................................................................................................... 28
Switch MAC3/MAC4 SW3/SW4-MII Interface ................................................................................................................... 28
Switch MAC3/MAC4 SW3/SW4-RMII Interface ................................................................................................................ 30
Advanced Functionality ......................................................................................................................................................... 31
QoS Priorit y Support .......................................................................................................................................................... 31
Spanning Tree Support ..................................................................................................................................................... 32
Rapid Spanning Tree Support ........................................................................................................................................... 33
Tail Tagging Mode ............................................................................................................................................................. 34
IGMP Support .................................................................................................................................................................... 35
Port Mirroring Support ....................................................................................................................................................... 35
VLAN Support .................................................................................................................................................................... 35
Rate Limiting Support ........................................................................................................................................................ 36
Ingress Rate Limit .............................................................................................................................................................. 36
Egress Rate Limit .............................................................................................................................................................. 37
Transmit Queue Ratio Prog ram m ing ................................................................................................................................. 37
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ......................... 37
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 5 Revision 1.4
Configuration Interface ...................................................................................................................................................... 37
SPI Slave Serial Bus Conf i gur ation ................................................................................................................................... 38
MII Management Interface (MIIM) ..................................................................................................................................... 41
Serial Management Interface (SMI) .................................................................................................................................. 41
Register Descriptions ............................................................................................................................................................ 43
Global Registers ................................................................................................................................................................ 44
Port Registers .................................................................................................................................................................... 54
Advanced Control Registers .............................................................................................................................................. 64
Data Rate Select ion in 100 BT ........................................................................................................................................... 79
Data Rate Select ion in 10 B T ............................................................................................................................................. 80
Static MAC Address Table .................................................................................................................................................... 82
VLAN Table ........................................................................................................................................................................... 84
Dynamic MAC Address Table ............................................................................................................................................... 87
MIB (Management Information Base) Counters ................................................................................................................... 88
For Port 1 ........................................................................................................................................................................... 88
For Port 2, the base is 0x40, same offset definition (0x40-0x5f) ....................................................................................... 89
For Port 3, the base is 0x60, same offset definition (0x60-0x7f) ....................................................................................... 89
For Port 4, the base is 0x80, same offset definition (0x80-0x9f) ....................................................................................... 89
All Ports Dropped Packet MIB Counters ........................................................................................................................... 89
Format of “All Dropped Packet” MIB Counter.................................................................................................................... 89
MIIM Registers ...................................................................................................................................................................... 91
Absolute Max imum Ratings .................................................................................................................................................. 95
Operating Ratings ................................................................................................................................................................. 95
Electrical Characteristics ....................................................................................................................................................... 95
Timing Diagrams ................................................................................................................................................................... 97
EEPROM Timing ............................................................................................................................................................... 97
MII Timing .......................................................................................................................................................................... 98
RMII Timing ..................................................................................................................................................................... 100
SPI Timing ....................................................................................................................................................................... 101
Auto-Negotiation Timing .................................................................................................................................................. 103
MDC/MDIO Timing .......................................................................................................................................................... 104
Reset Timing ................................................................................................................................................................... 105
Reset Circuit Diagram ..................................................................................................................................................... 106
Selection of Isolation Transformer ...................................................................................................................................... 107
Selection of Transformer Vendors ................................................................................................................................... 107
Selection of Reference Crystal ........................................................................................................................................ 107
Package Information ........................................................................................................................................................... 108
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 6 Revision 1.4
List of Figures
Figure 1. T ypical Stra ig ht Cabl e Connec t io n ...................................................................................................................... 18
Figure 2. Typical Crossover Cable Connection .................................................................................................................. 19
Figure 3. Auto-Negotiation .................................................................................................................................................. 20
Figure 4. Destination Address Look-up Flow Chart – Stage 1 ............................................................................................ 26
Figure 5. Destination Address Resolution Flow Chart – Stage 2 ........................................................................................ 27
Figure 6. 802.1p Priority Field Format ................................................................................................................................ 32
Figure 7. Tail Tag Frame Format ........................................................................................................................................ 34
Figure 8. KSZ8864CNX/RMNUB EEPROM Configuration Timing Diagram ...................................................................... 38
Figure 9. SPI Write Data Cycle ........................................................................................................................................... 39
Figure 10. SPI Read Data Cycle ........................................................................................................................................... 39
Figure 11. SPI Multiple Write ................................................................................................................................................ 40
Figure 12. SPI Multiple Read ................................................................................................................................................ 40
Figure 13. EEPROM Interface Input Receive Timing Diagram ............................................................................................. 97
Figure 14. EEPROM Interface Output Transmit Timing Diagram ......................................................................................... 97
Figure 15. MAC Mode MII Timing – Data Received from MII ............................................................................................... 98
Figure 16. MAC Mode MII Timing – Data Transmitted from MII ........................................................................................... 98
Figure 17. PHY Mode MII Timing – Data Received from MII ................................................................................................ 99
Figure 18. PHY Mode MII Timing – Data Transmitted from MII ............................................................................................ 99
Figure 19. RMII Timing – Data Received from RMII ........................................................................................................... 100
Figure 20. RMII Timing – Data Transmitted to RMII ........................................................................................................... 100
Figure 21. SPI Input Timing ................................................................................................................................................ 101
Figure 22. SPI Output Timing.............................................................................................................................................. 102
Figure 23. Auto-Negotiation Timing .................................................................................................................................... 103
Figure 24. MDC/ MDIO Timing ............................................................................................................................................. 104
Figure 25. Reset T im ing ...................................................................................................................................................... 105
Figure 26. Recom mended Res et Circ uit ............................................................................................................................. 106
Figure 27. Recom mended Circ uit for Interf ac ing with CPU /FPGA Reset ........................................................................... 106
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 7 Revision 1.4
List of Tables
Table 1. MDI/MDI-X Pin Definitions .................................................................................................................................... 17
Table 2. Internal Function Block Status .............................................................................................................................. 23
Table 3. Switch MAC 3 SW3-MII and MAC 4 SW4-MII Signals ......................................................................................... 29
Table 4. M A C3 SW3-RMII and MAC4 SW4-RMII Connection ........................................................................................... 30
Table 5. Tail Tag Rules ....................................................................................................................................................... 34
Table 6. FID+DA Look Up in the VLAN Mode .................................................................................................................... 36
Table 7. FID+SA Look Up in the VLAN Mode ..................................................................................................................... 36
Table 8. SPI Connections ................................................................................................................................................... 39
Table 9. MII Management Interface Frame Format ............................................................................................................ 41
Table 10. Serial Management Interface (SMI) Frame Format .............................................................................................. 41
Table 11. 100BT Rate Selection for the Rate Limit............................................................................................................... 79
Table 12. 10BT Rate Selection for the Rate Limit................................................................................................................. 80
Table 13. Format of Static MAC Table for Reads ................................................................................................................. 82
Table 14. Format of Static MAC Table for Writes ................................................................................................................. 83
Table 15. VLAN Table ........................................................................................................................................................... 84
Table 16. VLAN ID and Indirect Registers ............................................................................................................................ 86
Table 17. Dynamic MAC Address Table ............................................................................................................................... 87
Table 18. EEPROM Timing Parameters ............................................................................................................................... 97
Table 19. MAC Mode MII Timing Parameters ....................................................................................................................... 98
Table 20. PHY Mode MII Timing Parameters ....................................................................................................................... 99
Table 21. RMII Timing Parameters ..................................................................................................................................... 100
Table 22. SPI Input Timing Parameters .............................................................................................................................. 101
Table 23. SPI Output Timing Parameters ........................................................................................................................... 102
Table 24. Auto-Negotiation Timing Parameters .................................................................................................................. 103
Table 25. MDC/MDIO Typical Timing Parameters .............................................................................................................. 104
Table 26. Reset Timing Parameters ................................................................................................................................... 105
Table 27. Transformer Selection Criteria ............................................................................................................................ 107
Table 28. Qualified Magentic Vendors ................................................................................................................................ 107
Table 29. Typical Reference Crystal Characteristics .......................................................................................................... 107
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 8 Revision 1.4
Pin Configuration
64-Pin QFN
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 9 Revision 1.4
Pin Description
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
1 RXP1 I 1 Physical receiv e sig nal + (differential)
2 RXM1 I 1 Physical receiv e sig nal – (differential)
3 TXP1 O 1 Physical trans mit sig nal + (dif f erential)
4 TXM1 O 1 Physica l transmit signal – (differential)
5 VDDA12 P 1.2V analog power
6 GND GND Ground with all grounding of die bottom
7 ISET Set physical transmit output current. Pull-down with a 12.4kΩ 1% resistor.
8 VDDAT P 3.3V analog VDD
9 RXP2 I 2 Physical receive sig nal + (diffe r entia l)
10 RXM2 I 2 Phy sica l receiv e signal – (differential)
11 TXP2 O 2 Physical transmit signal + (di ff er enti al)
12 TXM2 O 2 Phy sica l tra ns mit sig nal – (differential)
13 VDDAT P 3.3V analog VDD
14 INTR_N OPU Interrupt. This pin is the Open-Drain output pin.
15 VDDC P 1.2V digital core VDD
16 SM3TXEN IPD 3 MAC3 switch MII/RMII transmit enable
17 SM3TXD3 IPD 3 MAC3 switch MII transmit bit 3
18 SM3TXD2 IPD 3 MAC3 switch MII transmit bit 2
19 SM3TXD1 IPD 3 MAC3 s witch MII/RMII transmit bit 1
20 SM3TXD0 IPD 3 MAC3 switch MII/RMII transmit bit 0
21 SM3TXC/
SM3REFCLK I/O 3
MAC3 switch MII transmit clock:
Input: SW3-MII MAC mode
Output: SW3-MII PHY mode
Input: SW3-RM I I referen ce clock
22 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry
23 SM3RXC I/O 3
MAC3 switch MII receive clock:
Input: SW3-MII MAC mode
Output: SW3-MII PHY mode
Output: SW3-RMII reference clock
Unused RMII clock can be pull-down or disable by Register 87.
24 SM3RXDV/
SM3CRSDV IPD/O 3 SM3RXDV: MAC3 switch SW3-MII receives data valid.
SM3CRSDV: MAC3 switch SW3-RMII carrier sense/receive data valid.
25 SM3RXD3 IPD/O 3
MAC3 switch MII receive bit 3.
Strap option:
PD (default) = enable flow control;
PU = disable flow control.
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 10 Revision 1.4
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
26 SM3RXD2 IPD/O 3 MAC3 switch MII receive bit 2 and strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
27 SM3RXD1 IPD/O 3
MAC3 switch MII/RMII receive bit 1
Strap option:
PD (default) = drop ex cessive coll is ion pac ket s;
PU = does not drop excessive collision packets.
28 SM3RXD0 IPD/O 3
MAC3 switch MII/RMII receive bit 0
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex m ode;
PU = enable for performance enhancement.
29 SM3CRS IPD/O 3 MAC3 switch MII carrier sense
30 GND GND Ground with all grounding of die bottom
31 SM3COL IPD/O 3 MAC3 switch MII collisions detect
32 SM4TXEN IPD 4 MAC4 switch MII/RMII transmit enable
33 SM4TXD3 IPD 4 MAC4 switch MII transmit bit 3
34 SM4TXD2 IPD 4 MAC4 switch MII transmit bit 2
35 SM4TXD1 IPD 4 MAC4 switch MII/RMII transmit bit 1
36 SM4TXD0 IPD 4 MAC4 switch MII/RMII transmit bit 0
37 SM4TXC/
SM4REFCLK I/O 4
MAC4 switch MII transmit clock:
Input: SW4-MII MAC mode clock.
Input: SW4-RM I I referen ce clock, ple ase al so see the strap-in pin P1LED1 for
the clock mode and normal mode.
Output: SW4-MII PHY modes.
38 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry
39 SM4RXC I/O 4
MAC4 switch MII receive clock:
Input: SW4-MII MAC mode.
Output: SW4-MII PHY mode.
Output: SW4-
RMII 50MHz reference clock (the device is default clock mode; the
clock source comes from X1/X2 pins 25MHz crystal).
When the device is set in normal mode, (the chip ’s clo ck source co mes from
SM4TXC), the SM4RXC reference clock output should be disabled by the
Register 87. Please also see the strap-in pin P1LED1 for the select ion of the
clock mode and normal mode.
40 SM4RXDV/
SM4CRSDV IPD/O 4 SM4RXDV: MAC4 switch SW4-MII receives data valid.
SM4CRSDV: MAC4 switch SW4-RMII carrier sense/receive data valid.
41 SM4RXD3 IPD/O 4
MAC4 switch MII receive bit 3
Strap option:
PD (default) = disable switch MII/R MII full-duplex flow control;
PU = enable switch MII/RMII full-duplex flow control.
42 SM4RXD2 IPD/O 4
MAC4 switch MII receive bit 2
Strap option:
PD (default) = switch MII/RMII in full-duplex m ode;
PU = switch MII/RMII in half-duplex mode.
43 SM4RXD1 IPD/O 4
MAC4 switch MII receive bit 1
Strap option:
PD (default) = MAC4 switch SW4-MII/RMII in 100Mbps mode;
PU = MAC4 switch SW5-MII/RMII in 10Mbps mode.
Micrel, Inc.
KSZ8864CNX/RMNUB
4, 2015 11 Revision 1.4
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
44 SM4RXD0 IPD/O 4
MAC4 Switch MII/RMII receive bit 0.
Strap option: LED mode
PD (default) = mode 0;
PU = Mode 1.
See “Register 11.”
Mode 0 Mode 1
PxLED1 Link/Act 100Lnk/Act
PxLED0 Speed Full dupl ex
45 SM4COL IPD/O 4 MAC4 Switch MII collision detect:
Input: SW4-MII MAC modes.
Output: SW4-MII PHY modes.
46 SM4CRS IPD/O 4 MAC4 Switch MII modes carrier sense:
Input: SW4-MII MAC modes.
Output: SW4-MII PHY modes.
47 SCONF1 IPD
MAC4 Switch SW4-MII enabled with PHY mode or MAC mode, have to configure
SCONF1 Pin 47 with SCONF0 Pin 48 together.
See pins configuration table b elow:
Pin#
(47,48) Port 4 Switch MAC4
SW4- MII
00
(Default) Port 4 SW4-MII PHY mode
01 Disable port 3 and port 4
10 Disable port 4 only
11 Port 4 SW4-MII MA C mode
48 SCONF0 IPD Port 4 Switch SW4-MII enabled wi th PHY mode or MAC mode, have to configure
SCONF0 pin 48 with SCONF1 Pin 47 together.
See Pin 47 description.
49 P2LED1 IPU/O 2 LED indicator for Port 2.
This pin has to be pulled down by a 1K resistor in the desi gn for
KSZ8864CNX/RMNUB.
50 P2LED0 IPU/O 2
LED indicator for Port 2.
Strap option: Switch MAC3 used only.
PU (default) = Select MII interfac e for the Switch MAC3 SW3-MII.
PD = Select RMII interface for the Switch MAC3 SW3-RMII.
51 P1LED1 IPU/O 1
LED indicator for Port 1.
Strap option: Switch RMII used only.
PU (default) = Select the device as clock mode, when use RMII interface, all
clock source come from pin x1/x2 crystal 25MHz.
PD = Select the device as normal mode when use RMII interface. All clock
sources come from SW4-RMII SM4TXC pin with an external input 50MHz clock.
In the normal mode, the 25MHz crystal clock from pin X1/X2 doesn’t take affec t
and should disable SW4-RMII SW4RXC 50MHz clock output by the register 87.
The normal mode is used when SW4-RMII receive an external 50MHz RMII
reference clock from pin SM4TXC.
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Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
52 P1LED0 IPU/O 1
LED indicator for Port 1.
Strap option: for Swi tch MAC4 only.
PU (default) = Select MII interface for the Switch MAC4 SW4-MII.
PD = Select RMII interface for the Switch MAC4 SW4-RMII.
53 MDC IPU All MII management interface clock. Or SMI interface clock
54 MDIO IPU/O All MII management data I/O. Or SMI interface data I/O
Features internal pull down to define pin state when not driven.
Note: Need an external pull-up when driven.
55 SPIQ IPU/O All SPI serial data output in SPI slave mode.
Note: Need an external pull-up when driven.
56 SPIC/SCL IPU/O All (1) Input clock up to 25MHz in SPI slave mode,
(2) Output cloc k at 61KHz in I2C master mode.
Note: Need an external pull-up when driven.
57 SPID/SDA IPU/O All (1) Serial data input in SPI slave mode;
(2) Serial data input/output in I2C master mode .
Note: Need an external pull-up when driven.
58 SPIS_N IPU All
Active low.
(1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the device is
deselected and SPIQ is held in high impedance state, a high-to-low transition to
initiate the SPI data transfer.
(2) Not used in I2C master mode.
59 PS1 IPD
Serial bus config urat ion pin.
For this case, if the EEPROM is not present, the Switch will start itself with the PS
[1.0] = 00 default register values.
Pin Configuration Serial Bus Configuration
PS[1.0]=00 I2C Master Mode for EEPROM
PS[1.0]=01 SMI Interface Mode
PS[1.0]=10 SPI Slave Mode for CPU Interface
PS[1.0]=11 Factory Test Mode (BIST)
60 PS0 IPD S erial bus config uration pin.
61 RST_N IPU Reset the device. Active low.
62 VDDC P 1.2V digital core VDD.
63 X1 I 25MHz crystal clock connection or 3.3V oscillator input. Crystal/oscillator should
be ≤ ±50ppm tolerance.
64 X2 O 25MHz crystal clo ck connec tio n.
Notes:
1. P = power supply
I = input
O = output
I/O = bidirectional
GND = ground
IPU = input with internal pull-up
IPD = input with internal pull-down
IPU/O = input with internal pull -up during reset ; output pi n otherwise
IPD/O = input with internal pull -down during reset; out put pin otherwise
2. PU = strap pin pull-up
PD = strap pull-down
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Pin for Strap-In Options
The KSZ8864CNX/RMNUB can function as a managed switch or unmanaged switch. If no EEPROM or microcontroller
exists, the KSZ8864CNX/RMNUB will operate from its default setting. The strap-in option pins can be configured by
external pull-up/down resistors and take effect after power-up reset or warm reset. The functions are described in the
following tab le.
Pin Number Pin Name Type
(3)
Port Pin Function
(4)
25 SM3RXD3 IPD/O
MAC3 Switch MII receive bit 3
Strap option:
PD (default) = enable flow control;
PU = disable flow control.
26 SM3RXD2 IPD/O MAC3 Switch MII receive bit 2 and Strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
27 SM3RXD1 IPD/O
MAC3 Switch MII/RMII receive bit 1
Strap option:
PD (default) = drop ex cessive coll is ion pac ket s;
PU = does not drop excessive collision packets.
28 SM3RXD0 IPD/O
MAC3 Switch MII/RMII receive bit 0
Strap option:
PD (default) = disable aggressive back-off algor it hm in half-duplex mode;
PU = enable for performance enhancement.
41 SM4RXD3 IPD/O
MAC4 Switch MII receive bit 3.
Strap option:
PD (default) = Disable Switch MII/RMII full-duplex flow control;
PU = Enable Switch MII/RMII full-duplex flow control .
42 SM4RXD2 IPD/O
MAC4 Switch MII receive bit 2.
Strap option:
PD (default) = Switch MII/RMII in full-duplex mode;
PU = Switc h MII/RMII in half-duplex mode.
43 SM4RXD1 IPD/O
MAC4 Switch MII/RMII receive bit 1.
Strap option:
PD (default) =MAC4 Switch SW4-MII/RMII in 100Mbps mode;
PU = MAC4 Switch SW-5MII/RMII in 10Mbps mode.
44 SM4RXD0 IPD/O
MAC4 Switch MII/RMII receive bit 0.
Strap option: LED mode
PD (default) = mode 0;
PU = mode 1.
See “Register 11.”
Mode 0 Mode 1
PxLED1 Link/Act 100Lnk/Act
PxLED0 Speed Full dupl ex
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Pin for Strap-In Options (Continued)
Pin Number Pin Name Type
(3)
Port Pin Function
(4)
47 SCONF1 IPD
MAC4 Switch SW4-MII enabled with PHY mode or MAC mode, have to configure
SCONF1 Pin 47 with SCONF0 Pin 48 together.
See pins configur atio n table b elow:
Pin# (47,48) Switch MAC4
SW4- MII/RMII
00 (Default) Port 4 SW4-MII PHY mode
01 Disable port 3 and port 4
10 Disable port 4 only
11 Port 4 SW4-MII MA C mode
48 SCONF0 IPD Port 4 Switch SW4-MII enabled with PHY mode or MAC mode, have to configure
SCONF0 Pin 48 with SCONF1 Pin 47 together.
See pin 47 description.
49 P2LED1 IPU/O 2 LED indicator for Port 2.
This pin has to be pulled down by 1K resistor in the design for
KSZ8864CNX/RMNUB.
50 P2LED0 IPU/O 2
LED indicator for Port 2.
Strap option: Switch MAC3 used only.
PU (default) = Select MII interface for the Switch MAC3 SW3-MII.
PD = Select RMII interface for the Switch MAC3 SW3-RMII.
51 P1LED1 IPU/O 1
LED indicator for Port 1.
Strap option: Switch RMII used only.
PU (default) = Select the device as clock mode. When use RMII interface, all
clock source come from Pin x1/x2 crystal 25MHz.
PD = Select the devi ce as nor mal mod e when use RMII interface. All clock
sources come from SW4-RMII SM4TXC pin with an external input 50MHz clock.
In the normal mode, the 25MHz crystal clock from pin X1/X2 doesn’t take affect
and should disable SW4-RMII SW4RXC 50MHz clock output by the Register 87.
The normal mode is used when SW4-RMII receive an external 50MHz RMII
reference clock from pin SM4TXC.
52 P1LED0 IPU/O 1
LED indicator for Port 1.
Strap option: for Swi tch MAC4 only.
PU (default) = Select MII interface for the Switch MAC4 SW4-MII.
PD = Select RMII interface for the Switch MAC4 SW4-RMII.
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Pin for Strap-In Options (Continued)
Pin Number Pin Name Type
(3)
Port Pin Function
(4)
59 PS1 IPD
Serial bus config urat ion pin.
For this case, if the EEPROM is not present, the Switch will start itself with the PS
[1.0] = 00 default register values.
Pin Configuration Serial Bus Configuration
PS[1.0]=00 I2C Master Mode for EEPROM
PS[1.0]=01 SMI Interface Mode
PS[1.0]=10 SPI Slave Mode for CPU Interface
PS[1.0]=11 Factory Test Mode (BIST)
Notes:
3. IPU = input with internal pull-up
IPD = input with internal pull-down
IPU/O = input with internal pull -up during reset; out put pin otherwise
IPD/O = input with internal pull -down during reset; out put pin otherwise
4. PU = strap pin pull-up
PD = strap pull-down
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Introduction
The KSZ8864CNX/RMNUB contains two 10/100 physical layer transceivers and four media access control (MAC) units
with an integrated L ayer 2 managed s witch. The device runs in multiple modes. They are two copper plus two MAC MII,
two copper plus t wo MAC RMII, two cop per plus 1 M AC MII plus 1 MAC R MII, a nd two copp er plus 1 M AC MII or 1 MAC
RMII. These are useful for implementing multiple products in many applications.
The KSZ8864CNX/RMNUB has the flexib ility to resi de in a m anaged or unm anaged desi gn. In a m anaged design, a hos t
processor has complete control of the KSZ8864CNX/RMNUB via the SPI bus, or partial control via the MDC/MDIO
interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8864CNX/RMNUB supports IEEE 802.3 10BASE-T/100BASE-TX on all ports with Auto
MDI/MDIX. The KSZ8864CNX/RMNUB can be used as fully managed 4-port switch through two microprocessors by its
two MII interface or RMII interface for an advance management application.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry with enhanced
mixed signal technology that makes the design more efficient and allows for lower power consumption and smaller chip
die size.
Major enhancements from the KS8864RMN to the KSZ8864CNX/RMNUB include further power saving, adding Micrel’s
LinkMD® feature and 0.11um silicon process technology. The KSZ8864CNX/RMNUB is completely pin-compatible with
the KSZ8864RMN.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversions, 4B/5B coding, scrambling, NRZ-to-NRZI
conversions, MLT3 encoding, and transmission. The circuit starts with a parallel-to-serial conversion, which converts the
MII data f rom the MAC into a 1 25M Hz ser ial bit s tream. T he data and c ontro l stream is then co nverted into 4B/5B co ding,
followed b y a scram bler. The ser ialized da ta is fur ther convert ed from NRZ to NRZ I form at, and then trans mitted in M LT3
current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1 transformer ratio. It has a typical
rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing
jitter. The wave-sha ped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recover y, NRZI -to-NRZ c onvers ion, d e-scr ambling, 4B/5 B deco ding, and s erial-to-para llel c onvers ion. T he rece iving
side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable.
Because the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its
character istics to optim ize the per formanc e. In this des ign, the variabl e equalizer will mak e an initial estim ation base d on
compar isons of incom ing si gnal str ength a gainst s om e k nown cable charac teris tics , then tun es itse lf f or opti m ization. T his
is an ongoing process and it can self-adjust against environmental changes such as temperature variations.
The equal ized signal then goes throu gh a DC restorat ion and data c onversion bl ock. The DC restoration c ircuit is used t o
compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert t he NRZI signal into the NRZ format. The signal is then sent through the de-scrambler, followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8864CNX/RMNUB generates 125MHz, 83MHz, 41MHz, 25MHz, and 10MHz clocks for system timing. Internal
clocks are generated from an external 25MHz crystal or oscillator.
Scrambler/De-Scramble r ( 100BASE-TX only)
The purpos e of the scram bler is to s pread the power s pectrum of the s ignal in or der to re duce EM I and base line wander.
The data is sc rambled thr ough the use of an 11-bit wide linear f eedback s hift regis ter (LFSR) . This c an gen erate a 204 7-
bit non-repet itive sequence . The receiver will then d e-scramble the incoming dat a stream with the sam e sequence at th e
transmitter.
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10BASE-T Transmit
The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics.
The y are interna lly wave-shaped and pr e-em phas i zed into ou tputs w ith typical 2.3 V amplitude. The harmonic c ontents are
at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the r ecei ve side , inp ut buf f er and le vel det ectin g s quelch c ircu its ar e em plo yed. A diff erentia l in put rec eiv er circ uit a nd
a PLL perf orm the decodin g function. T he Manchest er-enc oded data stream is separ ated into cloc k signal an d NRZ data.
A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the
RXP or RXM input from falsely triggering the decoder. W hen the input exceeds the squelch limit, the PLL locks onto the
incom ing signa l and t he KSZ8864CNX/RMNUB decodes a data fr ame. T he recei ver cl ock is m aintained ac ti ve duri ng id le
periods in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8864CNX/RMNUB supports HP Auto
MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-s ense f unc tio n de tec ts rem ot e trans mit and rec ei ve pair s and c or rec tly assigns tr ansmit and rec eiv e pairs f or the
switch device. This feature is extremely useful when end users are unaware of cable types and saves on an additional
uplink configuration connection. The auto-crossover feature can be disabled through the port control registers or MIIM
PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are:
Table 1. MDI/MDI-X Pin Definitions
MDI MDI-X
RJ-45 Pins Signals RJ-45 Pins Signals
1 TD+ 1 RD+
2 TD- 2 RD-
3 RD+ 3 TD+
6 RD- 6 TD-
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Strai g h t Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 1 depicts a
typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
Figure 1. Typical Straight Cable Connection
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Crossover Cab le
A cross over cable conn ects an MDI de vice to anoth er MDI device, or an MDI -X device to an other MDI -X devic e. Figure 2
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 2. Typical Crossover Cable Connection
Auto-Negotiation
The KSZ8864CNX/RMNUB conforms to the auto-negotiation protocol as described by the IEEE 802.3 committee. Auto-
negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link
partners advertise their capabilities to each other and then compare their own capabilities with those they received from
their link partners. T he highest speed an d duplex sett ing that is com mon to the two l ink partners is s elected as the m ode
of operation.
The following list shows the speed and duplex operation modes from highest to lowest.
• Highest: 100Base-TX, full-duplex
• High: 100Base-TX, half-duplex
• Low: 10Base-T, full-duplex
• Lowest: 10Bas e-T, half-duplex