GND
8LG 7
VCC
6
SYNC_EN
5
PWM_IN
4
CBOOT 3
HG 2
SW 1
LM2722
+
+
0.1PF
VIN (up to 35V)
VOUT
1PF
PWM SIGNAL
L1
Q1
Q2
D1
C1
C2
10
+5
CIN
COUT
U1
Note: for ultra low-frequency operation (such as
skip mode at light load), D1 should be a fast
recovery type diode instead of a Schottky.
SYNC_EN SIGNAL
D2
NRND
LM2722
www.ti.com
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
LM2722 High Speed Synchronous/Asynchronous MOSFET Driver
Check for Samples: LM2722
1FEATURES DESCRIPTION
The LM2722, part of the LM2726 family, is designed
2• Synchronous or Asynchronous Operation to be used with multi-phase controllers. This part
• Adaptive Shoot-Through Protection differs from the LM2726 by changing the functionality
• Input Under-Voltage-Lock-Out of the SYNC_EN pin from a whole chip enable to a
low side MOSFET enable. As a result, the SYNC_EN
• Typical 20ns Internal Delay pin now provides control between Synchronous and
• Plastic 8-pin SOIC package Asynchronous operations. Having this control can be
advantageous in portable systems since
APPLICATIONS Asynchronous operations can be more efficient at
very light loads.
• Driver for LM2723 Intel Mobile Northwood CPU
Core Power Supply. The LM2722 drives both top and bottom MOSFETs in
• High Current DC/DC Power Supplies a push-pull structure simultaneously. It takes a logic
level PWM input and splits it into two complimentary
• High Input Voltage Switching Regulators signals with a typical 20ns dead time in between. The
• Fast Transient Microprocessors built-in cross-conduction protection circuitry prevents
the top and bottom FETs from turning on
simultaneously. The cross-conduction protection
circuitry detects both the driver outputs and will not
turn on a driver until the other driver output is low.
With a bias voltage of 5V, the peak sourcing and
sinking current for each driver of the LM2722 is
typically 3A. In an SOIC-8 package, each driver is
able to handle 50mA average current. Input UVLO
(Under-Voltage-Lock-Out) forces both driver outputs
low to ensure proper power-up and power-down
operation. The gate drive bias voltage needed by the
high side MOSFET is obtained through an external
bootstrap. Minimum pulse width is as low as 55ns.
Typical Application
NOTE
TI is an Intel Mobile Voltage Positioning (IMVP) licensee.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PWM_IN
SYNC_EN
Power
On
Reset
Shoot-through
Protection
VCC
LG
GND
Logic
CBOOT
HG
SW
+4V ~ +7V
+
-
VIN (up to 35V)
VOUT
Q1
Q2
Items in bold
are external
to the IC.
D2
COUT
CIN
CBYP
D1
GND
8
LG
7
VCC
6
SYNC_EN
5
PWM_IN 4
CBOOT 3
HG 2
SW 1
NRND
LM2722
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
www.ti.com
Connection Diagram
Figure 1. SOIC (D)
(Top View)
Pin Functions
Pin Descriptions
Pin Name Function
1 SW Top driver return. Should be connected to the common node of top and bottom FETs
2 HG Top gate drive output
3 CBOOT Bootstrap. Accepts a bootstrap voltage for powering the high-side driver
4 PWM_IN Accepts a 5V-logic control signal
5 SYNC_EN Low gate Enable
6 VCC Connect to +5V supply
7 LG Bottom gate drive output
8 GND Ground
Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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NRND
LM2722
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SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
Absolute Maximum Ratings (1)
VCC 7.5V
CBOOT 42V
CBOOT to SW 8V
SW to PGND 36V
Junction Temperature +150°C
Power Dissipation
(2) 720mW
Storage Temperature −65° to 150°C
ESD Susceptibility
Human Body Model (3) 1kV
Soldering Time, Temperature 10sec., 300°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which
the device operates correctly. Operating Ratings do not imply ensured performance limits.
(2) Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PMAX = (TJMAX-TA) / θJA. The junction-to-ambient thermal resistance, θJA, for the LM2722, it is 172°C/W. For a TJMAX of 150°C
and TAof 25°C, the maximum allowable power dissipation is 0.7W.
(3) ESD machine model susceptibility is 100V.
Operating Ratings (1)
VCC 4V to 7V
Junction Temperature Range −40° to 125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which
the device operates correctly. Operating Ratings do not imply ensured performance limits.
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Electrical Characteristics
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA=
TJ= +25°C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol Parameter Condition Min Typ Max Units
POWER SUPPLY
Iq_op Operating Quiescent Current PWM_IN = 0V 190 300 µA
TOP DRIVER
Peak Pull-Up Current Test Circuit 1, Vbias = 5V, R = 3.0 A
0.1Ω
Pull-Up Rds_on ICBOOT = IHG = 0.7A 1.0 Ω
Peak Pull-down Current Test Circuit 2, Vbias = 5V, R = −3.2 A
0.1Ω
Pull-down Rds_on ISW = IHG = 0.7A 0.5 Ω
t4Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns
t6Fall Time 12 ns
t3Pull-Up Dead Time Timing Diagram 23 ns
t5Pull-Down Delay Timing Diagram, from PWM_IN 27 ns
Falling Edge
BOTTOM DRIVER
Peak Pull-Up Current Test Circuit 3, Vbias = 5V, R = 3.2 A
0.1Ω
Pull-up Rds_on IVCC = ILG = 0.7A 1.0 Ω
Peak Pull-down Current Test Circuit 4, Vbias = 5V, R = 3.2 A
0.1Ω
Pull-down Rds_on IGND = ILG = 0.7A 0.5 Ω
t8Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns
t2Fall Time 14 ns
t7Pull-up Dead Time Timing Diagram 28 ns
t1Pull-down Delay Timing Diagram, from PWM_IN 13 ns
Rising Edge
LOGIC
Vuvlo_up Power On Threshold VCC rises from 0V toward 5V 43.7 V
Vuvlo_dn Under-Voltage-Lock-Out 3.0 2.5 V
Threshold
Vuvlo_hys Under-Voltage-Lock-Out 0.7 V
Hysteresis
VIH_EN SYNC_EN Pin High Input 2.4 V
VIL_EN SYNC_EN Pin Low Input 0.8 V
Ileak_EN SYNC_EN Pin Leakage EN = 5V −2 2 µA
Current EN = 0V −2 2
ton_min Minimum Positive Input Pulse
Width 55
(1) ns
toff_min Minimum Negative Input Pulse
Width 55
(2)
VIH_PWM PWM_IN High Level Input When PWM_IN pin goes high 2.4
Voltage from 0V V
VIL_PWM PWM_IN Low Level Input When PWM_IN pin goes low 0.8
Voltage from 5V
(1) If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when
the top gate is off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
(2) If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the
bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
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Rds_pull_down =Vbias - Vx
Vx. R
Rds_pull_up =Vbias - Vx
Vx. R
Ipull_down =R
Vbias - Vx
Ipull_up =R
Vx
GND 8
HG 2
VCC
6
5
PWM_IN
4
CBOOT
3LG 7
SW 1R
Width = 200ns, One Shot
Vbias
VX
Vbias SYNC_EN
GND 8
HG 2
VCC
6
5
PWM_IN
4
CBOOT
3LG 7
SW 1R
Width = 200ns, One Shot
VX
Vbias SYNC_EN
GND 8
LG 7
VCC
6SYNC_EN
5
PWM_IN
4
CBOOT
3HG 2
SW 1R
Width = 200ns, One Shot.
VX
Vbias
GND 8
LG 7
VCC
6
5
PWM_IN
4
CBOOT
3HG 2
SW 1R
Width = 200ns,One Shot Vbias
VX
Vbias SYNC_EN
NRND
LM2722
www.ti.com
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
TEST CIRCUIT DIAGRAMS
Timing Diagram
Test Circuits
Figure 2. Test Circuit 1 Figure 3. Test Circuit 2
Figure 4. Test Circuit 3 Figure 5. Test Circuit 4
(1)
(2)
(3)
(4)
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LM2722
SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
www.ti.com
Typical Waveforms
Figure 6. Switching Waveforms of Test Circuit Figure 7. When Input Goes High
Figure 8. When Input Goes Low Figure 9. Minimum Positive Pulse
Application Information
MINIMUM PULSE WIDTH
In order for the shoot-through prevention circuitry in the LM2722 to work properly, the pulses into the PWM_IN
pin must be longer than 55ns. The internal logic waits until the first FET is off plus 20ns before turning on the
opposite FET. If, after a falling edge, a rising edge occurs sooner than the specified time, toff_min, the IC may
intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and
sooner, the driver may start to ignore the pulse and produce no output. This condition results in the PWM_IN pin
in a high state and neither FET turned on. To get out of this state, the PWM_IN pin must see a low signal for
greater than 55ns, before the rising edge.
This will also assure that the gate drive bias voltage has been restored by forcing the top FET source and Cboot
to ground first. Then the internal circuitry is reset and normal operation will resume.
Conversely, if, after a rising edge, a falling edge occurs sooner than the specified miniumum pulse width, ton_min,
the IC may intermittently fail to turn on the bottom FET. As the falling edge occurs sooner and sooner, the driver
will start to ignore the pulse and produce no output. This will result in the toff inductor current taking a path
through a diode provided for non-synchronous operation. The circuit will resume synchronous operation when the
rising PWM pulses exceed 55ns in duration.
HIGH INPUT VOLTAGES OR HIGH OUTPUT CURRENTS
At input voltages above twice the output voltage and at higher power levels, the designer may find snubber
networks and gate drive limiting useful in reducing EMI and preventing injurious transients. A small resistor, 1Ω
to 5Ω, between the driver outputs and the MOSFET gates will slightly increase the rise time and fall time of the
output stage and reduce switching noise. The trade-off is 1% to 2% in efficiency.
A series R-C snubber across in parallel with the bottom FET can also be used to reduce ringing. Values of 10nF
and 10Ωto 100Ωare a good starting point.
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NRND
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SNVS169D –NOVEMBER 2001–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 6
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PACKAGE OPTION ADDENDUM
www.ti.com 25-Aug-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2722MX/NOPB LIFEBUY SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 2722
M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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