1
Features
•Hardware
– ATSTK94 Onboard Features
Programmable Switches, LEDs and Alphanumeric Displays
Two RS232 Compatible Serial Ports
Multiple Clocks (4 MHz, 18.432 MHz, 32.768 kHz and Manual)
2-wire Serial Interface for Communication
Easy Access to all FPSLIC Pins via Headers
Push Button AVR and FPSLIC Reset
– Supports both Drop-In and In-System Programming (ISP)
– Runs Off Portable 9V DC Power Supply
– Designed to Work with Atmel System Designer™1.0 or Above
•Software
– Atmel’s System Designer
Atmel’s AVR Studio®
Atmel’s Configurator Programming System (CPS)
Co-verification, Powered by Mentor Graphics
Exemplar’s LeonardoSpectrum™
Model Technology™’s ModelSim®
Several C Compiler Evaluation Copies
– Atmel’s Integrated Development System (IDS) – FPGA Place & Route Tool
– Supports Windows®95/98/2000/Me and WindowsNT®
–OnlineHelp
•Contents
– ATSTK94 Starter Kit Board with 1 Configurator
– ATDH2225 Programming Dongle with 10-pin Ribbon Cable
– 9V DC, 200 mA, 2.1 mm Center Positive Power Supply
– Atmel System Designer CD with Evaluation License (4 Months)
– Detailed User Guide including Complete Board Schematics
– Software Tutorial and Sample Designs on Floppy Disk
Description
Atmel’s AT94K Starter Kit (ATSTK94) allows designers to, quickly and economically,
evaluate Atmel’s family of AT94K Field Programmable System Level Integrated Circuit
(FPSLIC) devices and AT17 FPSLIC Configuration Memory devices. The ATSTK94,
see Figure 1, board connects to any x86 PC via the parallel port through a 10-pin
header cable to program the AT17 FPSLIC Configuration EEPROM, which in turn pro-
grams the AT94K FPSLIC device. A truly portable solution, which allows engineers to
prototype and develop designs from their lab bench or office.
Rev. 2309B–FPSLI–01/02
Starter Kit
Programmable
SLI
ATSTK94
2ATSTK94
2309B–FPSLI–01/02
Figure 1. ATSTK94 FPSLIC Starter Kit Board
Switches
Jumpers
LEDs
UART0
UART1
Power Socket
Programming
Switch
Configurator
Header
Power LED
Alphanumeric Displays Configurator
Socket
Power
Switch
Reset
Switch
3
ATSTK94
2309B–FPSLI–01/02
Switches, LEDs, and
Alphanumeric
Displays
The user configures each Programmable Switch or LED for use, with either the FPGA or
AVR portion of the FPSLIC device. Furthermore, some switches may be configured for
use as AVR External Interrupts allowing simulation of external events. The board fea-
tures four Alphanumeric Displays which are connected to I/O pins of the embedded
AT40KAL FPGA core.
Program and Run Switch The Program and Run Switch controls the connection from the download cable to the
Configurator and the Configurator to the FPSLIC.
In the PROG position you can use the download cable and CPS to program the configu-
ration memory with your FPSLIC Bitstream file generated by System Designer.
In the Run position the FPSLIC device will load the Bitstream file and run your design. If
the design does not start, you can use the RESET button with JP19 in the RESET posi-
tion to force a reconfiguration of the device. In the Run position, the configurator will
boot the FPSLIC device with the current program.
ISP and Reset
Connections
There are 2 device reset connections in the FPSLIC device.
The AVR RESET will reset the AVR and start from the reset vector in the interrupt table.
RESET will cause the whole device to reset and reboot from the Configurator.
SW12 is used to perform the reset. Jumper 19 is used to determine whether it will be an
AVR reset or a full device reset, see Table 1.
If you have logic RESET signal in your design, you cannot use SW12 to perform this
reset; you should use one of the switches SW 1 –8 to perform your design reset. Your
design reset can be connected to any User IO on the FPGA side of FPSLIC. If you are
using SW1 –8, then you should use Pin locks to assign the correct user IO for the cor-
rect Switch.
Button/Switch
Connections
The jumpers, located next to the buttons/switches control the button/switch connections,
see Table 2.
The left side of the jumpers are connected to LEDs, the right side of the jumpers are
connected to Switches.
The A and F markings indicate a connection to the AVR or the FPGA.
When you press the switch it generates a “1”.
Table 1. Reset Connections
RESET Source Pin Hardware Settings
RESET SW12 108 JP19 Set to RESET (Default)
AVR RESET SW12 48 JP19 Set to AVR RESET
4ATSTK94
2309B–FPSLI–01/02
LED Connections The jumpers, located next to the LEDs, control the LED connections.
Alternate jumpers connect to the switches, see Table 3, and to the LEDs. A white line on
the silk screen indicates whether the jumper is for LED or the Switch.
With the A F text the right way up the left most Jumper is for the LED 1. The A and F
markings indicate a connection to the AVR or the FPGA.
When you drive a “1”to the LED it will light.
Table 2. Switch Connections
Switch Destination Pin Hardware Settings
SW1 FPGA User IO 202 Jumper Set to F
SW2 FPGA User IO 198 Jumper Set to F
SW3 FPGA User IO 192 Jumper Set to F
SW4 FPGA User IO 188 Jumper Set to F
SW5 FPGA User IO 180 Jumper Set to F
SW6 FPGA User IO 176 Jumper Set to F
SW7 FPGA User IO 172 Jumper Set to F
SW8 FPGA User IO 168 Jumper Set to F
SW1 AVR Interrupt INTP0 135 Jumper Set to A
SW2 AVR Interrupt INTP1 145 Jumper Set to A
SW3 AVR Interrupt INTP2 146 Jumper Set to A
SW4 AVR Interrupt INTP3 152 Jumper Set to A
SW5 AVR PortE PE0 109 Jumper Set to A
SW6 AVR PortE PE1 110 Jumper Set to A
SW7 AVR PortE PE2 113 Jumper Set to A
SW8 AVR PortE PE3 122 Jumper Set to A
Table 3. LED Connections
LED Source Pin Hardware Settings
L1 FPGA User IO 200 Jumper Set to F
L2 FPGA User IO 196 Jumper Set to F
L3 FPGA User IO 190 Jumper Set to F
L4 FPGA User IO 186 Jumper Set to F
L5 FPGA User IO 178 Jumper Set to F
L6 FPGA User IO 174 Jumper Set to F
L7 FPGA User IO 170 Jumper Set to F
L8 FPGA User IO 166 Jumper Set to F
L1 AVR PortD PD0 111 Jumper Set to A
L2 AVR PortD PD1 112 Jumper Set to A
L3 AVR PortD PD2 114 Jumper Set to A
5
ATSTK94
2309B–FPSLI–01/02
Alphanumeric
Connections
There are 4 digits of Alphanumeric on the board. The connections to the Alphanumeric
are shared between both bits on the same device, see Table 4. This means that Bit 0
and Bit 1 share connections, and Bit 2 and Bit 3 share connections for all the segments,
see Figure 2. The difference in connection is in the cathode connection that selects
between the 2 digits. The cathodes should be driven with a 1/10 Duty Cycle and a
0.1 ms Pulse Width, see Table 5.
L4 AVR PortD PD3 120 Jumper Set to A
L5 AVR PortD PD4 121 Jumper Set to A
L6 AVR PortD PD5 126 Jumper Set to A
L7 AVR PortD PD6 127 Jumper Set to A
L8 AVR PortD PD7 134 Jumper Set to A
Table 3. LED Connections
LED Source Pin Hardware Settings
Table 4. Alphanumeric Connections
LED 0 Source Pin LED 1 Source Pin
Anode A FPGA User IO 94 Anode A FPGA User IO 73
Anode B FPGA User IO 98 Anode B FPGA User IO 80
Anode C FPGA User IO 97 Anode C FPGA User IO 76
Anode D FPGA User IO 93 Anode D FPGA User IO 72
Anode E FPGA User IO 81 Anode E FPGA User IO 59
Anode F FPGA User IO 82 Anode F FPGA User IO 60
Anode G FPGA User IO 87 Anode G FPGA User IO 66
Anode H FPGA User IO 89 Anode H FPGA User IO 69
Anode J FPGA User IO 91 Anode J FPGA User IO 70
Anode K FPGA User IO 88 Anode K FPGA User IO 68
Anode L FPGA User IO 86 Anode L FPGA User IO 65
Anode M FPGA User IO 83 Anode M FPGA User IO 61
Anode N FPGA User IO 92 Anode N FPGA User IO 71
Anode P FPGA User IO 84 Anode P FPGA User IO 63
Anode D.P. FPGA User IO 95 Anode D.P. FPGA User IO 74
Cathode Bit 1 FPGA User IO 85 Cathode Bit 1 FPGA User IO 64
Cathode Bit 2 FPGA User IO 96 Cathode Bit 2 FPGA User IO 75
6ATSTK94
2309B–FPSLI–01/02
Figure 2. LEDs
Table 5. ASCII Code Table
Value DP P N M L K J H G F E D C B A
0 000000000111111
1 000000000000110
2 001000100011011
3 001000100001111
4 001000100100110
5 001000100101101
6 001000100111101
7 000000000000111
8 001000100111111
9 001000100101111
a 001000100011111
b 001000100111100
c 001000100011000
d 001000100011110
e 001000100111011
f 001000000110001
. 100000000000000
* 111111111000000
LED 1 LED 0
Bit 3 Bit 2
Bit 2 Bit 0
7
ATSTK94
2309B–FPSLI–01/02
RS232-compatible
UARTs
The RS232-compatible UARTs allow for communication between the two on-board
UARTs through the null-modem cable. It is also possible for communication between
the UARTs and other devices, such as your PC, by using a simple terminal program.
UART Connections The 2 UART connections, see Table 6, are made to DB9 connectors. Printf commands
are sent out on UART 0.
Multiple Clocks There are multiple clock circuits on the Starter Kit. A Manual Clock or the 4 MHz Oscilla-
tor are connected to 2 of the FPGA Global Clock pins. The 32,768 KHz (for the
implementation of the Real Time Clock calculations), 4 MHz, or 18.432 MHz can be
used to drive the AVR. The FPGA has 8 Global Clocks, 2 of these (GCLK5 and GCLK6)
can also be driven from the AVR system Clock. GCLK6 can alternatively be driven from
the Watchdog timer or one of the timer counters. For full details on the Clock circuits in
the FPSLIC device please refer to the AT94K datasheet available on the Atmel web site,
at http://www.atmel.com/atmel/acrobat/doc1138.pdf.
Table 6. UART Connections
UART Source /Destination Pin Hardware Settings
UART 0 RX0 140 Connect Cable to UART0
UART 0 TX0 141 Connect Cable to UART 0
UART1 RX1 149 Connect Cable to UART 1
UART1 TX1 150 Connect Cable to UART 1
Table 7. Clock Connections
Frequency Destination Pin Hardware Settings
Manual Clock FPGA GCLK7 162 Use MAN CLK Switch (SW9)
to Pulse Clock
Available Global
Clocks
FPGA GCLK1
FPGA GCLK2
FPGA GCLK3
FPGA GCLK4
FPGA GCLK7
FPGA GCLK8
4
47
57
100
162
204
32,768 KHz Crystal AVR TOSC 1 147 None
4 MHz Oscillator AVR System Clock 138 For Rev2 –JP17 towards side of
board, JP18 is unconnected.
For Rev3 and beyond –Position of
JP17 is changed, it is aligned with
FPGA and AVR jumpers. JP17 is
connected towards the inner side of
the board, JP18 is unconnected.
18.432 MHz Crystal AVR System Clock 138 For Rev2 –JP17 towards middle of
board, JP18 connected.
For Rev3 and beyond –Position of
JP17 is changed, it is aligned with
FPGA and AVR jumpers. JP17 is
connected towards the edge of the
board, JP18 is connected.
8ATSTK94
2309B–FPSLI–01/02
2-wire Serial Interface The 2-wire Serial Interface is the protocol from which the FPSLIC device receives con-
figuration data from the AT17LV010 Configuration Memory. The maximum size of an
AT94K40 design is approximately 800 kbits, thus leaving approximately 200 kbits of
unused space. By using the 2-wire Serial Interface, it is possible to use the unused
200 kbits as external data storage memory.
Related Documents •ATSTK94 Starter Kit User Guide (Supplied with ATSTK94)
•AT94K Series datasheet, available at
http://www.atmel.com/atmel/acrobat/doc1138.pdf.
•AT94K Series Configuration application note, available at
http://www.atmel.com/atmel/acrobat/doc2313.pdf.
•AT17LV010 datasheet, available at
http://www.atmel.com/atmel/acrobat/doc0944.pdf.
•Programming Specification for Atmel’s Configuration EEPROMs, available at
http://www.atmel.com/atmel/acrobat/doc0437.pdf.
•Additional application notes found on the Atmel web site, at
http://www.atmel.com/atmel/products/prod183.htm.
9
ATSTK94
2309B–FPSLI–01/02
Board Schematics
Clock Circuits
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SOCKETED
Label
OSC
and
XTAL
ATMEL CORPORATION
Title: Clock Circuits
Size: A Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 1 of 8
XTAL1_138
XTAL2_139
TOSC1_147
TOSC2_148
GCK4_100
GCK7_162
VCC
VCC
C23
27 pF
R22
200K
C24
33 pF
SW9
JP17
3JUMPER
1
2
3
R23
330 ohm
R3
1K
U11
4 MHz Osc
DIP8
1 4
8 5
N/C GND
VCC OUT
Y1
18.432 MHz Y2
32,768 Hz
C17
33 pF
C16
27 pF
JP18
JUMPER
1 2
C18
10 nF
R21
10M
10 ATSTK94
2309B–FPSLI–01/02
Alphanumeric Display Circuits
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Green Display Modules
E_59
M_61
L_65
K_68
J_70
D_72
DP_74
C_76
E_81
M_83
L_86
K_88
J_91
D_93
DP_95
C_97
F_60
P_63
1_64
G_66
H_69
N_71
A_73
2_75
B_80
F_82
P_84
1_85
G_87
H_89
N_92
A_94
2_96
B_98
U9
LPT3784G01
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
+E
+M
nc
+L
+K
+J
+D
+DP
+C +B
-2
+A
+N
+H
+G
-1
+P
+F
U10
LPT3784G01
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
+E
+M
nc
+L
+K
+J
+D
+DP
+C +B
-2
+A
+N
+H
+G
-1
+P
+F
ATMEL CORPORATION
Title: Alphanumeric Display Circuits
Size: A Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 2 of 8
11
ATSTK94
2309B–FPSLI–01/02
FPSLIC Connections
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M0_50
M2_56
GND
GND
GND
GND
OTS
GND
GCK1
VCC
PE5
GCK8
VCC
PE7
GND
VCC
PE4
FCK1
GND
PE6
VCC
FCK2
GCK2
VCC
GND
GND
VCC
VCC
VCC
GCK4
HDC
GCK3
GND
VCC
GND
GND
VCC
D0_151
RX1_149
CCLK_153
PD7_134
XTAL1_138
TOSC1_147
INTP1_145
RX0_140
PD1_112
RESET_108
PD2_114
PD5_126
PE1_110
SDA_124
PD4_121
SW3_192
SW2_198
LED2_196
TX1_150
PD0_111
PE2_113
INTP3_152
SCL_125
XTAL2_139
PD6_127
PE3_122
INTP0_135
INTP2_146
TX0_141
PD3_120
PE0_109
TOSC2_148
AVRRESET_48
K_68
E_59
D_72
F_60
2_75
L_65
A_73
J_70
G_66
H_69
DP_74
C_76
N_71
M_61
INIT_77
1_64
P_63
SW1_202
LED3_190
SW5_180
LED5_178LED1_200
LED4_186
B_80
LED8_166
SW8_168
SW6_176
LED7_170
SW4_188
SW7_172
GCK7_162
LED6_174
F_82
K_88
D_93
C_97
H_89
A_94
L_86
GCK4_100
E_81
G_87
N_92
M_83
1_85
2_96
B_98
CON_103
DP_95
P_84
J_91
PE7_133
VCC
U1
AT94K40-25DQC
6
7
10
11
51
60
61
62
8
9
1
2
3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
52
53
54
55
57
58
59
63
56
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
5
4
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
I/O
I/O
I/O
I/O
NC
I/O
I/O
LDC(I/O)
I/O
I/O
NC
GND
NC
I/O
I/O
GND
FCK1(I/O)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FCK2(I/O)
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OTS(I/O)
GCK2(I/O)
AVRRESET
GND
M0
NC
NC
NC
VCC
GCK3(I/O)
HDC(I/O)
I/O
I/O
M2
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(INIT)I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GCK4(I/O)
GND
NC
CON
NC
NC
VCC
NC
RESET
PE0
PE1
PD0
PD1
PE2
PD2
NC
NC
NC
NC
NC
PD3
PD4
PE3
CS0
SDA
SCL
PD5
PD6
PE4
PE5
VCC
GND
PE6
PE7
PD7
INTP0
NC
NC
XTAL1
XTAL2
RX0
TX0
GND
NC
NC
INTP1
INTP2
TOSC1
TOSC2
RX1
TX1
D0
INTP3
CCLK
VCC
NC
NC
NC
I/O
GCK1(I/O)
NC
I/O
GND
I/O
GCK7(I/O)
I/O
I/O
CS1(I/O)
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GCK8(I/O)
VCC
NC
NC
NC
0.1 uF
C4
0.1 uF
CON52
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
PIN26
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
PIN33
PIN34
PIN35
PIN36
PIN37
PIN38
PIN39
PIN40
PIN41
PIN42
PIN43
PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
PIN51
PIN52
CON52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
PIN26
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
PIN33
PIN34
PIN35
PIN36
PIN37
PIN38
PIN39
PIN40
PIN41
PIN42
PIN43
PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
PIN51
PIN52
PIN53
PIN54
PIN55
PIN56
PIN57
PIN58
PIN59
PIN60
PIN61
C2
0.1 uF
C1
0.1 uF CON52
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
PIN26
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
PIN33
PIN34
PIN35
PIN36
PIN37
PIN38
PIN39
PIN40
PIN41
PIN42
PIN43
PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
PIN51
PIN52
PIN53
PIN54
PIN55
PIN56
PIN57
PIN58
PIN59
PIN60
PIN61
CON52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
PIN26
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
PIN33
PIN34
PIN35
PIN36
PIN37
PIN38
PIN39
PIN40
PIN41
PIN42
PIN43
PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
PIN51
PIN52
PIN53
PIN54
PIN55
PIN56
PIN57
PIN58
PIN59
PIN60
PIN61
ATMEL CORPORATION
Title: FPSLIC Connections
Size: C Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 3 of 8
52 Pin Connectors are double rows of Probe
pins, 26 x 2 on each side of the chip.
Add labels to connectors every 10 pins.
Labels should match chip pin numbers
up to 208.
12 ATSTK94
2309B–FPSLI–01/02
ISP and Reset Circuits
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Close to program Configurator.
Clock and Data need to be isolated to
allow programming without removinng the cable.
SER_EN pulled low to program.
Need a 3-channel switch, single item.
10-pin header from ATDH2200
Label as shown
if possible
Label
RESET
AVR
DEVICE
D0_151
CCLK_153
SCL_125
SDA_124
CON_103
INIT_77
PE7_133
AVRRESET_48
RESET_108
VCC
VCCVCC
VCC
VCC
VCC
VCC
VCC
R4
2K7
JP23
J1
HDR2X5
U5_ISP
1 2
3 4
5 6
7 8
910
12
34
56
78
910
D3
1N4001
21
SW10
SW 4PDT
2
5
8
11
12
10
3
1
4
6
7
9
R11
4.7K
R20
2.7k
R7
150
JP19
1
2
3
R6
2K7
R5
2K7
SW12
C19
0.1 uF
JP20
JP21
JP22
U12
AT17C010_2J
SOCKET
PLCC20
4
2
8
6
15
17
14
10
20
5
7
CLK
DATA
CE
RESET/OE
READY
SER_ENPE7
CEO/A2
GND
VCC
WP1
WP2
ATMEL CORPORATION
Title: ISP and Reset Circuits
Size: A Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 4 of 8
13
ATSTK94
2309B–FPSLI–01/02
LED Circuits
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
150R
Code 151
GREEN LED same style as Starter Kit LEDs
LED0 swjmp0 sw0
ledjmp0
cap
For Silk screen do not label too many jumpers.
Indicate function of jumper by connecting
line as shown.
PD2_114
LED2_196
PD3_120
LED8_166
LED4_186
PD1_112
LED1_200
PD0_111
PD5_126
LED5_178
PD6_127
PD7_134
PD4_121
LED3_190
LED7_170
LED6_174
JP2
L2
LED
JP4
1
2
3
L3
LED
L4
LED
JP8
1
2
3
L5
LED
U68 RESNET
1
2
3
4
5
6
7
8
9
COM
R1
R2
R3
R4
R5
R6
R7
R8
L6
LED
L7
LED
L1
LED
L8
LED
JP7
1
2
3
JP5
1
2
3
JP6
1
2
3
JP1
1
2
3
JP3
1
2
3
ATMEL CORPORATION
Title: LED Circuits
Size: A Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 5 of 8
1
2
3
14 ATSTK94
2309B–FPSLI–01/02
Power Circuits
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+
-
+
-
500 mA
3.3V
Swicth as on Motherboard On Off
Red LED for Power
Power Socket as on Motherboard
VCC
P3
DCPOWER9V
LM317T1
3 2
1
IN OUT
ADJ
C22
100 uF
D4
1N4001
L10
LED
C21
0.1uF
R9
330
R8
2.2K
R10
3.3K
C20
1 uF
SW14
SPDT
1
2
3
ATMEL CORPORATION
Title: Power Circuits
Size: A Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 6\ of 8
15
ATSTK94
2309B–FPSLI–01/02
RS232 Circuits
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UART0
UART1
VCC VCC VCC VCC
GNDGNDGNDGND
TX0_141
RX0_140
RX1_149
TX1_150
VCC
VCC VCC
P1
CONNECTOR DB9
5
9
4
8
3
7
2
6
1
P2
CONNECTOR DB9
5
9
4
8
3
7
2
6
1
D2
1N6050
D1
1N6050
C15
0.33 uF
TP1
TEST POINT
1
C14
0.68 uF
C13
0.33 uF
L9
15 uH
TP7
TEST POINT
1
TP2
TEST POINT
1
TP8
TEST POINT
1
TP3
TEST POINT
1
TP4
TEST POINT
1
TP5
TEST POINT
1
R1
2K7
R2
2K7
TP6
TEST POINT
1
U8
MAX212CWG
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
LN
LP
VCC
SD
EN
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
T1IN
T2IN T3IN
V-
T3OUT
T2OUT
T1OUT
R5IN
R4IN
R3IN
R2IN
R1IN
V+
GND
ATMEL CORPORATION
Title: RS232 Circuits
Size: A Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 7 of 8
16 ATSTK94
2309B–FPSLI–01/02
Switch Circuits
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Switches similar to FPGA Starter Kit
Jumpers similar to FPGA Starter Kit
Clock Jumpers
For Silk screen do not label too many
jumpers for LED and Switches. Indicate
function of jumper by connecting line as shown.
LED0 swjmp0 sw0
ledjmp0
cap
330R
PE1_110
INTP1_145
PE2_113
SW4_188
SW7_172
SW1_202
SW8_168
INTP0_135
INTP2_146
SW3_192
SW6_176
PE3_122
PE0_109
INTP3_152
SW5_180
SW2_198
VCC
R13
1k
JP14
R14
1k
C7
10 nF
JP9
1
2
3
C5
10 nF
C8
10nF
R15
1k
JP16
U78 RESNET
1
2
3
4
5
6
7
8
9
COM
R1
R2
R3
R4
R5
R6
R7
R8
C9
10 nF
R16
1k
SW1
C10
10 nF
SW3
SW2
R17
1k
SW4
SW8
JP11
R18
1k
SW5
C11
10 nF
SW6
SW7
R19
1k
JP13
C12
10 nF
JP12
JP15
C6
10 nF
R12
1k
JP10
ATMEL CORPORATION
Tit le: Switch Circuits
Siz e: A Document Number: CHW5454 Rev: 4
Date: Wednesday, June 27, 2001 Sheet 8 of 8
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
17
ATSTK94
2309B–FPSLI–01/02
Device Pinout and
Board Connection
Summary
Table 8 shows the pin number for the FPSLIC device, the corresponding function of the
FPSLIC pin and then the function as it is laid out on the Starter Kit. Any pin that does not
have a board Function assigned may be used as a wire wrap or probe connection into
the FPSLIC device.
All probe pins on the board are connected to the corresponding IO of the chip.
Pins that connect to the Switches or LEDs may also be used as user-specific inputs or
outputs simply by leaving the corresponding Jumper disconnected.
Table 8. Pinout and Board Connection
Pin FPSLIC IO Type Board Function Hardware
1 No Connect
2GND GND
3 No Connect
4GCK1(IO)
5IO
6IO
7IO
8IO
9IO
10 IO
11 IO
12 IO
13 IO
14 GND GND
15 FCK1(IO)
16 IO
17 IO
18 IO
19 IO
20 IO
21 IO
22 IO
23 IO
24 IO
25 GND GND
26 VCC VCC
27 IO
28 IO
29 IO
18 ATSTK94
2309B–FPSLI–01/02
30 IO
31 IO
32 IO
33 IO
34 IO
35 IO
36 FCK2(IO)
37 GND GND
38 IO
39 IO
40 IO
41 IO
42 IO
43 IO
44 IO
45 IO
46 OTS(IO)
47 GCK2(IO)
48 AVRRESET AVR RESET JP19, SW12
49 GND GND
50 M0 GND
51 No Connect
52 No Connect
53 No Connect
54 No Connect
55 VCC
56 M2 GND
57 GCK3(IO)
58 HDC(IO)
59 IO ALPHANUMERIC 1 E LED1 E
60 IO ALPHANUMERIC 1 F LED1 F
61 IO ALPHANUMERIC 1 M LED1 M
62 LDC(IO)
63 IO ALPHANUMERIC 1 P LED1 P
64 IO ALPHANUMERIC 1
Cathode 1
LED1 Cathode 1
Table 8. Pinout and Board Connection
Pin FPSLIC IO Type Board Function Hardware
19
ATSTK94
2309B–FPSLI–01/02
65 IO ALPHANUMERIC 1 L LED1 L
66 IO ALPHANUMERIC 1 G LED1 G
67 GND GND
68 IO ALPHANUMERIC 1 K LED1 K
69 IO ALPHANUMERIC 1 H LED1 H
70 IO ALPHANUMERIC 1 J LED1 J
71 IO ALPHANUMERIC 1 N LED1 N
72 IO ALPHANUMERIC 1 D LED1 D
73 IO ALPHANUMERIC 1 A LED1 A
74 IO ALPHANUMERIC 1 DP LED1 DP
75 IO ALPHANUMERIC 1
Cathode 2
LED1 Cathode 2
76 IO ALPHANUMERIC 1 C LED1 C
77 INIT(IO) INIT AT17 RESET/OE
78 VCC VCC
79 GND GND
80 IO ALPHANUMERIC 1 B LED1 B
81 IO ALPHANUMERIC 0 E LED0 E
82 IO ALPHANUMERIC 0 F LED0 F
83 IO ALPHANUMERIC 0 M LED0 M
84 IO ALPHANUMERIC 0 P LED0 P
85 IO ALPHANUMERIC 0
Cathode 1
LED0 Cathode 1
86 IO ALPHANUMERIC 0 L LED0 L
87 IO ALPHANUMERIC 0 G LED0 G
88 IO ALPHANUMERIC 0 K LED0 K
89 IO ALPHANUMERIC 0 H LED0 H
90 GND GND
91 IO ALPHANUMERIC 0 J LED0 J
92 IO ALPHANUMERIC 0 N LED0 N
93 IO ALPHANUMERIC 0 D LED0 D
94 IO ALPHANUMERIC 0 A LED0 A
95 IO ALPHANUMERIC 0 DP LED0 DP
96 IO ALPHANUMERIC 0
Cathode 2
LED0 Cathode 2
97 IO ALPHANUMERIC 0 C LED0 C
98 IO ALPHANUMERIC 0 B LED0 B
Table 8. Pinout and Board Connection
Pin FPSLIC IO Type Board Function Hardware
20 ATSTK94
2309B–FPSLI–01/02
99 IO
100 GCK4 (IO) GCK4 –4 MHz Clock 4 MHz Oscillator
101 GND GND
102 No Connect
103 CON Configuration Control AT17 /CE
104 No Connect
105 No Connect
106 VCC VCC
107 No Connect
108 RESET FPSLIC Device RESET JP19, SW12
109 PE0 PortE 0 JP13 A
110 PE1 PortE 1 JP14 A
111 PD0 PortD 0 JP1 A
112 PD1 PortD 1 JP2 A
113 PE2 PortE 2 JP15 A
114 PD2 PortD 2 JP3 A
115 No Connect
116 No Connect
117 No Connect
118 No Connect
119 No Connect
120 PD3 PortD 3 JP4 A
121 PD4 PortD 4 JP5 A
122 PE3 PortE 3 JP16 A
123 CS0
124 SDA 2 Wire Serial Data AT17 Data
125 SCL 2 Wire Serial Clock AT17 Clock
126 PD5 PortD 5 JP6 A
127 PD6 PortD 6 JP7 A
128 PE4 PortE 4
129 PE5 PortE 5
130 VCC VCC
131 GND GND
132 PE6 PortE 6
133 PE7 PortE 7
134 PD7 PortD 7 JP8 A
Table 8. Pinout and Board Connection
Pin FPSLIC IO Type Board Function Hardware
21
ATSTK94
2309B–FPSLI–01/02
135 INTP0 External Interrupt 0 JP9 A
136 No Connect
137 No Connect
138 XTAL1 AVR System
Clock Input
JP17, Y1
139 XTAL2 AVR System Clock Pair JP18, Y1
140 RX0 UART 0 Receive UART 0 pin3
141 TX0 UART 0 Transmit UART 0 pin 2
142 GND GND
143 No Connect
144 No Connect
145 INTP1 External Interrupt 1 JP10 A
146 INTP2 External Interrupt 2 JP11 A
147 TOSC1 Oscillator Input Y2
148 TOSC2 Oscillator Pair Y2
149 RX1 UART 1 Receive UART 1 pin 2
150 TX1 UART 1 Transmit UART 1 pin 3
151 D0 Configuration
Data Input
AT1 7 D ata
152 INTP3 External Interrupt 3 JP12 A
153 CCLK Configuration Clock AT17 Clock
154 VCC
155 No Connect
156 No Connect
157 No Connect
158 No Connect
159 IO
160 GND
161 IO0
162 GCK7(IO) GCK7 Manual Clock MAN CLK (SW)
163 IO
164 IO
165 IO
166 IO LED 8 JP8 F
167 IO
168 IO Switch 8 JP16 F
169 IO
Table 8. Pinout and Board Connection
Pin FPSLIC IO Type Board Function Hardware
22 ATSTK94
2309B–FPSLI–01/02
170 IO LED 7 JP7 F
171 GND
172 IO Switch 7 JP15 F
173 IO
174 IO LED 6 JP6 F
175 IO
176 IO Switch 6 JP14 F
177 IO
178 IO LED 5 JP5 F
179 IO
180 IO Switch 5 JP13 F
181 IO
182 GND
183 VCC
184 IO
185 IO
186 IO LED 4 JP4 F
187 IO
188 IO Switch 4 JP12 F
189 IO
190 IO LED 3 JP3 F
191 IO
192 IO Switch 3 JP11 F
193 IO
194 GND
195 IO
196 IO LED 2 JP2 F
197 IO
198 IO Switch 2 JP10 F
199 IO
200 IO LED 1 JP1 F
201 IO
202 IO Switch 1 JP9 F
203 IO
204 GCK8(IO)
205 VCC
Table 8. Pinout and Board Connection
Pin FPSLIC IO Type Board Function Hardware
23
ATSTK94
2309B–FPSLI–01/02
206 No Connect
207 No Connect
208 No Connect
Table 8. Pinout and Board Connection
Pin FPSLIC IO Type Board Function Hardware
Printed on recycled paper.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
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2309B–FPSLI–01/02 xM
Atmel®,AVR
®and AVR Studio®are the registered trademarks of Atmel; FPSLIC™and System Designer™are
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