©2002 Fairchild Semiconductor Corporation IRFD9110 Rev. B
IRFD9110
0.7A, 100V, 1.200 Ohm, P-Channel Power
MOSFET
This P-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17541.
Features
• 0.7A, 100V
•r
DS(ON)
= 1.2
00Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Symbol
Packaging
HEXDIP
Ordering Information
PART NUMBER PACKAGE BRAND
IRFD9110 HEXDIP IRFD9110
NOTE: When ordering, use the entire part number.
G
D
S
SOURCE
GATE
DRAIN
Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation IRFD9110 Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRFD9110 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
-100 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
-100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
-0.7 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
-3.0 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20 V
Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
1.0 W
Dissipation Derating Factor (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008 W/
o
C
Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
190 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J,
T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= -250
µ
A, V
GS
= 0V, (Figure 9) -100 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= -250
µ
A -2 - -4 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0V - - -25
µ
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
C
= 125
o
C - - -250
µ
A
On-State Drain Current (Note 2) I
D(ON)
V
DS
> I
D(ON)
x r
DS(ON)MAX,
V
GS
= -10V,
(Figure 6)
-0.7 - - A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - -
±
100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= -0.3A, V
GS
= -10V, (Figures 8) - 1.000 1.200
Ω
Forward Transconductance (Note 2) gfs V
DS
≤
50V, I
D
= -0.6A, (Figure 11) 0.59 0.88 - S
Turn-On Delay Time t
d(ON)
V
DD
= 0.5 x Rated BV
DSS,
I
D
= -0.7A, R
G
= 9.1
Ω
,
V
GS
=-10V, (Figures 16, 17),
R
L
= 70
Ω
for V
DSS
= 50V
R
L
= 56
Ω
for V
DSS
= 40V
MOSFET Switching Times are Essentially
Independent of Operating Temperature
-1530ns
Rise Time t
r
-3060ns
Turn-Off Delay Time t
d(OFF)
-2040ns
Fall Time t
f
-2040ns
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
V
GS
= -10V, I
D
= -0.7A, V
DS
= 0.8V x Rated BV
DSS,
(Figures 13, 18, 19) Gate Charge is
Essentially Independent of Operating
Temperature
-1115nC
Gate to Source Charge Q
gs
- 5.7 - nC
Gate to Drain “Miller” Charge Q
gd
- 5.3 - nC
Input Capacitance C
ISS
V
DS
= -25V, V
GS
= 0V, f = 1MHz, (Figure 10) - 180 - pF
Output Capacitance C
OSS
-85- pF
Reverse Transfer Capacitance C
RSS
-30- pF
Internal Drain Inductance L
D
Measured From the Drain
Lead, 2mm (0.08in) From
Package to Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 4.0 - nH
Internal Source Inductance L
S
Measured From the
Source Lead, 2mm
(0.08in) From Header to
Source Bonding Pad
- 6.0 - nH
Thermal Resistance Junction to Ambient R
θ
JA
Typical Socket Mount - - 120
o
C/W
LS
LD
G
D
S
IRFD9110
©2002 Fairchild Semiconductor Corporation IRFD9110 Rev. B
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I
SD
Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Diode
- - -0.7 A
Pulse Source to Drain Current
(Note 3)
I
SDM
- - -3.0 A
Source to Drain Diode Voltage (Note 2) V
SD
T
J
= 25
o
C, I
SD
= -0.7A, V
GS
= 0V, (Figure 12) - - -1.5 V
Reverse Recovery Time t
rr
T
J
= 150
o
C, I
SD
= -0.7A, dI
SD
/dt = 100A/
µ
s - 120 - ns
Reverse Recovery Charge6466 Q
RR
T
J
= 150
o
C, I
SD
= -0.7A, dI
SD
/dt = 100A/
µ
s - 6.0 -
µ
C
NOTES:
2. Pulse test: pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. V
DD
= 25V, starting T
J
= 25
o
C, L = 582mH, R
G
= 25
Ω,
peak I
AS
= 0.7A. See Figures 14, 15.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. OUTPUT CHARACTERISTICS
G
D
S
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
TA, AMBIENT TEMPERATURE (oC)
50 75 10025 150
-1.0
-0.8
-0.6
0
-0.4
ID, DRAIN CURRENT (A)
-0.2
125
VDS, DRAIN TO SOURCE VOLTAGE (V)
1
ID, DRAIN CURRENT (A)
100
0.1
101
0.01
10µs
DC
1ms
10ms
100ms
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TJ = MAX RATED
TC = 25oC
100µs
ID, DRAIN CURRENT (A)
0 -10 -20 -30 -40
-1
-2
-3
-4
-5
-50
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
VGS = -5V
VGS = -7V
VGS = -8V
VGS = -10V
VGS = -9V
VGS = -6V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
IRFD9110
©2002 Fairchild Semiconductor Corporation IRFD9110 Rev. B
FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs is minimal.
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves Unless Otherwise Specified (Continued)
0
-1
0-2 -4 -6 -10
-2
-3
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
-4
-8
-5
VGS = -5V
VGS = -7V
VGS = -8V
VGS = -9V
VGS = -10V
VGS = -6V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-12.0
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-9.6
-7.2
-4.8
0-8-6-4-20 -10
-2.4
TJ = 25oC
TJ = -55oC
TJ = 125oC
VDS > ID(ON) x rDS(ON)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
2
5
-1 -2
DRAIN TO SOURCE ON RESISTANCE (Ω)
ID, DRAIN CURRENT (A)
-3
1
3
4
VGS = -10V
VGS = -20V
2µs PULSE TEST
0
NORMALIZED DRAIN TO SOURCE
2.5
1.5
1.0
0.5
0
-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120 160
2.0
80
VGS = -10V, ID = -0.3A
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.25
0.95
0.85
0.75
-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
80 120 160
1.05
1.15
ID = 250µA
500
100
00-20 -50
C, CAPACITANCE (pF)
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
400
200
-10 -30
CISS
COSS
CRSS
-40
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
IRFD9110
©2002 Fairchild Semiconductor Corporation IRFD9110 Rev. B
FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
0 -1.2 -2.4 -3.6 -4.8
0.5
1.0
1.5
2.0
2.5
-6.0
0
TJ = -55oC
TJ = 25oC
TJ = 125oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-0.4 -1.0 -1.2 -1.6 -1.8-0.6
-0.1
-1.0
-10
ISD, DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
-100
-0.8 -1.4
TJ = 25oC
TJ = 150oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
Qg(TOT), TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
04610
-15
- 5
5ID = -0.7A
0
-10
-20
28
VDS = -80V
VDS = -50V
VDS = -20V
tP
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
IRFD9110
©2002 Fairchild Semiconductor Corporation IRFD9110 Rev. B
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
VGS
RL
RG
DUT
+
-
VDD
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
0.3µF
12V
BATTERY 50kΩ
+VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
-VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
0
IG(REF)
IRFD9110
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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SILENT SWITCHER
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FASTr™
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HiSeC™
ISOPLANAR™
LittleFET™
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MicroPak™
MICROWIRE™
Rev. H4
ACEx™
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EcoSPARK™
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SuperSOT™-6
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STAR*POWER is used under license
VCX™