IRFD9110 Data Sheet January 2002 0.7A, 100V, 1.200 Ohm, P-Channel Power MOSFET Features * 0.7A, 100V This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. * rDS(ON) = 1.200 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance Symbol Formerly developmental type TA17541. D Ordering Information PART NUMBER IRFD9110 PACKAGE HEXDIP G BRAND IRFD9110 S NOTE: When ordering, use the entire part number. Packaging HEXDIP DRAIN GATE SOURCE (c)2002 Fairchild Semiconductor Corporation IRFD9110 Rev. B IRFD9110 TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Dissipation Derating Factor (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFD9110 -100 -100 -0.7 -3.0 20 1.0 0.008 190 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL Drain to Source Breakdown Voltage BVDSS Gate Threshold Voltage VGS(TH) Zero Gate Voltage Drain Current IDSS TEST CONDITIONS MIN TYP MAX UNITS -100 - - V VGS = VDS, ID = -250A -2 - -4 V VDS = Rated BVDSS, VGS = 0V - - -25 A ID = -250A, VGS = 0V, (Figure 9) VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) VDS > ID(ON) x rDS(ON)MAX, VGS = -10V, (Figure 6) VGS = 20V - - -250 A -0.7 - - A - - 100 nA rDS(ON) ID = -0.3A, VGS = -10V, (Figures 8) - 1.000 1.200 gfs VDS 50V, ID = -0.6A, (Figure 11) 0.59 0.88 - S VDD = 0.5 x Rated BVDSS, ID = -0.7A, RG = 9.1, VGS =-10V, (Figures 16, 17), RL = 70 for VDSS = 50V RL = 56 for VDSS = 40V MOSFET Switching Times are Essentially Independent of Operating Temperature - 15 30 ns - 30 60 ns - 20 40 ns - 20 40 ns VGS = -10V, ID = -0.7A, VDS = 0.8V x Rated BVDSS, (Figures 13, 18, 19) Gate Charge is Essentially Independent of Operating Temperature - 11 15 nC - 5.7 - nC - 5.3 - nC - 180 - pF - 85 - pF td(ON) tr td(OFF) tf Qg(TOT) Gate to Source Charge Qgs Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = -25V, VGS = 0V, f = 1MHz, (Figure 10) Internal Drain Inductance LD Measured From the Drain Lead, 2mm (0.08in) From Package to Center of Die Internal Source Inductance LS Measured From the Source Lead, 2mm (0.08in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D - 30 - pF - 4.0 - nH - 6.0 - nH - - 120 oC/W LD G LS S Thermal Resistance Junction to Ambient (c)2002 Fairchild Semiconductor Corporation RJA Typical Socket Mount IRFD9110 Rev. B IRFD9110 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - -0.7 A - - -3.0 A - - -1.5 V - 120 - ns - 6.0 - C D G S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time VSD trr Reverse Recovery Charge6466 QRR TJ = 25oC, ISD = -0.7A, VGS = 0V, (Figure 12) TJ = 150oC, ISD = -0.7A, dISD/dt = 100A/s TJ = 150oC, ISD = -0.7A, dISD/dt = 100A/s NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. VDD = 25V, starting TJ = 25oC, L = 582mH, RG = 25, peak IAS = 0.7A. See Figures 14, 15. Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER 1.2 -1.0 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 -0.8 -0.6 -0.4 -0.2 0.0 0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE -5 100s 1ms 1 10ms 0.1 100ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED 0.01 VGS = -10V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10s -4 VGS = -9V -3 VGS = -8V -2 VGS = -7V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -6V -1 DC VGS = -5V 0 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. FORWARD BIAS SAFE OPERATING AREA (c)2002 Fairchild Semiconductor Corporation 0 -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) -50 FIGURE 4. OUTPUT CHARACTERISTICS IRFD9110 Rev. B IRFD9110 Typical Performance Curves Unless Otherwise Specified (Continued) -5 -12.0 VGS = -10V -4 VGS = -9V -3 VGS = -8V -2 ID(ON), ON-STATE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -7V VGS = -6V -1 VGS = -5V VDS > ID(ON) x rDS(ON) PULSE DURATION = 80s -9.6 DUTY CYCLE = 0.5% MAX -7.2 TJ = 125oC TJ = -55oC -2.4 0 0 -4 -2 -8 -6 TJ = 25oC -4.8 0 -10 0 VDS, DRAIN TO SOURCE VOLTAGE (V) DRAIN TO SOURCE ON RESISTANCE () -8 -10 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2s PULSE TEST 4 3 VGS = -10V VGS = -20V 1 0 -6 FIGURE 6. TRANSFER CHARACTERISTICS 5 0 -4 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 2 -2 -1 VGS = -10V, ID = -0.3A PULSE DURATION = 80s 2.0 DUTY CYCLE = 0.5% MAX 1.5 1.0 0.5 0 -40 -3 -2 ID, DRAIN CURRENT (A) 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 NOTE: Heating effect of 2s is minimal. FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 500 1.25 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 400 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.05 0.95 0.85 300 CISS 200 COSS 100 CRSS 0.75 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation 0 0 -10 -30 -40 -20 VDS, DRAIN TO SOURCE VOLTAGE (V) -50 FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE IRFD9110 Rev. B IRFD9110 Typical Performance Curves PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 -100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TJ = -55oC TJ = 25oC ISD, DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 2.5 Unless Otherwise Specified (Continued) TJ = 125oC 1.5 1.0 0.5 -10 TJ = 150oC TJ = 25oC -1.0 -0.1 0 0 -1.2 -2.4 -3.6 -4.8 -6.0 -0.4 -0.6 ID , DRAIN CURRENT (A) FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT VGS, GATE TO SOURCE (V) 5 -0.8 -1.4 -1.0 -1.2 -1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) -1.8 FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE ID = -0.7A 0 -5 -10 VDS = -20V VDS = -50V VDS = -80V -15 -20 0 2 4 6 8 Qg(TOT) , TOTAL GATE CHARGE (nC) 10 FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS 0 - RG + 0V VGS DUT tP IAS VDD IAS VDS tP 0.01 FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation VDD BVDSS FIGURE 15. UNCLAMPED ENERGY WAVEFORMS IRFD9110 Rev. B IRFD9110 Test Circuits and Waveforms (Continued) tON tOFF td(OFF) td(ON) tr 0 RL - DUT VGS + 10% 10% VDS VDD RG tf VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 16. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) CURRENT REGULATOR FIGURE 17. RESISTIVE SWITCHING WAVEFORMS 0 VDS DUT 12V BATTERY 0.2F 50k 0.3F Qgs Qg(TOT) DUT G VGS Qgd D VDD 0 S IG(REF) IG CURRENT SAMPLING RESISTOR 0 +VDS ID CURRENT SAMPLING RESISTOR FIGURE 18. GATE CHARGE TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation IG(REF) FIGURE 19. GATE CHARGE WAVEFORMS IRFD9110 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET VCXTM STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4