© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 20
1Publication Order Number:
NLAS4684/D
NLAS4684
Ultra-Low Resistance
Dual SPDT Analog Switch
The NLAS4684 is an advanced CMOS analog switch fabricated in
Sub−micron silicon gate CMOS technology. The device is a dual
Independent Single Pole Double Throw (SPDT) switch featuring
Ultra−Low RON of 0.5 , for the Normally Closed (NC) switch, and
0.8 for the Normally Opened switch (NO) at 2.7 V.
The part also features guaranteed Break Before Make switching,
assuring the switches never short the driver.
The NLAS4684 is available in a 2.0 x 1.5 mm bumped die array.
The pitch of the solder bumps is 0.5 mm for easy handling.
Features
•Ultra−Low RON, t0.5 at 2.7 V
•Threshold Adjusted to Function with 1.8 V Control at
VCC = 2.7−3.3 V
•Single Supply Operation from 1.8−5.5 V
•Tiny 2 x 1.5 mm Bumped Die
•Low Crosstalk, t 83 dB at 100 kHz
•Full 0−VCC Signal Handling Capability
•High Isolation, −65 dB at 100 kHz
•Low Standby Current, t50 nA
•Low Distortion, t0.14% THD
•RON Flatness of 0.15
•Pin for Pin Replacement for MAX4684
•High Continuous Current Capability
$300 mA Through Each Switch
•Large Current Clamping Diodes at Analog Inputs
$300 mA Continuous Current Capability
•Pb−Free Packages are Available
Applications
•Cell Phone
•Speaker Switching
•Power Switching
•Modems
•Automotive
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MARKING
DIAGRAMS
Microbump−10
CASE 489AA
A1
DFN10
CASE 485C
NLAS
4684
ALYWG
G
1
1
A = Assembly Location
L = Wafer Lot
Y = Year
WW, W = Work Week
G= Pb−Free Package
4684
AYWG
G
Micro10
CASE 846B
A1
4684
AYWWG
G
1
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
0
1
IN 1, 2 NO 1, 2 NC 1, 2
OFF
ON
ON
OFF
(Note: Microdot may be in either location)
NLAS4684
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2
Figure 1. Pin Connections and Logic Diagram
(DFN10 and Micro10)
COM1
COM2 NO1
NO2
IN1
IN2
NC1
NC2
GND
VCC
(Top View)
5
4
3
2
1
6
7
8
9
10
COM1 COM2
NO1 NO2
IN1 IN2
NC1 NC2
C2
C3
C4
C1
A2
A3
A4
A1
GND
B1
B4
VCC
(Top View)
Figure 2. Pin Connections and Logic Diagram
(Microbump−10)
NLAS4684
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage *0.5 to )7.0 V
VIS Analog Input Voltage (VNO, VNC, or VCOM)*0.5 v VIS v VCC )0.5 V
VIN Digital Select Input Voltage *0.5 v VI v)7.0 V
Ianl1 Continuous DC Current from COM to NC/NO $300 mA
Ianl−pk 1Peak Current from COM to NC/NO, 10 duty cycle (Note 1) $500 mA
Iclmp Continuous DC Current into COM/NO/NC $300 mA
Iclmp 1Peak Current into Input Clamp Diodes at COM/NC/NO $500 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Defined as 10% ON, 90% off duty cycle.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage 1.8 5.5 V
VIN Digital Select Input Voltage GND 5.5 V
VIS Analog Input Voltage (NC, NO, COM) GND VCC V
TAOperating Temperature Range *55 )125 °C
tr, tfInput Rise or Fall Time, SELECT VCC = 3.3 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
0
0
100
20
ns/V
ESD Human Body Model − All Pins 5 kV
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Symbol Parameter Condition VCC $10%
Guaranteed Limit
Unit
*555C to 255Ct855Ct1255C
VIH Minimum High−Level Input
Voltage, Select Inputs
(Figure 9)
2.0
2.5
3.0
5.0
1.4
1.4
1.4
2.0
1.4
1.4
1.4
2.0
1.4
1.4
1.4
2.0
V
VIL Maximum Low−Level Input
Voltage, Select Inputs
(Figure 9)
2.0
2.5
3.0
5.0
0.5
0.5
0.5
0.8
0.5
0.5
0.5
0.8
0.5
0.5
0.5
0.8
V
IIN Maximum Input Leakage
Current, Select Inputs
VIN = 5.5 V or GND 5.5 $ 1.0 $ 1.0 $ 1.0 A
IOFF Power Off Leakage Current VIN = 5.5 V or GND 0$10 $10 $10 A
ICC Maximum Quiescent Supply
Current (Note 2)
Select and VIS = VCC or GND 5.5 $ 180 $ 200 $ 200 nA
2. Guaranteed by design.
NLAS4684
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4
DC ELECTRICAL CHARACTERISTICS − Analog Section
Symbol Parameter Condition VCC $10%
Guaranteed Maximum Limit
Unit
−555C to 255Ct855Ct1255C
Min Max Min Max Min Max
RON (NC) NC “ON” Resistance
(Note 3)
VIN v VIL
VIS = GND to VCC
IINI v 100 mA
2.5
3.0
5.0
0.6
0.5
0.4
0.7
0.5
0.4
0.8
0.5
0.5
RON (NO) NO “ON” Resistance
(Note 3)
VIN w VIH
VIS = GND to VCC
IINI v 100 mA
2.5
3.0
5.0
1.0
0.8
0.8
1.0
0.8
0.8
1.0
1.0
0.9
RFLAT (NC) NC_On−Resistance
Flatness (Notes 3, 5)
ICOM = 100 mA
VIS = 0 to VCC
2.5
3.0
5.0
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
RFLAT (NO) NO_On−Resistance
Flatness (Notes 3, 5)
ICOM = 100 mA
VIS = 0 to VCC
2.5
3.0
5.0
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
RON On−Resistance Match
Between Channels
(Notes 3 and 4)
VIS = 1.3 V;
ICOM = 100 mA
VIS = 1.5 V;
ICOM = 100 mA
VIS = 2.8 V;
ICOM = 100 mA
2.5
3.0
5.0
0.18
0.06
0.06
0.18
0.06
0.06
0.18
0.06
0.06
INC(OFF)
INO(OFF)
NC or NO Off
Leakage Current
(Figure 13) (Note 3)
VIN = VIL or VIH
VNO or VNC = 1.0
VCOM = 4.5 V
5.5 −1 1 −10 10 −100 100 nA
ICOM(ON) COM ON
Leakage Current
(Figure 13) (Note 3)
VIN = VIL or VIH
VNO 1.0 V or 4.5 V with
VNC floating or
VNC 1.0 V or 4.5 V with
VNO floating
VCOM = 1.0 V or 4.5 V
5.5 −2 2 −20 20 −200 200 nA
3. Guaranteed by design. Resistance measurements do not include test circuit or package resistance.
4. RON = RON(MAX) − RON(MIN) between NC1 and NC2 or between NO1 and NO2.
5. Flatness is defined as the difference between the maximum and minimum value of on−resistance as measured over the specified analog
signal ranges.
NLAS4684
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5
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) (Typical characteristics are at 25°C)
Symbol Parameter Test Conditions
VCC
(V)
VIS
(V)
Guaranteed Maximum Limit
Unit
*555C to 255Ct855Ct1255C
Min Typ Max Min Max Min Max
tON Turn−On Time RL = 50 CL = 35 pF
(Figures 4 and 5)
2.5
3.0
5.0
1.3
1.5
2.8
60
50
30
70
60
35
70
60
35
ns
tOFF Turn−Off Time RL = 50 CL = 35 pF
(Figures 4 and 5)
2.5
3.0
5.0
1.3
1.5
2.8
50
40
30
55
50
35
55
50
35
ns
tBBM Minimum Break−Before−Make
Time (Note 6)
VIS = 3.0
RL = 300 CL = 35 pF
(Figure 3)
3.0 1.5 2 15
ns
Typical @ 25, VCC = 5.0 V
CNC Off
CNO Off
CNC On
CNO On
NC Off Capacitance, f = 1 MHz
NO Off Capacitance, f = 1 MHz
NC On Capacitance, f = 1 MHz
NO On Capacitance, f = 1 MHz
102
104
322
330
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol Parameter Condition
VCC
V
Typical
Unit
255C
BW Maximum On−Channel −3dB
Bandwidth or Minimum Frequency
Response
VIN = 0 dBm NC
VIN centered between VCC and GND
(Figure 6) NO
3.0
3.0
6.5
9.5
MHz
VONL Maximum Feed−through On Loss VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND (Figure 6) 3.0 −0.05 dB
VISO Off−Channel Isolation (Note 7) f = 100 kHz; VIS = 1 V RMS; CL = 5 nF
VIN centered between VCC and GND(Figure 6) 3.0 −65
dB
QCharge Injection Select Input to
Common I/O (Figures 10 and 11)
VIN = VCC to GND, RIS = 0 , CL = 1 nF
Q = CL − VOUT (Figure 7)
3.0 15 pC
THD Total Harmonic Distortion THD +
Noise (Figure 9)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 , CL = 50 pF
VIS = 1 V RMS
3.0 0.14 %
VCT Channel−to−Channel Crosstalk f = 100 kHz; VIS = 1 V RMS, CL = 5 pF, RL = 50
VIN centered between VCC and GND (Figure 6)
3.0 −83 dB
6. −55°C specifications are guaranteed by design.
7. Off−Channel Isolation = 20log10 (Vcom/Vno) (See Figure 6).
NLAS4684
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6
Figure 3. tBBM (Time Break−Before−Make)
Output
DUT
50 35 pF
VCC
Switch Select Pin
90%
Output
Input
VCC
GND
90% of VOH
GND
Figure 4. tON/tOFF
50% 50%
90% 90%
tON tOFF
VOH
Output
Input
VCC
0 V
Figure 5. tON/tOFF
DUT
Open 35 pF
VCC
Input
50% 50%
10%
tON
tOFF
Output
Input
VCC
0 V
10%
50
0.1 FtBMM
Output
VOUT
VOL
VOUT VOH
VOL
DUT
Open
VCC
Input
Output
50 35 pF
VOUT
0.1 F
NLAS4684
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7
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
VISO = Off Channel Isolation = 20 Log for VIN at 100 kHz
VONL = On Channel Loss = 20 Log for VIN at 100 kHz to 50 MHz
Bandwidth (BW) = the frequency 3 dB below VONL
VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50
Output
DUT
Input
50
50 Generator
Reference
Transmitted
Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
50
ǒVOUT
VIN Ǔ
ǒVOUT
VIN Ǔ
Off On Off VOUT
VCC
GND
Output
VIN
CL
DUT
Figure 7. Charge Injection: (Q)
VIN
Open Output
Figure 8. Total Harmonic Distortion Plus Noise Versus Frequency
0.01
0.1
1
10
1 10 100 1000 10000 100000
FREQUENCY (Hz)
THD (%)
NC1
NO1
NLAS4684
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8
Figure 9. Voltage in Threshold on Logic Pins
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
02 46
Figure 10. Charge Injection versus Vis
VCC (V)
THRESHOLD VOLTAGE (V)
Threshold Falling
Threshold Rising
−800
−600
−400
−200
0
200
0246
Vin (V)
NO, VCC = 5 V
NC, VCC = 5 V
0
10
20
30
40
50
60
70
−55 −30 −520457095120
TEMPERATURE (°C)
T−on / T−off (ns)
T−off 5.0 V
T−on 5.0 VT−off 3.0 V
T−on 3.0 V
T−off 2.5 V
T−on 2.5 V
0.001
0.01
0.1
10
100
1000
−55 −54595
Comm / Closed Switch
Open Switch
1
TEMPERATURE (°C)
NO/NC CURRENT LEAKAGE (nA)
Figure 11. T−on / T−off Time versus
Temperature
Figure 12. T−on / T−off Time versus Temperature
Figure 13. NO/NC Current Leakage Off and On,
VCC = 5 V
CHARGE INJECTION “Q” (pC)
Figure 14. ICC Current Leakage versus
Temperature VCC = 5.5 V
0.001
0.01
0.1
1
10
100
1000
−55 −545 95
TEMPERATURE (°C)
ICC CURRENT LEAKAGE (nA)
0
10
20
30
40
50
60
70
1.8 2.8 3.8 4.8
VCC TEMPERATURE (°C)
T−on / T−off (ns)
T−off
T−on
80
90
100
NLAS4684
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9
Figure 15. NC On−Resistance versus
COM Voltage
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.0 0.5 1.0 1.5 2.0 2.5
Figure 16. NO On−Resistance versus
COM Voltage
VCOM (V)
RON ()
+85°C
+25°C
−40°C
0.1
0.3
0.5
0.7
0.9
1.1
1.3
0.0 1.0 2.0 3.0 4.0 5.
0
−40°C
+25°C
+85°C
Figure 17. NC On−Resistance versus
COM Voltage
VCOM (V)
RON ()
0
0.5
1
1.5
2
2.5
3
0.0 1.0 2.0 3.0 4.0 5.0
5.0 V
1.8 V
2.0 V
2.3 V
2.5 V
2.7 V
3.0 V
Figure 18. NO On−Resistance versus
COM Voltage
VCOM (V)
RON ()
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0.0 1.0 2.0 3.0 4.0 5.
0
2.5 V
5.0 V
1.8 V
2.0 V
2.3 V 2.7 V
3.0 V
RON ()
Figure 19. NC On−Resistance versus
COM Voltage
VCOM (V)
VCC = 2.5 V
ICOM = 100 mA
VCC = 2.5 V
ICOM = 100 mA
TA = +25°C
ICOM = 100 mA TA = +25°C
ICOM = 100 mA
Figure 20. NC On−Resistance versus
COM Voltage
0.1
0.15
0.2
0.25
0.3
0.35
0.0 1.0 2.0 3.0
VCC = 3 V
ICOM = 100 mA
AVERAGE RON ()
VCOM (V)
+85°C
+25°C
−40°C
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.0 1.0 2.0 3.0
+85°C+25°C
−40°C
AVERAGE RON ()
VCOM (V)
VCC = 3 V
ICOM = 100 mA
NLAS4684
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0.1
0.12
0.14
0.16
0.18
0.2
0.22
0.24
0.26
0.0 1.0 2.0 3.0 4.0 5.0
+85°C
+25°C
−40°C
Figure 21. NC On−Resistance versus
COM Voltage
VCOM (V)
AVERAGE RON ()
VCC = 5 V
ICOM = 100 mA
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.0 1.0 2.0 3.0 4.0 5.0
+85°C
+25°C
−40°C
AVERAGE RON ()
Figure 22. NO On−Resistance versus
COM Voltage
VCOM (V)
VCC = 5 V
ICOM = 100 mA
Figure 23. NC Bandwidth and Phase Shift
versus Frequency
Figure 24. NO Bandwidth and Phase Shift
versus Frequency
Figure 25. NC Off Isolation and Crosstalk Figure 26. NO Off Isolation and Crosstalk
FREQUENCY (MHz)
BANDWIDTH (dB/Div)
0.01 100101.00.1
PHASE (Degrees)
0
−10
Bandwidth (On − Loss)
Phase Shift
(Degrees)
0.001
0
−1
VCC = 3.0 V
TA = 25°C
10
−10
FREQUENCY (MHz)
BANDWIDTH (dB/Div)
0.01 100101.00.1
PHASE (Degrees)
0
−10
Bandwidth (On − Loss)
Phase Shift
(Degrees)
0.001
0
−1
VCC = 3.0 V
TA = 25°C
10
−10
FREQUENCY (MHz)
0.01 100101.00.1
NC Off−Isolation
Crosstalk
0.001
VCC = 3.0 V
TA = 25°C
0
−10
−
100
FREQUENCY (MHz)
0.01 100101.00.1
NO Off−Isolation
Crosstalk
0.001
VCC = 3.0 V
TA = 25°C
0
−10
−100
NLAS4684
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11
ORDERING INFORMATION
Device Package Shipping†
NLAS4684FCT1 Microbump−10 3000 / Tape & Reel
NLAS4684FCT1G Microbump−10
(Pb−Free)
3000 / Tape & Reel
NLAS4684FCTCG Microbump−10
(Pb−Free)
3000 / Tape & Reel
NLAS4684MNR2 DFN10 3000 / Tape & Reel
NLAS4684MNR2G DFN10
(Pb−Free)
3000 / Tape & Reel
NLAS4684MR2 Micro10 4000 / Tape & Reel
NLAS4684MR2G Micro10
(Pb−Free)
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NLAS4684
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12
PACKAGE DIMENSIONS
Microbump−10
CASE 489AA−01
ISSUE A
SEATING
PLANE
0.10 C NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION:
MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4 X
DIM
A
MIN MAX
−−−
MILLIMETERS
A1
A2 0.280 0.380
D1.965 BSC
E
b0.250 0.350
e0.500 BSC
D1
1.000 BSC
E1
1.500 BSC
0.650
AB
PIN ONE
CORNER
A0.15 BC
0.05 C
0.075 C
10 X b
1234
C
B
A
0.10 C
A
A1
A2
C
0.210 0.270
1.465 BSC
E
D
E1
D1
e
e
NLAS4684
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PACKAGE DIMENSIONS
DFN10, 3 x 3mm, 0.5mm Pitch
CASE 485C−01
ISSUE A
10X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
15
10 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
B
A
0.15 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
REFERENCE
0.10 C
0.08 C
(A3)
C
10X
10X
0.10 C
0.05 C
A B
NOTE 3
K
10X
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 2.45 2.55
E3.00 BSC
E2 1.75 1.85
e0.50 BSC
L0.35 0.45
L1 0.00 0.03
DETAIL A
K0.19 TYP
2X
2X
L1
DETAIL A
Bottom View
(Optional)
ÉÉ
ÉÉ
ÉÉ
A1
A3
DETAIL B
Side View
(Optional)
EDGE OF PACKAGE
MOLD CMPD
EXPOSED Cu
DETAIL B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.1746
2.6016
1.8508
0.5000 PITCH
0.5651
10X
3.3048
0.3008
10X
DIMENSIONS: MILLIMETERS
NLAS4684
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14
PACKAGE DIMENSIONS
Micro10
CASE 846B−03
ISSUE D
S
B
M
0.08 (0.003) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.95 1.10 0.037 0.043
D0.20 0.30 0.008 0.012
G0.50 BSC 0.020 BSC
H0.05 0.15 0.002 0.006
J0.10 0.21 0.004 0.008
K4.75 5.05 0.187 0.199
L0.40 0.70 0.016 0.028
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846B−01 OBSOLETE. NEW STANDARD
846B−02
−B−
−A−
D
K
G
PIN 1 ID 8 PL
0.038 (0.0015)
−T−SEATING
PLANE
C
HJL
ǒmm
inchesǓ
SCALE 8:1
10X 10X
8X
1.04
0.041
0.32
0.0126
5.28
0.208
4.24
0.167
3.20
0.126
0.50
0.0196
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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