Precision Analog Microcontroller, 12-Bit
Analog I/O, ARM7TDMI MCU
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E
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FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 16 ADC channels1
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
Up to 4 DAC outputs available1
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
On-chip peripherals
UART, 2× I2C® and SPI serial I/O
Up to 40-pin GPIO port1
4× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
3-phase, 16-bit PWM generator1
Programmable logic array (PLA)
External memory interface, up to 512 kB1
Power
Specified for 3 V operation
Active mode: 11 mA @ 5 MHz, 40 mA @ 41.78 MHz
Packages and temperature range
From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP1
Fully specified for –40°C to +125°C operation
Tools
Low cost QuickStart™ development system
Full third-party support
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
FUNCTIONAL BLOCK DIAGRAM
04955-001
1MSPS
12-BI T ADC
DAC0
12-BIT
DAC
DAC1
12-BIT
DAC
DAC2
12-BIT
DAC
DAC3
12-BIT
DAC
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
3-PHASE
PWM
EXT. MEMORY
INTERFACE
ADuC7026
ADC0
XCLKI
XCLKO
RST
VREF
ADC11
MUX
TEMP
SENSOR
BAND GAP
REF
OSC
AND PLL
PSM
POR
CMP0
CMP1
CMPOUT
PLA
4 GENE RAL-
PURPO SE TI M E RS
2k × 32 SRAM
31k × 16 FLAS H/EE P ROM
SERIAL I/O
UART, SPI, I2C
GPIO
JTAG
ARM7T DMI-BAS ED MCU WI T H
ADDIT IO NAL PERIP HE RALS
Figure 1.
1 Depending on part model. See Ordering Guide for more information.
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 2 of 96
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Detailed Block Diagram .............................................................. 5
Specifications ..................................................................................... 6
Timing Specifications .................................................................. 9
Absolute Maximum Ratings .......................................................... 16
ESD Caution ................................................................................ 16
Pin Configurations and Function Descriptions ......................... 17
ADuC7019/ADuC7020/ADuC7021/ADuC7022 .................. 17
ADuC7024/ADuC7025 ............................................................. 21
ADuC7026/ADuC7027 ............................................................. 24
ADuC7028 ................................................................................... 27
ADuC7029 ................................................................................... 29
Typical Performance Characteristics ........................................... 31
Terminology .................................................................................... 34
ADC Specifications .................................................................... 34
DAC Specifications..................................................................... 34
Overview of the ARM7TDMI Core ............................................. 35
Thumb Mode (T) ........................................................................ 35
Long Multiply (M) ...................................................................... 35
EmbeddedICE (I) ....................................................................... 35
Exceptions ................................................................................... 35
ARM Registers ............................................................................ 35
Interrupt Latency ........................................................................ 36
Memory Organization ................................................................... 37
Memory Access ........................................................................... 37
Flash/EE Memory ....................................................................... 37
SRAM ........................................................................................... 37
Memory Mapped Registers ....................................................... 37
ADC Circuit Overview .................................................................. 41
Transfer Function ....................................................................... 41
Typical Operation ....................................................................... 42
MMRs Interface .......................................................................... 42
Converter Operation .................................................................. 44
Driving the Analog Inputs ........................................................ 45
Calibration................................................................................... 46
Temperature Sensor ................................................................... 46
Band Gap Reference ................................................................... 46
Nonvolatile Flash/EE Memory ..................................................... 47
Programming .............................................................................. 47
Security ........................................................................................ 48
Flash/EE Control Interface ....................................................... 48
Execution Time from SRAM and Flash/EE ............................ 50
Reset and Remap ........................................................................ 50
Other Analog Peripherals .............................................................. 52
DAC .............................................................................................. 52
Power Supply Monitor ............................................................... 53
Comparator ................................................................................. 53
Oscillator and PLL—Power Control ........................................ 54
Digital Peripherals .......................................................................... 57
3-Phase PWM ............................................................................. 57
Description of the PWM Block ................................................ 58
General-Purpose Input/Output................................................ 63
Serial Port Mux ........................................................................... 65
UART Serial Interface ................................................................ 65
Serial Peripheral Interface ......................................................... 69
I2C-Compatible Interfaces ......................................................... 71
Programmable Logic Array (PLA)........................................... 75
Processor Reference Peripherals ................................................... 78
Interrupt System ......................................................................... 78
Timers .......................................................................................... 79
External Memory Interfacing ................................................... 84
Hardware Design Considerations ................................................ 88
Power Supplies ............................................................................ 88
Grounding and Board Layout Recommendations ................. 89
Clock Oscillator .......................................................................... 89
Power-On Reset Operation ....................................................... 90
Typical System Configuration .................................................. 90
Development Tools......................................................................... 91
PC-Based Tools ........................................................................... 91
In-Circuit Serial Downloader ................................................... 91
Outline Dimensions ....................................................................... 92
Ordering Guide .......................................................................... 95
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 3 of 96
REVISION HISTORY
7/12—Rev. D to Rev. E
Changed SCLOCK to SCLK When Refering to SPI Clock,
SPIMISO to MISO when Refering to SPI MISO, SPIMOSI to
MOSI when Refering to SPI MOSI, and SPICSL to CS when
Refering to SPI Chip Select ............................................... Universal
Changes to Table 4, Table 5, and Figure 5 .................................... 11
Changes to Endnote 1 in Table 6 and Figure 6 ............................ 12
Changes to Table 7 and Figure 7 ................................................... 13
Changes to Table 8 and Figure 8 ................................................... 14
Changes to Table 9 and Figure 9 ................................................... 15
Changed EPAD Note in Figure 12 and Table 11 ......................... 18
Changed EPAD Note in Figure 13 and Table 12 ......................... 21
Changes to Bit 6 in Table 18 ........................................................... 43
Changes to Example Source Code (External Crystal Selection)
Section and Example Source Code (External Clock Selection)
Section ............................................................................................... 55
Changes to Serial Peripheral Interface Section ........................... 69
Changes to SPICON[10] and SPICON[9] Descriptions in
Table 123 ........................................................................................... 70
Changes to Timer Interval Down Equation and Added Timer
Interval Up Equation ...................................................................... 79
Added Hour:Minute:Second:1/128 Format Section ................... 80
Changes to Table 189 ...................................................................... 84
Removed CP-40-10 Package .......................................................... 92
Changes to Ordering Guide ........................................................... 96
5/11—Rev. C to Rev. D
Changes to Table 4 .......................................................................... 11
Changes to Table 105 ...................................................................... 67
Updated Outline Dimensions ........................................................ 91
Changes to Ordering Guide ........................................................... 94
12/09—Rev. B to Rev. C
Added ADuC7029 Part ..................................................... Universal
Added Table Numbers and Renumbered Tables ............... Universal
Changes to Figure Numbers ............................................. Universal
Changes to Table 1 ............................................................................ 6
Changes to Figure 3 .......................................................................... 9
Changes to Table 3 and Figure 4 ................................................... 10
Changes to Table 10 ........................................................................ 16
Changes to Figure 55 ...................................................................... 53
Changes to Serial Peripheral Interface Section ........................... 69
Changes to Table 137 ...................................................................... 73
Changes to Figure 71 and Figure 72 ............................................. 85
Changes to Figure 73 and Figure 74 ............................................. 86
Updated Outline Dimensions........................................................ 91
Changes to Ordering Guide ........................................................... 94
3/07—Rev. A to Rev. B
Added ADuC7028 Part ..................................................... Universal
Updated Format ................................................................. Universal
Changes to Figure 2 .......................................................................... 5
Changes to Table 1 ............................................................................ 6
Changes to ADuC7026/ADuC7027 Section ............................... 23
Changes to Figure 21 ...................................................................... 28
Changes to Figure 32 Caption ....................................................... 30
Changes to Table 14 ........................................................................ 35
Changes to ADC Circuit Overview Section ................................ 38
Changes to Programming Section ................................................ 44
Changes to Flash/EE Control Interface Section .......................... 45
Changes to Table 24 ........................................................................ 47
Changes to RSTCLR Register Section .......................................... 48
Changes to Figure 52 ...................................................................... 49
Changes to Figure 53 ...................................................................... 50
Changes to Comparator Section ................................................... 50
Changes to Oscillator and PLL—Power Control Section .......... 51
Changes to Digital Peripherals Section ........................................ 54
Changes to Interrupt System Section ........................................... 75
Changes to Timers Section ............................................................ 76
Changes to External Memory Interfacing Section ..................... 80
Added IOVDD Supply Sensitivity Section ..................................... 84
Changes to Ordering Guide ........................................................... 90
1/06—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 6
Added the Flash/EE Memory Reliability Section ....................... 43
Changes to Table 30 ........................................................................ 52
Changes to Serial Peripheral Interface ......................................... 66
Changes to Ordering Guide ........................................................... 90
10/05—Revision 0: Initial Version
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 4 of 96
GENERAL DESCRIPTION
The ADuC7019/20/21/22/24/25/26/27/28/29 are fully integrated,
1 MSPS, 12-bit data acquisition systems incorporating high
performance multichannel ADCs, 16-bit/32-bit MCUs, and
Flash®/EE memory on a single chip.
The ADC consists of up to 12 single-ended inputs. An additional
four inputs are available but are multiplexed with the four DAC
output pins. The four DAC outputs are available only on certain
models (ADuC7020, ADuC7026, ADuC7028, and ADuC7029).
However, in many cases where the DAC outputs are not present,
these pins can still be used as additional ADC inputs, giving a
maximum of 16 ADC input channels. The ADC can operate in
single-ended or differential input mode. The ADC input voltage
is 0 V to VREF. A low drift band gap reference, temperature sensor,
and voltage comparator complete the ADC peripheral set.
Depending on the part model, up to four buffered voltage
output DACs are available on-chip. The DAC output range is
programmable to one of three voltage ranges.
The devices operate from an on-chip oscillator and a PLL
generating an internal high frequency clock of 41.78 MHz
(UCLK). This clock is routed through a programmable clock
divider from which the MCU core clock operating frequency
is generated. The microcontroller core is an ARM7TDMI®,
16-bit/32-bit RISC machine, which offers up to 41 MIPS peak
performance. Eight kilobytes of SRAM and 62 kilobytes of
nonvolatile Flash/EE memory are provided on-chip. The
ARM7TDMI core views all memory and registers as a single
linear array.
On-chip factory firmware supports in-circuit serial download
via the UART or I2C serial interface port; nonintrusive emulation
is also supported via the JTAG interface. These features are
incorporated into a low cost QuickStart™ development system
supporting this MicroConverter® family.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. When
operating at 41.78 MHz, the power dissipation is typically
120 mW. The ADuC7019/20/21/22/24/25/26/27/28/29 are
available in a variety of memory models and packages (see
Ordering Guide).
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 5 of 96
DETAILED BLOCK DIAGRAM
04955-002
77
ADC0
78
ADC1
79
ADC2/CMP0
80
ADC3/CMP1
1
ADC4
2
ADC5
3
ADC6
4
ADC7
5
ADC8
6
ADC9
7
ADC10
76
ADC11
9
ADCNEG
20
BM/P0.0/CMP
OUT
/PLAI[7]/MS0
18
P4.6/AD14/PLAO[14]
19
P4.7/AD15/PLAO[15]
*SEE O RDERING G UIDE FOR
FEATURE AVAILABILITY ON
DIF FERE NT MO DE LS.
55
P4.0/AD8/PLAO[8]
56
P4.1/AD9/PLAO[9]
63
P4.2/AD10/PLAO[10]
64
P4.3/AD11/PLAO[11]
65
P4.4/AD12/PLAO[12]
66
P4.5/AD13/PLAO[13]
62
P1.0/T1/SPM0/PLAI[0]
61
P1.1/SPM1/PLAI[1]
60
P1.2/SPM2/PLAI[2]
59
P1.3/SPM3/PLAI[3]
58
P1.4/SPM4/PLAI[4]/IRQ2
57
P1.5/SPM5/PLAI[5]/IRQ3
52
P1.6/SPM6/PLAI[6]
14
TMS
15
TDI
23
TDO
22
TCK
21
P0.6/T1/MRST/PLAO[3]
49
P2.1/WS/PWM0
H
/PLAO[6]
50
P2.2/RS/PWM0
L
/PLAO[7]
17
P2.3/AE
33
P2.4/PWM0
H
/MS00
35
P2.5/PWM0
L
/MS1
36
P2.6/PWM1
H
/MS2
48
P2.7/PWM1
L
/MS3
24
P0.2/PWM2
L
/BHE
16
P0.1/PWM2
H
/BLE
34
P0.3/TRST/A16/ADC
BUSY
42
P2.0/SPM9/PLAO[5]/CONV
START
51
P1.7/SPM7/PLAO[0]
MUX
12-BIT
VOLTAGE
OUT PUT DAC BUF
10
DAC0*/ADC12
12-BIT
VOLTAGE
OUT PUT DAC BUF
11
DAC1*/ADC13
12-BIT
VOLTAGE
OUT PUT DAC BUF
12
DAC2*/ADC14
12-BIT
VOLTAGE
OUT PUT DAC BUF
13
DAC3*/ADC15
29
P3.0/AD0/PWM0
H
/PLAI[8]
30
P3.1/AD1/PWM0
L
/PLAI[9]
31
P3.2/AD2/PWM1
H
/PLAI[10]
32
P3.3/AD3/PWM1
L
/PLAI[11]
38
P3.4/AD4/PWM2
H
/PLAI[12]
39
P3.5/AD5/PWM2
L
/PLAI[13]
46
P3.6/AD6/PWM
TRIP
/PLAI[14]
47
P3.7/AD7/PWM
SYNC
/PLAI[15]
44
XCLKO
45
XCLKI
40
IRQ0/P0.4/PWM
TRIP
/PLAO[1]/MS1
41
IRQ1/P0.5/ADC
BUSY
/PLAO[2]/MS2
43
P0.7/ECLK/XCLK/SPM8/PLAO[4]
ADuC7026*
69
DAC
REF
70
DACGND
75
DACV
DD
37
RST
27
LV
DD
28
DGND
54
IOV
DD
25
IOGND
26
IOV
DD
53
IOGND
74
AV
DD
73
AV
DD
67
REFGND
71
AGND
72
AGND
8
GND
REF
3-PHASE
PWM
DAC
CONTROL
ARM7TDMI
MCU
CORE
62kB F LAS H/EE
(31k × 16 BI TS)
8192 BYT ES US ER RAM
(2k × 32 BI TS) WAKE-UP/
RTC TI MER
POW ER SUPPLY
MONITOR
PROG. CLOCK
DIVIDER
JTAG
EMULATOR
DOWNLOADER
PROG. LOGIC
ARRAY
SPI/I
2
C SERI AL
INTERFACE
SERIAL PORT M ULTIPLEXER
UART
SERI AL PORT POR INTERRUPT
CONTROLLER
12- BIT S AR
ADC 1M SPS ADC
CONTROL
PLL
OSC
68
V
REF
V
REF
BAND GAP
REFERENCE
CMP
OUT
/IRQ
MUX
DAC
TEMP
SENSOR
Figure 2.
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 6 of 96
SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2
ADC Power-Up Time 5 μs
DC Accuracy1, 2
Resolution 12 Bits
Integral Nonlinearity ±0.6 ±1.5 LSB 2.5 V internal reference
±1.0 LSB 1.0 V external reference
Differential Nonlinearity
3, 4
±0.5 +1/−0.9 LSB 2.5 V internal reference
+0.7/−0.6 LSB 1.0 V external reference
DC Code Distribution 1 LSB ADC input is a dc voltage
ENDPOINT ERRORS5
Offset Error ±1 ±2 LSB
Offset Error Match ±1 LSB
Gain Error
±2
±5
LSB
Gain Error Match ±1 LSB
DYNAMIC PERFORMANCE f
IN
= 10 kHz sine wave, f
SAMPLE
= 1 MSPS
Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components
Total Harmonic Distortion (THD) −78 dB
Peak Harmonic or Spurious Noise
(PHSN)
−75 dB
Channel-to-Channel Crosstalk
−80
dB
Measured on adjacent channels
ANALOG INPUT
Input Voltage Ranges
Differential Mode V
CM
6
± V
REF
/2 V
Single-Ended Mode 0 to V
REF
V
Leakage Current ±1 ±6 µA
Input Capacitance 20 pF During ADC acquisition
ON-CHIP VOLTAGE REFERENCE 0.47 µF from V
REF
to AGND
Output Voltage
2.5
V
Accuracy ±5 mV T
A
= 25°C
Reference Temperature Coefficient ±40 ppm/°C
Power Supply Rejection Ratio 75 dB
Output Impedance 70 Ω T
A
= 25°C
Internal V
REF
Power-On Time 1 ms
EXTERNAL REFERENCE INPUT
Input Voltage Range 0.625
AV
DD
V
DAC CHANNEL SPECIFICATIONS R
L
= 5 kΩ, C
L
= 100 pF
DC Accuracy
7
Resolution 12 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Offset Error
±15
mV
2.5 V internal reference
Gain Error8 ±1 %
Gain Error Mismatch 0.1 % % of full scale on DAC0
ANALOG OUTPUTS
Output Voltage Range_0 0 to DAC
REF
V DAC
REF
range: DACGND to DACV
DD
Output Voltage Range_1 0 to 2.5 V
Output Voltage Range_2 0 to DACV
DD
V
Output Impedance 2 Ω
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 7 of 96
Parameter Min Typ Max Unit Test Conditions/Comments
DAC AC CHARACTERISTICS
Voltage Output Settling Time 10 µs
Digital-to-Analog Glitch Energy ±20 nV-sec 1 LSB change at major carry (where maximum
number of bits simultaneously changes in the
DACxDAT register)
COMPARATOR
Input Offset Voltage ±15 mV
Input Bias Current 1 µA
Input Voltage Range AGND AV
DD
− 1.2 V
Input Capacitance 7 pF
Hysteresis
4, 6
2 15 mV Hysteresis turned on or off via the CMPHYST bit in
the CMPCON register
Response Time 3 µs 100 mV overdrive and configured with CMPRES = 11
TEMPERATURE SENSOR
Voltage Output at 25°C 780 mV
Voltage TC −1.3 mV/°C
Accuracy ±3 °C
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
2.79
V
Two selectable trip points
3.07 V
Power Supply Trip Point Accuracy ±2.5 % Of the selected nominal trip point voltage
POWER-ON-RESET 2.36 V
GLITCH IMMUNITY ON RESET PIN3 50 µs
WATCHDOG TIMER (WDT)
Timeout Period
0
512
sec
FLASH/EE MEMORY
Endurance
9
10,000 Cycles
Data Retention
10
20 Years T
J
= 85°C
DIGITAL INPUTS All digital inputs excluding XCLKI and XCLKO
Logic 1 Input Current ±0.2 ±1 µA V
IH
= IOV
DD
or V
IH
= 5 V
Logic 0 Input Current −40 −60 µA VIL = 0 V; except TDI on
ADuC7019/20/21/22/24/25/29
−80 −120 µA V
IL
= 0 V; TDI on ADuC7019/20/21/22/24/25/29
Input Capacitance 10 pF
LOGIC INPUTS
3
All logic inputs excluding XCLKI
V
INL
, Input Low Voltage 0.8 V
V
INH
, Input High Voltage 2.0 V
LOGIC OUTPUTS All digital outputs excluding XCLKO
V
OH
, Output High Voltage 2.4 V I
SOURCE
= 1.6 mA
V
OL
, Output Low Voltage11 0.4 V I
SINK
= 1.6 mA
CRYSTAL INPUTS XCLKI and XCLKO
Logic Inputs, XCLKI Only
V
INL
, Input Low Voltage 1.1 V
V
INH
, Input High Voltage 1.7 V
XCLKI Input Capacitance 20 pF
XCLKO Output Capacitance 20 pF
INTERNAL OSCILLATOR 32.768 kHz
±3 %
±24 % T
A
= 0°C to 85°C range
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 8 of 96
Parameter Min Typ Max Unit Test Conditions/Comments
MCU CLOCK RATE
From 32 kHz Internal Oscillator 326 kHz CD12 = 7
From 32 kHz External Crystal
41.78
MHz
CD
12
= 0
Using an External Clock 0.05 44 MHz T
A
= 85°C
0.05 41.78 MHz T
A
= 125°C
START-UP TIME Core clock = 41.78 MHz
At Power-On 130 ms
From Pause/Nap Mode 24 ns CD12 = 0
3.06 µs CD12 = 7
From Sleep Mode 1.58 ms
From Stop Mode
1.7
ms
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay 12 ns From input pin to output pin
Element Propagation Delay 2.5 ns
POWER REQUIREMENTS
13, 14
Power Supply Voltage Range
AV
DD
to AGND and IOV
DD
to IOGND 2.7 3.6 V
Analog Power Supply Currents
AVDD Current
200
µA
ADC in idle mode; all parts except ADuC7019
400 µA ADC in idle mode; ADuC7019 only
DACV
DD
Current
15
3 25 µA
Digital Power Supply Current
IOV
DD
Current in Normal Mode Code executing from Flash/EE
7 10 mA CD12 = 7
11 15 mA CD
12
= 3
40 45 mA CD
12
= 0 (41.78 MHz clock)
IOV
DD
Current in Pause Mode 25 30 mA CD12 = 0 (41.78 MHz clock)
IOV
DD
Current in Sleep Mode 250 400 µA T
A
= 85°C
600 1000 µA T
A
= 125°C
Additional Power Supply Currents
ADC 2 mA @ 1 MSPS
0.7 mA @ 62.5 kSPS
DAC 700 µA per DAC
ESD TESTS 2.5 V reference, T
A
= 25°C
HBM Passed Up To 4 kV
FCIDM Passed Up To 0.5 kV
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Apply to all ADC input channels.
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 49. Based on external ADC
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 DAC linearity is calculated using a reduced code range of 100 to 3995.
8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
9 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
11 Test carried out with a maximum of eight I/Os set to a low output level.
12 See the POWCON register.
13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
14 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
15 On the ADuC7019/20/21/22, this current must be added to the AVDD current.
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 9 of 96
TIMING SPECIFICATIONS
Table 2. External Memory Write Cycle
Parameter Min Typ Max Unit
CLK1 UCLK
tMS_AFTER_CLKH 0 4 ns
tADDR_AFTER_CLKH 4 8 ns
tAE_H_AFTER_MS ½ CLK
tAE (XMxPAR[14:12] + 1) × CLK
tHOLD_ADDR_AFTER_AE_L ½ CLK + (!XMxPAR[10]) × CLK
tHOLD_ADDR_BEFORE_WR_L (!XMxPAR[8]) × CLK
tWR_L_AFTER_AE_L ½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK
tDATA_AFTER_WR_L 8 12 ns
tWR (XMxPAR[7:4] + 1) × CLK
tWR_H_AFTER_CLKH 0 4 ns
tHOLD_DATA_AFTER_WR_H (!XMxPAR[8]) × CLK
tBEN_AFTER_AE_L ½ CLK
tRELEASE_MS_AFTER_WR_H (!XMxPAR[8] + 1) × CLK
1 See Table 78.
04955-052
CLK
CLK
tMS_AFTER_CLKH
tAE_H_AFTER_MS
tAE
tWR_L_AFTER_AE_L
MSx
AE
WS
RS
AD[16:1] FFFF 9ABC 5678 9ABE 1234
BLE
BHE
A16
tWR tWR_H_AFTER_CLKH
tHOLD_DATA_AFTER_WR_H
tHOLD_ADDR_AFTER_AE_L
tHOLD_ADDR_BEFORE_WR_L
tDATA_AFTER_WR_L
tBEN_AFTER_AE_L
tADDR_AFTER_CLKH
tRELEASE_MS_AFTER_WR_H
Figure 3. External Memory Write Cycle (See Table 78)
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 10 of 96
Table 3. External Memory Read Cycle
Parameter Min Typ Max Unit
CLK1 1/MD clock ns typ × (POWCON[2:0] + 1)
tMS_AFTER_CLKH 4 8 ns
tADDR_AFTER_CLKH 4 16 ns
tAE_H_AFTER_MS ½ CLK
tAE (XMxPAR[14:12] + 1) × CLK
tHOLD_ADDR_AFTER_AE_L ½ CLK + (! XMxPAR[10] ) × CLK
tRD_L_AFTER_AE_L ½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
tRD_H_AFTER_CLKH 0 4
tRD (XMxPAR[3:0] + 1) × CLK
tDATA_BEFORE_RD_H 16 ns
tDATA_AFTER_RD_H 8 + (! XMxPAR[9]) × CLK
tRELEASE_MS_AFTER_RD_H 1 × CLK
1 See Table 78.
04955-053
ECLK
MSx
AE
WS
RS
AD[16:1]
BHE
BLE
A16
FFFF 2348 XXXX CDEF XX 234A XX 89AB
CLK
t
AE_H_AFTER_MS
t
AE
t
HOLD_ADDR_AFTER_AE_L
t
RD_L_AFTER_AE_L
t
RD
t
RD_H_AFTER_CLKH
t
ADDR_AFTER_CLKH
t
RELEASE_MS_AFTER_RD_H
t
DATA_BEFORE_RD_H
t
DATA_AFTER_RD_H
t
MS_AFTER_CLKH
Figure 4. External Memory Read Cycle (See Table 78)
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 11 of 96
Table 4. I2C Timing in Fast Mode (400 kHz)
Slave Master
Parameter Description Min Max Typ Unit
tL SCL low pulse width1 200 1360 ns
tH SCL high pulse width1 100 1140 ns
tSHD Start condition hold time 300 ns
tDSU Data setup time 100 740 ns
tDHD Data hold time 0 400 ns
tRSU Setup time for repeated start 100 ns
tPSU Stop condition setup time 100 400 ns
tBUF Bus-free time between a stop condition and a start condition 1.3 s
tR Rise time for both SCL and SDA 300 200 ns
tF Fall time for both SCL and SDA 300 ns
tSUP Pulse width of spike suppressed 50 ns
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 57.
Table 5. I2C Timing in Standard Mode (100 kHz)
Slave Master
Parameter Description Min Max Typ Unit
tL SCL low pulse width1 4.7 μs
tH SCL high pulse width1 4.0 ns
tSHD Start condition hold time 4.0 μs
tDSU Data setup time 250 ns
tDHD Data hold time 0 3.45 μs
tRSU Setup time for repeated start 4.7 μs
tPSU Stop condition setup time 4.0 μs
tBUF Bus-free time between a stop condition and a start condition 4.7 μs
tR Rise time for both SCL and SDA 1 μs
tF Fall time for both SCL and SDA 300 ns
1 tHCLK depends on the clock divider or CD bits in the POWCON MMR. tHCLK = tUCLK/2CD; see Figure 57.
0
4955-054
SDA (I/O)
t
BUF
MSB LSB ACK MSB
1982–71
SCL (I)
PS
STOP
CONDITION START
CONDITION
S(R)
REPEATED
START
t
SUP
t
R
t
F
t
F
t
R
t
H
t
L
t
SUP
t
DSU
t
DHD
t
RSU
t
DHD
t
DSU
t
SHD
t
PSU
Figure 5. I2C Compatible Interface Timing
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 12 of 96
Table 6. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × tHCLK ns
tSH SCLK high pulse width1 (SPIDIV + 1) × tHCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge2 1 × tUCLK ns
tDHD Data input hold time after SCLK edge2 2 × tUCLK ns
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
1 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 57.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
0
4955-055
SCLK
(POL ARIT Y = 0)
SCLK
(POL ARIT Y = 1)
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
SH
t
SL
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
Figure 6. SPI Master Mode Timing (Phase Mode = 1)
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 13 of 96
Table 7. SPI Master Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width1 (SPIDIV + 1) × tHCLK ns
tSH SCLK high pulse width1 (SPIDIV + 1) × tHCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDOSU Data output setup before SCLK edge 75 ns
tDSU Data input setup time before SCLK edge2 1 × tUCLK ns
tDHD Data input hold time after SCLK edge2 2 × tUCLK ns
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
1 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 57.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
04955-056
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
MOSI MSB BITS 6 TO 1 LSB
MI S O MSB IN BITS 6 TO 1 LSB IN
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
Figure 7. SPI Master Mode Timing (Phase Mode = 0)
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 14 of 96
Table 8. SPI Slave Mode Timing (Phsae Mode = 1)
Parameter Description Min Typ Max Unit
tCS CS to SCLK edge1 (2 × tHCLK) + (2 × tUCLK) ns
tSL SCLK low pulse width2 (SPIDIV + 1) × tHCLK ns
tSH SCLK high pulse width2 (SPIDIV + 1) × tHCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge1 1 × tUCLK ns
tDHD Data input hold time after SCLK edge1 2 × tUCLK ns
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
tSFS CS high after SCLK edge 0 ns
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
2 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 57.
04955-057
SCLK
(POL ARIT Y = 0)
CS
SCLK
(POL ARIT Y = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO MSB BITS 6 TO 1 LSB
MOSI MSB IN BITS 6 TO 1 LSB IN
t
DHD
t
DSU
t
DAV
t
DR
t
DF
t
CS
Figure 8. SPI Slave Mode Timing (Phase Mode = 1)
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 15 of 96
Table 9. SPI Slave Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
tCS CS to SCLK edge1 (2 × tHCLK) + (2 × tUCLK) ns
tSL SCLK low pulse width2 (SPIDIV + 1) × tHCLK ns
tSH SCLK high pulse width2 (SPIDIV + 1) × tHCLK ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge1 1 × tUCLK ns
tDHD Data input hold time after SCLK edge1 2 × tUCLK ns
tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
tSR SCLK rise time 5 12.5 ns
tSF SCLK fall time 5 12.5 ns
tDOCS Data output valid after CS edge 25 ns
tSFS CS high after SCLK edge 0 ns
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
2 tHCLK depends on the clock divider or CD bits in the POWCONMMR. tHCLK = tUCLK/2CD; see Figure 57.
04955-058
SCLK
(POLARITY = 0)
CS
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO
MOSI MSB IN BITS 6 TO 1 LSB IN
t
DHD
t
DSU
MSB BIT S 6 TO 1 LSB
t
DOCS
t
DAV
t
DR
t
DF
t
CS
Figure 9. SPI Slave Mode Timing (Phase Mode = 0)
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 16 of 96
ABSOLUTE MAXIMUM RATINGS
AGND = REFGND = DACGND = GNDREF, TA = 25°C, unless
otherwise noted.
Table 10.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Parameter Rating
AV
DD
to IOV
DD
−0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
IOV
DD
to IOGND, AV
DD
to AGND −0.3 V to +6 V
Digital Input Voltage to IOGND −0.3 V to +5.3 V
Digital Output Voltage to IOGND −0.3 V to IOV
DD
+ 0.3 V
VREF to AGND
−0.3 V to AVDD + 0.3 V
Analog Inputs to AGND
−0.3 V to AV
DD
+ 0.3 V
Analog Outputs to AGND −0.3 V to AV
DD
+ 0.3 V
Operating Temperature Range, Industrial –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
θ
JA
Thermal Impedance
40-Lead LFCSP 26°C/W
49-Ball CSP_BGA 80°C/W
64-Lead LFCSP 24°C/W
64-Ball CSP_BGA 75°C/W
64-Lead LQFP 47°C/W
80-Lead LQFP 38°C/W
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec) 240°C
RoHS Compliant Assemblies
(20 sec to 40 sec)
260°C
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 17 of 96
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADuC7019/ADuC7020/ADuC7021/ADuC7022
04955-064
ADuC7019/
ADuC7020
TOP VI EW
(No t t o Scal e)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
ADC3/CMP1
ADC4
NOTES
1. THE EXPOSED PADDL E MUST BE L EF T UNCONNECTED.
GND
REF
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
TMS
TDI
BM/P0.0/CMP
OUT
/PLAI[7]
P1.3/SPM3/PLAI[3]
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P1.6/SPM6/PLAI[6]
P1.7/SPM7/PLAO[0]
XCLKI
XCLKO
P0.7/ECLK/XCLK/SPM8/PLAO[4]
P2.0/SPM9/PLAO[5]/CONV
START
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
P0.6/T1/MRST/PLAO[3]
TCK
TDO
IOGND
IOV
DD
LV
DD
DGND
P0.3/TRST/ADC
BUSY
RST
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
ADC2/CMP0
ADC1
ADC0
AV
DD
AGND
V
REF
P4.2/PLAO[10]
P1.0/T1/SPM0/PLAI[0]
P1.1/SPM1/PLAI[1]
P1.2/SPM2/PLAI[2]
40
39
38
37
36
35
34
33
32
31
Figure 10. 40-Lead LFCSP_VQ Pin Configuration (ADuC7019/ADuC7020)
04955-065
ADuC7021
TOP VI EW
(No t t o Scal e)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
ADC4
ADC5
ADC6
ADC7
GND
REF
DAC0/ADC12
DAC1/ADC13
TMS
TDI
BM/P0.0/CMP
OUT
/PLAI[7]
P1.3/SPM3/PLAI[3]
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P1.6/SPM6/PLAI[6]
P1.7/SPM7/PLAO[0]
XCLKI
XCLKO
P0.7/ECLK/XCLK/SPM8/PLAO[4]
P2.0/SPM9/PLAO[5]/CONV
START
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
P0.6/T1/MRST/PLAO[3]
TCK
TDO
IOGND
IOV
DD
LV
DD
DGND
P0.3/TRST/ADC
BUSY
RST
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
ADC3/CMP1
ADC2/CMP0
ADC1
ADC0
AV
DD
AGND
V
REF
P1.0/T1/SPM0/PLAI[0]
P1.1/SPM1/PLAI[1]
P1.2/SPM2/PLAI[2]
40
39
38
37
36
35
34
33
32
31
NOTES
1. THE EXPOSED PADDL E MUST BE L EF T UNCONNECTED.
Figure 11. 40-Lead LFCSP_VQ Pin Configuration (ADuC7021)
ADuC7019/20/21/22/24/25/26/27/28/29 Data Sheet
Rev. E | Page 18 of 96
04955-066
ADuC7022
TOP VI EW
(No t t o Scal e)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
ADC5
ADC6
ADC7
ADC8
ADC9
GND
REF
TMS
TDI
BM/P0.0/CMP
OUT
/PLAI[7]
P0.6/T1/MRST/PLAO[3]
P1.2/SPM2/PLAI[2]
P1.3/SPM3/PLAI[3]
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P1.6/SPM6/PLAI[6]
P1.7/SPM7/PLAO[0]
XCLKI
XCLKO
P0.7/ECLK/XCLK/SPM8/PLAO[4]
P2.0/SPM9/PLAO[5]/CONV
START
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
TCK
TDO
IOGND
IOV
DD
LV
DD
DGND
P0.3/TRST/ADC
BUSY
RST
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
ADC4
ADC3/CMP1
ADC2/CMP0
ADC1
ADC0
AV
DD
AGND
V
REF
P1.0/T1/SPM0/PLAI[0]
P1.1/SPM1/PLAI[1]
40
39
38
37
36
35
34
33
32
31
NOTES
1. THE EXPOSED PADDL E MUST BE S OLDERED AND EITHER CONNECTE D TO AGND O R L EFT FL OATING .
Figure 12. 40-Lead LFCSP_VQ Pin Configuration (ADuC7022)
Table 11. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No.
7019/7020 7021 7022 Mnemonic Description
38 37 36 ADC0 Single-Ended or Differential Analog Input 0.
39 38 37 ADC1 Single-Ended or Differential Analog Input 1.
40 39 38 ADC2/CMP0 Single-Ended or Differential Analog Input 2/Comparator Positive Input.
1 40 39 ADC3/CMP1 Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/
Comparator Negative Input.
2 1 40 ADC4 Single-Ended or Differential Analog Input 4.
‒ 2 1 ADC5 Single-Ended or Differential Analog Input 5.
‒ 3 2 ADC6 Single-Ended or Differential Analog Input 6.
‒ 4 3 ADC7 Single-Ended or Differential Analog Input 7.
‒ ‒ 4 ADC8 Single-Ended or Differential Analog Input 8.
‒ ‒ 5 ADC9 Single-Ended or Differential Analog Input 9.
3 5 6 GNDREF Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from IOGND and DGND.
4 6 ‒ DAC0/ADC12 DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.
5 7 ‒ DAC1/ADC13 DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.
6 ‒ ‒ DAC2/ADC14 DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.
7 ‒ ‒ DAC3/ADC15 DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor
must be connected between this pin and AGND/Single-Ended or
Differential Analog Input 15 (see Figure 43).
8 8 7 TMS Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOVDD. In some cases, an external
pull-up resistor (~100K) is also required to ensure that the part does not
enter an erroneous state.
9 9 8 TDI Test Data In, JTAG Test Port Input. Debug and download access.
Data Sheet ADuC7019/20/21/22/24/25/26/27/28/29
Rev. E | Page 19 of 96
Pin No.
7019/7020 7021 7022 Mnemonic Description
10 10 9 BM/P0.0/CMPOUT/PLAI[7] Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter
serial download mode if BM is low at reset and execute code if BM is
pulled high at reset through a 1 kΩ resistor/General-Purpose Input and
Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
11
11
10
P0.6/T1/MRST/PLAO[3]
Multifunction Pin. Driven low after reset. General-Purpose Output Port 0.6/
Timer1 Input/Power-On Reset Output/Programmable Logic Array Output
Element 3.
12 12 11 TCK Test Clock, JTAG Test Port Input. Debug and download access. This pin has
an internal pull-up resistor to IOVDD. In some cases an external pull-up
resistor (~100K) is also required to ensure that the part does not enter an
erroneous state.
13 13 12 TDO Test Data Out, JTAG Test Port Output. Debug and download access.
14 14 13 IOGND Ground for GPIO (see Table 78). Typically connected to DGND.
15 15 14 IOVDD 3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage
Regulator.
16 16 15 LVDD 2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 µF capacitor to DGND only.
17 17 16 DGND Ground for Core Logic.
18 18 17 P0.3/TRST/ADCBUSY General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/
ADC
BUSY
Signal Output.
19 19 18 RST Reset Input, Active Low.
20
20
19
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-
Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable
Logic Array Output Element 1.
21 21 20 IRQ1/P0.5/ADCBUSY/PLAO[2] Multifunction I/O Pin. External Interrupt Request 1, Active High/General-
Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable
Logic Array Output Element 2.
22 22 21 P2.0/SPM9/PLAO[5]/CONVSTART Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/
Programmable Logic Array Output Element 5/Start Conversion Input Signal
for ADC.
23 23 22 P0.7/ECLK/XCLK/SPM8/PLAO[4] Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/
Output for External Clock Signal/Input to the Internal Clock Generator
Circuits/UART/ Programmable Logic Array Output Element 4.
24 24 23 XCLKO Output from the Crystal Oscillator Inverter.
25 25 24 XCLKI Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits.
26 26 25 P1.7/SPM7/PLAO[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART,
SPI/Programmable Logic Array Output Element 0.
27 27 26 P1.6/SPM6/PLAI[6] Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART,
SPI/Programmable Logic Array Input Element 6.
28 28 27 P1.5/SPM5/PLAI[5]/IRQ3 Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART,
SPI/Programmable Logic Array Input Element 5/External Interrupt
Request 3, Active High.
29 29 28 P1.4/SPM4/PLAI[4]/IRQ2 Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART,
SPI/Programmable Logic Array Input Element 4/External Interrupt
Request 2, Active High.
30 30 29 P1.3/SPM3/PLAI[3] Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART,
I2C1/Programmable Logic Array Input Element 3.
31 31 30 P1.2/SPM2/PLAI[2] Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART,
I2C1/Programmable Logic Array Input Element 2.
32 32 31 P1.1/SPM1/PLAI[1] Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART,
I2C0/Programmable Logic Array Input Element 1.
33 33 32 P1.0/T1/SPM0/PLAI[0] Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/
Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0.
34 ‒ ‒ P4.2/PLAO[10] General-Purpose Input and Output Port 4.2/Programmable Logic Array
Output Element 10.