1
FEATURES
DESCRIPTION
APPLICATIONS
TYPICAL APPLICATION DIAGRAM
L2
SGND
TPS53124RGE
(QFN24)
DRVH2
VBST2
EN2
LL1
DRVL1
DRVH1
VBST1
EN1
VFB2
TEST1
VO2
VO1
VFB1
GND
TRIP2
PGND2
V5FILT
VREG5
TRIP1
PGND1
DRVL2
LL2
C3
3.3uH
C9
C1
VO2
1.8V
C5
0.1uF
Input Voltage
PGND
1.05 V
4.7uF
C4
C6
Q4
3.3uH
PGND
Q3
R4
R5 R2
R1
C2
0.1uF
Q1
Q2
PGND
SGND
VO1
C7
4.7 uF
C8
1 uF
R6 R3
24
22
23
19
20
21
13 14 15 16 17 18
8
9
10
11
12
7
123456
Power PAD
PGND
SGND
VIN
TEST2
4.7uF L1
TPS53124
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..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
Dual Synchronous Step-Down Controller For Low-Voltage Power Rails
2
High Efficiency, Low-Power ConsumptionD-Cap Mode Enables Fast Transient Response
The TPS53124 is a dual, Adaptive on-time DCAP™mode synchronous controller. The part enablesHigh Initial Reference Accuracy
system designers to cost effectively complete theLow Output Ripple
suite of digital TV power bus regulators with theWide Input Voltage Range: 4.5 V to 24 V
absolute lowest external component count and loweststandby consumption. The main control loop for theOutput Voltage Range: 0.76 V to 5.5 V
TPS53124 uses the D-CAP™ mode that optimizedLow-Side R
DS(on)
Loss-less Current Sensing
for low ESR output capacitors such as POSCAP orAdaptive Gate Drivers with Integrated Boost
SP-CAP promises fast transient response with noDiode
external compensation. The part provides aconvenient and efficient operation with conversionInternal 1.2-ms Voltage-Servo Soft Start
voltages from 4.5 V to 24 V and output voltage fromBuilt-In 5-V Linear Regulator
0.76 V to 5.5 V.
The TPS53124 is available in the 24-pin RGEpackage and in the 28-pin PW package and isDigital TV Power Supply
specified from -40 °C to 85 °C ambient temperatureNetworking Home Terminal
range.Digital STB
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DCAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
TSSOP-28 APPLICATION DIAGRAM
TPS53124PW
(TSSOP28)
LL1
DRVL1
DRVH1
VBST1
EN1
VFB2
VO2
VO1
VFB1
GND
TRIP2
NC
VREG 5
TRIP 1
PGND 1
C3
C1
4.7uF
L1
3.3uH
R4
R5
R2
R1
C2
0.1uF Q1
Q2
VO1
C7
4.7uF
C8
1uF
R3
R6
3
28
8
25
26
27
19
9 20
22
23
245
7
1
10
11
VIN
TEST2
L2
DRVH2
VBST2
EN2
PGND 2
DRVL 2
LL 2 3.3uH
VO2
C5
0.1uF
C4
C6
Q4
Q3
14 15
16
17
18
12
4.7uF
V5 FILT 21
13 NC
TEST1
6NC
2NC
VIN
VIN
4
C9
VIN
DRVH
TPS53124
SLUS825B FEBRUARY 2008 REVISED MAY 2008 .....................................................................................................................................................
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ORDERING INFORMATION
(1)
ORDERING PARTT
A
PACKAGE PINS OUTPUT SUPPLY ECO PLANNUMBER
Plastic quad TPS53124RGET 24 Tape and ReelFlat pack (QFN) TPS53124RGER 24 Tape and Reel
Green (RoHS & no-40 °C to 85 °C
Sb/Br)TSSOP TPS53124PWR 28 Tape and ReelTSSOP TPS53124PW 28 Tube
(1) All packaging options have Cu NIPDAU lead/ball finish.
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS53124
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..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
over operating free-air temperature range (unless otherwise noted)
PARAMETER VALUE UNIT
VIN,EN1,EN2 -0.3 to 26VBST1,VBST2 -0.3 to 32Input Voltage Range VVBST1,VBST2(wrt LLx) -0.3 to 6V5FILT,VFB1,VFB2,TRIP1,TRIP2,VO1,VO2, TEST1,TEST2 -0.3 to 6DRVH1, DRVH2 -1 to 32DRVH1, DRVH2 (wrt LLx) -0.3 to 6Output Voltage Range LL1,LL2 -2 to 26 VDRVL1,DRVL2,VREG5 -0.3 to 6PGND1, PGND2 -0.3 to 0.3Operating ambient temperature
-40 to 85range, T
A
°CStorage Temperature Range, T
STG
-55 to 150Junction Temperature Range, T
J
-40 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2 oz. trace and copper pad with solder)
DERATING FACTOR ABOVE T
APACKAGE T
A
<25 °C POWER RATING T
A
= 85 °C POWER RATING= 25 °C
24-pin QFN 2.33 W 23.3 mW/ °C 0.93 W28-pin TSSOP 0.78 W 7.8 mW/ °C 0.31 W
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
VIN 4.5 24Supply Input Voltage Range VV5FILT 4.5 5.5VBST1, VBST2 -0.1 30VBST1, VBST2 (wrt LLx) -0.1 5.5Input Voltage Range VFB1,VFB2,VO1,VO2 -0.1 5.5 VTRIP1,TRIP2 -0.1 0.3EN1,EN2 -0.1 24DRVH1,DRVH2 -0.1 30VBST1, VBST2 (wrt LLx) -0.1 5.5Output Voltage Range LL1,LL2 1.8 24 VDRVL1,DRVL2, VREG5 -0.1 5.5PGND1, PGND2 -0.1 0.1Operating Free-Air Temperature, T
A
-40 85
°COperating Junction Temperature, T
J
-40 125
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ELECTRICAL CHARACTERISTICS
TPS53124
SLUS825B FEBRUARY 2008 REVISED MAY 2008 .....................................................................................................................................................
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over operating free-air temperature range, , VIN = 12 V, (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Supply Current
VIN current, T
A
= 25 °C, VREG5 tied to V5FLT,I
IN
VIN supply current EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.8 V, LL1 = 450 800
µALL2 = 0.5 VI
VINSDN
VIN shutdown current VIN current, T
A
= 25 °C, no load, EN1 = EN2 = 0 V 10
VFB Voltage and Discharge Resistance
Bandgap initial regulationV
BG
T
A
= 25 °C -1% 1%accuracy
T
A
= 25 °C 755 765 775VFB threshold voltage    V
VFBTH
mV   
T
A
= -40 °C to 85 °C 752 778I
VFB
VFB input current VFBx = 0.8 V, T
A
= 25 °C -0.01 +/-0.1 µAR
DISCHG
V
O
discharge resistance ENx = 0 V, VOx = 0.5 V,T
A
= 25 °C 40 80
VREG5 Output
V
VREG5
VREG5 output voltage T
A
= 25 °C ,5.5 V < VIN < 24 V, 0 < I
VREG5
< 10 mA 4.8 5 5.2 VV
LN5
     Line regulation 5.5 V < VIN < 24 V, I
VREG5
= 10 mA 20
mVV
LD5
     Load regulation 1 mA < I
VREG5
< 10 mA 40I
VREG5
Output current VIN = 5.5 V, VREG5 = 4.0 V, T
A
= 25 °C 170 mA
Output: N-Channel MOSFET Gate Drivers
Source, I
DRVHx
= -100 mA 5.5 11R
DRVH
DRVH resistance Sink, I
DRVHx
= 100 mA 2.5 5Source, I
DRVLx
= - 100 mA 4 8R
DRVL
DRVL resistance Sink, I
DRVLx
= 100 mA 2 4DRVHx-low to DRVLx-on 20 50 80T
D
Dead time nsDRVLx-low to DRVHx-on 20 40 80
Internal BST Diode
V
FBST
Forward voltage V
VREG5-VBSTx
, I
F
= 10 mA, T
A
= 25 °C 0.7 0.8 0.9 VI
VBSTLK
VBST leakage current VBST = 29 V, LL = 24 V, T
A
= 25 °C 0.1 1 µA
ON-Time Timer Control
T
ON1
CH1 ON time LL1 = 12 V, VO1 = 1.5 V 390T
ON2
CH2 ON time LL2 = 12 V, VO2 = 1.05 V 210
nsT
ON(min)
CH2 ON time LL2 = 12 V, VO2 = 0.76 V 160T
OFF(min)
CH1/CH2 min OFF time LL = 0.7 V T
A
= 25 °C, VFB = 0.7 V 390
Soft Start
T
SS
Internal SS time Internal soft start VFB = 0.735 V 0.85 1.2 1.4 ms
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TPS53124
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..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range, , VIN = 12 V, (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
UVLO
Wake up 3.7 4 4.3V
UV5VFILT
V5FILT UVLO threshold VHysteresis 0.2 0.3 0.4
LOGIC Threshold
V
ENH
ENx H-level input voltage EN 1/2 2
VV
ENL
ENx L-level input voltage EN 1/2 0.3
Current Sense
I
TRIP
TRIP source current VTRIPx = 0.1 V, T
A
= 25 °C 8.5 10 11.5 µATC
ITRIP
I
TRIP
temperature coefficient On the basis of 25 °C 4000 ppm/ °C(V
TRIPx-GND
- V
PGNDx-LLx
) voltage,V
TRIPx-GND
= 60
-10 0 10mV, T
A
= 25 °CV
OCL(off)
OCP compensation offset
(V
TRIPx-GND
- V
PGNDx-LLx
) voltage, V
TRIPx-GND
= 60
-15 15 mVmVCurrent limit threshold settingV
R(trip)
V
TRIPx-GND
voltage 30 200range
Output Undervoltage and Overvoltage Protection
V
OVP
Output OVP trip threshold OVP detect 110% 115% 120%T
OVPDEL
Output OVP prop delay 1.5 µsUVP detect 65% 70% 75%V
UVP
Output UVP trip threshold
Hysteresis (recovery < 20 µs) 10%T
UVPDEL
Output UVP delay 17 30 40 µsT
UVPEN
Output UVP enable delay 1.2 2 2.5 ms
Thermal Shutdown
Shutdown temperature
(1)
150T
SDN
Thermal shutdown threshold °CHysteresis
(1)
20
(1) Ensured by design. Not production tested.
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DEVICE INFORMATION
TPS53124
SLUS825B FEBRUARY 2008 REVISED MAY 2008 .....................................................................................................................................................
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TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME GFN24 TSSOP28
Supply input for high-side NFET driver (boost terminal). ConnectVBST1, capacitor from this pin to respective LL terminals. An internal PN diode is23, 8 1, 14 IVBST2 connected between VREG5 to each of these pins. User can add externalschottky diode if forward drop is critical to drive the NFET.EN1, EN2 24, 7 3, 12 I Channel 1 and Channel 2 enable pins.Output connections to SMPS. These terminals serve ON-time adjustment,VO1, VO2 1, 6 4, 11 I
output discharge.VFB1, VFB2 2, 5 5, 10 I SMPS feedback inputs. Connect with feedback resistor divider.GND 3 7 I Signal ground pin.High-side NFET driver outputs. LL referenced floating drivers. The gateDRVH1,
22, 9 28, 15 O drive voltage is defined by the voltage across VBST to LL node flyingDRVH2
capacitor.
Switch-node connections for high-side drivers. Also serve as input toLL1, LL2 21, 10 27, 16 I/O
current comparators.DRVL1, Synchronous NFET driver outputs. PGND referenced drivers. The gate20, 11 26, 17 ODRVL2 drive voltage is defined by VREG5 voltage.Ground returns for DRVL1 and DRVL2. Also serve as input of currentPGND1,
19, 12 25, 18 I/O comparators. Connect PGND1, PGND2 and GND strongly together nearPGND2
the device.
Over-current trip point set input. Connect resistor from this pin to GND toTRIP1, set threshold for synchronous R
DS(on)
sense. Voltage across this pin and18, 13 24, 19 ITRIP2 GND is compared to voltage across PGND and LL at over currentcomparator.VIN 17 23 I Supply Input for 5-V linear regulator.5-V supply input for the entire control circuit except the NFET drivers.V5FILT 15 21 I Connect capacitor (typical 1 µF) from GND to V5FILT. V5FILT isconnected to VREG5 via internal resistor.5-V power supply output. VREG5 is connected to V5FILT via internalVREG5 16 20 O
resistor.TEST1,
4, 14 8, 20 I/O Used for test only. Pin should be connected to GNDTEST2
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Pinout Diagrams
TRIP1
VIN
VO1
VFB1
GND
TEST1
VREG5
V5FILT
TEST2
TRIP2
VFB2
VO2
EN2 EN1
VBST1
DRVH1
LL1
DRVL1
PGND1
VBST2
DRVH2
LL2
DRVL2
PGND2
16
15
14
13
18
17
1
2
3
4
5
6
9
10
11
12
7
823
20
24
22
21
19
VBST1
NC
EN1
VO1
VFB1
NC
GND
TEST1
NC
VFB2
VO2
EN2
NC
VBST2
DRVH1
LL1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
TEST2
TRIP2
PGND2
DRVL2
LL2
DRVH2
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T P S 5 3 1 2 4
15
TPS53124
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..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
QFN Package (Top View) TSSOP Package (Top View)
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TPS53124
SLUS825B FEBRUARY 2008 REVISED MAY 2008 .....................................................................................................................................................
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Functional Block Diagram
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DETAILED DESCRIPTION
PWM Operation
Low-Side Driver
High-Side Driver
PWM Frequency and Adaptive On-Time Control
Soft Start
Output Discharge Control
TPS53124
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..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
The main control loop of the switching mode power supply (SMPS) is designed as an adaptive on-time pulsewidth modulation (PWM) controller. It supports a proprietary D-CAP™ Mode. D-CAP™ Mode uses internalcompensation circuit and is suitable for low external component count configuration with appropriate amount ofESR at the output capacitor(s). The output ripple bottom voltage is monitored at a feedback point voltage.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. ThisMOSFET is turned off, or becomes OFF state, after internal one-shot timer expires. This one shot is determinedby the converter s input voltage ,VIN, and the output voltage ,VOUT, to keep frequency fairly constant over theinput voltage range, hence it is called adaptive on-time control. The high-side MOSFET is turned on again whenfeedback information indicates insufficient output voltage. Repeating operation in this manner, the controllerregulates the output voltage.
The low-side driver is designed to drive high current low R
DS(on)
N-channel MOSFET(s). The drive capability isrepresented by its internal resistance. A dead time to prevent shoot through is internally generated betweenhigh-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. 5-V biasvoltage is delivered from internal regulator VREG5 output. The instantaneous drive current is supplied by aninput capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge atV
GS
= 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 Vmakes the driving power which need to be dissipated from TPS53124 package.
The high-side driver is designed to drive high current, low R
DS(on)
N-channel MOSFET(s). When configured as afloating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated bythe gate charge at V
GS
= 5 V times switching frequency. The instantaneous drive current is supplied by the flyingcapacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance.
TPS53124 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into theon-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to theoutput voltage so that the duty ratio will be kept as VOUT/VIN technically with the same cycle time.
The TPS53124 has an internal, 1.2 ms, voltage servo softstart for each channel. When the ENx pin becomeshigh, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of theoutput voltage is maintained during start up. As TPS53124 shares one DAC with both channels, if ENx pin is setto high while another channel is starting up, soft start is postponed until another channel soft start hascompleted. If both of EN1 and EN2 are set high at a same time, both channels start up at same time.
TPS53124 discharges the output when ENx is low, or the controller is turned off by the protection functions(OVP, UVP, UVLO, and thermal shutdown). TPS53124 discharges outputs using an internal 40- MOSFETwhich is connected to VOx and PGNDx. The external low-side MOSFET is not turned on for the output dischargeoperation to avoid the possibility of causing negative voltage at the output.
This discharge ensures that, on start, the regulated voltage always start from zero volts.
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Current Protection
10
TRIP TRIP
V ( mV ) R ( k ) ( A )m= W ´
(1)
1
2 2
IN OUT OUT
TRIP RIPPLE TRIP
OCP
DS( on ) DS ( on ) IN
(V V ) V
V I V
IR R L f V
- ´
= + = + ´
´ ´
(2)
Over/Under Voltage Protection
UVLO Protection
Thermal Shutdown
TPS53124
SLUS825B FEBRUARY 2008 REVISED MAY 2008 .....................................................................................................................................................
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TPS53124 has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state during the inductor current is larger than the over-current trip level.In order to provide both good accuracy and cost effective solution, TPS53124 supports temperaturecompensated MOSFET R
DS(on)
sensing. TRIPx pin should be connected to GND through the trip voltage settingresistor, R
TRIP
. TRIPx terminal sources 10- µA I
TRIP
current at the ambient temperature and the trip level is set tothe OCL trip voltage V
TRIP
as below:
The trip level should be in the range of 30 mV to 200 mV over all operational temperature. The inductor current ismonitored by the voltage between PGNDx pin and LLx pin. I
TRIP
has 4000ppm/ °C temperature slope tocompensate the temperature dependency of the R
DS(on)
. PGNDx is used as the positive current sensing node sothat PGNDx should be connected to the source terminal of the bottom MOSFET.
As the comparison is done during the OFF state, V
TRIP
sets valley level of the inductor current. Thus, the loadcurrent at over-current threshold, I
OCP
, can be calculated as follows:
In an over-current condition, the current to the load exceeds the current to the output capacitor; thus the outputvoltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold andshutdown.
TPS53124 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedbackvoltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuitlatches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goeshigh and an internal UVP delay counter begins counting. After 30 µs, TPS53124 latches OFF both top andbottom MOSFET drivers, and shut off both drivers of another channel. This function is enabled approximately 2.0ms.
TPS53124 has V5FILT Under Voltage Lock Out protection (UVLO). When the V5FILT voltage is lower thanUVLO threshold voltage TPS53124 is shut off. This is non-latch protection.
TPS53124 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150 °C),the switchers will be shut off as both DRVH and DRVL at low, the output discharge function enabled. ThenTPS53124 is shut off. This is non-latch protection.
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Typical Characteristics
-50 0 150
TJJunction Temperature - °C
0
100
200
300
500
600
50 100
IIN - Supply Current - mA
VIN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
400
-50 0 150
TJJunction Temperature - °C
0
2
4
6
8
50 100
IVIN(SDN)- Shutdown Current - mA
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
-50 0 150
TJJunction Temperature - °C
0
5
10
15
20
50 100
ITRIP- Source Current - mA
ITRIP SOURCE CURRENT
vs
JUNCTION TEMPERATURE
0 5 25
VIN - Input Voltage - V
0
100
200
400
500
10 20
fSW - Switching Frequency - kHz
SWITCHING FREQUENCY IO= 1A
vs
JUNCTION TEMPERATURE
15
300
CH1
CH2
TPS53124
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..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
Figure 1. Figure 2.
Figure 3. Figure 4.
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0 1.0 4.0
IOUT - Output Current - A
0
100
200
400
500
2.0 3.0
fSW - Switching Frequency - kHz
SWITCHING FREQUENCY IO= 1A
vs
OUTPUT CURRENT
300
CH1
CH2
0 1.0 4.0
IOUT1 - Output Current - A
1000
1025
1050
1075
1100
2.0 3.0
VOUT1 - Output Voltage - V
1.05-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VI= 5.5 V
VI= 12 V
VI= 24 V
0 1.0 4.0
IOUT2 - Output Current - A
1.725
1.750
1.775
1.800
1.875
2.0 3.0
VOUT2 - Output Voltage - V
1.8-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VI= 5.5 V VI= 12 V
VI= 24 V
1.825
1.850
0 5 25
VIN - Input Voltage - V
1000
1025
1050
1075
1100
15 20
VOUT1 - Output Voltage - V
1.05-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
IO= 0 A
IO= 2 A
10
TPS53124
SLUS825B FEBRUARY 2008 REVISED MAY 2008 .....................................................................................................................................................
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Typical Characteristics (continued)
Figure 5. Figure 6.
Figure 7. Figure 8.
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1.8-V LOAD TRANSIENT RESPONSE
t - Time - 20 ms/div
VOUT2
(100 mV/div)
IOUT2
(2 A/div)
1.725
1.750
1.775
1.800
1.875
VOUT2 - Output Voltage - V
1.8-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.825
1.850
0 5 25
VIN - Input Voltage - V
15 2010
IO= 0 A
IO= 2 A
TPS53124
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..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
Typical Characteristics (continued)
Figure 9. Figure 10.
Figure 11.
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APPLICATION INFORMATION
Loop Compensation and External Parts Selection
Ref
R1
R2
Voltage Devider
Switching Modulator
PWM Logic
control
Driver
DRVH
DRVL
Vin
Lx
ESR
Co
Vc
1
2 3
SW
O
O
f
fESR Cp
= £
´ ´
(3)
[ ]
10
OUT
RIPPLE
FBx
V
V mV
V
= ´
(4)
TPS53124
SLUS825B FEBRUARY 2008 REVISED MAY 2008 .....................................................................................................................................................
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A buck converter system using D-CAP™ Mode can be simplified as below.
Figure 12. Simplifying the Modulator
The output voltage is compared with internal reference voltage after divider resistors,R1 and R2. The PWMcomparator determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enoughto keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The dcoutput voltage may have line regulation due to ripple amplitude that slightly increases as the input voltageincrease.
For the loop stability, the 0dB frequency, f
0
, defined below need to be lower than 1/3 of the switching frequency.
Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external componentsconfiguration and extremely short response time, a sufficient amount of feedback signal needs to be provided byexternal circuit to reduce jitter level. This is due to not employing an error amplifier in the loop. The requiredsignal level is approximately 10 mV at the comparing point(VFB terminal). This gives Vripples at the output nodebecomes Equation 4 . The output capacitor s ESR should meet this requirement.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS53124
( ) ( )
1 3
IN (max) OUT OUT IN(max) OUT OUT
IND( ripple ) OUT (max)
IN (max) IN (max)
Lf f
V V V V V V
V V
I I
- ´ - ´
= × = ´
´ ´
(5)
1IN (max) OUT OUT
TRIP
IND( peak )
DS ( on ) IN (max)
(V V ) V
V
R L f V
I- ´
= + ´
´
(6)
TPS53124
www.ti.com
..................................................................................................................................................... SLUS825B FEBRUARY 2008 REVISED MAY 2008
The external components selection is much simpler in D-CAP™ Mode.1. Choose inductor.
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximumoutput current. Larger ripple current increases output ripple voltage, improves S/N ratio and contributes to astable operation.
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peakinductor current before saturation. The peak inductor current can be estimated as follows.
2. Choose output capacitor.
Polymer aluminum capacitor, organic semiconductor capacitor or specialty polymer capacitor arerecommended. Determine ESR to meet required ripple voltage indicated previously.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS53124
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53124PWR TSSOP PW 28 2000 330.0 16.4 7.1 10.4 1.6 12.0 16.0 Q1
TPS53124RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS53124RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS53124RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS53124RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53124PWR TSSOP PW 28 2000 367.0 367.0 38.0
TPS53124RGER VQFN RGE 24 3000 367.0 367.0 35.0
TPS53124RGER VQFN RGE 24 3000 367.0 367.0 35.0
TPS53124RGET VQFN RGE 24 250 210.0 185.0 35.0
TPS53124RGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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