© Semiconductor Components Industries, LLC, 2010
October, 2010 − Rev. 2
1Publication Order Number:
NCV8668/D
NCV8668
Very Low Iq 150 mA LDO
Regulator with Window
Watchdog, Enable and
Reset
The NCV8668 is 150 mA LDO regulator with integrated window
watchdog and reset functions dedicated for microprocessor
applications. Its robustness allows NCV8668 to be used in severe
automotive environments. Very low quiescent current as low as 38 mA
typical makes it suitable for applications permanently connected to
battery requiring very low quiescent current with or without load. The
Enable function can be used for further decrease of quiescent current
down to 1 mA.
The NCV8668 contains protection functions as current limit and
thermal shutdown.
Features
•Output Voltage Options: 3.3 V and 5 V
•Output Voltage Accuracy: $1.5% (TJ = 25°C to 125°C)
•Output Current up to 150 mA
•Very Low Quiescent Current: Typ 38 mA (max 43 mA)
•Very Low Dropout Voltage
•Enable Function
•Microprocessor Compatible Control Functions:
♦Reset with Adjustable Power−on Delay
♦Window Watchdog
•Wide Input Voltage Operation Range: up to 40 V
•Protection Features:
♦Current Limitation
♦Reverse Output Current
♦Thermal Shutdown
•These are Pb−Free Devices
Typical Applications
•Body Control Module
•Instruments and Clusters
•Occupant Protection and Comfort
•Powertrain
VBAT
NCV8668
Vin Vout
GND
Vout
Cin
0. 1 mF
RO
WDI
WM1
WM2
Microprocessor
VDD
RESET
I/O
I/O
I/O
Cout
2.2 mF
EN
ON
OFF
Figure 1. Application Schematic
SOIC−14
CASE 751A
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
ZZ = Timing, Reset Threshold,
Watchdog Control Options*
XX,X = Voltage Options
= 5 V (XX = 50, X = 5)
= 3.3 V (XX = 33, X = 3)
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
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1
14
V8668ZZXXG
AWLYWW
1
14
SOIC−8
D SUFFIX
CASE 751A
1
8
668ZZX
ALYW
G
1
8
SOIC−8 EP
CASE 751AC
1
8
1
8
668ZZX
AYWWG
G
*See APPLICATION INFORMATION Section.
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Driver with
Current
Limit
Thermal
Shutdown Vref
Vout
GND
RESET
GENERATOR
and
WINDOW
WATCHDOG
Vin
RO
WDI
WM1
WM2
*
* 5 V OPTION ONLY
Enable
EN
Figure 2. Simplified Block Diagram
WDI
RO
Vout
GND
WM 2
WM 1
GND
GND GND
GND
114
GND
GND Vin
EN
SOIC−14
WM 2
WM 1
GND
RO EN
Vin
Vout
WDI
18
SOIC−8
WM 2
WM 1
GND
RO EN
Vin
Vout
WDI
18
SOIC−8 EP
Figure 3. Pin Connections
(Top View)
PIN FUNCTION DESCRIPTION
Pin No.
SOIC−14
Pin No.
SOIC−8
Pin No.
SOIC−8 EP
Pin
Name Description
1 1 1 RO Reset Output. 30 kW internal Pull−Up resistor connected to Vout. (Open Drain
output for 2.5 V, 2.6 V, and 3.3 V voltage options) RO goes Low when Vout
drops by more than 7% from nominal.
2, 3, 4, 5, 10,
11, 12
2 2 GND Power Supply Ground.
For SOIC−14
− connect pin 2 and 3 to GND
− connect pin 4−5 and 10−12 to heatsink area with GND potential
6 3 3 WM2 Watchdog Mode Bit 2; Watchdog and Reset mode selection. Connect to Vout
or GND.
7 4 4 WM1 Watchdog Mode Bit 1; Watchdog and Reset mode selection. Connect to Vout
or GND.
8 5 5 WDI Watchdog Input; Trigger Input for Watchdog pulses. When not used, connect
to Vout or GND.
9 6 6 Vout Regulated Output Voltage. Connect 2.2 mF capacitor with ESR < 100 W to
ground.
13 7 7 Vin Positive Power Supply Input. Connect 0.1 mF capacitor to ground.
14 8 8 EN Enable Input; low level disables the IC.
EPAD GND Exposed Pad is Connected to Ground
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ABSOLUTE MAXIMUM RATINGS
Rating Symbol Min Max Unit
Input Voltage (Note 1)
DC
Transient, t < 100 ms
Vin −0.3
−
40
45
V
Input Current Iin −5−mA
Output Voltage (Note 2) Vout −0.3 5.5 V
Output Current Iout −3Current Limited mA
Enable Input Voltage Range
DC
Transient, t < 100 ms
VEN −0.3
−
40
45
V
Enable Input Current Range IEN −1 1 mA
Reset Output Voltage (Note 3) VRO −0.3 5.5 V
Reset Output Current IRO −3 3 mA
Watchdog Input Voltage VWDI −0.3 5.5 V
Watchdog Mode 1 Voltage VWM1 −0.3 5.5 V
Watchdog Mode 1 Current IWM1 −5 5 mA
Watchdog Mode 2 Voltage VWM2 −0.3 5.5 V
Watchdog Mode 2 Current IWM2 −5 5 mA
Junction Temperature TJ−40 150 °C
Storage Temperature TSTG −55 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. The Output voltage must not exceed the Input voltage.
3. The Reset Output voltage must not exceed the Output voltage.
ESD CAPABILITY (Note 4)
Rating Symbol Min Max Unit
ESD Capability, Human Body Model ESDHBM −2 2 kV
ESD Capability, Machine Model ESDMM −200 200 V
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
LEAD SOLDERING TEMPERATURE AND MSL (Note 5)
Rating Symbol Min Max Unit
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 5)
TSLD −265 peak °C
Moisture Sensitivity Level (SOIC−14, SOIC−8)
(SOIC−8EP)
MSL 1
2
−
5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
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THERMAL CHARACTERISTICS (Note 6)
Rating Symbol Value Unit
Thermal Characteristics, SOIC−14 (Note 6)
Thermal Resistance, Junction−to−Air (Note 7)
Thermal Reference, Junction−to−Lead4 (Note 7)
RqJA
RYJL
95
18.2
°C/W
Thermal Characteristics, SOIC−8 (Note 6)
Thermal Resistance, Junction−to−Air (Note 7)
Thermal Reference, Junction−to−Lead4 (Note 7)
RqJA
RYJL
132
49.2
°C/W
Thermal Characteristics, SOIC−8 EP (Note 6)
Thermal Resistance, Junction−to−Air (Note 7)
Thermal Reference, Junction−to−Lead4 (Note 7)
Thermal Reference, Junction−to−Pad (Note 7)
RqJA
RYJL4
RYJPad
80
28.5
14.8
°C/W
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
7. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
RECOMMENDED OPERATING RANGES (Note 8)
Rating Symbol Min Max Unit
Input Voltage (Note 9) Vin 4.5 40 V
Junction Temperature TJ−40 150 °C
8. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
9. Minimum Vin = 4.5 V or (Vout + VDO), whichever is higher.
ELECTRICAL CHARACTERISTICS
Vin = 13.2 V, Cin = 0.1 mF, Cout = 2.2 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted.
(Notes 10 and 11)
Parameter Test Conditions Symbol Min Typ Max Unit
REGULATOR OUTPUT
Output Voltage (Accuracy %)
3.3 V
5.0 V
TJ = 25°C to 125°C
Vin = 4.5 V to 16 V, Iout = 0.1 mA to 100 mA
Vin = 5.5 V to 16 V, Iout = 0.1 mA to 100 mA
Vout 3.2505
4.925
(−1.5%)
3.3
5.0
3.3495
5.075
(+1.5%)
V
Output Voltage (Accuracy %)
3.3 V
5.0 V
Vin = 4.5 V to 40 V, Iout = 0.1 mA to 100 mA
Vin = 4.5 V to 16 V, Iout = 0.1 mA to 150 mA
Vin = 5.55 V to 40 V, Iout = 0.1 mA to 100 mA
Vin = 5.7 V to 16 V, Iout = 0.1 mA to 150 mA
Vout 3.234
3.234
4.9
4.9
(−2%)
3.3
3.3
5.0
5.0
3.366
3.366
5.1
5.1
(+2%)
V
Output Voltage (Accuracy %)
3.3 V
5.0 V
TJ = −40°C to 125°C
Vin = 4.5 V to 28 V, Iout = 0 mA
Vin = 5.5 V to 28 V, Iout = 0 mA
Vout 3.234
4.9
(−2%)
3.3
5.0
3.366
5.1
(+2%)
V
Line Regulation
5.0 V
3.3 V
Vin = 5.5 V to 28 V, Iout = 5 mA
Vin = 4.5 V to 28 V, Iout = 5 mA
Regline −20 0 20 mV
Load Regulation Iout = 0.1 mA to 150 mA Regload −40 10 40 mV
Dropout Voltage (Note 12)
5.0 V Iout = 100 mA
Iout = 150 mA
VDO −
−
225
300
450
600
mV
Output Capacitor for Stability (Note 13)
Iout = 5 mA to 150 mA
Iout = 0 mA to 5 mA
Cout
ESR
2.2
−
1
−
−
−
−
100
100
mF
W
W
10.Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
12.Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. If Vout < 5 V, then VDO = Vin – Vout. Maximum dro-
pout voltage value is limited by minimum input voltage Vin = 4.5 V recommended for guaranteed operation at maximum output current.
13.Values based on design and/or characterization.
14.Recommended for typical trigger time. TWD = tCW + 1/2 * tOW
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ELECTRICAL CHARACTERISTICS
Vin = 13.2 V, Cin = 0.1 mF, Cout = 2.2 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted.
(Notes 10 and 11)
Parameter UnitMaxTypMinSymbolTest Conditions
Disable and Quiescent Current
Disable Current VEN = 0 V,TJ < 85°C IDIS − − 1mA
Quiescent Current (Iq = Iin – Iout)
Iout = 100 mA, TJ = 25°C
Iout = 100 mA, TJ v 125°C
Iq−
−
38
−
43
44
mA
Current Limit Protection
Current Limit Vout = 0.96 x Vout_nom ILIM 205 −525 mA
Short Circuit Current Limit Vout = 0 V ISC 205 −525 mA
Reverse Output Current Protection
Reverse Output Current Protection VEN = 0 V, Iout = −1 mA Vout_rev −2 5.5 V
PSRR
Power Supply Ripple Rejection (Note 13) f = 100 Hz, 0.5Vpp PSRR −60 −dB
Enable Thresholds
Enable Input Threshold Voltage
Logic High
Logic Low
Vth(EN) 3
−
−
−
−
0.8
V
Enable Input Current
Logic High
Logic Low
VEN = 5 V
VEN = 0 V, TJ < 85°C
IEN_ON
IEN_OFF
−
−
3
0.5
5
1
mA
Window Watchdog
Watchdog Mode Bit 1 Threshold Voltage
Voltage Increasing, Logic High
3.3 V
5.0 V
Voltage Decreasing, Logic Low
VWM1,H
VWM1,L
−
−
0.8
−
−
−
2.65
4.0
−
V
Watchdog Mode Bit 2 Threshold Voltage
Voltage Increasing, Logic High
3.3 V
5.0 V
Voltage Decreasing, Logic Low
VWM2,H
VWM2,L
−
−
0.8
−
−
−
2.65
4.0
−
V
Watchdog Input WDI Threshold Voltage
Voltage Increasing, Logic High
3.3 V
5.0 V
Voltage Decreasing, Logic Low
VWDI,H
VWDI,L
−
−
0.8
−
−
−
2.65
4.0
−
V
Watchdog Input WDI Current
Logic High
Logic Low
VWDI,H = 5 V
VWDI,L = 0 V, TJ < 85 °C
IWDI,H
IWDI,L
−
−
3
0.5
4
1
mA
Watchdog Sampling Time Fast: WM2 = L
Slow: WM1 = L AND WM2 = H
tsam 0.4
0.8
0.5
1.0
0.6
1.2
ms
Ignore Window Time Fast: WM2 = L
Slow: WM1 = L AND WM2 = H
tIW 25.6
51.2
32.0
64.0
38.4
76.8
ms
Open Window Time Fast: WM2 = L
Slow: WM1 = L AND WM2 = H
tOW 25.6
51.2
32.0
64.0
38.4
76.8
ms
Closed Window Time Fast: WM2 = L
Slow: WM1 = L AND WM2 = H
tCW 25.6
51.2
32.0
64.0
38.4
76.8
ms
10.Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
12.Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. If Vout < 5 V, then VDO = Vin – Vout. Maximum dro-
pout voltage value is limited by minimum input voltage Vin = 4.5 V recommended for guaranteed operation at maximum output current.
13.Values based on design and/or characterization.
14.Recommended for typical trigger time. TWD = tCW + 1/2 * tOW
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ELECTRICAL CHARACTERISTICS
Vin = 13.2 V, Cin = 0.1 mF, Cout = 2.2 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted.
(Notes 10 and 11)
Parameter UnitMaxTypMinSymbolTest Conditions
Window Watchdog
Window Watchdog Trigger Time
(Note 14)
Fast: WM2 = L
Slow: WM1 = L AND WM2 = H
tWD −
−
48
96
−
−
ms
Watchdog Deactivation Current
Threshold
3.3 V
5.0 V
Iout decreasing
Vin > 4.5 V
Vin > 5.5 V
Iout_WD_OFF
0.5
0.5
−
−
−
−
mA
Watchdog Activating Current Threshold
3.3 V
5.0 V
Iout increasing
Vin > 4.5 V
Vin > 5.5 V
Iout_WD_ON −
−
2
2
5
5
mA
Reset Output RO
Input Voltage Reset Threshold
3.3 V
Vin decreasing, Vout > VRT Vin_RT −3.8 4.2
V
Output Voltage Reset Threshold
3.3 V
5.0 V
Vout decreasing
Vin > 4.5 V
Vin > 5.5 V
VRT 90
90
93
93
96
96
%Vout
Reset Hysteresis VRH −2.0 −%Vout
Maximum Reset Sink Current
3.3 V
5.0 V
Vout = 3 V, VRO = 0.25 V
Vout = 4.5 V, VRO = 0.25 V
IRomax 1.3
1.75
−
−
−
−
mA
Reset Output Low Voltage Vout > 1 V, IRO < 200 mAVROL −0.15 0.25 V
Reset Output High Voltage
5.0 V
VROH 4.5 − − V
Reset High Level Leakage Current
3.3 V
IROLK − − 1mA
Integrated Reset Pull Up Resistor
5.0 V
RRO 15 30 50 kW
Reset Delay Time Fast: WM1 = L AND WM2 = L
Slow:WM1 = H OR (WM1 = L AND WM2 = H)
tRD 12.8
25.6
16
32
19.2
38.4
ms
Reset Reaction Time (See Figure 24) tRR 16 25 38 ms
THERMAL SHUTDOWN
Thermal Shutdown Temperature
(Note 13)
TSD 150 175 195 °C
Thermal Shutdown Hysteresis (Note 13) TSH −25 −°C
10.Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [TJ. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
12.Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. If Vout < 5 V, then VDO = Vin – Vout. Maximum dro-
pout voltage value is limited by minimum input voltage Vin = 4.5 V recommended for guaranteed operation at maximum output current.
13.Values based on design and/or characterization.
14.Recommended for typical trigger time. TWD = tCW + 1/2 * tOW
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TYPICAL CHARACTERISTICS
Figure 4. Quiescent Current vs Temperature Figure 5. Quiescent Current vs Input Voltage
(5 V option)
Figure 6. Quiescent Current vs Output Current Figure 7. Output Voltage vs Temperature
(5 V option)
Figure 8. Output Voltage vs Input Voltage
(5 V option)
Figure 9. Dropout Voltage vs Output Current
(5 V option)
Vin = 13.2 V
Iout = 100 mA
TJ, JUNCTION TEMPERATURE (°C)
Iq, QUIESCENT CURRENT (mA)
30
31
32
33
34
35
36
37
38
0 20 40 60 120−40 −20 80 100 140 160
39
40
Vin, INPUT VOLTAGE (V)
Iq, QUIESCENT CURRENT (mA)
0
50
100
150
200
0 5 10 15 3020 25 35 40
Iq, QUIESCENT CURRENT (mA)
Iout, OUTPUT CURRENT (mA)
30
31
32
33
34
35
36
37
150°C
25°C
−40°C
0 25 50 75 150100 125 4.90
4.95
5.00
5.05
5.10
0 20 40 60 120
TJ, JUNCTION TEMPERATURE (°C)
Vout, OUTPUT VOLTAGE (V)
−40 −20 80 100 140 160
0
1
2
3
4
5
6
012
Vout, OUTPUT VOLTAGE (V)
Vin, INPUT VOLTAGE (V)
3456 0
100
200
300
400
500
600
VDO, DROPOUT VOLTAGE (mV)
Iout, OUTPUT CURRENT (mA)
150°C
25°C
−40°C
0 25 50 75 150100 125
Iout = 0 mA
TJ = 25°C
Vin = 13.2 V
38
39
40
Vin = 13.2 V
Iout = 100 mA
78
Iout = 1 mA
TJ = 25°C
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TYPICAL CHARACTERISTICS
Figure 10. Dropout vs Temperature
(5 V option)
Figure 11. Current Limit vs. Input Voltage
Figure 12. Current Limit vs. Temperature Figure 13. Cout ESR Stability Region vs Output
Current
Figure 14. Line Transients
(5 V option)
Figure 15. Load Transients
(5 V option)
150 mA
TJ, JUNCTION TEMPERATURE (°C)
0 20 40 60 120−40 −20 80 100 140 160
0
100
200
300
400
500
600
VDO, DROPOUT VOLTAGE (mV)
100 mA
200
250
300
350
400
TJ, JUNCTION TEMPERATURE (°C)
ILIM, ISC, CURRENT LIMIT (mA)
0 20 40 60 120−40 −20 80 100 140 160
ESR, STABILITY REGION (W)
Iout, OUTPUT CURRENT (mA)
0.01
0.1
1
10
100
1 10 1000100
Vin = 13.2 V
TJ = −40°C to 150°C
CLOAD = 2.2 mF − 100 mF
Stable Region
Vout
(50 mV/div)
12.2 V
5.1 V
700
800
Vin, INPUT VOLTAGE (V)
ILIM, ISC, CURRENT LIMIT (mA)
0
100
200
300
400
0 5 10 15 3020 25 35 40
TJ = 25°C
ILIM @ Vout = 4.8 V (5 V option)
ISC @ Vout = 0 V
Vin = 13.2 V
ILIM @ Vout = 4.8 V (5 V option)
ISC @ Vout = 0 V
TJ = 25°C
Iout = 1 mA
Cout = 10 mF
trise/fall = 1 ms (Vin)
14.2 V
4.97 V
Vin
(1 V/div)
TIME (100 ms/div)
Vout
(100 mV/div)
0.1 mA
5 V
TJ = 25°C
Vin = 13.2 V
Cout = 10 mF
trise/fall = 1 ms (Iout)
150 mA
4.82 V
Iout
(100 mA/div)
TIME (20 ms/div)
5.14 V
Unstable
Region
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TYPICAL CHARACTERISTICS
Figure 16. Power Up/Down Response
(5 V option)
Figure 17. PSRR vs. Frequency
(5 V option)
Figure 18. Noise vs. Frequency
(5 V option)
Figure 19. Disable Current vs Temperature
Figure 20. Disable Current vs. Input Voltage Figure 21. Enable Current vs. Enable Voltage
f, FREQUENCY (Hz)
PSRR (dB)
0
1000
2000
3000
40
50
60
70
80
100
1000
10
10000 100000
90
100
TJ = 25°C
Vin = 13.2 V ±0.5 Vpp
Cout = 2.2 mF
Iout = 0.1 mA
f, FREQUENCY (Hz)
NOISE DENSITY (nV/√Hz)
4000
5000
6000
1000 10000 100000
TJ = 25°C
Vin = 13.2 V
Cout = 2.2 mF
Iout = 150 mA
30
20
10
0
10010
0
1
2
3
4
TJ, JUNCTION TEMPERATURE (°C)
IDIS, DISABLE CURRENT (mA)
0 20 40 60 120−40 −20 80 100 140 160
Vin = 13.2 V
VEN = 0 V
Vin, INPUT VOLTAGE (V)
IDIS, DISABLE CURRENT (mA)
0
1
2
3
4
0 5 10 15 3020 25 35 40
VEN = 0 V
150°C
125°C
85°C
VEN, ENABLE VOLTAGE (V)
IEN, ENABLE CURRENT (mA)
0
10
20
30
50
0 5 10 15 3020 25 35 40
150°C
25°C
−40°C
Vin = 13.2 V
40
TJ = 25°C
VEN = Vin
Rout = 5 kW
Vin
(5 V/div)
Vout
(5 V/div)
TIME (100 ms/div)
VRO
(5 V/div)
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TYPICAL CHARACTERISTICS
Figure 22. Reset Threshold vs Temperature
(5 V option)
Figure 23. Reset Delay Time vs Temperature
4.60
4.65
4.70
4.75
4.80
TJ, JUNCTION TEMPERATURE (°C)
VRT
, RESET THRESHOLD (V)
0 20 40 60 120−40 −20 80 100 140 160
Vin = 13.2 V
14
15
16
17
18
TJ, JUNCTION TEMPERATURE (°C)
tRD, RESET DELAY TIME (ms)
0 20 40 60 120−40 −20 80 100 140 160
Vin = 13.2 V
Reset Mode = FAST
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TYPICAL CHARACTERISTICS
Vin
t
Vout
t
VRO
t
VRT+V
Rhys
<t
RR
tRD tRR
VROH
VROL
VRT
Figure 24. Reset Function and Timing Diagram
Reset &
Disabled
Watchdog
Reset
Trigger
Long
Open
Window
Open
Window
Closed
Window
Ignore
Window
Disabled
Watchdog
No Trigger
Trigger
Trigger
No Trigger
No Trigger
Trigger
WD_ON or
Iout > Iout_WD_ON
WD_ONWD_ON
WD_OFF or
Iout < Iout_WD_OFF
WD_OFF or
Iout < Iout_WD_OFF
WD_OFF or
Iout < Iout_WD_OFF
WD_OFF or
Iout < Iout_WD_OFF
WD_OFF or
Iout < Iout_WD_OFF
WM1 L L H H
WM2 L H L H
Window Watchdog Mode FAST SLOW FAST OFF
Reset Mode FAST SLOW SLOW SLOW
Figure 25. Window Watchdog State Diagram, Watchdog and Reset Modes
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TYPICAL CHARACTERISTICS
t
t
t
t
t
t
IW 1st
LONG
OW
CW OW OW IW 1st
LONG
OW
1st
LONG
OW
1st
LONG
OW
IW IW
IW
CW CW CW OW
tRD tRD tRD tRD
tRR
tIW tOW
tCW
tmax=4xtOW
Iout_WD_OFF
Iout_WD_ON
Current Controled
WD −Tu rn o f f
Don‘t Care
during IW
Missing Pulse
during OW
Pulse
during CW
Normal
Operation
VRT
Vout
Iout
VRO
WINDOW
VWDI
Vin
+V Rhys
VRT
VROH
VROL
tWD
Figure 26. Window Watchdog Signal Diagram
Closed window Open window
WDI
WDI
Closed window
Open window
WDI
WDI
Valid
Not valid
Watchdog
trigger signal
Watchdog decoder sample point
tECW tEOW
Figure 27. Valid WDI trigger signal
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13
DEFINITIONS
General
All measurements are performed using short pulse low duty
cycle techniques to maintain junction temperature as close
as possible to ambient temperature.
Output Voltage
The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.
Line Regulation
The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.
Load Regulation
The change in output voltage for a change in output current
measured for specific input voltage over operating ambient
temperature range.
Dropout Voltage
The input to output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. It is measured when the output drops 100 mV
below its nominal value. The junction temperature, load
current, and minimum input supply requirements affect the
dropout level.
Quiescent Currents
Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output current.
Current Limit and Short Circuit Current Limit
Current Limit is value of output current by which output
voltage drops below 96% of its nominal value. Short Circuit
Current Limit is output current value measured with output
of the regulator shorted to ground.
PSRR
Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).
Line Transient Response
Typical output voltage overshoot and undershoot response
when the input voltage is excited with a given slope.
Load Transient Response
Typical output voltage overshoot and undershoot response
when the output current is excited with a given slope
between low−load and high−load conditions.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Maximum Package Power Dissipation
The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.
APPLICATIONS INFORMATION
The NCV8668 regulator is self−protected with internal
thermal shutdown and internal current limit. Typical
characteristics are shown in Figures 4 to 27.
Input Decoupling (Cin)
A ceramic or tantalum 0.1 mF capacitor is recommended
and should be connected close to the NCV8668 package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
If extremely fast input voltage transients are expected then
appropriate input filter must be used in order to decrease
rising and/or falling edges below 50 V/ms for proper
operation. The filter can be composed of several capacitors
in parallel.
Output Decoupling (Cout)
The NCV8668 is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. Stability region of ESR versus Output
Current is shown in Figure 13. The minimum output
decoupling value is 2.2 mF and can be augmented to fulfill
stringent load transient requirements. The regulator works
with ceramic chip capacitors as well as tantalum devices.
Larger values improve noise rejection and load regulation
transient response.
Enable Operation
The Enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet.
Reset Operation
A reset signal is provided on the Reset Output (RO) pin to
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 24. This is in the form of a logic signal on
RO. Output voltage conditions below the RESET threshold
cause RO to go low. The RO integrity is maintained down
to VOUT = 1.0 V. The Reset Output (RO) circuitry includes
NCV8668
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14
a pull−up resistor (30 kW) internally connected to the output
(VOUT). No external pull−up is necessary.
For voltage option 3.3 V RO is open drain output and
external pull−up resistor is required.
Reset signal is also generated in case when input voltage
decreases below its minimum operating limit (4.5 V). The
Input Voltage Reset Threshold is typically 3.8 V. This
applies only to voltage options with nominal value below
minimum operating input voltage (3.3 V).
Window Watchdog Operation
The watchdog slow, fast or off state is set by pins WM1
and WM2 (see table in Figure 25). The timing values used
in this description refer to typ. Values when WM1 and WM2
are connected to GND (fast watchdog and reset timing). The
state diagram of the window watchdog (WWD) and the
watchdog and reset mode selection table is shown in
Figure 25. The WWD timing is shown in Figure 26. After
power−on, the reset output signal at the RO pin
(microprocessor reset) is kept LOW for the reset delay time
tRD (16 ms). RO signal transition from LOW to HIGH
triggers the ignore window (IW) with duration of tIW
(32 ms). During this window the signal at the WDI pin is
ignored. When IW ends a long open window with maximum
duration of (128 ms, tmax = 4xtOW) is started. When a valid
trigger signal is detected during long open window, a closed
window (CW) with duration of tCW (32 ms) is initialized
immediately. WDI signal transition from HIGH to LOW is
taken as a trigger. As valid trigger two HIGH samples
followed by two LOW samples (with sampling time tsam =
0.5 ms) have to be present before end of the long window.
Valid WDI trigger signal is shown in Figure 27. When CW
ends a standard open window (OW) with maximum duration
of tOW (32 ms) is initiated immediately. The OW ends
immediately when valid trigger appears at WDI input. For
normal operation the microprocessor timing of WDI pulses
must be stable and correspond to tWD. A reset signal is
generated (RO goes LOW) if there is no valid trigger
(missing pulse at WDI pin) during OW or if a pre−trigger
occurs during the CW (unexpected pulse at WDI pin).
Thermal Considerations
As power in the NCV8668 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV8668 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV8668 can handle is given by:
PD(MAX) +ƪTJ(MAX) *TAƫ
RqJA
(eq. 1)
Since TJ is not recommended to exceed 150°C, then the
NCV8668 soldered on 645 mm2, 1 oz copper area, FR4 can
dissipate up to 1.3 W for SOIC−14 package when the
ambient temperature (TA) is 25°C. See Figure 28 for RqJA
versus PCB area. The power dissipated by the NCV8668 can
be calculated from the following equations:
PD+VinǒIq@IoutǓ)IoutǒVin *VoutǓ(eq. 2)
or
Vin(MAX) +
PD(MAX) )ǒVout IoutǓ
Iout )Iq
(eq. 3)
Figure 28. Thermal Resistance vs PCB Copper Area
COPPER HEAT SPREADER AREA (mm2)
RqJA, THERMAL RESISTANCE (°C/W)
80
90
100
110
120
0 100 200 300 600400 500 700
PCB 2 oz Cu
SOIC−14
130
140
PCB 1 oz Cu
Hints
Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCV8668, and
make traces as short as possible.
NCV8668
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15
ORDERING INFORMATION
Device Vout
tRD
Fast/
Slow
IW/OW/CW
Time Fast/
Slow
1st LOW
Time Fast/
Slow VRT
Output
Current
WW ON/
OFF Marking Package Shipping†
NCV8668ABD250R2G 5.0 V 16 /
32 ms
32 / 64 ms 128 /
256 ms
93% Yes V8668AB50G SOIC−14
(Pb−Free)
2500 / Tape &
Reel
NCV8668ABD150R2G 5.0 V 16 /
32 ms
32 / 64 ms 128 /
256 ms
93% Yes 668AB5 SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NCV8668ABPD50R2G 5.0 V 16 /
32 ms
32 / 64 ms 128 /
256 ms
93% Yes 668AB5 SOIC−8
EPAD
(Pb−Free)
2500 / Tape &
Reel
NCV8668ABPD33R2G 3.3 V 16 /
32 ms
32 / 64 ms 128 /
256 ms
93% Yes 668AB3 SOIC−8
EPAD
(Pb−Free)
2500 / Tape &
Reel
NCV8668ABD133R2G 3.3 V 16 /
32 ms
32 / 64 ms 128 /
256 ms
93% Yes 668AB3 SOIC−8
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: Contact factory for other package, output voltage, timing and reset threshold options
NCV8668
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16
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NCV8668
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17
PACKAGE DIMENSIONS
ÉÉÉ
ÉÉÉ
SOIC−8 EP
CASE 751AC−01
ISSUE B
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
ÇÇ
H
C0.10
D
E1
A
D
PIN ONE
2 X
8 X
SEATING
PLANE
EXPOSED
GAUGE
PLANE
14
58
D
C0.10 A-B
2 X
E
B
e
C0.10
2 X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DETAIL A
END VIEW
SECTION A−A
8 X b
A-B0.25 D
C
C
C0.10
C0.20
A
A2
G
F
14
58
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.00 0.10
A2 1.35 1.65
b0.31 0.51
b1 0.28 0.48
c0.17 0.25
c1 0.17 0.23
D4.90 BSC
E6.00 BSC
e1.27 BSC
L0.40 1.27
L1 1.04 REF
F2.24 3.20
G1.55 2.51
h0.25 0.50
q0 8
h
AA
DETAIL A
(b)
b1
c
c1
0.25
L
(L1)
q
PAD
E1 3.90 BSC
__
A1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
LOCATION
Exposed
Pad
1.52
0.060
2.03
0.08
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
7.0
0.275
2.72
0.107
NCV8668
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18
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NCV8668/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
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