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FEATURES
10 years minimu m data retention in the
absence o f exter na l po wer
Dat a is aut omatical l y p r ot ected during power
loss
Rep laces 128k x 8 vo lat ile static RAM,
EEPROM or Flash memory
Unlim ited write cycles
Low-po wer CMOS
Read and wr it e acces s times of 70 ns
Lit hiu m e nergy source is electrical l y
d iscon nect ed to retain freshness until power is
applied for the first time
Full ±10% VCC operating r ange (DS1245Y)
Optional ±5% VCC oper at ing range
(DS1245AB)
Optional indust r ial temperatur e range of
-40°C to +85°C, des ignated I N D
JEDEC standard 32-pin DIP package
Power Cap Modu le (PCM) p ackag e
- D irectly sur face-mountable mo dule
- Rep laceab le snap-on Po werCap provides
lith iu m backup batt ery
- Standardized p inout for all non volat ile
SRAM products
- Det ach ment featur e o n Po w erCap a llows
easy remova l using a r egular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A16 - Address Inputs
DQ0 - DQ7 - Data I n/Dat a Out
CE
- Chip E na ble
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+5V)
GND - Ground
NC - No Connect
DS1245Y/AB
1024k Nonvolatile SRAM
www.maxim-ic.com
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1
2
3
4
5
6
7
8
9
10
11
12
14
31
740-mil Extended
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
NC
DQ2
GND
15
16
18
17
DQ4
DQ3
1
NC
2
3
A15
A16
NC
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
NC
GND
V
BAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
19-5638; Rev 11/10
DS1245Y/AB
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DESCRIPTION
The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, nonvolatile SRAMs organized as
131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
c on tr ol cir cuitry wh i ch c on s tantl y mon itor s VCC for an out-of-t o ler a nc e co nditio n. Whe n s u c h a c o nd ition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled t o p revent dat a cor ruption. DI P-package DS1245 devices ca n be used in place o f e xist ing 1 28k x
8 stat ic RAMs direct ly confo r ming t o the popular byt ewide 32-p in DIP standard. DS1245 devices in th e
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be execut ed and no addit ional sup port circuitry is required for micro pr ocessor interfac ing.
READ MODE
The DS1245 execut es a r ead cycle w hen ever
WE
(Wr ite Enable) is inactive (high) and
CE
(Chip Enable)
and
OE
(Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 -
A16) de fines w hich of the 131,072 bytes of dat a is t o be accessed. Valid data w ill be availab le to the eig ht
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that
CE
and
OE
(Out put Enable) a ccess times are a lso satisf ied. I f
OE
and
CE
access times are not satisfied,
t hen data acces s must be measured from the lat er occur ring sig na l (
CE
or
OE
) and the limiting par amet er
is eith er tCO for
CE
or tOE for
OE
rather than address access.
WRITE MODE
The DS1245 executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
input s are stab le. T h e later occur r ing fa l ling edge of
CE
or
WE
w ill determine the star t of the write c ycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during writ e
cyc les to avoid bus co nt ent io n. Ho we ver, if t he o ut put dr iver s ar e e nabled (
CE
and
OE
ac tive) t hen
WE
will disab le the outp uts in tODW from it s fa lling edg e.
DATA RETENTION MODE
The DS1245AB provides full functional capa bilit y for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1245Y provides full functional capability for VCC greater than 4.5 volts and write-
prot ect s by 4. 25 vo lt s. Dat a is maint ained in the abse nce of VCC with ou t an y a d dition al suppo rt c ircu itr y.
The nonvolatile static RAMs constantly mo nitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write-protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy sour ce.
No rma l RAM oper at io n can re su me after VCC exceeds 4.75 vo lt s fo r the DS1245AB and 4. 5 volts fo r t he
DS1245Y.
FRESH NESS SEAL
Each DS1245 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full en er gy capa city. When VCC is fir st ap plied at a level greater than 4.25 volts, the lit h iu m energy sou r ce
is enabled for bat tery back-up o peration.
DS1245Y/AB
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PACKAGES
The DS1245 devices are available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM).
The 32-p in DI P int eg rat es a lith ium bat t ery, a n SRA M me mor y a nd a no nvo latile co nt ro l funct io n int o a
single package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolat ile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1245 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1245 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1245 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separ ate containers. See the DS9034 PC d ata sheet for fur ther information.
DS1245Y/AB
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +6. 0V
Operating T emperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85° C
Stor ag e T emperat ur e Range
EDIP -40°C to +85°C
Power Cap -55°C to +125°C
Lead Temperature (soldering, 10s) +260°C
Sold ering Te mperature (reflow, P ower Cap ) +260°C
Note: EDIP i s wa ve or ha nd soldered o nly.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1245AB Power S upply Voltage VCC 4.75 5.0 5.25 V
DS1245Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.8 V
DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1245AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1245Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -1.0 +1.0 µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
St andby Curr ent
CE
=2.2V ICCS1 200 600 µA
St andby Curr ent
CE
=VCC-0.5V ICCS2 50 150 µA
Operating Cur r ent ICCO1 85 mA
Writ e Pr otection Voltage (DS1245AB) VTP 4.50 4.62 4.75 V
Writ e Pr otection Voltage (DS1245Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
I nput/O utput C apa cita nce CI/O 5 10 pF
DS1245Y/AB
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AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5% for DS1245AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1245Y)
PARAMETER SYMBOL DS1245AB-70
DS1245Y-70 UNITS NOTES
MIN MAX
Re a d Cycle Time tRC 70 ns
Access Time tACC 70 ns
OE
to O utput Va lid tOE 35 ns
CE
to Output Va lid tCO 70 ns
OE
or
CE
to O utput Ac tive tCOE 5 ns 5
Output High Z from Deselection tOD 25 ns 5
Output Hold fro m Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 55 ns 3
A ddress Setup Time tAW 0 ns
Write Reco ver y Ti me tWR1
tWR2
5
15
ns
ns 12
13
Output High Z from
WE
tODW 25 ns 5
Output Active from
WE
tOEW 5 ns 5
Dat a S et up Time tDS 30 ns 4
Da ta Hold Time tDH1
tDH2
0
10
ns
ns 12
13
DS1245Y/AB
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1245Y/AB
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WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
DS1245Y/AB
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POWER-DOWN/POWER-UP TIMING (TA: See N ot e 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC sl ew f rom VTP t o 0V tF 150 µs
VCC slew from 0 V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to E nd of Write Pr otectio n tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Retent ion T ime tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH dur ing wr ite c ycle, the output bu ffers re main in a high impedance state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h igh.
4. tDH, tDS ar e measur ed from the ear lier of
CE
or
WE
go ing h ig h.
5. T hese para met er s ar e sampled with a 5 pF load an d ar e not 100 % tested .
6. I f the
CE
low transit io n occurs simultaneo usly w it h o r lat ter than the
WE
lo w t rans it ion, t he output
buffers remain in a high impedance state during t his per iod.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
bu ffe r s r e ma in in h ig h imp ed a nc e st a t e during this period.
8. If
WE
is low or th e
WE
lo w t ra ns ition o cc ur s p r io r t o o r s imu lt ane o u s ly with t h e
CE
lo w t ra ns ition ,
t he output buffers re main in a high impedance st ate during this period.
9. Each DS1245 has a bu ilt -in sw it c h that d isco nnect s the lithiu m source u nt il the user fir st app lies VCC.
The expect ed tDR is de fined as accu mu lat ive t ime in t he a bse nce of VCC starting fro m the t ime power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production test ing.
10. E ach DS1245 has a bu ilt -in sw it c h that d isc o n nects t he lit hium sou r ce until V CC is fir st applied by t he
user. The expected tDR is defined as accu mulat ive t ime in the a bs ence o f VCC st art ing fro m the t ime
power is first applied by the user.
11. All AC and DC electrical characteristics are valid over the full operating temperature range. For
co mmer cia l pr od uct s, this r ang e is 0°C t o 70°C. For industria l pro ducts (IND), this range is -40°C t o
+85°C.
12. I n a po wer-dow n conditio n the volt age on an y pin may no t exc ee d the volt age on VCC.
DS1245Y/AB
9 of 10
13. tWR1 and tDH1 are mea sur ed fro m
WE
go ing h ig h.
14. tWR2 and tDH2 are mea sur ed fro m
CE
go ing h ig h.
15. DS1245 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100 pF + 1TTL Gate
Cycle = 200 ns for operating curr ent I nput Pulse Levels: 0 - 3.0V
All voltages ar e r eferenced to ground Timing Measur ement Referen ce Le vels
Input: 1.5V
Output : 1. 5V
Input puls e R ise and Fall Times: 5 ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
SPEED GRADE
(ns)
DS1245AB-70+
0°C to +70°C
5V
±
5%
32 740 EDIP
70
DS1245ABP-70+
0°C to +70°C
5V ± 5%
34 PowerCap*
70
DS1245AB-70IND+
-40°C to +85°C
5V ± 5%
32 740 EDIP
70
DS1245ABP-70IND+
-40°C to +85°C
5V ± 5%
34 PowerCap*
70
DS1245Y-70+
0°C to +70°C
5V
±
10%
32 740 EDIP
70
DS1245YP-70+
0°C to +70°C
5V
±
10%
34 PowerCap*
70
DS1245Y-70IND+
-40°C to +85°C
5V
±
10%
32 740 EDIP
70
DS1245YP-70IND+
-40°C to +85°C
5V ± 10%
34 PowerCap*
70
+Denotes a lead(Pb)-free/RoHS-compli ant package.
*DS9034PC+ or DS9034PCI+ (Pow erCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline informa ti on a nd land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, b ut the dr aw ing pertains to the p ackag e regard less of RoHS s tatu s .
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
32 EDIP MDT32+6 21-0245 —
34 PCAP PC2+3 21-0246 —
DS1245Y/AB
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added Package Information table; re moved the DIP module p ackag e
drawing and dimension table
10, 11, 12
11/10
Updated the storage information, soldering temperature, and lead
t emperat ur e info rmation in t he Absolute Maximum Ratings section;
r emove d the -85, -100, and -120 MIN/MAX info rmat io n fro m the AC
Electrical Characteristics table; updat ed the Ordering Information
t able (re moved -85, -100, and -120 parts and lead e d -70 parts);
re moved the PowerCap mo dule drawings a nd updated the Package
Information table
1, 4, 5, 9