nRF52840
Product Specification
v1.1
4413_417 v1.1 / 2019-02-28
Feature list
Features:
•Bluetooth® 5, IEEE 802.15.4-2006, 2.4 GHz transceiver
• -95 dBm sensitivity in 1 Mbps Bluetooth® low energy mode
• -103 dBm sensitivity in 125 kbps Bluetooth® low energy mode (long range)
• -20 to +8 dBm TX power, configurable in 4 dB steps
• On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series
• Supported data rates:
•Bluetooth® 5: 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps
• IEEE 802.15.4-2006: 250 kbps
• Proprietary 2.4 GHz: 2 Mbps, 1 Mbps
• Single-ended antenna output (on-chip balun)
• 128-bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption)
• 4.8 mA peak current in TX (0 dBm)
• 4.6 mA peak current in RX
• RSSI (1 dB resolution)
• ARM® Cortex®-M4 32-bit processor with FPU, 64 MHz
• 212 EEMBC CoreMark score running from flash memory
• 52 µA/MHz running CoreMark from flash memory
• Watchpoint and trace debug modules (DWT, ETM, and ITM)
• Serial wire debug (SWD)
• Rich set of security features
• ARM® TrustZone® Cryptocell 310 security subsystem
• NIST SP800-90A and SP800-90B compliant random number generator
• AES-128: ECB, CBC, CMAC/CBC-MAC, CTR, CCM/CCM*
• Chacha20/Poly1305 AEAD supporting 128- and 256-bit key size
• SHA-1, SHA-2 up to 256 bits
• Keyed-hash message authentication code (HMAC)
• RSA up to 2048-bit key size
• SRP up to 3072-bit key size
• ECC support for most used curves, among others P-256 (secp256r1) and
Ed25519/Curve25519
• Application key management using derived key model
• Secure boot ready
• Flash access control list (ACL)
• Root-of-trust (RoT)
• Debug control and configuration
• Access port protection (CTRL-AP)
• Secure erase
• Flexible power management
• 1.7 V to 5.5 V supply voltage range
• On-chip DC/DC and LDO regulators with automated low
current modes
• 1.8 V to 3.3 V regulated supply for external components
• Automated peripheral power management
• Fast wake-up using 64 MHz internal oscillator
• 0.4 µA at 3 V in System OFF mode, no RAM retention
• 1.5 µA at 3 V in System ON mode, no RAM retention, wake on
RTC
• 1 MB flash and 256 kB RAM
• Advanced on-chip interfaces
• USB 2.0 full speed (12 Mbps) controller
• QSPI 32 MHz interface
• High-speed 32 MHz SPI
• Type 2 near field communication (NFC-A) tag with wake-on
field
• Touch-to-pair support
• Programmable peripheral interconnect (PPI)
• 48 general purpose I/O pins
• EasyDMA automated data transfer between memory and
peripherals
• Nordic SoftDevice ready with support for concurrent multi-
protocol
• 12-bit, 200 ksps ADC - 8 configurable channels with programmable
gain
• 64 level comparator
• 15 level low-power comparator with wake-up from System OFF
mode
• Temperature sensor
• 4x 4-channel pulse width modulator (PWM) unit with EasyDMA
• Audio peripherals: I2S, digital microphone interface (PDM)
• 5x 32-bit timer with counter mode
• Up to 4x SPI master/3x SPI slave with EasyDMA
• Up to 2x I2C compatible 2-wire master/slave
• 2x UART (CTS/RTS) with EasyDMA
• Quadrature decoder (QDEC)
• 3x real-time counter (RTC)
• Single crystal operation
• Package variants
• aQFN™73 package, 7 x 7 mm
• WLCSP93 package, 3.544 x 3.607 mm
4413_417 v1.1 ii
Feature list
Applications:
• Advanced computer peripherals and I/O devices
• Mouse
• Keyboard
• Multi-touch trackpad
• Advanced wearables
• Health/fitness sensor and monitor devices
• Wireless payment enabled devices
• Internet of things (IoT)
• Smart home sensors and controllers
• Industrial IoT sensors and controllers
• Interactive entertainment devices
• Remote controls
• Gaming controllers
4413_417 v1.1 iii
Contents
Feature list..................................... ii
1Revision history................................ 12
2About this document............................. 14
2.1 Document naming and status ........................... 14
2.2 Peripheral naming and abbreviations ........................ 14
2.3 Register tables ................................. 15
2.3.1 Fields and values .............................. 15
2.4 Registers ....................................15
2.4.1 DUMMY .................................. 15
3Block diagram................................. 17
4Core components............................... 19
4.1 CPU ......................................19
4.1.1 Floating point interrupt ............................19
4.1.2 CPU and support module configuration ..................... 19
4.1.3 Electrical specification ............................ 20
4.2 Memory .................................... 20
4.2.1 RAM - Random access memory ........................ 21
4.2.2 Flash - Non-volatile memory ......................... 21
4.2.3 Memory map ................................ 21
4.2.4 Instantiation ................................ 23
4.3 NVMC — Non-volatile memory controller ...................... 24
4.3.1 Writing to flash ............................... 24
4.3.2 Erasing a page in flash ............................ 25
4.3.3 Writing to user information configuration registers (UICR) ............. 25
4.3.4 Erasing user information configuration registers (UICR) ............... 25
4.3.5 Erase all .................................. 25
4.3.6 Access port protection behavior ........................ 25
4.3.7 Partial erase of a page in flash ......................... 25
4.3.8 Cache ................................... 26
4.3.9 Registers .................................. 26
4.3.10 Electrical specification ............................ 30
4.4 FICR — Factory information configuration registers .................. 31
4.4.1 Registers .................................. 31
4.5 UICR — User information configuration registers ................... 42
4.5.1 Registers .................................. 43
4.6 EasyDMA ................................... 46
4.6.1 EasyDMA error handling ........................... 48
4.6.2 EasyDMA array list .............................. 48
4.7 AHB multilayer ................................. 49
4.8 Debug and trace ................................ 50
4.8.1 DAP - Debug access port ........................... 51
4.8.2 CTRL-AP - Control access port ......................... 51
4.8.3 Debug interface mode ............................ 53
4.8.4 Real-time debug ...............................54
4.8.5 Trace ................................... 54
4413_417 v1.1 iv
5Power and clock management........................ 55
5.1 Power management unit (PMU) .......................... 55
5.2 Current consumption .............................. 55
5.2.1 Electrical specification ............................ 56
5.3 POWER — Power supply ............................. 61
5.3.1 Main supply ................................ 61
5.3.2 USB supply ................................. 66
5.3.3 System OFF mode .............................. 67
5.3.4 System ON mode .............................. 68
5.3.5 RAM power control ............................. 68
5.3.6 Reset ................................... 69
5.3.7 Registers .................................. 70
5.3.8 Electrical specification ............................ 80
5.4 CLOCK — Clock control ............................. 82
5.4.1 HFCLK controller .............................. 83
5.4.2 LFCLK controller ............................... 84
5.4.3 Registers .................................. 87
5.4.4 Electrical specification ............................ 96
6Peripherals................................... 99
6.1 Peripheral interface ............................... 99
6.1.1 Peripheral ID ................................ 99
6.1.2 Peripherals with shared ID .......................... 100
6.1.3 Peripheral registers ............................. 100
6.1.4 Bit set and clear .............................. 100
6.1.5 Tasks ................................... 100
6.1.6 Events .................................. 100
6.1.7 Shortcuts ................................. 101
6.1.8 Interrupts ................................. 101
6.2 AAR — Accelerated address resolver ....................... 102
6.2.1 EasyDMA ................................. 102
6.2.2 Resolving a resolvable address ........................ 102
6.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR .103
6.2.4 IRK data structure ............................. 103
6.2.5 Registers ................................. 103
6.2.6 Electrical specification ............................ 107
6.3 ACL — Access control lists ............................ 107
6.3.1 Registers ................................. 109
6.4 CCM — AES CCM mode encryption ........................ 111
6.4.1 Key-steam generation ............................ 111
6.4.2 Encryption ................................ 112
6.4.3 Decryption ................................ 112
6.4.4 AES CCM and RADIO concurrent operation ................... 113
6.4.5 Encrypting packets on-the-fly in radio transmit mode ............... 113
6.4.6 Decrypting packets on-the-fly in radio receive mode ............... 114
6.4.7 CCM data structure ............................. 115
6.4.8 EasyDMA and ERROR event ......................... 116
6.4.9 Registers ................................. 116
6.4.10 Electrical specification ........................... 123
6.5 COMP — Comparator ..............................123
6.5.1 Differential mode ..............................124
6.5.2 Single-ended mode ............................. 125
6.5.3 Registers ................................. 127
6.5.4 Electrical specification ............................ 134
4413_417 v1.1 v
6.6 CRYPTOCELL — ARM TrustZone CryptoCell 310 ................... 135
6.6.1 Usage .................................. 136
6.6.2 Always-on (AO) power domain ........................ 136
6.6.3 Lifecycle state (LCS) ............................. 136
6.6.4 Cryptographic key selection ......................... 137
6.6.5 Direct memory access (DMA) .........................137
6.6.6 Standards ................................. 138
6.6.7 Registers ................................. 138
6.6.8 Host interface ............................... 139
6.7 ECB — AES electronic codebook mode encryption .................. 142
6.7.1 Shared resources .............................. 142
6.7.2 EasyDMA ................................. 142
6.7.3 ECB data structure ............................. 142
6.7.4 Registers ................................. 143
6.7.5 Electrical specification ............................ 145
6.8 EGU — Event generator unit ........................... 146
6.8.1 Registers ................................. 146
6.8.2 Electrical specification ............................ 148
6.9 GPIO — General purpose input/output ...................... 148
6.9.1 Pin configuration .............................. 149
6.9.2 Registers ................................. 151
6.9.3 Electrical specification ............................ 156
6.10 GPIOTE — GPIO tasks and events ........................ 157
6.10.1 Pin events and tasks ............................ 157
6.10.2 Port event ................................ 158
6.10.3 Tasks and events pin configuration ...................... 158
6.10.4 Registers ................................. 159
6.10.5 Electrical specification ........................... 163
6.11 I2S — Inter-IC sound interface ..........................163
6.11.1 Mode .................................. 164
6.11.2 Transmitting and receiving ......................... 164
6.11.3 Left right clock (LRCK) ........................... 165
6.11.4 Serial clock (SCK) ............................. 165
6.11.5 Master clock (MCK) ............................ 166
6.11.6 Width, alignment and format ........................ 166
6.11.7 EasyDMA .................................168
6.11.8 Module operation ............................. 170
6.11.9 Pin configuration ............................. 172
6.11.10 Registers ................................ 173
6.11.11 Electrical specification ...........................182
6.12 LPCOMP — Low power comparator ....................... 183
6.12.1 Shared resources ............................. 184
6.12.2 Pin configuration ............................. 184
6.12.3 Registers ................................. 185
6.12.4 Electrical specification ........................... 191
6.13 MWU — Memory watch unit .......................... 191
6.13.1 Registers ................................. 192
6.14 NFCT — Near field communication tag ...................... 205
6.14.1 Overview ................................ 206
6.14.2 Operating states ..............................208
6.14.3 Pin configuration ............................. 209
6.14.4 EasyDMA .................................209
6.14.5 Frame assembler ............................. 210
6.14.6 Frame disassembler ............................ 211
4413_417 v1.1 vi
6.14.7 Frame timing controller .......................... 212
6.14.8 Collision resolution ............................ 213
6.14.9 Antenna interface ............................. 214
6.14.10 NFCT antenna recommendations ...................... 214
6.14.11 Battery protection ............................ 215
6.14.12 References ............................... 215
6.14.13 Registers ................................ 215
6.14.14 Electrical specification ...........................233
6.15 PDM — Pulse density modulation interface .................... 234
6.15.1 Master clock generator ...........................235
6.15.2 Module operation ............................. 235
6.15.3 Decimation filter ............................. 235
6.15.4 EasyDMA .................................236
6.15.5 Hardware example .............................237
6.15.6 Pin configuration ............................. 237
6.15.7 Registers ................................. 238
6.15.8 Electrical specification ........................... 244
6.16 PPI — Programmable peripheral interconnect ................... 245
6.16.1 Pre-programmed channels ......................... 246
6.16.2 Registers ................................. 247
6.17 PWM — Pulse width modulation ........................ 251
6.17.1 Wave counter ...............................252
6.17.2 Decoder with EasyDMA ...........................255
6.17.3 Limitations ................................ 262
6.17.4 Pin configuration ............................. 262
6.17.5 Registers ................................. 263
6.18 QDEC — Quadrature decoder .......................... 271
6.18.1 Sampling and decoding ...........................272
6.18.2 LED output ................................ 273
6.18.3 Debounce filters ............................. 273
6.18.4 Accumulators ............................... 274
6.18.5 Output/input pins ............................. 274
6.18.6 Pin configuration ............................. 274
6.18.7 Registers ................................. 275
6.18.8 Electrical specification ........................... 286
6.19 QSPI — Quad serial peripheral interface ..................... 286
6.19.1 Configuring peripheral ........................... 287
6.19.2 Write operation .............................. 287
6.19.3 Read operation .............................. 288
6.19.4 Erase operation .............................. 288
6.19.5 Execute in place ..............................288
6.19.6 Sending custom instructions .........................288
6.19.7 Deep power-down mode .......................... 289
6.19.8 Instruction set .............................. 290
6.19.9 Interface description ............................ 290
6.19.10 Registers ................................ 295
6.19.11 Electrical specification ...........................307
6.20 RADIO — 2.4 GHz radio ............................ 307
6.20.1 Packet configuration ............................ 308
6.20.2 Address configuration ........................... 309
6.20.3 Data whitening .............................. 310
6.20.4 CRC ................................... 310
6.20.5 Radio states ............................... 311
6.20.6 Transmit sequence ............................ 311
4413_417 v1.1 vii
6.20.7 Receive sequence ............................. 313
6.20.8 Received signal strength indicator (RSSI) .................... 314
6.20.9 Interframe spacing .............................314
6.20.10 Device address match ........................... 315
6.20.11 Bit counter ............................... 316
6.20.12 IEEE 802.15.4 operation .......................... 316
6.20.13 EasyDMA ................................ 324
6.20.14 Registers ................................ 325
6.20.15 Electrical specification ...........................354
6.21 RNG — Random number generator ....................... 359
6.21.1 Bias correction .............................. 360
6.21.2 Speed .................................. 360
6.21.3 Registers ................................. 360
6.21.4 Electrical specification ........................... 363
6.22 RTC — Real-time counter ........................... 363
6.22.1 Clock source ............................... 363
6.22.2 Resolution versus overflow and the PRESCALER ................. 363
6.22.3 COUNTER register ............................. 364
6.22.4 Overflow features ............................. 365
6.22.5 TICK event ................................ 365
6.22.6 Event control feature ........................... 365
6.22.7 Compare feature ............................. 366
6.22.8 TASK and EVENT jitter/delay .........................368
6.22.9 Reading the COUNTER register ....................... 370
6.22.10 Registers ................................ 371
6.22.11 Electrical specification ...........................376
6.23 SAADC — Successive approximation analog-to-digital converter ............ 376
6.23.1 Input configuration ............................ 377
6.23.2 Reference voltage and gain settings ..................... 379
6.23.3 Digital output ............................... 379
6.23.4 EasyDMA .................................379
6.23.5 Continuous sampling ............................381
6.23.6 Oversampling ............................... 381
6.23.7 Event monitoring using limits ........................ 381
6.23.8 Calibration ................................ 382
6.23.9 Registers ................................. 382
6.23.10 Electrical specification ...........................397
6.24 SPI — Serial peripheral interface master ..................... 398
6.24.1 Functional description ........................... 398
6.24.2 Registers ................................. 401
6.24.3 Electrical specification ........................... 405
6.25 SPIM — Serial peripheral interface master with EasyDMA .............. 406
6.25.1 SPI master transaction sequence ....................... 407
6.25.2 D/CX functionality ............................. 408
6.25.3 Pin configuration ............................. 409
6.25.4 EasyDMA .................................409
6.25.5 Low power ................................ 410
6.25.6 Registers ................................. 410
6.25.7 Electrical specification ........................... 421
6.26 SPIS — Serial peripheral interface slave with EasyDMA ................422
6.26.1 Shared resources ............................. 423
6.26.2 EasyDMA .................................423
6.26.3 SPI slave operation ............................ 424
6.26.4 Pin configuration ............................. 426
4413_417 v1.1 viii
6.26.5 Registers ................................. 426
6.26.6 Electrical specification ........................... 437
6.27 SWI — Software interrupts ........................... 439
6.27.1 Registers ................................. 439
6.28 TEMP — Temperature sensor .......................... 439
6.28.1 Registers ................................. 440
6.28.2 Electrical specification ........................... 446
6.29 TWI — I2C compatible two-wire interface ..................... 446
6.29.1 Functional description ........................... 446
6.29.2 Master mode pin configuration ....................... 447
6.29.3 Shared resources ............................. 447
6.29.4 Master write sequence ........................... 448
6.29.5 Master read sequence ........................... 448
6.29.6 Master repeated start sequence ....................... 449
6.29.7 Low power ................................ 450
6.29.8 Registers ................................. 450
6.29.9 Electrical specification ........................... 458
6.30 TIMER — Timer/counter ............................ 459
6.30.1 Capture ................................. 460
6.30.2 Compare .................................460
6.30.3 Task delays ................................ 460
6.30.4 Task priority ............................... 460
6.30.5 Registers ................................. 461
6.31 TWIM — I2C compatible two-wire interface master with EasyDMA ........... 465
6.31.1 EasyDMA .................................466
6.31.2 Master write sequence ........................... 467
6.31.3 Master read sequence ........................... 468
6.31.4 Master repeated start sequence ....................... 469
6.31.5 Low power ................................ 470
6.31.6 Master mode pin configuration ....................... 470
6.31.7 Registers ................................. 470
6.31.8 Electrical specification ........................... 481
6.31.9 Pullup resistor .............................. 482
6.32 TWIS — I2C compatible two-wire interface slave with EasyDMA ............ 482
6.32.1 EasyDMA .................................485
6.32.2 TWI slave responding to a read command ................... 485
6.32.3 TWI slave responding to a write command ...................486
6.32.4 Master repeated start sequence ....................... 487
6.32.5 Terminating an ongoing TWI transaction ....................488
6.32.6 Low power ................................ 488
6.32.7 Slave mode pin configuration ........................ 488
6.32.8 Registers ................................. 489
6.32.9 Electrical specification ........................... 499
6.33 UART — Universal asynchronous receiver/transmitter ................ 499
6.33.1 Functional description ........................... 500
6.33.2 Pin configuration ............................. 500
6.33.3 Shared resources ............................. 501
6.33.4 Transmission ............................... 501
6.33.5 Reception ................................ 501
6.33.6 Suspending the UART ........................... 502
6.33.7 Error conditions .............................. 502
6.33.8 Using the UART without flow control ..................... 502
6.33.9 Parity and stop bit configuration ....................... 503
6.33.10 Registers ................................ 503
4413_417 v1.1 ix
6.33.11 Electrical specification ...........................512
6.34 UARTE — Universal asynchronous receiver/transmitter with EasyDMA ......... 512
6.34.1 EasyDMA .................................513
6.34.2 Transmission ............................... 513
6.34.3 Reception ................................ 514
6.34.4 Error conditions .............................. 515
6.34.5 Using the UARTE without flow control .................... 515
6.34.6 Parity and stop bit configuration ....................... 516
6.34.7 Low power ................................ 516
6.34.8 Pin configuration ............................. 516
6.34.9 Registers ................................. 516
6.34.10 Electrical specification ...........................529
6.35 USBD — Universal serial bus device ....................... 529
6.35.1 USB device states ............................. 530
6.35.2 USB terminology ............................. 531
6.35.3 USB pins ................................. 532
6.35.4 USBD power-up sequence ......................... 532
6.35.5 USB pull-up ............................... 533
6.35.6 USB reset ................................ 533
6.35.7 USB suspend and resume .......................... 534
6.35.8 EasyDMA .................................535
6.35.9 Control transfers ............................. 536
6.35.10 Bulk and interrupt transactions ....................... 539
6.35.11 Isochronous transactions ......................... 542
6.35.12 USB register access limitations ....................... 544
6.35.13 Registers ................................ 545
6.35.14 Electrical specification ...........................569
6.36 WDT — Watchdog timer ............................ 570
6.36.1 Reload criteria .............................. 570
6.36.2 Temporarily pausing the watchdog ...................... 570
6.36.3 Watchdog reset .............................. 570
6.36.4 Registers ................................. 571
6.36.5 Electrical specification ........................... 574
7Hardware and layout.............................575
7.1 Pin assignments ................................ 575
7.1.1 aQFN73 ball assignments .......................... 575
7.1.2 WLCSP ball assignments ........................... 578
7.2 Mechanical specifications ............................ 581
7.2.1 aQFN73 7 x 7 mm package ......................... 581
7.2.2 WLCSP 3.544 x 3.607 mm package ...................... 582
7.3 Reference circuitry ............................... 583
7.3.1 Circuit configuration no. 1 .......................... 584
7.3.2 Circuit configuration no. 2 .......................... 586
7.3.3 Circuit configuration no. 3 .......................... 588
7.3.4 Circuit configuration no. 4 .......................... 590
7.3.5 Circuit configuration no. 5 .......................... 592
7.3.6 Circuit configuration no. 6 .......................... 594
7.3.7 Circuit configuration no. 1 for CKAA WLCSP ................... 596
7.3.8 Circuit configuration no. 2 for CKAA WLCSP ................... 598
7.3.9 Circuit configuration no. 3 for CKAA WLCSP ................... 600
7.3.10 Circuit configuration no. 4 for CKAA WLCSP .................. 602
7.3.11 Circuit configuration no. 5 for CKAA WLCSP .................. 604
7.3.12 Circuit configuration no. 6 for CKAA WLCSP .................. 606
4413_417 v1.1 x
7.3.13 PCB guidelines .............................. 608
7.3.14 PCB layout example ............................ 609
8Recommended operating conditions.................... 611
9Absolute maximum ratings......................... 612
10 Ordering information............................ 613
10.1 Package marking ............................... 613
10.2 Box labels .................................. 613
10.3 Order code ................................. 614
10.4 Code ranges and values ............................ 615
10.5 Product options ............................... 616
11 Legal notices................................. 618
11.1 Liability disclaimer .............................. 618
11.2 Life support applications ............................ 618
11.3 RoHS and REACH statement .......................... 618
11.4 Trademarks ................................. 618
11.5 Copyright notice ............................... 619
4413_417 v1.1 xi
1Revision history
Date Version Description
February 2019 1.1 The following content has been added or updated:
• Added information for the WLCSP package variant in Pin
assignments on page 575, Mechanical specifications on
page 581, Reference circuitry on page 583, FICR —
Factory information configuration registers on page 31,
Absolute maximum ratings on page 612, and Ordering
information on page 613.
•Reference circuitry on page 583: Updated RF-Match in
aQFN™73 reference circuitry for all configurations. Added
optional 4.7 Ω resistor to USB supply.
•UICR — User information configuration registers on page
42: Removed NRFFW[13] and NRFFW[14] registers.
•CPU on page 19: Corrected value of parameter
CMFLASH/mA.
•POWER — Power supply on page 61: Clarified range of
voltages in both Normal and High voltage modes.
•CLOCK — Clock control on page 82: Corrected value of
parameter PD_LFXO to a less restrictive value.
•EasyDMA on page 46: Added section about EasyDMA
error handling. Corrected example code in section
EasyDMA array list.
•NVMC — Non-volatile memory controller on page 24:
Added note about the necessity to halt the CPU before
isuing NVMC commands from the debugger.
•ACL — Access control lists on page 107: Corrected
register access to ReadWriteOnce (RWO) for some
registers.
•I2S — Inter-IC sound interface on page 163: Removed
invalid values from register MCKFREQ, see parameter fMCK.
Fixed figure for Memory mapping for 8-bit stereo.
•SAADC — Successive approximation analog-to-digital
converter on page 376: Corrected description of
functionality of SAMPLE task.
•SPIS — Serial peripheral interface slave with EasyDMA
on page 422: Exposed the LIST register. Corrected SPI
modes table.
•TWIS — I2C compatible two-wire interface slave with
EasyDMA on page 482: Exposed the LIST register.
•UART — Universal asynchronous receiver/transmitter on
page 499: Added STOP bit configuration description.
•RADIO — 2.4 GHz radio on page 307: Added equations
to convert from HW RSSI to 802.15.4 range and dBm.
Clarified RSSI timing. Clarified that TX ramp up time is
affected by RU field in MODECNF0. Added IEEE 802.15.4
4413_417 v1.1 12
Revision history
Date Version Description
radio timing parameters to the electrical specifications.
Added sensitivity parameter for 2 Mbit NRF mode.
•USBD — Universal serial bus device on page 529:
Pointed that isochronous transfers have to be finished
before the next SOF event, or the result of the transfer is
undefined.
•Legal notices on page 618: Updated text and image.
March 2018 1.0 First release
4413_417 v1.1 13
2About this document
This product specification is organized into chapters based on the modules and peripherals that are
available in this IC.
The peripheral descriptions are divided into separate sections that include the following information:
• A detailed functional description of the peripheral
• Register configuration for the peripheral
• Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 611.
2.1 Document naming and status
Nordic uses three distinct names for this document, which are reflecting the maturity and the status of the
document and its content.
Document name Description
Objective Product Specification (OPS) Applies to document versions up to 0.7.
This product specification contains target
specifications for product development.
Preliminary Product Specification (PPS) Applies to document versions 0.7 and up to 1.0.
This product specification contains preliminary
data. Supplementary data may be published from
Nordic Semiconductor ASA later.
Product Specification (PS) Applies to document versions 1.0 and higher.
This product specification contains final product
specifications. Nordic Semiconductor ASA reserves
the right to make changes at any time without
notice in order to improve design and supply the
best possible product.
Table 1: Defined document names
2.2 Peripheral naming and abbreviations
Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for
identification and reference. This name is used in chapter headings and references, and it will appear in
the ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to
identify the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is
normally only used if a peripheral can be instantiated more than once. The peripheral instance name is
also used in the CMSIS to identify the peripheral instance.
4413_417 v1.1 14
About this document
2.3 Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three colored rows describe the position and size of the different fields in the register. The following rows
describe the fields in more detail.
2.3.1 Fields and values
The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has
enumerated values, then every value will be identified with a unique value id in the Value Id column.
A blank space means that the field is reserved and read as undefined, and it also must be written as 0
to secure forward compatibility. If a register is divided into more than one field, a unique field name is
specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when
values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/
off, and so on.
Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal
values have no prefix.
The Value column can be populated in the following ways:
• Individual enumerated values, for example 1, 3, 9.
• Range of values, e.g. [0..4], indicating all values from and including 0 and 4.
• Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field's translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but
the first field. Subsequent fields will indicate inheritance with '..'.
A feature marked Deprecated should not be used for new designs.
2.4 Registers
Register Offset Description
DUMMY 0x514 Example of a register controlling a dummy feature
Table 2: Register overview
2.4.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D C C C B A A
Reset 0x00050002 0 0000000000001010000000000000010
ID AccessField Value ID Value Description
A RW FIELD_A Example of a field with several enumerated values
Disabled 0 The example feature is disabled
NormalMode 1 The example feature is enabled in normal mode
ExtendedMode 2 The example feature is enabled along with extra
functionality
4413_417 v1.1 15
About this document
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D C C C B A A
Reset 0x00050002 0 0000000000001010000000000000010
ID AccessField Value ID Value Description
B RW FIELD_B Example of a deprecated field Deprecated
Disabled 0 The override feature is disabled
Enabled 1 The override feature is enabled
C RW FIELD_C Example of a field with a valid range of values
ValidRange [2..7] Example of allowed values for this field
D RW FIELD_D Example of a field with no restriction on the values
4413_417 v1.1 16
3Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that share
physical pins with other signals.
4413_417 v1.1 17
Block diagram
nRF52840
APB0
AHB TO APB
BRIDGE
RADIO
CPU
ARM
CORTEX-M4
AHB-AP
RNG
TEMP
WDT
NVMC
ANT
POWER
nRESET RTC [0..2]
PPI
TIMER [0..4]
NVIC
UICRFICR
SW-DP
CODE
EasyDMA master
QDEC
SAADC
GPIOTE
P0.0 – P0.31
P1.0 – P1.15
AIN0 – AIN7
LED
A
B
UARTE [0..1]
SPIS [0..2] MOSI
MISO
CSN
COMP
EasyDMA
RXD
TXD
CTS
RTS
ETM
SysTick
TPIU
TP
EasyDMA
LPCOMP
EasyDMA
master
master
NFCT
NFC1
NFC2
EasyDMA master
master
SWDIO
SWCLK
CTRL-AP
PWM [0..3]
OUT0 – OUT3
I2S
MCK
LRCK
SCL
SDOUT
SDIN
PDM
CLK
DIN
SCK
EasyDMA master
EasyDMA master
EasyDMA master
I-Cache
slave
slave
slave
slave
slave
master
CLOCK
XL2
XL1
XC2
XC1
USBD
D-
D+
EasyDMA master
VBUS
SPIM [0..3]
SCK
MISO
EasyDMA
MOSI
master
TWIM [0..1] SCL
SDA
EasyDMA
master
QSPI IO3
IO2
IO1
IO0
EasyDMA
master CSN
SCK
ECB
EasyDMA
master
CCM
EasyDMA
master
AAR
EasyDMA
master
CryptoCell
DMA
master
TWIS [0..1] SCL
SDA
EasyDMA
master
RAM0
slave
RAM1
slave
RAM2
slave
RAM3
slave
RAM4
slave
RAM5
slave
RAM6
slave
RAM7
slave
GPIO
slave
RAM8
slave
AHB multilayer
P0.0 – P0.31
P1.0 – P1.15
P0.0 – P0.31
P1.0 – P1.15
Figure 1: Block diagram
4413_417 v1.1 18
4Core components
4.1 CPU
The ARM® Cortex-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2
technology) that implements a superset of 16- and 32-bit instructions to maximize code density and
performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing, including:
• Digital signal processing (DSP) instructions
• Single-cycle multiply and accumulate (MAC) instructions
• Hardware divide
• 8- and 16-bit single instruction multiple data (SIMD) instructions
• Single-precision floating-point unit (FPU)
The ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM®Cortex® processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 series. An instruction cache can
be enabled to minimize flash wait states when fetching instructions. For more information on cache,
see Cache on page 26. The section Electrical specification on page 20 shows CPU performance
parameters including wait states in different modes, CPU current and efficiency, and processing power and
efficiency based on the CoreMark® benchmark.
The ARM system timer (SysTick) is present on nRF52840. The SysTick's clock will only tick when the CPU is
running or when the system is in debug interface mode.
4.1.1 Floating point interrupt
The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which
in turn will trigger the FPU interrupt.
See Instantiation on page 23 for more information about the exceptions triggering the FPU interrupt.
To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within
the floating-point status and control register (FPSCR) needs to be cleared. For more information about the
FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
4.1.2 CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the
device.
4413_417 v1.1 19
Core components
Option / Module Description Implemented
Core options
NVIC Nested vector interrupt controller 48 vectors
PRIORITIES Priority bits 3
WIC Wakeup interrupt controller NO
Endianness Memory system endianness Little endian
Bit-banding Bit banded memory NO
DWT Data watchpoint and trace YES
SysTick System tick timer YES
Modules
MPU Memory protection unit YES
FPU Floating-point unit YES
DAP Debug access port YES
ETM Embedded trace macrocell YES
ITM Instrumentation trace macrocell YES
TPIU Trace port interface unit YES
ETB Embedded trace buffer NO
FPB Flash patch and breakpoint unit YES
HTM AMBA™ AHB trace macrocell NO
4.1.3 Electrical specification
4.1.3.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol Description Min. Typ. Max. Units
WFLASH CPU wait states, running CoreMark from flash, cache
disabled
2
WFLASHCACHE CPU wait states, running CoreMark from flash, cache
enabled
3
WRAM CPU wait states, running CoreMark from RAM 0
CMFLASH CoreMark, running CoreMark from flash, cache enabled 212 CoreMark
CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache
enabled
3.3 CoreMark/
MHz
CMFLASH/mA CoreMark per mA, running CoreMark from flash, cache
enabled, DCDC 3V
64 CoreMark/
mA
4.2 Memory
The nRF52840 contains 1 MB of flash and 256 kB of RAM that can be used for code and data storage.
The CPU and peripherals with EasyDMA can access memory via the AHB multilayer interconnect.
The CPU is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Memory
layout on page 21.
4413_417 v1.1 20
Core components
RAM3
AHB slave
RAM2
AHB slave
RAM1
AHB slave
RAM0
AHB slave
RAM7
AHB slave
RAM6
AHB slave
RAM5
AHB slave
RAM4
AHB slave
AHB multilayer interconnect
AHB
slave
Page 0
Page 1
Page 2
Page 3..254
Page 255
0x0000 0000
0x0000 2000
0x0000 3000
0x000F F000
Flash
ICODE/DCODE
AHB
slave
NVMC
ICODE
DCODE
Peripheral
EasyDMA
DMA bus
Peripheral
EasyDMA
DMA bus
CPU
ARM Cortex-M4
System bus
ICODE
DCODE
AHB2APB
AHB
APB
0x0000 1000
I-Cache
0x2000 0000
0x2000 1000
0x2000 2000
0x2000 3000
0x2000 4000
0x2000 5000
0x2000 6000
0x2000 7000
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
0x2000 8000
0x2000 9000
0x2000 A000
0x2000 B000
0x2000 C000
0x2000 D000
0x2000 E000
0x2000 F000
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Data RAM
System
0x0080 0000
0x0080 1000
0x0080 2000
0x0080 3000
0x0080 4000
0x0080 5000
0x0080 6000
0x0080 7000
0x0080 8000
0x0080 9000
0x0080 A000
0x0080 B000
0x0080 C000
0x0080 D000
0x0080 E000
0x0080 F000
Code RAM
ICODE / DCODE
Section 0
Section 1
Section 2
Section 3
Section 4
Section 5
0x2001 0000 0x0081 0000
0x2001 8000 0x0081 8000
0x2002 0000 0x0082 0000
0x2002 8000 0x0082 8000
0x2003 0000 0x0083 0000
0x2003 8000 0x0083 8000
RAM8
AHB slave
Figure 2: Memory layout
See AHB multilayer on page 49 and EasyDMA on page 46 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
4.2.1 RAM - Random access memory
The RAM interface is divided into 9 RAM AHB slaves.
RAM AHB slave 0-7 is connected to 2x4 kB RAM sections each and RAM AHB slave 8 is connected to 6x32
kB sections, as shown in Memory layout on page 21.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,
which is configured via RAM register (see the POWER — Power supply on page 61).
4.2.2 Flash - Non-volatile memory
The flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased and also on how it can be written.
Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 24.
The flash is divided into 256 pages of 4 kB each that can be accessed by the CPU via both the ICODE and
DCODE buses as shown in Memory layout on page 21.
4.2.3 Memory map
The complete memory map for the nRF52840 is shown in Memory map on page 22. As described in
Memory on page 20, Code RAM and Data RAM are the same physical RAM.
4413_417 v1.1 21
Core components
Device
Device
Device
RAM
RAM
Peripheral
SRAM
Code
Private peripheral bus
AHB peripherals
APB peripherals
UICR
FICR
Data RAM
Code RAM
Flash
0xFFFFFFFF
0x00000000
0x20000000
0x40000000
0x60000000
0x80000000
0xA0000000
0xC0000000
0xE0000000
0x00000000
0x10000000
0x40000000
0x50000000
0xE0000000
0x00800000
0x10001000
0x20000000
XIP 0x12000000
0x19FFFFFF
System address map Address map
Figure 3: Memory map
4413_417 v1.1 22
Core components
4.2.4 Instantiation
ID Base address Peripheral Instance Description
0 0x40000000 CLOCK CLOCK Clock control
0 0x40000000 POWER POWER Power control
0 0x50000000 GPIO GPIO General purpose input and output Deprecated
0 0x50000000 GPIO P0 General purpose input and output, port 0
0 0x50000300 GPIO P1 General purpose input and output, port 1
1 0x40001000 RADIO RADIO 2.4 GHz radio
2 0x40002000 UART UART0 Universal asynchronous receiver/transmitter Deprecated
2 0x40002000 UARTE UARTE0 Universal asynchronous receiver/transmitter with EasyDMA,
unit 0
3 0x40003000 SPI SPI0 SPI master 0 Deprecated
3 0x40003000 SPIM SPIM0 SPI master 0
3 0x40003000 SPIS SPIS0 SPI slave 0
3 0x40003000 TWI TWI0 Two-wire interface master 0 Deprecated
3 0x40003000 TWIM TWIM0 Two-wire interface master 0
3 0x40003000 TWIS TWIS0 Two-wire interface slave 0
4 0x40004000 SPI SPI1 SPI master 1 Deprecated
4 0x40004000 SPIM SPIM1 SPI master 1
4 0x40004000 SPIS SPIS1 SPI slave 1
4 0x40004000 TWI TWI1 Two-wire interface master 1 Deprecated
4 0x40004000 TWIM TWIM1 Two-wire interface master 1
4 0x40004000 TWIS TWIS1 Two-wire interface slave 1
5 0x40005000 NFCT NFCT Near field communication tag
6 0x40006000 GPIOTE GPIOTE GPIO tasks and events
7 0x40007000 SAADC SAADC Analog to digital converter
8 0x40008000 TIMER TIMER0 Timer 0
9 0x40009000 TIMER TIMER1 Timer 1
10 0x4000A000 TIMER TIMER2 Timer 2
11 0x4000B000 RTC RTC0 Real-time counter 0
12 0x4000C000 TEMP TEMP Temperature sensor
13 0x4000D000 RNG RNG Random number generator
14 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption
15 0x4000F000 AAR AAR Accelerated address resolver
15 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption
16 0x40010000 WDT WDT Watchdog timer
17 0x40011000 RTC RTC1 Real-time counter 1
18 0x40012000 QDEC QDEC Quadrature decoder
19 0x40013000 COMP COMP General purpose comparator
19 0x40013000 LPCOMP LPCOMP Low power comparator
20 0x40014000 EGU EGU0 Event generator unit 0
20 0x40014000 SWI SWI0 Software interrupt 0
21 0x40015000 EGU EGU1 Event generator unit 1
21 0x40015000 SWI SWI1 Software interrupt 1
22 0x40016000 EGU EGU2 Event generator unit 2
22 0x40016000 SWI SWI2 Software interrupt 2
23 0x40017000 EGU EGU3 Event generator unit 3
23 0x40017000 SWI SWI3 Software interrupt 3
24 0x40018000 EGU EGU4 Event generator unit 4
24 0x40018000 SWI SWI4 Software interrupt 4
25 0x40019000 EGU EGU5 Event generator unit 5
25 0x40019000 SWI SWI5 Software interrupt 5
4413_417 v1.1 23
Core components
ID Base address Peripheral Instance Description
26 0x4001A000 TIMER TIMER3 Timer 3
27 0x4001B000 TIMER TIMER4 Timer 4
28 0x4001C000 PWM PWM0 Pulse width modulation unit 0
29 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface
30 0x4001E000 ACL ACL Access control lists
30 0x4001E000 NVMC NVMC Non-volatile memory controller
31 0x4001F000 PPI PPI Programmable peripheral interconnect
32 0x40020000 MWU MWU Memory watch unit
33 0x40021000 PWM PWM1 Pulse width modulation unit 1
34 0x40022000 PWM PWM2 Pulse width modulation unit 2
35 0x40023000 SPI SPI2 SPI master 2 Deprecated
35 0x40023000 SPIM SPIM2 SPI master 2
35 0x40023000 SPIS SPIS2 SPI slave 2
36 0x40024000 RTC RTC2 Real-time counter 2
37 0x40025000 I2S I2S Inter-IC sound interface
38 0x40026000 FPU FPU FPU interrupt
39 0x40027000 USBD USBD Universal serial bus device
40 0x40028000 UARTE UARTE1 Universal asynchronous receiver/transmitter with EasyDMA,
unit 1
41 0x40029000 QSPI QSPI External memory interface
42 0x5002A000 CC_HOST_RGF CC_HOST_RGF Host platform interface
42 0x5002A000 CRYPTOCELL CRYPTOCELL CryptoCell subsystem control interface
45 0x4002D000 PWM PWM3 Pulse width modulation unit 3
47 0x4002F000 SPIM SPIM3 SPI master 3
N/A 0x10000000 FICR FICR Factory information configuration
N/A 0x10001000 UICR UICR User information configuration
Table 3: Instantiation table
4.3 NVMC — Non-volatile memory controller
The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory
and the UICR (user information configuration registers).
The CONFIG on page 27 is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing
(CONFIG.WEN = Een). The user must make sure that writing and erasing are not enabled at the same time.
Having both enabled at the same time may result in unpredictable behavior.
The CPU must be halted before initiating a NVMC operation from the debug system.
4.3.1 Writing to flash
When write is enabled, full 32-bit words can be written to word-aligned addresses in the flash.
As illustrated in Memory on page 20, the flash is divided into multiple pages. The same 32-bit word in
the flash can only be written n WRITE number of times before a page erase must be performed.
The NVMC is only able to write 0 to bits in the flash that are erased (set to 1). It cannot rewrite a bit back
to 1. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits,
write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1.
Note that the restriction on the number of writes (nWRITE) still applies in this case.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code
from the flash while the NVMC is writing to the flash.
4413_417 v1.1 24
Core components
NVM writing time can be reduced by using READYNEXT. If this status bit is set to '1', code can perform
the next data write to the flash. This write will be buffered and will be taken into account as soon as the
ongoing write operation is completed.
4.3.2 Erasing a page in flash
When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page
27.
After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified
by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the
flash.
See Partial erase of a page in flash on page 25 for information on dividing the page erase time into
shorter chunks.
4.3.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as flash. After UICR has been
written, the new UICR configuration will only take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR on
page 29 or ERASEALL on page 28. The time it takes to write a word to UICR is specified by tWRITE.
The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR.
4.3.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR on page 29.
After erasing UICR all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. The
CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.
4.3.5 Erase all
When erase is enabled, flash and UICR can be erased completely in one operation by using the ERASEALL
on page 28. This operation will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted if the CPU
executes code from the flash while the NVMC performs the erase operation.
4.3.6 Access port protection behavior
When access port protection is enabled, parts of the NVMC functionality will be blocked in order to
prevent intentional or unintentional erase of UICR.
CTRL-AP ERASEALL NVMC ERASEPAGE NVMC ERASEPAGE
PARTIAL
NVMC ERASEALL NVMC ERASEUICR
APPROTECT
Disabled Allowed Allowed Allowed Allowed Allowed
Enabled Allowed Allowed Allowed Allowed Blocked
Table 4: NVMC Protection
4.3.7 Partial erase of a page in flash
Partial erase is a feature in the NVMC to split a page erase time into shorter chunks, so this can be used to
prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in
the flash and does not work with UICR.
4413_417 v1.1 25
Core components
When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL
on page 29. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page
29. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number
of times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the
cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one
erase cycle.
After the erase is done, all bits in the page are set to '1'. The CPU is halted if the CPU executes code from
the flash while the NVMC performs the partial erase operation.
The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started
but the total erase time is less than tERASEPAGE.
4.3.8 Cache
An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
See the Memory map in Memory map on page 21 for the location of flash.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-
states for a cache miss, where the instruction is not available in the cache and needs to be fetched from
flash, depends on the processor frequency and is shown in CPU on page 19
Enabling the cache can increase CPU performance and reduce power consumption by reducing the
number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will
use some current when enabled. If the reduction in average current due to reduced flash accesses is larger
than the cache power requirement, the average current to execute the program code will reduce.
When disabled, the cache does not use current and does not retain its content.
It is possible to enable cache profiling to analyze the performance of the cache for your program using
the ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every
instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after
reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to
get correct numbers.
4.3.9 Registers
Base address Peripheral Instance Description Configuration
0x4001E000 NVMC NVMC Non-volatile memory controller
Table 5: Instances
Register Offset Description
READY 0x400 Ready flag
READYNEXT 0x408 Ready flag
CONFIG 0x504 Configuration register
ERASEPAGE 0x508 Register for erasing a page in code area
ERASEPCR1 0x508 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated
ERASEALL 0x50C Register for erasing all non-volatile user memory
ERASEPCR0 0x510 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated
ERASEUICR 0x514 Register for erasing user information configuration registers
ERASEPAGEPARTIAL 0x518 Register for partial erase of a page in code area
ERASEPAGEPARTIALCFG 0x51C Register for partial erase configuration
ICACHECNF 0x540 I-code cache configuration register.
IHIT 0x548 I-code cache hit counter.
4413_417 v1.1 26
Core components
Register Offset Description
IMISS 0x54C I-code cache miss counter.
Table 6: Register overview
4.3.9.1 READY
Address offset: 0x400
Ready flag
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000001 0 0000000000000000000000000000001
ID AccessField Value ID Value Description
A R READY NVMC is ready or busy
Busy 0 NVMC is busy (on-going write or erase operation)
Ready 1 NVMC is ready
4.3.9.2 READYNEXT
Address offset: 0x408
Ready flag
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R READYNEXT NVMC can accept a new write operation
Busy 0 NVMC cannot accept any write operation
Ready 1 NVMC is ready
4.3.9.3 CONFIG
Address offset: 0x504
Configuration register
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW WEN Program memory access mode. It is strongly recommended
to only activate erase and write modes when they are
actively used. Enabling write or erase will invalidate the
cache and keep it invalidated.
Ren 0 Read only access
Wen 1 Write enabled
Een 2 Erase enabled
4.3.9.4 ERASEPAGE
Address offset: 0x508
Register for erasing a page in code area
4413_417 v1.1 27
Core components
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ERASEPAGE Register for starting erase of a page in code area
The value is the address to the page to be erased.
(Addresses of first word in page). Note that the erase must
be enabled using CONFIG.WEN before the page can be
erased. Attempts to erase pages that are outside the code
area may result in undesirable behaviour, e.g. the wrong
page may be erased.
4.3.9.5 ERASEPCR1 ( Deprecated )
Address offset: 0x508
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ERASEPCR1 Register for erasing a page in code area. Equivalent to
ERASEPAGE.
4.3.9.6 ERASEALL
Address offset: 0x50C
Register for erasing all non-volatile user memory
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ERASEALL Erase all non-volatile memory including UICR registers. Note
that the erase must be enabled using CONFIG.WEN before
the non-volatile memory can be erased.
NoOperation 0 No operation
Erase 1 Start chip erase
4.3.9.7 ERASEPCR0 ( Deprecated )
Address offset: 0x510
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ERASEPCR0 Register for starting erase of a page in code area. Equivalent
to ERASEPAGE.
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4.3.9.8 ERASEUICR
Address offset: 0x514
Register for erasing user information configuration registers
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ERASEUICR Register starting erase of all user information configuration
registers. Note that the erase must be enabled using
CONFIG.WEN before the UICR can be erased.
NoOperation 0 No operation
Erase 1 Start erase of UICR
4.3.9.9 ERASEPAGEPARTIAL
Address offset: 0x518
Register for partial erase of a page in code area
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ERASEPAGEPARTIAL Register for starting partial erase of a page in code area
The value is the address to the page to be partially erased
(address of the first word in page). Note that the erase must
be enabled using CONFIG.WEN before every erase page
partial and disabled using CONFIG.WEN after every erase
page partial. Attempts to erase pages that are outside the
code area may result in undesirable behaviour, e.g. the
wrong page may be erased.
4.3.9.10 ERASEPAGEPARTIALCFG
Address offset: 0x51C
Register for partial erase configuration
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAA
Reset 0x0000000A 0 0000000000000000000000000001010
ID AccessField Value ID Value Description
A RW DURATION Duration of the partial erase in milliseconds
The user must ensure that the total erase time is long
enough for a complete erase of the flash page.
4.3.9.11 ICACHECNF
Address offset: 0x540
I-code cache configuration register.
4413_417 v1.1 29
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW CACHEEN Cache enable
Disabled 0 Disable cache. Invalidates all cache entries.
Enabled 1 Enable cache
B RW CACHEPROFEN Cache profiling enable
Disabled 0 Disable cache profiling
Enabled 1 Enable cache profiling
4.3.9.12 IHIT
Address offset: 0x548
I-code cache hit counter.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW HITS Number of cache hits
4.3.9.13 IMISS
Address offset: 0x54C
I-code cache miss counter.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW MISSES Number of cache misses
4.3.10 Electrical specification
4.3.10.1 Flash programming
Symbol Description Min. Typ. Max. Units
nWRITE Number of times a 32-bit word can be written before erase 2
nENDURANCE Erase cycles per page 10000
tWRITE Time to write one 32-bit word 411µs
tERASEPAGE Time to erase one page 851ms
tERASEALL Time to erase all flash 1691ms
tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total
execution time for one partial page erase is defined as
ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc.
1.051
1Applies when HFXO is used. Timing varies according to HFINT accuracy when HFINT is used.
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4.3.10.2 Cache size
Symbol Description Min. Typ. Max. Units
SizeICODE I-Code cache size 2048 Bytes
4.4 FICR — Factory information configuration registers
Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by
the user. These registers contain chip-specific information and configuration.
4.4.1 Registers
Base address Peripheral Instance Description Configuration
0x10000000 FICR FICR Factory information configuration
Table 7: Instances
Register Offset Description
CODEPAGESIZE 0x010 Code memory page size
CODESIZE 0x014 Code memory size
DEVICEID[0] 0x060 Device identifier
DEVICEID[1] 0x064 Device identifier
ER[0] 0x080 Encryption root, word 0
ER[1] 0x084 Encryption root, word 1
ER[2] 0x088 Encryption root, word 2
ER[3] 0x08C Encryption root, word 3
IR[0] 0x090 Identity Root, word 0
IR[1] 0x094 Identity Root, word 1
IR[2] 0x098 Identity Root, word 2
IR[3] 0x09C Identity Root, word 3
DEVICEADDRTYPE 0x0A0 Device address type
DEVICEADDR[0] 0x0A4 Device address 0
DEVICEADDR[1] 0x0A8 Device address 1
INFO.PART 0x100 Part code
INFO.VARIANT 0x104 Build code (hardware version and production configuration)
INFO.PACKAGE 0x108 Package option
INFO.RAM 0x10C RAM variant
INFO.FLASH 0x110 Flash variant
INFO.UNUSED8[0] 0x114 Reserved
INFO.UNUSED8[1] 0x118 Reserved
INFO.UNUSED8[2] 0x11C Reserved
PRODTEST[0] 0x350 Production test signature 0
PRODTEST[1] 0x354 Production test signature 1
PRODTEST[2] 0x358 Production test signature 2
TEMP.A0 0x404 Slope definition A0
TEMP.A1 0x408 Slope definition A1
TEMP.A2 0x40C Slope definition A2
TEMP.A3 0x410 Slope definition A3
TEMP.A4 0x414 Slope definition A4
TEMP.A5 0x418 Slope definition A5
TEMP.B0 0x41C Y-intercept B0
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Register Offset Description
TEMP.B1 0x420 Y-intercept B1
TEMP.B2 0x424 Y-intercept B2
TEMP.B3 0x428 Y-intercept B3
TEMP.B4 0x42C Y-intercept B4
TEMP.B5 0x430 Y-intercept B5
TEMP.T0 0x434 Segment end T0
TEMP.T1 0x438 Segment end T1
TEMP.T2 0x43C Segment end T2
TEMP.T3 0x440 Segment end T3
TEMP.T4 0x444 Segment end T4
NFC.TAGHEADER0 0x450 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
NFC.TAGHEADER1 0x454 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
NFC.TAGHEADER2 0x458 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
NFC.TAGHEADER3 0x45C Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
TRNG90B.BYTES 0xC00 Amount of bytes for the required entropy bits
TRNG90B.RCCUTOFF 0xC04 Repetition counter cutoff
TRNG90B.APCUTOFF 0xC08 Adaptive proportion cutoff
TRNG90B.STARTUP 0xC0C Amount of bytes for the startup tests
TRNG90B.ROSC1 0xC10 Sample count for ring oscillator 1
TRNG90B.ROSC2 0xC14 Sample count for ring oscillator 2
TRNG90B.ROSC3 0xC18 Sample count for ring oscillator 3
TRNG90B.ROSC4 0xC1C Sample count for ring oscillator 4
Table 8: Register overview
4.4.1.1 CODEPAGESIZE
Address offset: 0x010
Code memory page size
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R CODEPAGESIZE Code memory page size
4.4.1.2 CODESIZE
Address offset: 0x014
Code memory size
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R CODESIZE Code memory size in number of pages
Total code space is: CODEPAGESIZE * CODESIZE
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4.4.1.3 DEVICEID[n] (n=0..1)
Address offset: 0x060 + (n × 0x4)
Device identifier
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R DEVICEID 64 bit unique device identifier
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of
the device identifier.
4.4.1.4 ER[n] (n=0..3)
Address offset: 0x080 + (n × 0x4)
Encryption root, word n
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R ER Encryption root, word n
4.4.1.5 IR[n] (n=0..3)
Address offset: 0x090 + (n × 0x4)
Identity Root, word n
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R IR Identity Root, word n
4.4.1.6 DEVICEADDRTYPE
Address offset: 0x0A0
Device address type
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R DEVICEADDRTYPE Device address type
Public 0 Public address
Random 1 Random address
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4.4.1.7 DEVICEADDR[n] (n=0..1)
Address offset: 0x0A4 + (n × 0x4)
Device address n
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R DEVICEADDR 48 bit device address
DEVICEADDR[0] contains the least significant bits of
the device address. DEVICEADDR[1] contains the most
significant bits of the device address. Only bits [15:0] of
DEVICEADDR[1] are used.
4.4.1.8 INFO.PART
Address offset: 0x100
Part code
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00052840 0 0000000000001010010100001000000
ID AccessField Value ID Value Description
A R PART Part code
N52840 0x52840 nRF52840
Unspecified 0xFFFFFFFF Unspecified
4.4.1.9 INFO.VARIANT
Address offset: 0x104
Build code (hardware version and production configuration)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R VARIANT Build code (hardware version and production
configuration). Encoded as ASCII.
AAAA 0x41414141 AAAA
BAAA 0x42414141 BAAA
CAAA 0x43414141 CAAA
AABA 0x41414241 AABA
AABB 0x41414242 AABB
AACA 0x41414341 AACA
AAAB 0x41414142 AAAB
Unspecified 0xFFFFFFFF Unspecified
4.4.1.10 INFO.PACKAGE
Address offset: 0x108
4413_417 v1.1 34
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Package option
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R PACKAGE Package option
QI 0x2004 QIxx - 73-pin aQFN
CK 0x2005 CKxx - WLCSP
Unspecified 0xFFFFFFFF Unspecified
4.4.1.11 INFO.RAM
Address offset: 0x10C
RAM variant
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R RAM RAM variant
K16 0x10 16 kByte RAM
K32 0x20 32 kByte RAM
K64 0x40 64 kByte RAM
K128 0x80 128 kByte RAM
K256 0x100 256 kByte RAM
Unspecified 0xFFFFFFFF Unspecified
4.4.1.12 INFO.FLASH
Address offset: 0x110
Flash variant
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R FLASH Flash variant
K128 0x80 128 kByte FLASH
K256 0x100 256 kByte FLASH
K512 0x200 512 kByte FLASH
K1024 0x400 1 MByte FLASH
K2048 0x800 2 MByte FLASH
Unspecified 0xFFFFFFFF Unspecified
4.4.1.13 PRODTEST[n] (n=0..2)
Address offset: 0x350 + (n × 0x4)
Production test signature n
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R PRODTEST Production test signature n
Done 0xBB42319F Production tests done
NotDone 0xFFFFFFFF Production tests not done
4.4.1.14 TEMP.A0
Address offset: 0x404
Slope definition A0
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAA
Reset 0xFFFFF320 1 1111111111111111111001100100000
ID AccessField Value ID Value Description
A R A A (slope definition) register.
4.4.1.15 TEMP.A1
Address offset: 0x408
Slope definition A1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAA
Reset 0xFFFFF343 1 1111111111111111111001101000011
ID AccessField Value ID Value Description
A R A A (slope definition) register.
4.4.1.16 TEMP.A2
Address offset: 0x40C
Slope definition A2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAA
Reset 0xFFFFF35D 1 1111111111111111111001101011101
ID AccessField Value ID Value Description
A R A A (slope definition) register.
4.4.1.17 TEMP.A3
Address offset: 0x410
Slope definition A3
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAA
Reset 0xFFFFF400 1 1111111111111111111010000000000
ID AccessField Value ID Value Description
A R A A (slope definition) register.
4.4.1.18 TEMP.A4
Address offset: 0x414
Slope definition A4
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAA
Reset 0xFFFFF452 1 1111111111111111111010001010010
ID AccessField Value ID Value Description
A R A A (slope definition) register.
4.4.1.19 TEMP.A5
Address offset: 0x418
Slope definition A5
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAA
Reset 0xFFFFF37B 1 1111111111111111111001101111011
ID AccessField Value ID Value Description
A R A A (slope definition) register.
4.4.1.20 TEMP.B0
Address offset: 0x41C
Y-intercept B0
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAAAA
Reset 0xFFFF3FCC 1 1111111111111110011111111001100
ID AccessField Value ID Value Description
A R B B (y-intercept)
4.4.1.21 TEMP.B1
Address offset: 0x420
Y-intercept B1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAAAA
Reset 0xFFFF3F98 1 1111111111111110011111110011000
ID AccessField Value ID Value Description
A R B B (y-intercept)
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4.4.1.22 TEMP.B2
Address offset: 0x424
Y-intercept B2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAAAA
Reset 0xFFFF3F98 1 1111111111111110011111110011000
ID AccessField Value ID Value Description
A R B B (y-intercept)
4.4.1.23 TEMP.B3
Address offset: 0x428
Y-intercept B3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAAAA
Reset 0xFFFF0012 1 1111111111111110000000000010010
ID AccessField Value ID Value Description
A R B B (y-intercept)
4.4.1.24 TEMP.B4
Address offset: 0x42C
Y-intercept B4
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAAAA
Reset 0xFFFF004D 1 1111111111111110000000001001101
ID AccessField Value ID Value Description
A R B B (y-intercept)
4.4.1.25 TEMP.B5
Address offset: 0x430
Y-intercept B5
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAAAAAAAA
Reset 0xFFFF3E10 1 1111111111111110011111000010000
ID AccessField Value ID Value Description
A R B B (y-intercept)
4.4.1.26 TEMP.T0
Address offset: 0x434
Segment end T0
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0xFFFFFFE2 1 1111111111111111111111111100010
ID AccessField Value ID Value Description
A R T T (segment end) register
4.4.1.27 TEMP.T1
Address offset: 0x438
Segment end T1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0xFFFFFF00 1 1111111111111111111111100000000
ID AccessField Value ID Value Description
A R T T (segment end) register
4.4.1.28 TEMP.T2
Address offset: 0x43C
Segment end T2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0xFFFFFF14 1 1111111111111111111111100010100
ID AccessField Value ID Value Description
A R T T (segment end) register
4.4.1.29 TEMP.T3
Address offset: 0x440
Segment end T3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0xFFFFFF19 1 1111111111111111111111100011001
ID AccessField Value ID Value Description
A R T T (segment end) register
4.4.1.30 TEMP.T4
Address offset: 0x444
Segment end T4
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0xFFFFFF50 1 1111111111111111111111101010000
ID AccessField Value ID Value Description
A R T T (segment end) register
4413_417 v1.1 39
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4.4.1.31 NFC.TAGHEADER0
Address offset: 0x450
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFF5F 1 1111111111111111111111101011111
ID AccessField Value ID Value Description
A R MFGID Default Manufacturer ID: Nordic Semiconductor ASA has
ICM 0x5F
B R UD1 Unique identifier byte 1
C R UD2 Unique identifier byte 2
D R UD3 Unique identifier byte 3
4.4.1.32 NFC.TAGHEADER1
Address offset: 0x454
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A-D R UD[i] (i=4..7) Unique identifier byte i
4.4.1.33 NFC.TAGHEADER2
Address offset: 0x458
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A-D R UD[i] (i=8..11) Unique identifier byte i
4.4.1.34 NFC.TAGHEADER3
Address offset: 0x45C
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST, and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A-D R UD[i] (i=12..15) Unique identifier byte i
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4.4.1.35 TRNG90B.BYTES
Address offset: 0xC00
Amount of bytes for the required entropy bits
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R BYTES Amount of bytes for the required entropy bits
4.4.1.36 TRNG90B.RCCUTOFF
Address offset: 0xC04
Repetition counter cutoff
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R RCCUTOFF Repetition counter cutoff
4.4.1.37 TRNG90B.APCUTOFF
Address offset: 0xC08
Adaptive proportion cutoff
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R APCUTOFF Adaptive proportion cutoff
4.4.1.38 TRNG90B.STARTUP
Address offset: 0xC0C
Amount of bytes for the startup tests
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000210 0 0000000000000000000001000010000
ID AccessField Value ID Value Description
A R STARTUP Amount of bytes for the startup tests
4.4.1.39 TRNG90B.ROSC1
Address offset: 0xC10
Sample count for ring oscillator 1
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R ROSC1 Sample count for ring oscillator 1
4.4.1.40 TRNG90B.ROSC2
Address offset: 0xC14
Sample count for ring oscillator 2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R ROSC2 Sample count for ring oscillator 2
4.4.1.41 TRNG90B.ROSC3
Address offset: 0xC18
Sample count for ring oscillator 3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R ROSC3 Sample count for ring oscillator 3
4.4.1.42 TRNG90B.ROSC4
Address offset: 0xC1C
Sample count for ring oscillator 4
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A R ROSC4 Sample count for ring oscillator 4
4.5 UICR — User information configuration registers
The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for
configuring user-specific settings.
For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page
24 and Memory on page 20 chapters.
4413_417 v1.1 42
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4.5.1 Registers
Base address Peripheral Instance Description Configuration
0x10001000 UICR UICR User information configuration
Table 9: Instances
Register Offset Description
UNUSED0 0x000 Reserved
UNUSED1 0x004 Reserved
UNUSED2 0x008 Reserved
UNUSED3 0x010 Reserved
NRFFW[0] 0x014 Reserved for Nordic firmware design
NRFFW[1] 0x018 Reserved for Nordic firmware design
NRFFW[2] 0x01C Reserved for Nordic firmware design
NRFFW[3] 0x020 Reserved for Nordic firmware design
NRFFW[4] 0x024 Reserved for Nordic firmware design
NRFFW[5] 0x028 Reserved for Nordic firmware design
NRFFW[6] 0x02C Reserved for Nordic firmware design
NRFFW[7] 0x030 Reserved for Nordic firmware design
NRFFW[8] 0x034 Reserved for Nordic firmware design
NRFFW[9] 0x038 Reserved for Nordic firmware design
NRFFW[10] 0x03C Reserved for Nordic firmware design
NRFFW[11] 0x040 Reserved for Nordic firmware design
NRFFW[12] 0x044 Reserved for Nordic firmware design
NRFHW[0] 0x050 Reserved for Nordic hardware design
NRFHW[1] 0x054 Reserved for Nordic hardware design
NRFHW[2] 0x058 Reserved for Nordic hardware design
NRFHW[3] 0x05C Reserved for Nordic hardware design
NRFHW[4] 0x060 Reserved for Nordic hardware design
NRFHW[5] 0x064 Reserved for Nordic hardware design
NRFHW[6] 0x068 Reserved for Nordic hardware design
NRFHW[7] 0x06C Reserved for Nordic hardware design
NRFHW[8] 0x070 Reserved for Nordic hardware design
NRFHW[9] 0x074 Reserved for Nordic hardware design
NRFHW[10] 0x078 Reserved for Nordic hardware design
NRFHW[11] 0x07C Reserved for Nordic hardware design
CUSTOMER[0] 0x080 Reserved for customer
CUSTOMER[1] 0x084 Reserved for customer
CUSTOMER[2] 0x088 Reserved for customer
CUSTOMER[3] 0x08C Reserved for customer
CUSTOMER[4] 0x090 Reserved for customer
CUSTOMER[5] 0x094 Reserved for customer
CUSTOMER[6] 0x098 Reserved for customer
CUSTOMER[7] 0x09C Reserved for customer
CUSTOMER[8] 0x0A0 Reserved for customer
CUSTOMER[9] 0x0A4 Reserved for customer
CUSTOMER[10] 0x0A8 Reserved for customer
CUSTOMER[11] 0x0AC Reserved for customer
CUSTOMER[12] 0x0B0 Reserved for customer
CUSTOMER[13] 0x0B4 Reserved for customer
CUSTOMER[14] 0x0B8 Reserved for customer
CUSTOMER[15] 0x0BC Reserved for customer
4413_417 v1.1 43
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Register Offset Description
CUSTOMER[16] 0x0C0 Reserved for customer
CUSTOMER[17] 0x0C4 Reserved for customer
CUSTOMER[18] 0x0C8 Reserved for customer
CUSTOMER[19] 0x0CC Reserved for customer
CUSTOMER[20] 0x0D0 Reserved for customer
CUSTOMER[21] 0x0D4 Reserved for customer
CUSTOMER[22] 0x0D8 Reserved for customer
CUSTOMER[23] 0x0DC Reserved for customer
CUSTOMER[24] 0x0E0 Reserved for customer
CUSTOMER[25] 0x0E4 Reserved for customer
CUSTOMER[26] 0x0E8 Reserved for customer
CUSTOMER[27] 0x0EC Reserved for customer
CUSTOMER[28] 0x0F0 Reserved for customer
CUSTOMER[29] 0x0F4 Reserved for customer
CUSTOMER[30] 0x0F8 Reserved for customer
CUSTOMER[31] 0x0FC Reserved for customer
PSELRESET[0] 0x200 Mapping of the nRESET function (see POWER chapter for details)
PSELRESET[1] 0x204 Mapping of the nRESET function (see POWER chapter for details)
APPROTECT 0x208 Access port protection
NFCPINS 0x20C Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
DEBUGCTRL 0x210 Processor debug control
REGOUT0 0x304 GPIO reference voltage / external output supply voltage in high voltage mode
Table 10: Register overview
4.5.1.1 NRFFW[n] (n=0..12)
Address offset: 0x014 + (n × 0x4)
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW NRFFW Reserved for Nordic firmware design
4.5.1.2 NRFHW[n] (n=0..11)
Address offset: 0x050 + (n × 0x4)
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW NRFHW Reserved for Nordic hardware design
4.5.1.3 CUSTOMER[n] (n=0..31)
Address offset: 0x080 + (n × 0x4)
Reserved for customer
4413_417 v1.1 44
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW CUSTOMER Reserved for customer
4.5.1.4 PSELRESET[n] (n=0..1)
Address offset: 0x200 + (n × 0x4)
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not
the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start
independently of the levels present on any of the GPIOs.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW PIN 18 GPIO pin number onto which nRESET is exposed
B RW PORT 0 Port number onto which nRESET is exposed
C RW CONNECT Connection
Disconnected 1 Disconnect
Connected 0 Connect
4.5.1.5 APPROTECT
Address offset: 0x208
Access port protection
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW PALL Enable or disable access port protection.
See Debug and trace on page 50 for more information.
Disabled 0xFF Disable
Enabled 0x00 Enable
4.5.1.6 NFCPINS
Address offset: 0x20C
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW PROTECT Setting of pins dedicated to NFC functionality
Disabled 0 Operation as GPIO pins. Same protection as normal GPIO
pins
NFC 1 Operation as NFC antenna pins. Configures the protection
for NFC operation
4.5.1.7 DEBUGCTRL
Address offset: 0x210
Processor debug control
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW CPUNIDEN Configure CPU non-intrusive debug features
Enabled 0xFF Enable CPU ITM and ETM functionality (default behavior)
Disabled 0x00 Disable CPU ITM and ETM functionality
B RW CPUFPBEN Configure CPU flash patch and breakpoint (FPB) unit
behavior
Enabled 0xFF Enable CPU FPB unit (default behavior)
Disabled 0x00 Disable CPU FPB unit. Writes into the FPB registers will be
ignored.
4.5.1.8 REGOUT0
Address offset: 0x304
GPIO reference voltage / external output supply voltage in high voltage mode
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
ID AccessField Value ID Value Description
A RW VOUT Output voltage from of REG0 regulator stage. The maximum
output voltage from this stage is given as VDDH - VEXDIF.
1V8 0 1.8 V
2V1 1 2.1 V
2V4 2 2.4 V
2V7 3 2.7 V
3V0 4 3.0 V
3V3 5 3.3 V
DEFAULT 7 Default voltage: 1.8 V
4.6 EasyDMA
EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM.
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EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for
direct access to Data RAM. EasyDMA is not able to access flash.
A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example,
for reading and writing of data between the peripheral and RAM. This concept is illustrated in EasyDMA
example on page 47.
Peripheral
READER
Peripheral
core
AHB multilayer
AHB
WRITER
AHB
RAM
RAM
RAM
EasyDMA
EasyDMA
Figure 4: EasyDMA example
An EasyDMA channel is implemented in the following way, but some variations may occur:
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000;
uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for
reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed
that the peripheral will:
• Read 5 bytes from the readerBuffer located in RAM at address 0x20000000.
• Process the data.
• Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005.
The memory layout of these buffers is illustrated in EasyDMA memory layout on page 48.
4413_417 v1.1 47
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readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3]
readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2]
writerBuffer[3] writerBuffer[4] writerBuffer[5]
0x20000000
0x20000004
0x20000008
Figure 5: EasyDMA memory layout
The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer
(writerBuffer). Otherwise, the channel would overflow the writerBuffer.
Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many
bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see how
many bytes WRITER wrote to RAM.
Note that the PTR register of a READER or WRITER must point to a valid memory region before use. The
reset value of a PTR register is not guaranteed to point to valid memory. See Memory on page 20 for
more information about the different memory regions and EasyDMA connectivity.
4.6.1 EasyDMA error handling
Some errors may occur during DMA handling.
If READER.PTR or WRITER.PTR is not pointing to a valid memory region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 20 for more information about the different
memory regions.
If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might
occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall
and wait for access to be granted, or lose data.
4.6.2 EasyDMA array list
EasyDMA is able to operate in Array List mode.
The Array List mode is implemented in channels where the LIST register is available.
The array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other
in RAM.
4413_417 v1.1 48
Core components
The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in
the code example below using a READER EasyDMA channel as an example:
#define BUFFER_SIZE 4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3] __at__ 0x20000000;
MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &ReaderList;
MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList;
The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA
uses the READER.MAXCNT register to determine when the buffer is full.
buffer[0] buffer[1]0x20000000 : ReaderList[0]
0x20000004 : ReaderList[1]
0x20000008 : ReaderList[2]
buffer[2] buffer[3]
READER.PTR = &ReaderList
buffer[0] buffer[1] buffer[2] buffer[3]
buffer[0] buffer[1] buffer[2] buffer[3]
Figure 6: EasyDMA array list
4.7 AHB multilayer
AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is
resolved using priorities.
Each bus master is connected to the slave devices using an interconnection matrix. The bus masters are
assigned priorities. Priorities are used to resolve access when two (or more) bus masters request access to
the same slave device. The following applies:
• If two (or more) bus masters request access to the same slave device, the master with the highest
priority is granted the access first.
• Bus masters with lower priority are stalled until the higher priority master has completed its
transaction.
• If the higher priority master pauses at any point during its transaction, the lower priority master in
queue is temporarily granted access to the slave device until the higher priority master resumes its
activity.
• Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.
Some peripherals, for example radio, do not have a safe stalling mechanism (no internal data buffering,
nor opportunity to pause incoming data). Being a low priority bus master might cause loss of data for such
4413_417 v1.1 49
Core components
peripherals upon bus contention. To avoid AHB bus contention when using multiple bus masters, apply
one of the following guidelines:
• As a good general rule, avoid situations where more than one bus master is accessing the same slave.
• If more than one bus master is accessing the same slave, make sure that the bus bandwidth is not
exhausted.
Below is a list of bus masters in the system and their priorities.
Bus master name Description
CPU
CTRL-AP
USB
CRYPTOCELL
SPIM1/SPIS1/TWIM1/TWIS1 Same priority and mutually exclusive
RADIO
CCM/ECB/AAR Same priority and mutually exclusive
SAADC
UARTE0
SPIM0/SPIS0/TWIM0/TWIS0 Same priority and mutually exclusive
SPIM2/SPIS2 Same priority and mutually exclusive
NFCT
I2S
PDM
PWM0
PWM1
PWM2
QSPI
PWM3
UARTE1
SPIM3
Table 11: AHB bus masters (listed in priority order, highest to lowest)
Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available
slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection
matrix is illustrated in Memory on page 20.
4.8 Debug and trace
Debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging.
4413_417 v1.1 50
Core components
DAP
CPU
ARM Cortex-M4
SWDCLK
SWDIO
SW-DP
POWER
CxxxPWRUPREQ
CxxxPWRUPRACK
Power
External
debugger
Peripherals
RAM & flash
APB/AHB
AHB
AHB-AP
DAP bus
interconnect
APPROTECT.PALL
CTRL-AP
UICR
NVMC
ETM
ITM
TPIU
Trace
TraceTRACEDATA[3]
TRACEDATA[2]
TRACEDATA[1]
TRACEDATA[0] / SWO
TRACECLK
Figure 7: Overview
The main features of the debug and trace system are:
• Two-pin serial wire debug (SWD) interface
• Flash patch and breakpoint (FPB) unit supports:
• Two literal comparators
• Six instruction comparators
• Data watchpoint and trace (DWT) unit
• Four comparators
• Instrumentation trace macrocell (ITM)
• Embedded trace macrocell (ETM)
• Trace port interface unit (TPIU)
• 4-bit parallel trace of ITM and ETM trace data
• Serial wire output (SWO) trace of ITM data
4.8.1 DAP - Debug access port
An external debugger can access the device via the DAP.
The debug access port (DAP) implements a standard ARM® CoreSight™ serial wire debug port (SW-DP),
which implements the serial wire debug protocol (SWD). SWD is a two-pin serial interface, see SWDCLK
and SWDIO in Overview on page 51.
In addition to the default access port in CPU (AHB-AP), the DAP includes a custom control access port
(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 51.
Note:
• The SWDIO line has an internal pull-up resistor.
• The SWDCLK line has an internal pull-down resistor.
4.8.2 CTRL-AP - Control access port
The control access port (CTRL-AP) is a custom access port that enables control of the device when other
access ports in the DAP are disabled by the access port protection.
4413_417 v1.1 51
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Access port protection blocks the debugger from read and write access to all CPU registers and memory-
mapped addresses. See the UICR register APPROTECT on page 45 for more information on enabling
access port protection.
Control access port has the following features:
• Soft reset, see Reset on page 69 for more information
• Disabling of access port protection, which is the reason why CTRL-AP allows control of the device even
when all other access ports in the DAP are disabled by the access port protection
Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. This command will erase
the flash, UICR, and RAM.
4.8.2.1 Registers
Register Offset Description
RESET 0x000 Soft reset triggered through CTRL-AP
ERASEALL 0x004 Erase all
ERASEALLSTATUS 0x008 Status register for the ERASEALL operation
APPROTECTSTATUS 0x00C Status register for access port protection
IDR 0x0FC CTRL-AP identification register, IDR
Table 12: Register overview
4.8.2.1.1 RESET
Address offset: 0x000
Soft reset triggered through CTRL-AP
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW RESET Soft reset triggered through CTRL-AP. See Reset behavior in
POWER chapter for more details.
NoReset 0 Reset is not active
Reset 1 Reset is active. Device is held in reset.
4.8.2.1.2 ERASEALL
Address offset: 0x004
Erase all
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W ERASEALL Erase all flash and RAM
NoOperation 0 No operation
Erase 1 Erase all flash and RAM
4.8.2.1.3 ERASEALLSTATUS
Address offset: 0x008
4413_417 v1.1 52
Core components
Status register for the ERASEALL operation
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R ERASEALLSTATUS Status register for the ERASEALL operation
Ready 0 ERASEALL is ready
Busy 1 ERASEALL is busy (on-going)
4.8.2.1.4 APPROTECTSTATUS
Address offset: 0x00C
Status register for access port protection
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R APPROTECTSTATUS Status register for access port protection
Enabled 0 Access port protection enabled
Disabled 1 Access port protection not enabled
4.8.2.1.5 IDR
Address offset: 0x0FC
CTRL-AP identification register, IDR
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID E E E E D D D D C C C C C C C B B B B A A A A A A A A
Reset 0x02880000 0 0000010100010000000000000000000
ID AccessField Value ID Value Description
A R APID AP identification
B R CLASS Access port (AP) class
NotDefined 0x0 No defined class
MEMAP 0x8 Memory access port
C R JEP106ID JEDEC JEP106 identity code
D R JEP106CONT JEDEC JEP106 continuation code
E R REVISION Revision
4.8.2.2 Electrical specification
4.8.2.2.1 Control access port
Symbol Description Min. Typ. Max. Units
Rpull Internal SWDIO and SWDCLK pull up/down resistance 13 kΩ
fSWDCLK SWDCLK frequency 0.125 8 MHz
4.8.3 Debug interface mode
Before an external debugger can access either CPU's access port (AHB-AP) or the control access port
(CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.
4413_417 v1.1 53
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If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and
the DIF flag in RESETREAS on page 75 will be set. The device is in the debug interface mode as long
as the debugger is requesting power via CxxxPWRUPREQ. Once the debugger stops requesting power
via CxxxPWRUPREQ, the device is back in normal mode. Some peripherals behave differently in Debug
Interface mode compared to normal mode. These differences are described in more detail in the chapters
of the peripherals that are affected.
When a debug session is over, the external debugger must make sure to put the device back into normal
mode since the overall power consumption is higher in debug interface mode than in normal mode.
For details on how to use the debug capabilities, read the debug documentation of your IDE.
4.8.4 Real-time debug
The nRF52840 supports real-time debugging.
Real-time debugging allows interrupts to execute to completion in real time when breakpoints are set
in thread mode or lower priority interrupts. This enables developers to set breakpoints and single-step
through the code without the risk of real-time event-driven threads running at higher priority failing.
For example, this enables the device to continue to service the high-priority interrupts of an external
controller or sensor without failure or loss of state synchronization while the developer steps through
code in a low-priority thread.
4.8.5 Trace
The device supports ETM and ITM trace.
Trace data from the ETM and the ITM is sent to an external debugger via a 4-bit wide parallel trace port
interface unit (TPIU), see TRACEDATA[0] through TRACEDATA[3] and TRACECLK in Overview on page
51.
In addition to parallel trace, the TPIU supports serial trace via the serial wire output (SWO) trace protocol.
Parallel and serial trace cannot be used at the same time. ETM trace is only supported in Parallel Trace
mode, while ITM trace is supported in both Parallel and Serial Trace modes.
For details on how to use the trace capabilities, read the debug documentation of your IDE.
TPIU's trace pins are multiplexed with GPIOs, and SWO and TRACEDATA[0] use the same GPIO, see Pin
assignments on page 575 for more information.
Trace speed is configured in the TRACECONFIG on page 95 register. The speed of the trace pins
depends on the DRIVE setting of the GPIOs that the trace pins are multiplexed with. Only S0S1 and H0H1
drives are suitable for debugging. S0S1 is the default DRIVE at reset. If parallel or serial trace port signals
are not fast enough in the debugging conditions, all GPIOs in use for tracing should be set to high drive
(H0H1). The user shall make sure that DRIVE setting for these GPIOs is not overwritten by software during
the debugging session.
4.8.5.1 Electrical specification
4.8.5.1.1 Trace port
Symbol Description Min. Typ. Max. Units
Tcyc Clock period, as defined by ARM (See Embedded Trace
Macrocell Architecture Specification->Trace Port Physical
Interface->Timing specifications on ARM Information
Center)
62.5 500 ns
4413_417 v1.1 54
5Power and clock management
5.1 Power management unit (PMU)
Power and clock management in nRF52840 is designed to automatically ensure maximum power
efficiency.
The core of the power and clock management system is the power management unit (PMU) illustrated in
Power management unit on page 55.
MCU
Internal
voltage
regulators
External
power sources
External
crystals
Internal
oscillators
PMU
CPU
Memory
Peripheral
Figure 8: Power management unit
The PMU automatically detects which power and clock resources are required by the different
components in the system at any given time. It will then start/stop and choose operation modes in supply
regulators and clock sources, without user interaction, to achieve the lowest power consumption possible.
5.2 Current consumption
As the system is being constantly tuned by the Power management unit (PMU) on page 55, estimating
the current consumption of an application can be challenging if the designer is not able to perform
measurements directly on the hardware. To facilitate the estimation process, a set of current consumption
scenarios are provided to show the typical current drawn from the VDD supply.
Each scenario specifies a set of operations and conditions applying to the given scenario. Current
consumption scenarios, common conditions on page 56 shows a set of common conditions used in
all scenarios, unless otherwise stated in the description of a given scenario. All scenarios are listed in
Electrical specification on page 56.
4413_417 v1.1 55
Power and clock management
Condition Value
Supply 3 V on VDD/VDDH (Normal voltage mode)
Temperature 25°C
CPU WFI (wait for interrupt)/WFE (wait for event) sleep
Peripherals All idle
Clock Not running
Regulator LDO
RAM Full 256 kB retention
Compiler2GCC v4.9.3 20150529 (arm-none-eabi-gcc).
Compiler flags: -O0 -falign-functions=16 -fno-strict-
aliasing -mcpu=cortex-m4 -mfloat-abi=soft -msoft-
float -mthumb.
Cache enabled2Yes
32 MHz crystal3SMD 2520, 32 MHz, 10 pF +/- 10 ppm
Table 13: Current consumption scenarios, common conditions
5.2.1 Electrical specification
5.2.1.1 Sleep
Symbol Description Min. Typ. Max. Units
ION_RAMOFF_EVENT System ON, no RAM retention, wake on any event 0.97 µA
ION_RAMON_EVENT System ON, full 256 kB RAM retention, wake on any event 2.35 µA
ION_RAMON_POF System ON, full 256 kB RAM retention, wake on any event,
power-fail comparator enabled
2.35 µA
ION_RAMON_GPIOTE System ON, full 256 kB RAM retention, wake on GPIOTE
input (event mode)
17.37 µA
ION_RAMON_GPIOTEPORTSystem ON, full 256 kB RAM retention, wake on GPIOTE
PORT event
2.36 µA
ION_RAMOFF_RTC System ON, no RAM retention, wake on RTC (running from
LFRC clock)
1.50 µA
ION_RAMON_RTC System ON, full 256 kB RAM retention, wake on RTC
(running from LFRC clock)
3.16 µA
IOFF_RAMOFF_RESET System OFF, no RAM retention, wake on reset 0.40 µA
IOFF_RAMOFF_LPCOMP System OFF, no RAM retention, wake on LPCOMP 0.86 µA
IOFF_RAMON_RESET System OFF, full 256 kB RAM retention, wake on reset 1.86 µA
ION_RAMOFF_EVENT_5V System ON, no RAM retention, wake on any event, 5 V
supply on VDDH, REG0 output = 3.3 V
1.29 µA
IOFF_RAMOFF_RESET_5V System OFF, no RAM retention, wake on reset, 5 V supply on
VDDH, REG0 output = 3.3 V
0.95 µA
2Applying only when CPU is running from flash memory
3Applying only when HFXO is running
4413_417 v1.1 56
Power and clock management
0
0.5
1
1.5
2
2.5
3
3.5
4
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Current consumption [µA]
Supply voltage [V]
-40 ºC 25 ºC 85 ºC
Figure 9: System OFF, no RAM retention, wake on reset (typical values)
0
2
4
6
8
10
12
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Current consumption [µA]
Supply voltage [V]
-40 ºC 25 ºC 85 ºC
Figure 10: System ON, no RAM retention, wake on any event (typical values)
4413_417 v1.1 57
Power and clock management
5.2.1.2 COMP active
Symbol Description Min. Typ. Max. Units
ICOMP,LP COMP enabled, low power mode 30.1 µA
ICOMP,NORM COMP enabled, normal mode 31.8 µA
ICOMP,HS COMP enabled, high-speed mode 35.1 µA
5.2.1.3 CPU running
Symbol Description Min. Typ. Max. Units
ICPU0 CPU running CoreMark @64 MHz from flash, Clock = HFXO,
Regulator = DC/DC
3.3 mA
ICPU1 CPU running CoreMark @64 MHz from flash, Clock = HFXO 6.3 mA
ICPU2 CPU running CoreMark @64 MHz from RAM, Clock = HFXO,
Regulator = DC/DC
2.8 mA
ICPU3 CPU running CoreMark @64 MHz from RAM, Clock = HFXO 5.2 mA
ICPU4 CPU running CoreMark @64 MHz from flash, Clock = HFINT,
Regulator = DC/DC
3.1 mA
5.2.1.4 NFCT active
Symbol Description Min. Typ. Max. Units
Isense Current in SENSE STATE4100 nA
Iactivated Current in ACTIVATED STATE 400 µA
5.2.1.5 Radio transmitting/receiving
Symbol Description Min. Typ. Max. Units
IRADIO_TX0 Radio transmitting @ 8 dBm output power, 1 Mbps
Bluetooth® low energy (BLE) mode, Clock = HFXO, Regulator
= DC/DC
16.40 mA
IRADIO_TX1 Radio transmitting @ 0 dBm output power, 1 Mbps BLE
mode, Clock = HFXO, Regulator = DC/DC
6.40 mA
IRADIO_TX2 Radio transmitting @ -40 dBm output power, 1 Mbps BLE
mode, Clock = HFXO, Regulator = DC/DC
3.83 mA
IRADIO_TX3 Radio transmitting @ 0 dBm output power, 1 Mbps BLE
mode, Clock = HFXO
10.80 mA
IRADIO_TX4 Radio transmitting @ -40 dBm output power, 1 Mbps BLE
mode, Clock = HFXO
4.82 mA
IRADIO_TX5 Radio transmitting @ 0 dBm output power, 250 kbit/s IEE
802.15.4-2006 mode, Clock = HFXO, Regulator = DC/DC
6.40 mA
IRADIO_RX0 Radio receiving @ 1 Mbps BLE mode, Clock = HFXO,
Regulator = DC/DC
6.26 mA
IRADIO_RX1 Radio receiving @ 1 Mbps BLE mode, Clock = HFXO 10.10 mA
IRADIO_RX2 Radio receiving @ 250 kbit/s IEE 802.15.4-2006 mode, Clock
= HFXO, Regulator = DC/DC
6.53 mA
4This current does not apply when in NFC field
4413_417 v1.1 58
Power and clock management
12
14
16
18
20
22
24
26
28
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Current consumption [mA]
Supply voltage [V]
-40 ºC 25 ºC 85 ºC
Figure 11: Radio transmitting @ 8 dBm output power, 1 Mbps
BLE mode, Clock = HFXO, Regulator = DC/DC (typical values)
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Current consumption [mA]
Supply voltage [V]
-40 ºC 25 ºC 85 ºC
Figure 12: Radio transmitting @ 0 dBm output power, 1 Mbps
BLE mode, Clock = HFXO, Regulator = DC/DC (typical values)
4413_417 v1.1 59
Power and clock management
5.2.1.6 RNG active
Symbol Description Min. Typ. Max. Units
IRNG0 RNG running 635 µA
5.2.1.7 SAADC active
Symbol Description Min. Typ. Max. Units
ISAADC,RUN SAADC sampling @ 16 ksps, Acquisition time = 20 µs, Clock =
HFXO, Regulator = DC/DC
1.24 mA
5.2.1.8 TEMP active
Symbol Description Min. Typ. Max. Units
ITEMP0 TEMP started 1.05 mA
5.2.1.9 TIMER running
Symbol Description Min. Typ. Max. Units
ITIMER0 One TIMER instance running @ 1 MHz, Clock = HFINT 418 µA
ITIMER1 Two TIMER instances running @ 1 MHz, Clock = HFINT 418 µA
ITIMER2 One TIMER instance running @ 1 MHz, Clock = HFXO 646 µA
ITIMER3 One TIMER instance running @ 16 MHz, Clock = HFINT 595 µA
ITIMER4 One TIMER instance running @ 16 MHz, Clock = HFXO 823 µA
5.2.1.10 WDT active
Symbol Description Min. Typ. Max. Units
IWDT,STARTED WDT started 3.1 µA
5.2.1.11 Compounded
Symbol Description Min. Typ. Max. Units
IS0 CPU running CoreMark from flash, Radio transmitting @
0 dBm output power, 1 Mbps Bluetooth® low energy (BLE)
mode, Clock = HFXO, Regulator = DC/DC
8.1 mA
IS1 CPU running CoreMark from flash, Radio receiving @ 1
Mbps BLE mode, Clock = HFXO, Regulator = DC/DC
8.6 mA
IS2 CPU running CoreMark from flash, Radio transmitting @ 0
dBm output power, 1 Mbps BLE mode, Clock = HFXO
15.4 mA
IS3 CPU running CoreMark from flash, Radio receiving @ 1
Mbps BLE mode, Clock = HFXO
16.2 mA
IS4 CPU running CoreMark from flash, Radio transmitting @
0 dBm output power, 1 Mbps BLE mode, Clock = HFXO,
Regulator = DC/DC, 5 V supply on VDDH, REG0 output = 3.3
V
11.9 mA
IS5 CPU running CoreMark from flash, Radio receiving @ 1
Mbps BLE mode, Clock = HFXO, Regulator = DC/DC, 5 V
supply on VDDH, REG0 output = 3.3 V
12.7 mA
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Power and clock management
5.3 POWER — Power supply
The power supply consists of a number of LDO and DC/DC regulators that are utilized to maximize the
system's power efficiency.
This device has the following power supply features:
• On-chip LDO and DC/DC regulators
• Global System ON/OFF modes
• Individual RAM section power control for all system modes
• Analog or digital pin wakeup from System OFF
• Supervisor hardware to manage power-on reset, brownout, and power failure
• Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency
• External circuitry supply
• Separate USB supply
5.3.1 Main supply
The main supply voltage is connected to the VDD/VDDH pins. The system will enter one of two supply
voltage modes, normal or high voltage mode, depending on how the supply voltage is connected to these
pins.
Normal voltage mode is entered when the supply voltage is connected to both the VDD and VDDH pins
(pin VDD shorted to pin VDDH). For the supply voltage range to connect to both VDD and VDDH pins see
parameter VDD.
High voltage mode is entered when the supply voltage is only connected to the VDDH pin and the VDD
pin is not connected to any voltage supply. For the supply voltage range to connect to VDDH pin see
parameter VDDH.
The register MAINREGSTATUS on page 79 can be used for reading out the current supply voltage
mode.
5.3.1.1 Main voltage regulators
The system contains two main supply regulator stages, REG0 and REG1.
Each regulator stage has the following regulator type options:
• Low-dropout regulator (LDO)
• Buck regulator (DC/DC)
In normal voltage mode, only the REG1 regulator stage is used and the REG0 stage is automatically
disabled. In high voltage mode, both regulator stages (REG0 and REG1) are used. The output voltage of
REG0 can be configured in register REGOUT0 on page 46. This output voltage is connected to VDD and is
the input voltage to REG1.
By default, the LDO regulators are enabled and the DC/DC regulators are disabled. Registers DCDCEN0 on
page 78 and DCDCEN on page 78 are used to independently enable the DC/DC regulators for the
two stages (REG0 and REG1 respectively).
When a DC/DC converter is enabled, the LDO for the corresponding regulator stage will be disabled.
External LC filters must be connected for each of the DC/DC regulators being used. The advantage of
using a DC/DC regulator is that the overall power consumption is normally reduced as the efficiency of
such a regulator is higher than that of a LDO. The efficiency benefit of using a DC/DC regulator becomes
particularly prominent when the regulator voltage drop (difference between input and output voltage)
is high. The efficiency of internal regulators vary with the supply voltage and the current drawn from the
regulators.
4413_417 v1.1 61
Power and clock management
Note: Do not enable DC/DC regulator without an external LC filter being connected as this will
inhibit device operation, including debug access, until an LC filter is connected.
5.3.1.2 GPIO levels
The GPIO high reference voltage always equals the level on the VDD pin.
In normal voltage mode, the GPIO high level equals the voltage supplied to the VDD pin. In High Voltage
mode it equals the level specified in register REGOUT0 on page 46.
5.3.1.3 External circuitry supply
In High Voltage mode, the output from REG0 can be used to supply external circuitry from the VDD pin.
The VDD output voltage is configured in the register REGOUT0 on page 46.
The supported output voltage range depends on the supply voltage provided on the VDDH pin. Minimum
difference between voltage supplied on the VDDH pin and the voltage output on the VDD pin is defined by
the VREG0,DROP parameter in Regulator specifications, REG0 stage on page 80.
Supplying external circuitry is allowed in both System OFF and System ON mode.
Note: The maximum allowed current drawn by external circuitry is dependent on the total internal
current draw. The maximum current that can be drawn externally from REG0 is defined in Regulator
specifications, REG0 stage on page 80).
5.3.1.4 Regulator configuration examples
The voltage regulators can be configured in several ways, depending on the selected Supply Voltage mode
(normal/high) and the regulator type option (LDO or DC/DC).
Four configuration examples are illustrated in images below.
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC4
1.3V System power
Supply
Figure 13: Normal Voltage mode, LDO only
4413_417 v1.1 62
Power and clock management
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC4
1.3V System power
Supply
Figure 14: Normal Voltage mode, DC/DC REG1 enabled
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC4
1.3V System power
Supply
REGOUT0
Figure 15: High Voltage mode, LDO only
4413_417 v1.1 63
Power and clock management
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC4
1.3V System power
Supply
REGOUT0
Figure 16: High Voltage mode, DC/DC for REG0 and REG1 enabled
5.3.1.5 Power supply supervisor
The power supply supervisor enables monitoring of the connected power supply.
The power supply supervisor provides:
• Power-on reset, signalling to the circuit when a supply is connected.
• An optional power-fail comparator (POF), to signal the application when the supply voltages drop
below a configured threshold.
• A fixed brownout reset detector, to hold the system in reset when the voltage is too low for safe
operation.
The power supply supervisor is illustrated in Power supply supervisor on page 65.
4413_417 v1.1 64
Power and clock management
POFCON.POF
MUX VPOF
...........
MUX
2.8 V
1.8 V
1.7 V
4.2 V
...........
2.8 V
2.7 V
VDD
VDDH
VPOFH
POFWARN
VBOR
Brownout reset
Power-on reset
C
R
VDD
POFCON.THRESHOLD
POFCON.POF
(VDDH>VDD)
POFCON.THRESHOLDVDDH
Figure 17: Power supply supervisor
4413_417 v1.1 65
Power and clock management
5.3.1.6 Power-fail comparator
Using the power-fail comparator (POF) is optional. When enabled, it can provide the CPU an early warning
of an impending power supply failure.
To enable and configure the power-fail comparator, see the register POFCON on page 77.
When the supply voltage falls below the defined threshold, the power-fail comparator will generate an
event (POFWARN) which can be used by an application to prepare for power failure. This event will also
be generated if the supply voltage is already below the threshold at the time the power-fail comparator is
enabled, or if the threshold is re-configured to a level above the supply voltage.
If the power failure warning is enabled and the supply voltage is below the threshold, the power-fail
comparator will prevent the NVMC from performing write operations to the flash.
The comparator features a hysteresis of VHYST, as illustrated in Power-fail comparator (BOR = brownout
reset) on page 66.
Supply (VDD or VDDH)
t
MCU
POFWARN
VPOF
VPOF+VHYST
POFWARN
1.7V
BOR
Figure 18: Power-fail comparator (BOR = brownout reset)
To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not
running.
5.3.2 USB supply
When using the USB peripheral, a 5 V USB supply needs to be provided on the VBUS pin.
The USB peripheral has a dedicated internal voltage regulator for converting the VBUS supply to 3.3 V
used by the USB signalling interface (D+ and D- lines, and pull-up on D+). The rest of the USB peripheral
(USBD) is supplied through the main supply like any other on-chip feature. As a consequence, both VBUS
and either VDDH or VDD supplies are required for USB peripheral operation.
When VBUS rises into its valid range, the software is notified through a USBDETECTED event. A
USBREMOVED event is sent when VBUS goes below its valid range. Use these events to implement the
USBD start-up sequence described in the USBD chapter.
When VBUS rises into its valid range while the device is in System OFF, the device resets and transitions to
System ON mode. The RESETREAS register will have the VBUS bit set to indicate the source of the wake-up.
See VBUS detection specifications on page 82 for the levels at which the events are sent (VBUS,DETECT
and VBUS,REMOVE) or at which the system is woken up from System OFF (VBUS,DETECT).
4413_417 v1.1 66
Power and clock management
When the USBD peripheral is enabled through the ENABLE register, and VBUS is detected, the regulator
is turned on. A USBPWRRDY event is sent when the regulator's worst case settling time has elapsed,
indicating to the software that it can enable the USB pull-up to signal a USB connection to the host.
The software can read the state of the VBUS detection and regulator output readiness at any time through
the USBREGSTATUS register.
USB supply
LDO
VBUS
DECUSB
3.3 V USB power
5 V USB
supply
Figure 19: USB voltage regulator
To ensure stability, the input and output of the USB regulator need to be decoupled with a suitable
decoupling capacitor. See Reference circuitry on page 583 for the recommended values.
5.3.3 System OFF mode
System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core
functionality is powered down and all ongoing tasks are terminated.
The device can be put into System OFF mode using the register SYSTEMOFF on page 76. When in
System OFF mode, the device can be woken up through one of the following signals:
1. The DETECT signal, optionally generated by the GPIO peripheral.
2. The ANADETECT signal, optionally generated by the LPCOMP module.
3. The SENSE signal, optionally generated by the NFC module to wake-on-field.
4. Detecting a valid USB voltage on the VBUS pin (VBUS,DETECT).
5. A reset.
The system is reset when it wakes up from the System OFF mode.
One or more RAM sections can be retained in System OFF mode, depending on the settings in the
RAM[n].POWER registers. RAM[n].POWER are retained registers. Note that these registers are usually
overwritten by the start-up code provided with the nRF application examples.
Before entering the System OFF mode, the user must make sure that all on-going EasyDMA transactions
have been completed. See peripheral specific chapters for more information about how to acquire the
status of EasyDMA transactions.
4413_417 v1.1 67
Power and clock management
5.3.3.1 Emulated System OFF mode
If the device is in Debug Interface mode, System OFF will be emulated to secure that all required resources
needed for debugging are available during System OFF.
See Debug and trace on page 50 for more information. Required resources needed for debugging include
the following key components: Debug and trace on page 50, CLOCK — Clock control on page 82,
POWER — Power supply on page 61, NVMC — Non-volatile memory controller on page 24, CPU on
page 19, flash, and RAM. Since the CPU is kept on in an emulated System OFF mode, it is recommended
to add an infinite loop directly after entering System OFF, to prevent the CPU from executing code that
normally should not be executed.
5.3.4 System ON mode
System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or
peripherals can be in IDLE or RUN mode, depending on the configuration set by the software and the state
of the application executing.
Register RESETREAS on page 75 provides information about the source causing the wakeup or reset.
The system can switch the appropriate internal power sources on and off, depending on how much power
is needed at any given time. The power requirement of a peripheral is directly related to its activity level,
and the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or
events are generated.
5.3.4.1 Sub power modes
In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in
one of the two sub power modes.
The sub power modes are:
• Constant Latency
• Low-power
In Constant Latency mode, the CPU wakeup latency and the PPI task response are constant and kept at
a minimum. This is secured by forcing a set of basic resources to be turned on while in sleep. Having a
constant and predictable latency is at the cost of having increased power consumption. The Constant
Latency mode is selected by triggering the CONSTLAT task.
In Low-power mode, the automatic power management system described in System ON mode on page
68 ensures that the most efficient supply option is chosen to save most power. Having the lowest
power possible is at the cost of having a varying CPU wakeup latency and PPI task response. The Low-
power mode is selected by triggering the LOWPWR task.
When the system enters System ON mode, it is by default in Low-power sub power mode.
5.3.5 RAM power control
The RAM power control registers are used for configuring the following:
• The RAM sections to be retained during System OFF
• The RAM sections to be retained and accessible during System ON
In System OFF, retention of a RAM section is configured in the RETENTION field of the corresponding
register RAM[n].POWER (n=0..8) on page 79.
In System ON, retention and accessibility for a RAM section is configured in the RETENTION and POWER
fields of the corresponding register RAM[n].POWER (n=0..8) on page 79.
The following table summarizes the behavior of these registers.
4413_417 v1.1 68
Power and clock management
Configuration RAM section status
System on/off RAM[n].POWER.POWER RAM[n].POWER.RETENTION Accessible Retained
Off x Off No No
Off x On No Yes
On Off Off No No
On Off1On No Yes
On On x Yes Yes
Table 14: RAM section configuration. x = don't care.
The advantage of not retaining RAM contents is that the overall current consumption is reduced.
See chapter Memory on page 20 for more information on RAM sections.
5.3.6 Reset
Several sources may trigger a reset.
After a reset has occurred, register RESETREAS can be read to determine which source has triggered the
reset.
5.3.6.1 Power-on reset
The power-on reset generator initializes the system at power-on.
The system is held in reset state until the supply has reached the minimum operating voltage and the
internal voltage regulators have started.
5.3.6.2 Pin reset
A pin reset is generated when the physical reset pin on the device is asserted.
Pin reset is configured via the PSELRESET[0] and PSELRESET[1] registers.
5.3.6.3 Wakeup from System OFF mode reset
The device is reset when it wakes up from System OFF mode.
The debug access port (DAP) is not reset following a wake up from System OFF mode if the device is in
Debug Interface mode. See chapter Debug and trace on page 50 for more information.
5.3.6.4 Soft reset
A soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register
(AIRCR) in the ARM® core is set.
See ARM documentation for more details.
A soft reset can also be generated via the register RESET on page 52 in the CTRL-AP.
5.3.6.5 Watchdog reset
A Watchdog reset is generated when the watchdog times out.
See chapter WDT — Watchdog timer on page 570 for more information.
5.3.6.6 Brownout reset
The brownout reset generator puts the system in reset state if VDD drops below the brownout reset (BOR)
threshold.
1Not useful setting. RAM section power off gives negligible reduction in current consumption when
retention is on.
4413_417 v1.1 69
Power and clock management
See section Power fail comparator on page 82 for more information.
5.3.6.7 Retained registers
A retained register is a register that will retain its value in System OFF mode and through a reset,
depending on reset source. See the individual peripheral chapters for information on which of their
registers are retained.
5.3.6.8 Reset behavior
The various reset sources and their targets are summarized in the table below.
Reset targetReset source
CPU Peripherals GPIO DebugaSWJ-DP RAM WDT Retained
registers
RESETREAS
CPU lockup 6x x x
Soft reset x x x
Wakeup from System OFF
mode reset
x x x 7x 8
Watchdog reset 9x xxx xxx
Pin reset x x x x x x x
Brownout reset x x x x x x x x x
Power-on reset x x x x x x x x x
Note: The RAM is never reset, but depending on a reset source the content of RAM may be
corrupted.
5.3.7 Registers
Base address Peripheral Instance Description Configuration
0x40000000 POWER POWER Power control
Table 15: Instances
Register Offset Description
TASKS_CONSTLAT 0x78 Enable Constant Latency mode
TASKS_LOWPWR 0x7C Enable Low-power mode (variable latency)
EVENTS_POFWARN 0x108 Power failure warning
EVENTS_SLEEPENTER 0x114 CPU entered WFI/WFE sleep
EVENTS_SLEEPEXIT 0x118 CPU exited WFI/WFE sleep
EVENTS_USBDETECTED 0x11C Voltage supply detected on VBUS
EVENTS_USBREMOVED 0x120 Voltage supply removed from VBUS
EVENTS_USBPWRRDY 0x124 USB 3.3 V supply ready
5All debug components excluding SWJ-DP. See Debug and trace on page 50 chapter for more
information about the different debug components.
6Reset from CPU lockup is disabled if the device is in Debug Interface mode. CPU lockup is not
possible in System OFF.
7The debug components will not be reset if the device is in Debug Interface mode.
8RAM is not reset on wakeup from System OFF mode. RAM, or certain parts of RAM, may not be
retained after the device has entered System OFF mode, depending on the settings in the RAM
registers.
9Watchdog reset is not available in System OFF.
4413_417 v1.1 70
Power and clock management
Register Offset Description
INTENSET 0x304 Enable interrupt
INTENCLR 0x308 Disable interrupt
RESETREAS 0x400 Reset reason
RAMSTATUS 0x428 RAM status register Deprecated
USBREGSTATUS 0x438 USB supply status
SYSTEMOFF 0x500 System OFF register
POFCON 0x510 Power-fail comparator configuration
GPREGRET 0x51C General purpose retention register
GPREGRET2 0x520 General purpose retention register
DCDCEN 0x578 Enable DC/DC converter for REG1 stage
DCDCEN0 0x580 Enable DC/DC converter for REG0 stage
MAINREGSTATUS 0x640 Main supply status
RAM[0].POWER 0x900 RAM0 power control register
RAM[0].POWERSET 0x904 RAM0 power control set register
RAM[0].POWERCLR 0x908 RAM0 power control clear register
RAM[1].POWER 0x910 RAM1 power control register
RAM[1].POWERSET 0x914 RAM1 power control set register
RAM[1].POWERCLR 0x918 RAM1 power control clear register
RAM[2].POWER 0x920 RAM2 power control register
RAM[2].POWERSET 0x924 RAM2 power control set register
RAM[2].POWERCLR 0x928 RAM2 power control clear register
RAM[3].POWER 0x930 RAM3 power control register
RAM[3].POWERSET 0x934 RAM3 power control set register
RAM[3].POWERCLR 0x938 RAM3 power control clear register
RAM[4].POWER 0x940 RAM4 power control register
RAM[4].POWERSET 0x944 RAM4 power control set register
RAM[4].POWERCLR 0x948 RAM4 power control clear register
RAM[5].POWER 0x950 RAM5 power control register
RAM[5].POWERSET 0x954 RAM5 power control set register
RAM[5].POWERCLR 0x958 RAM5 power control clear register
RAM[6].POWER 0x960 RAM6 power control register
RAM[6].POWERSET 0x964 RAM6 power control set register
RAM[6].POWERCLR 0x968 RAM6 power control clear register
RAM[7].POWER 0x970 RAM7 power control register
RAM[7].POWERSET 0x974 RAM7 power control set register
RAM[7].POWERCLR 0x978 RAM7 power control clear register
RAM[8].POWER 0x980 RAM8 power control register
RAM[8].POWERSET 0x984 RAM8 power control set register
RAM[8].POWERCLR 0x988 RAM8 power control clear register
Table 16: Register overview
5.3.7.1 TASKS_CONSTLAT
Address offset: 0x78
Enable Constant Latency mode
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_CONSTLAT Enable Constant Latency mode
Trigger 1 Trigger task
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Power and clock management
5.3.7.2 TASKS_LOWPWR
Address offset: 0x7C
Enable Low-power mode (variable latency)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_LOWPWR Enable Low-power mode (variable latency)
Trigger 1 Trigger task
5.3.7.3 EVENTS_POFWARN
Address offset: 0x108
Power failure warning
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_POFWARN Power failure warning
NotGenerated 0 Event not generated
Generated 1 Event generated
5.3.7.4 EVENTS_SLEEPENTER
Address offset: 0x114
CPU entered WFI/WFE sleep
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_SLEEPENTER CPU entered WFI/WFE sleep
NotGenerated 0 Event not generated
Generated 1 Event generated
5.3.7.5 EVENTS_SLEEPEXIT
Address offset: 0x118
CPU exited WFI/WFE sleep
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep
NotGenerated 0 Event not generated
Generated 1 Event generated
4413_417 v1.1 72
Power and clock management
5.3.7.6 EVENTS_USBDETECTED
Address offset: 0x11C
Voltage supply detected on VBUS
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_USBDETECTED Voltage supply detected on VBUS
NotGenerated 0 Event not generated
Generated 1 Event generated
5.3.7.7 EVENTS_USBREMOVED
Address offset: 0x120
Voltage supply removed from VBUS
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_USBREMOVED Voltage supply removed from VBUS
NotGenerated 0 Event not generated
Generated 1 Event generated
5.3.7.8 EVENTS_USBPWRRDY
Address offset: 0x124
USB 3.3 V supply ready
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_USBPWRRDY USB 3.3 V supply ready
NotGenerated 0 Event not generated
Generated 1 Event generated
5.3.7.9 INTENSET
Address offset: 0x304
Enable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW POFWARN Write '1' to enable interrupt for event POFWARN
Set 1 Enable
Disabled 0 Read: Disabled
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
Enabled 1 Read: Enabled
B RW SLEEPENTER Write '1' to enable interrupt for event SLEEPENTER
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW SLEEPEXIT Write '1' to enable interrupt for event SLEEPEXIT
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
D RW USBDETECTED Write '1' to enable interrupt for event USBDETECTED
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
E RW USBREMOVED Write '1' to enable interrupt for event USBREMOVED
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
F RW USBPWRRDY Write '1' to enable interrupt for event USBPWRRDY
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
5.3.7.10 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW POFWARN Write '1' to disable interrupt for event POFWARN
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW SLEEPENTER Write '1' to disable interrupt for event SLEEPENTER
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW SLEEPEXIT Write '1' to disable interrupt for event SLEEPEXIT
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
D RW USBDETECTED Write '1' to disable interrupt for event USBDETECTED
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
E RW USBREMOVED Write '1' to disable interrupt for event USBREMOVED
Clear 1 Disable
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
F RW USBPWRRDY Write '1' to disable interrupt for event USBPWRRDY
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
5.3.7.11 RESETREAS
Address offset: 0x400
Reset reason
Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none
of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator,
which will indicate a power-on-reset or a brownout reset.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW RESETPIN Reset from pin-reset detected
NotDetected 0 Not detected
Detected 1 Detected
B RW DOG Reset from watchdog detected
NotDetected 0 Not detected
Detected 1 Detected
C RW SREQ Reset from soft reset detected
NotDetected 0 Not detected
Detected 1 Detected
D RW LOCKUP Reset from CPU lock-up detected
NotDetected 0 Not detected
Detected 1 Detected
E RW OFF Reset due to wake up from System OFF mode when wakeup
is triggered from DETECT signal from GPIO
NotDetected 0 Not detected
Detected 1 Detected
F RW LPCOMP Reset due to wake up from System OFF mode when wakeup
is triggered from ANADETECT signal from LPCOMP
NotDetected 0 Not detected
Detected 1 Detected
G RW DIF Reset due to wake up from System OFF mode when wakeup
is triggered from entering into debug interface mode
NotDetected 0 Not detected
Detected 1 Detected
H RW NFC Reset due to wake up from System OFF mode by NFC field
detect
NotDetected 0 Not detected
Detected 1 Detected
I RW VBUS Reset due to wake up from System OFF mode by VBUS rising
into valid range
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
NotDetected 0 Not detected
Detected 1 Detected
5.3.7.12 RAMSTATUS ( Deprecated )
Address offset: 0x428
RAM status register
Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent
to a block comprising RAM0.S0 and RAM1.S0, RAM block 1 is equivalent to a block comprising RAM2.S0
and RAM3.S0, RAM block 2 is equivalent to a block comprising RAM4.S0 and RAM5.S0 and RAM block 3 is
equivalent to a block comprising RAM6.S0 and RAM7.S0. A RAM block field will indicate ON as long as any
of the RAM sections associated with a block are on.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A-D R RAMBLOCK[i] (i=0..3) RAM block i is on or off/powering up
Off 0 Off
On 1 On
5.3.7.13 USBREGSTATUS
Address offset: 0x438
USB supply status
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R VBUSDETECT VBUS input detection status (USBDETECTED and
USBREMOVED events are derived from this information)
NoVbus 0 VBUS voltage below valid threshold
VbusPresent 1 VBUS voltage above valid threshold
B R OUTPUTRDY USB supply output settling time elapsed
NotReady 0 USBREG output settling time not elapsed
Ready 1 USBREG output settling time elapsed (same information as
USBPWRRDY event)
5.3.7.14 SYSTEMOFF
Address offset: 0x500
System OFF register
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W SYSTEMOFF Enable System OFF mode
Enter 1 Enable System OFF mode
5.3.7.15 POFCON
Address offset: 0x510
Power-fail comparator configuration
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D B B B B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW POF Enable or disable power failure warning
Disabled 0 Disable
Enabled 1 Enable
B RW THRESHOLD Power-fail comparator threshold setting. This setting applies
both for normal voltage mode (supply connected to both
VDD and VDDH) and high voltage mode (supply connected
to VDDH only). Values 0-3 set threshold below 1.7 V and
should not be used as brown out detection will be activated
before power failure warning on such low voltages.
V17 4 Set threshold to 1.7 V
V18 5 Set threshold to 1.8 V
V19 6 Set threshold to 1.9 V
V20 7 Set threshold to 2.0 V
V21 8 Set threshold to 2.1 V
V22 9 Set threshold to 2.2 V
V23 10 Set threshold to 2.3 V
V24 11 Set threshold to 2.4 V
V25 12 Set threshold to 2.5 V
V26 13 Set threshold to 2.6 V
V27 14 Set threshold to 2.7 V
V28 15 Set threshold to 2.8 V
D RW THRESHOLDVDDH Power-fail comparator threshold setting for high voltage
mode (supply connected to VDDH only). This setting does
not apply for normal voltage mode (supply connected to
both VDD and VDDH).
V27 0 Set threshold to 2.7 V
V28 1 Set threshold to 2.8 V
V29 2 Set threshold to 2.9 V
V30 3 Set threshold to 3.0 V
V31 4 Set threshold to 3.1 V
V32 5 Set threshold to 3.2 V
V33 6 Set threshold to 3.3 V
V34 7 Set threshold to 3.4 V
V35 8 Set threshold to 3.5 V
V36 9 Set threshold to 3.6 V
V37 10 Set threshold to 3.7 V
V38 11 Set threshold to 3.8 V
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D B B B B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
V39 12 Set threshold to 3.9 V
V40 13 Set threshold to 4.0 V
V41 14 Set threshold to 4.1 V
V42 15 Set threshold to 4.2 V
5.3.7.16 GPREGRET
Address offset: 0x51C
General purpose retention register
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW GPREGRET General purpose retention register
This register is a retained register
5.3.7.17 GPREGRET2
Address offset: 0x520
General purpose retention register
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW GPREGRET General purpose retention register
This register is a retained register
5.3.7.18 DCDCEN
Address offset: 0x578
Enable DC/DC converter for REG1 stage
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW DCDCEN Enable DC/DC converter for REG1 stage.
Disabled 0 Disable
Enabled 1 Enable
5.3.7.19 DCDCEN0
Address offset: 0x580
Enable DC/DC converter for REG0 stage
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW DCDCEN Enable DC/DC converter for REG0 stage.
Disabled 0 Disable
Enabled 1 Enable
5.3.7.20 MAINREGSTATUS
Address offset: 0x640
Main supply status
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R MAINREGSTATUS Main supply status
Normal 0 Normal voltage mode. Voltage supplied on VDD.
High 1 High voltage mode. Voltage supplied on VDDH.
5.3.7.21 RAM[n].POWER (n=0..8)
Address offset: 0x900 + (n × 0x10)
RAMn power control register
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x0000FFFF 0 0000000000000001111111111111111
ID AccessField Value ID Value Description
A-P RW S[i]POWER (i=0..15) Keep RAM section Si on or off in System ON mode.
RAM sections are always retained when on, but can
also be retained when off depending on the settings in
SiRETENTION. All RAM sections will be off in System OFF
mode.
Off 0 Off
On 1 On
Q-f RW S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is off
Off 0 Off
On 1 On
5.3.7.22 RAM[n].POWERSET (n=0..8)
Address offset: 0x904 + (n × 0x10)
RAMn power control set register
When read, this register will return the value of the POWER register.
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x0000FFFF 0 0000000000000001111111111111111
ID AccessField Value ID Value Description
A-P W S[i]POWER (i=0..15) Keep RAM section Si of RAMn on or off in System ON mode
On 1 On
Q-f W S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is
switched off
On 1 On
5.3.7.23 RAM[n].POWERCLR (n=0..8)
Address offset: 0x908 + (n × 0x10)
RAMn power control clear register
When read, this register will return the value of the POWER register.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x0000FFFF 0 0000000000000001111111111111111
ID AccessField Value ID Value Description
A-P W S[i]POWER (i=0..15) Keep RAM section Si of RAMn on or off in System ON mode
Off 1 Off
Q-f W S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is
switched off
Off 1 Off
5.3.8 Electrical specification
5.3.8.1 Regulator operating conditions
Symbol Description Min. Typ. Max. Units
VDD,POR VDD supply voltage needed during power-on reset. 1.75 V
VDD Normal voltage mode operating voltage. 1.7 3.0 3.6 V
VDDH High voltage mode operating voltage. 2.5 3.7 5.5 V
CVDD Effective decoupling capacitance on the VDD pin. 2.7 4.7 5.5 µF
CDEC4 Effective decoupling capacitance on the DEC4 pin. 0.7 1 1.3 µF
5.3.8.2 Regulator specifications, REG0 stage
Symbol Description Min. Typ. Max. Units
VDDOUT VDD output voltage. 1.8 3.3 V
VDDOUT,ERR VDD output voltage error (deviation from setting in
REGOUT0 on page 46).
-10 5 %
IEXT,OFF External current draw10 allowed in High voltage mode
(supply on VDDH) during System OFF.
1 mA
IEXT,LOW External current draw10 allowed in High voltage mode
(supply on VDDH) when radio output power is higher than 4
dBm.
5 mA
10 External current draw is defined as the sum of all GPIO currents and the current being drawn from
VDD.
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Symbol Description Min. Typ. Max. Units
IEXT,HIGH External current draw10 allowed in High voltage mode
(supply on VDDH) when radio output power is lower than or
equal to 4 dBm.
25 mA
VREG0,DROP Minimum voltage drop in REG0 (difference between voltage
supplied on VDDH pin and voltage output on VDD pin).
0.3 V
5.3.8.3 Device startup times
Symbol Description Min. Typ. Max. Units
tPOR Time in power-on reset after supply reaches minimum
operating voltage, depending on supply rise time
tPOR,10µs VDD rise time 10 µs 1 10 ms
tPOR,10ms VDD rise time 10 ms11.9 ms
tPOR,60ms VDD rise time 60 ms11.23 110 ms
tRISE,REG0OUT REG0 output (VDD) rise time after VDDH reaches minimum
VDDH supply voltage11.
tRISE,REG0OUT,10µs VDDH rise time 10 µs11.0.22 1.55 ms
tRISE,REG0OUT,10ms VDDH rise time 10 ms11.5 ms
tRISE,REG0OUT,100ms VDDH rise time 100 ms11.30 50 80 ms
tPINR Reset time when using pin reset, depending on pin
capacitance
tPINR,500nF 500 nF capacitance at reset pin. 32.5 ms
tPINR,10µF 10 µF capacitance at reset pin. 650 ms
tR2ON Time from power-on reset to System ON.
tR2ON,NOTCONF If reset pin not configured. tPOR ms
tR2ON,CONF If reset pin configured. tPOR +
tPINR
ms
tOFF2ON Time from OFF to CPU execute. 16.5 µs
tIDLE2CPU Time from IDLE to CPU execute. 3.0 µs
tEVTSET,CL1 Time from HW event to PPI event in Constant Latency
System ON mode.
0.0625 µs
tEVTSET,CL0 Time from HW event to PPI event in Low Power System ON
mode.
0.0625 µs
11 See Recommended operating conditions on page 611 for more information.
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5.3.8.4 Power fail comparator
Symbol Description Min. Typ. Max. Units
VPOF,NV Nominal power level warning thresholds (falling supply
voltage) in Normal voltage mode (supply on VDD). Levels are
configurable between Min. and Max. in 100 mV increments.
1.7 2.8 V
VPOF,HV Nominal power level warning thresholds (falling supply
voltage) in High voltage mode (supply on VDDH). Levels are
configurable in 100 mV increments.
2.7 4.2 V
VPOFTOL Threshold voltage tolerance (applies in both Normal voltage
mode and High voltage mode).
-5 5 %
VPOFHYST Threshold voltage hysteresis (applies in both Normal voltage
mode and High voltage mode).
40 50 60 mV
VBOR,OFF Brownout reset voltage range System OFF mode. Brownout
only applies to the voltage on VDD.
1.2 1.62 V
VBOR,ON Brownout reset voltage range System ON mode. Brownout
only applies to the voltage on VDD.
1.57 1.6 1.63 V
5.3.8.5 USB operating conditions
Symbol Description Min. Typ. Max. Units
VBUS Supply voltage on VBUS pin 4.35 5 5.5 V
VDPDM Voltage on D+ and D- lines VSS - 0.3 VUSB33
+ 0.3
V
5.3.8.6 USB regulator specifications
Symbol Description Min. Typ. Max. Units
IUSB,QUIES USB regulator quiescent current drawn from VBUS (USBD
enabled)
170 µA
tUSBPWRRDY Time from USB enabled to USBPWRRDY event triggered,
VBUS supply provided
1 ms
VUSB33 On voltage at the USB regulator output (DECUSB pin) 3.0 3.3 3.6 V
RSOURCE,VBUS Maximum source resistance on VBUS, including cable 2 Ω
CDECUSB Decoupling capacitor on the DECUSB pin 2.35 4.7 5.5 µF
5.3.8.7 VBUS detection specifications
Symbol Description Min. Typ. Max. Units
VBUS,DETECT Voltage at which rising VBUS gets reported by USBDETECTED 3.4 4.0 4.3 V
VBUS,REMOVE Voltage at which decreasing VBUS gets reported by
USBREMOVED
3.0 3.6 3.9 V
5.4 CLOCK — Clock control
The clock control system can source the system clocks from a range of internal or external high and low
frequency oscillators and distribute them to modules based upon a module’s individual requirements.
Clock distribution is automated and grouped independently by module to limit current consumption in
unused branches of the clock tree.
Listed here are the main features for CLOCK:
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• 64 MHz on-chip oscillator
• 64 MHz crystal oscillator, using external 32 MHz crystal
• 32.768 kHz +/-500 ppm RC oscillator
• 32.768 kHz crystal oscillator, using external 32.768 kHz crystal
• 32.768 kHz oscillator synthesized from 64 MHz oscillator
• Firmware (FW) override control of crystal oscillator activity for low latency start up
• Automatic internal oscillator and clock control, and distribution for ultra-low power
LFCLKSTARTHFCLKSTART LFCLKSTOPHFCLKSTOP
LFCLKSTARTEDHFCLKSTARTED
CLOCK
32.768 kHz
32 MHz
LFCLK
Clock control
XL1
XL2
HFCLK
Clock control
XC1
XC2
CAL SYNT
LFXO
Crystal oscillator
HFXO
Crystal oscillator
PCLK32KI
PCLK1M
PCLK16M
HCLK64M
LFRC
RC oscillator
HFINT
Internal oscillator
PCLK32M
Figure 20: Clock control
5.4.1 HFCLK controller
The HFCLK controller provides several clock signals in the system.
These are as follows:
• HCLK64M: 64 MHz CPU clock
• PCLK1M: 1 MHz peripheral clock
• PCLK16M: 16 MHz peripheral clock
• PCLK32M: 32 MHz peripheral clock
The HFCLK controller uses the following high frequency clock (HFCLK) sources:
• 64 MHz internal oscillator (HFINT)
• 64 MHz crystal oscillator (HFXO)
For illustration, see Clock control on page 83.
The HFCLK controller will automatically provide the clock(s) requested by the system. If the system does
not request any clocks from the HFCLK controller, the controller will enter a power saving mode.
The HFINT source will be used when HFCLK is requested and HFXO has not been started.
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Power and clock management
The HFXO is started by triggering the HFCLKSTART task and stopped by triggering the HFCLKSTOP task.
When the HFCLKSTART task is triggered, the HFCLKSTARTED event is generated once the HFXO startup
time has elapsed. The HFXO startup time is given as the sum of the following:
• HFXO power-up time, as specified in 64 MHz crystal oscillator (HFXO) on page 96.
• HFXO debounce time, as specified in register HFXODEBOUNCE on page 94.
The HFXO must be running to use the RADIO or the calibration mechanism associated with the 32.768 kHz
RC oscillator.
5.4.1.1 64 MHz crystal oscillator (HFXO)
The 64 MHz crystal oscillator (HFXO) is controlled by a 32 MHz external crystal.
The crystal oscillator is designed for use with an AT-cut quartz crystal in parallel resonant mode. To achieve
correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet.
Circuit diagram of the 64 MHz crystal oscillator on page 84 shows how the 32 MHz crystal is connected
to the 64 MHz crystal oscillator.
C1 C2
32 MHz
crystal
XC1 XC2
Figure 21: Circuit diagram of the 64 MHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. For more
information, see Reference circuitry on page 583. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin
is the pin input capacitance on the XC1 and XC2 pins. See table 64 MHz crystal oscillator (HFXO) on page
96. The load capacitors C1 and C2 should have the same value.
For reliable operation, the crystal load capacitance, shunt capacitance, equivalent series resistance, and
drive level must comply with the specifications in table 64 MHz crystal oscillator (HFXO) on page 96. It
is recommended to use a crystal with lower than maximum load capacitance and/or shunt capacitance. A
low load capacitance will reduce both start up time and current consumption.
5.4.2 LFCLK controller
The system supports several low frequency clock sources.
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As illustrated in Clock control on page 83, the system supports the following low frequency clock
sources:
• 32.768 kHz RC oscillator (LFRC)
• 32.768 kHz crystal oscillator (LFXO)
• 32.768 kHz synthesized from HFCLK (LFSYNT)
The LFCLK controller and all of the LFCLK clock sources are always switched off when in System OFF mode.
The LFCLK clock is started by first selecting the preferred clock source in register LFCLKSRC on page 94
and then triggering the LFCLKSTART task. If the LFXO is selected as the clock source, the LFCLK will initially
start running from the 32.768 kHz LFRC while the LFXO is starting up and automatically switch to using the
LFXO once this oscillator is running. The LFCLKSTARTED event will be generated when the LFXO has been
started.
The LFCLK clock is stopped by triggering the LFCLKSTOP task.
Register LFCLKSRC on page 94 controls the clock source, and its allowed swing. The truth table for
various situations is as follows:
SRC EXTERNAL BYPASS Comment
0 0 0 Normal operation, LFRC is source
0 0 1 DO NOT USE
0 1 X DO NOT USE
1 0 0 Normal XTAL operation
1 1 0 Apply external low swing signal to XL1, ground XL2
1 1 1 Apply external full swing signal to XL1, leave XL2 grounded or unconnected
1 0 1 DO NOT USE
2 0 0 Normal operation, LFSYNT is source
2 0 1 DO NOT USE
2 1 X DO NOT USE
Table 17: LFCLKSRC configuration depending on clock source
It is not allowed to write to register LFCLKSRC on page 94 when the LFCLK is running.
A LFCLKSTOP task will stop the LFCLK oscillator. However, the LFCLKSTOP task can only be triggered after
the STATE field in register LFCLKSTAT on page 93 indicates LFCLK running state.
The synthesized 32.768 kHz clock depends on the HFCLK to run. If high accuracy is required for the LFCLK
running off the synthesized 32.768 kHz clock, the HFCLK must running from the HFXO source.
5.4.2.1 32.768 kHz RC oscillator (LFRC)
The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC).
The LFRC oscillator has two modes of operation, normal and ultra-low power (ULP) mode, enabling the
user to trade power consumption against accuracy of the clock. The LFRC mode is configured in register
LFRCMODE on page 96.
The LFRC oscillator has to be stopped before changing the mode of the oscillator.
The LFRC frequency will be affected by variation in temperature. The LFRC oscillator can be calibrated to
improve accuracy by using the HFXO as a reference oscillator during calibration. The LFRC oscillator does
not require additional external components.
5.4.2.2 Calibrating the 32.768 kHz RC oscillator
After the LFRC oscillator is started and running, it can be calibrated by triggering the CAL task.
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The LFRC oscillator will then temporarily request the HFCLK to be used as a reference for the calibration. A
DONE event will be generated when calibration has finished. The HFCLK crystal oscillator has to be started
(by triggering the HFCLKSTART task) in order for the calibration mechanism to work.
It is not allowed to stop the LFRC or write to LFRCMODE on page 96 during an ongoing calibration.
5.4.2.3 Calibration timer
The calibration timer can be used to time the calibration interval of the 32.768 kHz RC oscillator.
The calibration timer is started by triggering the CTSTART task and stopped by triggering the CTSTOP task.
The calibration timer will always start counting down from the value specified in CTIV ( Retained ) on page
95 and generate a CTTO event when it reaches 0. The calibration timer will automatically stop when it
reaches 0.
Calibration
timer
CTSTART
CTSTOP
CTTO
CTIV
CTSTARTED
CTSTOPPED
Figure 22: Calibration timer
After a CTSTART task has been triggered, the calibration timer will ignore further tasks until it has returned
the CTSTARTED event. Likewise, after a CTSTOP task has been triggered, the calibration timer will ignore
further tasks until it has returned a CTSTOPPED event. Triggering CTSTART while the calibration timer
is running will immediately return a CTSTARTED event. Triggering CTSTOP when the calibration timer is
stopped will immediately return a CTSTOPPED event.
5.4.2.4 32.768 kHz crystal oscillator (LFXO)
For higher LFCLK accuracy (when better than +/- 500 ppm accuracy is required), the low frequency crystal
oscillator (LFXO) must be used.
The following external clock sources are supported:
• Low swing clock signal applied to the XL1 pin. The XL2 pin shall then be grounded.
• Rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be grounded or left unconnected.
To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal
data sheet. Circuit diagram of the 32.768 kHz crystal oscillator on page 86 shows the LFXO circuitry.
C1 C2
32.768 kHz
crystal
XL1 XL2
Figure 23: Circuit diagram of the 32.768 kHz crystal oscillator
The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:
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Power and clock management
C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. Cpcb1 and
Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins (see Low
frequency crystal oscillator (LFXO) on page 97). The load capacitors C1 and C2 should have the same
value.
For more information, see Reference circuitry on page 583.
5.4.2.5 32.768 kHz synthesized from HFCLK (LFSYNT)
LFCLK can also be synthesized from the HFCLK clock source. The accuracy of LFCLK will then be the
accuracy of the HFCLK.
Using the LFSYNT clock avoids the requirement for a 32.768 kHz crystal, but increases average power
consumption as the HFCLK will need to be requested in the system.
5.4.3 Registers
Base address Peripheral Instance Description Configuration
0x40000000 CLOCK CLOCK Clock control
Table 18: Instances
Register Offset Description
TASKS_HFCLKSTART 0x000 Start HFXO crystal oscillator
TASKS_HFCLKSTOP 0x004 Stop HFXO crystal oscillator
TASKS_LFCLKSTART 0x008 Start LFCLK
TASKS_LFCLKSTOP 0x00C Stop LFCLK
TASKS_CAL 0x010 Start calibration of LFRC
TASKS_CTSTART 0x014 Start calibration timer
TASKS_CTSTOP 0x018 Stop calibration timer
EVENTS_HFCLKSTARTED 0x100 HFXO crystal oscillator started
EVENTS_LFCLKSTARTED 0x104 LFCLK started
EVENTS_DONE 0x10C Calibration of LFRC completed
EVENTS_CTTO 0x110 Calibration timer timeout
EVENTS_CTSTARTED 0x128 Calibration timer has been started and is ready to process new tasks
EVENTS_CTSTOPPED 0x12C Calibration timer has been stopped and is ready to process new tasks
INTENSET 0x304 Enable interrupt
INTENCLR 0x308 Disable interrupt
HFCLKRUN 0x408 Status indicating that HFCLKSTART task has been triggered
HFCLKSTAT 0x40C HFCLK status
LFCLKRUN 0x414 Status indicating that LFCLKSTART task has been triggered
LFCLKSTAT 0x418 LFCLK status
LFCLKSRCCOPY 0x41C Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
LFCLKSRC 0x518 Clock source for the LFCLK
HFXODEBOUNCE 0x528 HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task.
CTIV 0x538 Calibration timer interval Retained
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Register Offset Description
TRACECONFIG 0x55C Clocking options for the trace port debug interface
LFRCMODE 0x5B4 LFRC mode configuration
Table 19: Register overview
5.4.3.1 TASKS_HFCLKSTART
Address offset: 0x000
Start HFXO crystal oscillator
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_HFCLKSTART Start HFXO crystal oscillator
Trigger 1 Trigger task
5.4.3.2 TASKS_HFCLKSTOP
Address offset: 0x004
Stop HFXO crystal oscillator
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_HFCLKSTOP Stop HFXO crystal oscillator
Trigger 1 Trigger task
5.4.3.3 TASKS_LFCLKSTART
Address offset: 0x008
Start LFCLK
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_LFCLKSTART Start LFCLK
Trigger 1 Trigger task
5.4.3.4 TASKS_LFCLKSTOP
Address offset: 0x00C
Stop LFCLK
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_LFCLKSTOP Stop LFCLK
Trigger 1 Trigger task
5.4.3.5 TASKS_CAL
Address offset: 0x010
Start calibration of LFRC
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_CAL Start calibration of LFRC
Trigger 1 Trigger task
5.4.3.6 TASKS_CTSTART
Address offset: 0x014
Start calibration timer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_CTSTART Start calibration timer
Trigger 1 Trigger task
5.4.3.7 TASKS_CTSTOP
Address offset: 0x018
Stop calibration timer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_CTSTOP Stop calibration timer
Trigger 1 Trigger task
5.4.3.8 EVENTS_HFCLKSTARTED
Address offset: 0x100
HFXO crystal oscillator started
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_HFCLKSTARTED HFXO crystal oscillator started
NotGenerated 0 Event not generated
Generated 1 Event generated
5.4.3.9 EVENTS_LFCLKSTARTED
Address offset: 0x104
LFCLK started
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_LFCLKSTARTED LFCLK started
NotGenerated 0 Event not generated
Generated 1 Event generated
5.4.3.10 EVENTS_DONE
Address offset: 0x10C
Calibration of LFRC completed
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_DONE Calibration of LFRC completed
NotGenerated 0 Event not generated
Generated 1 Event generated
5.4.3.11 EVENTS_CTTO
Address offset: 0x110
Calibration timer timeout
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_CTTO Calibration timer timeout
NotGenerated 0 Event not generated
Generated 1 Event generated
5.4.3.12 EVENTS_CTSTARTED
Address offset: 0x128
Calibration timer has been started and is ready to process new tasks
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_CTSTARTED Calibration timer has been started and is ready to process
new tasks
NotGenerated 0 Event not generated
Generated 1 Event generated
5.4.3.13 EVENTS_CTSTOPPED
Address offset: 0x12C
Calibration timer has been stopped and is ready to process new tasks
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_CTSTOPPED Calibration timer has been stopped and is ready to process
new tasks
NotGenerated 0 Event not generated
Generated 1 Event generated
5.4.3.14 INTENSET
Address offset: 0x304
Enable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW HFCLKSTARTED Write '1' to enable interrupt for event HFCLKSTARTED
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW LFCLKSTARTED Write '1' to enable interrupt for event LFCLKSTARTED
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW DONE Write '1' to enable interrupt for event DONE
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
D RW CTTO Write '1' to enable interrupt for event CTTO
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
E RW CTSTARTED Write '1' to enable interrupt for event CTSTARTED
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
F RW CTSTOPPED Write '1' to enable interrupt for event CTSTOPPED
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
5.4.3.15 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW HFCLKSTARTED Write '1' to disable interrupt for event HFCLKSTARTED
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW LFCLKSTARTED Write '1' to disable interrupt for event LFCLKSTARTED
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW DONE Write '1' to disable interrupt for event DONE
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
D RW CTTO Write '1' to disable interrupt for event CTTO
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
E RW CTSTARTED Write '1' to disable interrupt for event CTSTARTED
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
F RW CTSTOPPED Write '1' to disable interrupt for event CTSTOPPED
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
5.4.3.16 HFCLKRUN
Address offset: 0x408
Status indicating that HFCLKSTART task has been triggered
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R STATUS HFCLKSTART task triggered or not
NotTriggered 0 Task not triggered
Triggered 1 Task triggered
5.4.3.17 HFCLKSTAT
Address offset: 0x40C
HFCLK status
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R SRC Source of HFCLK
RC 0 64 MHz internal oscillator (HFINT)
Xtal 1 64 MHz crystal oscillator (HFXO)
B R STATE HFCLK state
NotRunning 0 HFCLK not running
Running 1 HFCLK running
5.4.3.18 LFCLKRUN
Address offset: 0x414
Status indicating that LFCLKSTART task has been triggered
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R STATUS LFCLKSTART task triggered or not
NotTriggered 0 Task not triggered
Triggered 1 Task triggered
5.4.3.19 LFCLKSTAT
Address offset: 0x418
LFCLK status
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R SRC Source of LFCLK
RC 0 32.768 kHz RC oscillator (LFRC)
Xtal 1 32.768 kHz crystal oscillator (LFXO)
Synth 2 32.768 kHz synthesized from HFCLK (LFSYNT)
B R STATE LFCLK state
NotRunning 0 LFCLK not running
Running 1 LFCLK running
5.4.3.20 LFCLKSRCCOPY
Address offset: 0x41C
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R SRC Clock source
RC 0 32.768 kHz RC oscillator (LFRC)
Xtal 1 32.768 kHz crystal oscillator (LFXO)
Synth 2 32.768 kHz synthesized from HFCLK (LFSYNT)
5.4.3.21 LFCLKSRC
Address offset: 0x518
Clock source for the LFCLK
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW SRC Clock source
RC 0 32.768 kHz RC oscillator (LFRC)
Xtal 1 32.768 kHz crystal oscillator (LFXO)
Synth 2 32.768 kHz synthesized from HFCLK (LFSYNT)
B RW BYPASS Enable or disable bypass of LFCLK crystal oscillator with
external clock source
Disabled 0 Disable (use with Xtal or low-swing external source)
Enabled 1 Enable (use with rail-to-rail external source)
C RW EXTERNAL Enable or disable external source for LFCLK
Disabled 0 Disable external source (use with Xtal)
Enabled 1 Enable use of external source instead of Xtal (SRC needs to
be set to Xtal)
5.4.3.22 HFXODEBOUNCE
Address offset: 0x528
HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task.
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The EVENTS_HFCLKSTARTED event is generated after the HFXO power up time + the HFXO debounce time
has elapsed. It is not allowed to change the value of this register while the HFXO is starting.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0x00000010 0 0000000000000000000000000010000
ID AccessField Value ID Value Description
A RW HFXODEBOUNCE 0x01..0xFF HFXO debounce time. Debounce time = HFXODEBOUNCE *
16 us.
Db256us 0x10 256 us debounce time. Recommended for TSX-3225, FA-20H
and FA-128 crystals.
Db1024us 0x40 1024 us debounce time. Recommended for NX1612AA and
NX1210AB crystals.
5.4.3.23 CTIV ( Retained )
Address offset: 0x538
This register is a retained register
Calibration timer interval
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW CTIV Calibration timer interval in multiple of 0.25 seconds.
Range: 0.25 seconds to 31.75 seconds.
5.4.3.24 TRACECONFIG
Address offset: 0x55C
Clocking options for the trace port debug interface
This register is a retained register. Reset behavior is the same as debug components.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B B A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW TRACEPORTSPEED Speed of trace port clock. Note that the TRACECLK pin will
output this clock divided by two.
32MHz 0 32 MHz trace port clock (TRACECLK = 16 MHz)
16MHz 1 16 MHz trace port clock (TRACECLK = 8 MHz)
8MHz 2 8 MHz trace port clock (TRACECLK = 4 MHz)
4MHz 3 4 MHz trace port clock (TRACECLK = 2 MHz)
B RW TRACEMUX Pin multiplexing of trace signals. See pin assignment chapter
for more details.
GPIO 0 No trace signals routed to pins. All pins can be used as
regular GPIOs.
Serial 1 SWO trace signal routed to pin. Remaining pins can be used
as regular GPIOs.
Parallel 2 All trace signals (TRACECLK and TRACEDATA[n]) routed to
pins.
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5.4.3.25 LFRCMODE
Address offset: 0x5B4
LFRC mode configuration
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW MODE Set LFRC mode
Normal 0 Normal mode
ULP 1 Ultra-low power mode (ULP)
B RW STATUS Active LFRC mode. This field is read only.
Normal 0 Normal mode
ULP 1 Ultra-low power mode (ULP)
5.4.4 Electrical specification
5.4.4.1 64 MHz internal oscillator (HFINT)
Symbol Description Min. Typ. Max. Units
fNOM_HFINT Nominal output frequency 64 MHz
fTOL_HFINT Frequency tolerance ±1.5 ±8 %
5.4.4.2 64 MHz crystal oscillator (HFXO)
Symbol Description Min. Typ. Max. Units
fNOM_HFXO Nominal output frequency 64 MHz
fXTAL_HFXO External crystal frequency 32 MHz
fTOL_HFXO Frequency tolerance requirement for 2.4 GHz proprietary
radio applications
±60 ppm
fTOL_HFXO_BLE Frequency tolerance requirement, Bluetooth low energy
applications, packet length <= 200 bytes
±40 ppm
fTOL_HFXO_BLE_LP Frequency tolerance requirement, Bluetooth low energy
applications, packet length > 200 bytes
±30 ppm
CL_HFXO Load capacitance 12 pF
C0_HFXO Shunt capacitance 7 pF
RS_HFXO_7PF Equivalent series resistance 3 pF < C0 <= 7 pF 60 Ω
RS_HFXO_3PF Equivalent series resistance C0 <= 3 pF 100 Ω
PD_HFXO Drive level 100 µW
CPIN_HFXO Input capacitance XC1 and XC2 3 pF
ISTBY_X32M Core standby current for various crystals
ISTBY_X32M_X0 Epson TSX-3225 80 µA
ISTBY_X32M_X1 Epson FA-20H 72 µA
ISTBY_X32M_X2 Epson FA-128 70 µA
ISTBY_X32M_X3 NDK NX1612AA 136 µA
ISTBY_X32M_X4 NDK NX1210AB 143 µA
ISTART_X32M Average startup current for various crystals, first 1 ms
ISTART_X32M_X0 Epson TSX-3225 328 µA
ISTART_X32M_X1 Epson FA-20H 363 µA
ISTART_X32M_X2 Epson FA-128 396 µA
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Symbol Description Min. Typ. Max. Units
ISTART_X32M_X3 NDK NX1612AA 783 µA
ISTART_X32M_X4 NDK NX1210AB 833 µA
tPOWER_X32M Power-up time for various crystals
tPOWER_X32M_X0 Epson TSX-3225 50 µs
tPOWER_X32M_X1 Epson FA-20H 60 µs
tPOWER_X32M_X2 Epson FA-128 75 µs
tPOWER_X32M_X3 NDK NX1612AA 195 µs
tPOWER_X32M_X4 NDK NX1210AB 210 µs
5.4.4.3 Low frequency crystal oscillator (LFXO)
Symbol Description Min. Typ. Max. Units
fNOM_LFXO Crystal frequency 32.768 kHz
fTOL_LFXO_BLE Frequency tolerance requirement for BLE stack ±500 ppm
fTOL_LFXO_ANT Frequency tolerance requirement for ANT stack ±50 ppm
CL_LFXO Load capacitance 12.5 pF
C0_LFXO Shunt capacitance 2 pF
RS_LFXO Equivalent series resistance 100 kΩ
PD_LFXO Drive level 0.5 μW
Cpin Input capacitance on XL1 and XL2 pads 4 pF
ILFXO Run current for 32.768 kHz crystal oscillator 0.23 µA
tSTART_LFXO Startup time for 32.768 kHz crystal oscillator 0.25 s
5.4.4.4 Low frequency RC oscillator (LFRC), Normal mode
Symbol Description Min. Typ. Max. Units
fNOM_LFRC Nominal frequency 32.768 kHz
fTOL_LFRC Frequency tolerance, uncalibrated ±5 %
fTOL_CAL_LFRC Frequency tolerance after calibration12 ±500 ppm
ILFRC Run current 0.7 µA
tSTART_LFRC Startup time 1000 μs
5.4.4.5 Low frequency RC oscillator (LFRC), Ultra-low power mode (ULP)
Symbol Description Min. Typ. Max. Units
fNOM_LFULP Nominal frequency 32.768 kHz
fTOL_UNCAL_LFULP Frequency tolerance, uncalibrated ±7 %
fTOL_CAL_LFULP Frequency tolerance after calibration13 ±2000 ppm
ILFULP Run current 0.3 µA
tSTART_LFULP Startup time 1500 μs
5.4.4.6 Synthesized low frequency clock (LFSYNT)
12 Constant temperature within ±0.5 °C, calibration performed at least every 8 seconds, averaging
interval > 7.5 ms, defined as 3 sigma
13 Constant temperature within ±0.5 °C, calibration performed at least every 8 seconds, averaging
interval > 125 ms, defined as 3 sigma
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Symbol Description Min. Typ. Max. Units
fNOM_LFSYNT Nominal frequency 32.768 kHz
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6Peripherals
6.1 Peripheral interface
Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral
events are indicated to the CPU by event registers and interrupts if they are configured for a given event.
Peripheral
core
TASK
OR
Task signal from PPI
write
task
event
EVENT m
IRQ signal to NVIC
INTEN m
Peripheral
SHORTSk
Event signal to PPI
Figure 24: Tasks, events, shortcuts, and interrupts
6.1.1 Peripheral ID
Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit
registers.
See Instantiation on page 23 for more information about which peripherals are available and where they
are located in the address map.
There is a direct relationship between peripheral ID and base address. For example, a peripheral with base
address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1, and a
peripheral with base address 0x4001F000 is assigned ID=31.
Peripherals may share the same ID, which may impose one or more of the following limitations:
• Some peripherals share some registers or other common resources.
• Operation is mutually exclusive. Only one of the peripherals can be used at a time.
• Switching from one peripheral to another must follow a specific pattern (disable the first, then enable
the second peripheral).
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6.1.2 Peripherals with shared ID
In general (with the exception of ID 0), peripherals sharing an ID and base address may not be used
simultaneously. The user can only enable one peripheral at the time on this specific ID.
When switching between two peripherals sharing an ID, the user should do the following to prevent
unwanted behavior:
• Disable the previously used peripheral.
• Remove any programmable peripheral interconnect (PPI) connections set up for the peripheral that is
being disabled.
• Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF.
• Explicitly configure the peripheral that you are about to enable and do not rely on configuration values
that may be inherited from the peripheral that was disabled.
• Enable the now configured peripheral.
See which peripherals are sharing ID in Instantiation on page 23.
6.1.3 Peripheral registers
Most peripherals feature an ENABLE register. Unless otherwise specified in the relevant chapter, the
peripheral registers (in particular the PSEL registers) must be configured before enabling the peripheral.
Note that the peripheral must be enabled before tasks and events can be used.
6.1.4 Bit set and clear
Registers with multiple single-bit bit fields may implement the set-and-clear pattern. This pattern enables
firmware to set and clear individual bits in a register without having to perform a read-modify-write
operation on the main register.
This pattern is implemented using three consecutive addresses in the register map, where the main
register is followed by dedicated SET and CLR registers (in that exact order).
The SET register is used to set individual bits in the main register while the CLR register is used to clear
individual bits in the main register. Writing 1 to a bit in SET or CLR register will set or clear the same bit in
the main register respectively. Writing 0 to a bit in SET or CLR register has no effect. Reading the SET or
CLR register returns the value of the main register.
Note: The main register may not be visible and hence not directly accessible in all cases.
6.1.5 Tasks
Tasks are used to trigger actions in a peripheral, for example to start a particular behavior. A peripheral can
implement multiple tasks with each task having a separate register in that peripheral's task register group.
A task is triggered when firmware writes 1 to the task register, or when the peripheral itself or another
peripheral toggles the corresponding task signal. See Tasks, events, shortcuts, and interrupts on page
99.
6.1.6 Events
Events are used to notify peripherals and the CPU about events that have happened, for example a state
change in a peripheral. A peripheral may generate multiple events with each event having a separate
register in that peripheral’s event register group.
An event is generated when the peripheral itself toggles the corresponding event signal, and the event
register is updated to reflect that the event has been generated. See Tasks, events, shortcuts, and
interrupts on page 99. An event register is only cleared when firmware writes 0 to it.
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Events can be generated by the peripheral even when the event register is set to 1.
6.1.7 Shortcuts
A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is
enabled, the associated task is automatically triggered when its associated event is generated.
Using a shortcut is the equivalent to making the same connection outside the peripheral and through the
PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay
through the PPI.
Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut
can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a
maximum of 32 shortcuts for each peripheral.
6.1.8 Interrupts
All peripherals support interrupts. Interrupts are generated by events.
A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example,
the peripheral with ID=4 is connected to interrupt number 4 in the nested vectored interrupt controller
(NVIC).
Using the INTEN, INTENSET and INTENCLR registers, every event generated by a peripheral can be
configured to generate that peripheral's interrupt. Multiple events can be enabled to generate interrupts
simultaneously. To resolve the correct interrupt source, the event registers in the event group of
peripheral registers will indicate the source.
Some peripherals implement only INTENSET and INTENCLR registers, and the INTEN register is not
available on those peripherals. See the individual peripheral chapters for details. In all cases, reading back
the INTENSET or INTENCLR register returns the same information as in INTEN.
Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET
and INTENCLR registers.
The relationship between tasks, events, shortcuts, and interrupts is shown in Tasks, events, shortcuts, and
interrupts on page 99.
Interrupt clearing
Clearing an interrupt by writing 0 to an event register, or disabling an interrupt using the INTENCLR
register, can take up to four CPU clock cycles to take effect. This means that an interrupt may reoccur
immediatelly, even if a new event has not come, if the program exits an interrupt handler after the
interrupt is cleared or disabled but before four clock cycles have passed.
Note: To avoid an interrupt reoccurring before a new event has come, the program should perform
a read from one of the peripheral registers. For example, the event register that has been cleared,
or the INTENCLR register that has been used to disable the interrupt. This will cause a one to three-
cycle delay and ensure the interrupt is cleared before exiting the interrupt handler.
Care should be taken to ensure the compiler does not remove the read operation as an optimization. If the
program can guarantee a four-cycle delay after event being cleared or interrupt disabled in any other way,
then a read of a register is not required.
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6.2 AAR — Accelerated address resolver
Accelerated address resolver is a cryptographic support function for implementing the Resolvable Private
Address Resolution Procedure described in the Bluetooth Core specification v4.0. Resolvable Private
Address generation should be achieved using ECB and is not supported by AAR.
The procedure allows two devices that share a secret key to generate and resolve a hash based on their
device address. The AAR block enables real-time address resolution on incoming packets when configured
as described in this chapter. This allows real-time packet filtering (whitelisting) using a list of known shared
keys (Identity Resolving Keys (IRK) in Bluetooth).
6.2.1 EasyDMA
The AAR implements EasyDMA for reading and writing to the RAM. The EasyDMA will have finished
accessing the RAM when the END, RESOLVED, and NOTRESOLVED events are generated.
If the IRKPTR on page 107, ADDRPTR on page 107, and the SCRATCHPTR on page 107 is not
pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See
Memory on page 20 for more information about the different memory regions.
6.2.2 Resolving a resolvable address
As per Bluetooth specification, a private resolvable address is composed of six bytes.
random
LSB MSB
1 0
hash
(24-bit)
prand
(24-bit)
Figure 25: Resolvable address
To resolve an address the register ADDRPTR on page 107 must point to the start of the packet. The
resolver is started by triggering the START task. A RESOLVED event is generated when the AAR manages to
resolve the address using one of the Identity Resolving Keys (IRK) found in the IRK data structure. The AAR
will use the IRK specified in the register IRK0 to IRK15 starting from IRK0. The register NIRK on page 106
specifies how many IRKs should be used. The AAR module will generate a NOTRESOLVED event if it is not
able to resolve the address using the specified list of IRKs.
The AAR will go through the list of available IRKs in the IRK data structure and for each IRK try to resolve
the address according to the Resolvable Private Address Resolution Procedure described in the Bluetooth
Core specification v4.0 [Vol 3] chapter 10.8.2.3. The time it takes to resolve an address varies due to the
location in the list of the resolvable address. The resolution time will also be affected by RAM accesses
performed by other peripherals and the CPU. See the Electrical specifications for more information about
resolution time.
The AAR only compares the received address to those programmed in the module without checking the
address type.
The AAR will stop as soon as it has managed to resolve the address, or after trying to resolve the address
using NIRK number of IRKs from the IRK data structure. The AAR will generate an END event after it has
stopped.
4413_417 v1.1 102
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AAR
ADDR
Scratch area
IRK data
structure
ADDR: resolvable address
ADDRPTR
SCRATCHPTR
IRKPTR
S1LS0
RESOLVED
START
Figure 26: Address resolution with packet preloaded into RAM
6.2.3 Use case example for chaining RADIO packet reception with
address resolution using AAR
The AAR may be started as soon as the 6 bytes required by the AAR have been received by the RADIO and
stored in RAM. The ADDRPTR pointer must point to the start of packet.
AAR
S0 ADDRL S1
Scratch area
IRK data
structure
RADIO
RXEN
From remote
transmitter
S0: S0 field of RADIO (optional)
L: Length field of RADIO (optional)
S1: S1 field of RADIO (optional)
ADDR: resolvable address
PACKETPTR
ADDRPTR
SCRATCHPTR
IRKPTR
RESOLVED
START
Figure 27: Address resolution with packet loaded into RAM by the RADIO
6.2.4 IRK data structure
The IRK data structure is located in RAM at the memory location specified by the IRKPTR register.
Property Address offset Description
IRK0 0 IRK number 0 (16 - byte)
IRK1 16 IRK number 1 (16 - byte)
.. .. ..
IRK15 240 IRK number 15 (16 - byte)
Table 20: IRK data structure overview
6.2.5 Registers
Base address Peripheral Instance Description Configuration
0x4000F000 AAR AAR Accelerated address resolver
Table 21: Instances
Register Offset Description
TASKS_START 0x000 Start resolving addresses based on IRKs specified in the IRK data structure
TASKS_STOP 0x008 Stop resolving addresses
EVENTS_END 0x100 Address resolution procedure complete
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Register Offset Description
EVENTS_RESOLVED 0x104 Address resolved
EVENTS_NOTRESOLVED 0x108 Address not resolved
INTENSET 0x304 Enable interrupt
INTENCLR 0x308 Disable interrupt
STATUS 0x400 Resolution status
ENABLE 0x500 Enable AAR
NIRK 0x504 Number of IRKs
IRKPTR 0x508 Pointer to IRK data structure
ADDRPTR 0x510 Pointer to the resolvable address
SCRATCHPTR 0x514 Pointer to data area used for temporary storage
Table 22: Register overview
6.2.5.1 TASKS_START
Address offset: 0x000
Start resolving addresses based on IRKs specified in the IRK data structure
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_START Start resolving addresses based on IRKs specified in the IRK
data structure
Trigger 1 Trigger task
6.2.5.2 TASKS_STOP
Address offset: 0x008
Stop resolving addresses
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_STOP Stop resolving addresses
Trigger 1 Trigger task
6.2.5.3 EVENTS_END
Address offset: 0x100
Address resolution procedure complete
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_END Address resolution procedure complete
NotGenerated 0 Event not generated
Generated 1 Event generated
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6.2.5.4 EVENTS_RESOLVED
Address offset: 0x104
Address resolved
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_RESOLVED Address resolved
NotGenerated 0 Event not generated
Generated 1 Event generated
6.2.5.5 EVENTS_NOTRESOLVED
Address offset: 0x108
Address not resolved
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_NOTRESOLVED Address not resolved
NotGenerated 0 Event not generated
Generated 1 Event generated
6.2.5.6 INTENSET
Address offset: 0x304
Enable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW END Write '1' to enable interrupt for event END
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW RESOLVED Write '1' to enable interrupt for event RESOLVED
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW NOTRESOLVED Write '1' to enable interrupt for event NOTRESOLVED
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
6.2.5.7 INTENCLR
Address offset: 0x308
Disable interrupt
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW END Write '1' to disable interrupt for event END
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW RESOLVED Write '1' to disable interrupt for event RESOLVED
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW NOTRESOLVED Write '1' to disable interrupt for event NOTRESOLVED
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
6.2.5.8 STATUS
Address offset: 0x400
Resolution status
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R STATUS [0..15] The IRK that was used last time an address was resolved
6.2.5.9 ENABLE
Address offset: 0x500
Enable AAR
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ENABLE Enable or disable AAR
Disabled 0 Disable
Enabled 3 Enable
6.2.5.10 NIRK
Address offset: 0x504
Number of IRKs
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAA
Reset 0x00000001 0 0000000000000000000000000000001
ID AccessField Value ID Value Description
A RW NIRK [1..16] Number of Identity root keys available in the IRK data
structure
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6.2.5.11 IRKPTR
Address offset: 0x508
Pointer to IRK data structure
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW IRKPTR Pointer to the IRK data structure
6.2.5.12 ADDRPTR
Address offset: 0x510
Pointer to the resolvable address
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ADDRPTR Pointer to the resolvable address (6-bytes)
6.2.5.13 SCRATCHPTR
Address offset: 0x514
Pointer to data area used for temporary storage
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW SCRATCHPTR Pointer to a scratch data area used for temporary storage
during resolution. A space of minimum 3 bytes must be
reserved.
6.2.6 Electrical specification
6.2.6.1 AAR Electrical Specification
Symbol Description Min. Typ. Max. Units
tAAR Address resolution time per IRK. Total time for several IRKs
is given as (1 µs + n * t_AAR), where n is the number of IRKs.
(Given priority to the actual destination RAM block).
6 µs
tAAR,8 Time for address resolution of 8 IRKs. (Given priority to the
actual destination RAM block).
49 µs
6.3 ACL — Access control lists
The Access control lists (ACL) peripheral is designed to assign and enforce access permissions to different
regions of the on-chip flash memory map.
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Flash memory regions can be assigned individual ACL permission schemes. The following registers are
involved:
• PERM register, where the permissions are configured.
• ADDR register, where the word-aligned start address for the flash page is defined.
• SIZE register, where the size of the region the permissions are applied to is determined.
Important: The size of the region in bytes is restricted to a multiple of the flash page size. See
Memory on page 20 for more information.
...
0
1
2
...
N+1
N
On-chip flash memory
0x00000000
0ACL[0].ADDR
l
31
0
ACL[7].ADDR
l
31
0ACL[0].SIZE
l
31
3
1 1
0ACL[0].PERM
l
31
1 1
Read/
Write
protect
0ACL[7].PERM
l
31
0 1
Write
protect
000000
0ACL[7].SIZE
l
31
000000 01 0 0 0 0 0 000
0 0 0 0 0 0
00
Figure 28: Protected regions of on-chip flash memory
There are four defined ACL permission schemes, with different combinations of read/write permissions:
Read Write Protection description
0 0 No protection. Entire region can be executed, read, written or erased.
0 1 Region can be executed and read, but not written or erased.
1 0 Region can be written and erased, but not executed or read.
1 1 Region is locked for all access until next reset.
Table 23: Permission schemes
Important: If a permission violation to a protected region is detected by the ACL peripheral, the
request is blocked and a Bus Fault exception is triggered.
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Access control to a configured region is enforced by the hardware two CPU clock cycles after the ADDR,
SIZE, and PERM registers for an ACL instance have been successfully written. The protection is only
enforced if a valid start address of the flash page boundary is written into the ADDR register, and the
values of the SIZE and PERM registers are not zero.
The ADDR, SIZE, and PERM registers can only be written once. All ACL configuration registers are cleared
on reset (by resetting the device from any reset source), which is also the only way of clearing the
configuration registers. To ensure that the desired permission schemes are always enforced by the ACL
peripheral, the device boot sequence must perform the necessary configuration.
Debugger read access to a read-protected region will be Read-As-Zero (RAZ), while debugger write access
to a write-protected region will be Write-Ignored (WI).
6.3.1 Registers
Base address Peripheral Instance Description Configuration
0x4001E000 ACL ACL Access control lists
Table 24: Instances
Register Offset Description
ACL[0].ADDR 0x800 Configure the word-aligned start address of region 0 to protect
ACL[0].SIZE 0x804 Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect.
ACL[0].PERM 0x808 Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE
ACL[0].UNUSED0 0x80C Reserved
ACL[1].ADDR 0x810 Configure the word-aligned start address of region 1 to protect
ACL[1].SIZE 0x814 Size of region to protect counting from address ACL[1].ADDR. Write '0' as no effect.
ACL[1].PERM 0x818 Access permissions for region 1 as defined by start address ACL[1].ADDR and size ACL[1].SIZE
ACL[1].UNUSED0 0x81C Reserved
ACL[2].ADDR 0x820 Configure the word-aligned start address of region 2 to protect
ACL[2].SIZE 0x824 Size of region to protect counting from address ACL[2].ADDR. Write '0' as no effect.
ACL[2].PERM 0x828 Access permissions for region 2 as defined by start address ACL[2].ADDR and size ACL[2].SIZE
ACL[2].UNUSED0 0x82C Reserved
ACL[3].ADDR 0x830 Configure the word-aligned start address of region 3 to protect
ACL[3].SIZE 0x834 Size of region to protect counting from address ACL[3].ADDR. Write '0' as no effect.
ACL[3].PERM 0x838 Access permissions for region 3 as defined by start address ACL[3].ADDR and size ACL[3].SIZE
ACL[3].UNUSED0 0x83C Reserved
ACL[4].ADDR 0x840 Configure the word-aligned start address of region 4 to protect
ACL[4].SIZE 0x844 Size of region to protect counting from address ACL[4].ADDR. Write '0' as no effect.
ACL[4].PERM 0x848 Access permissions for region 4 as defined by start address ACL[4].ADDR and size ACL[4].SIZE
ACL[4].UNUSED0 0x84C Reserved
ACL[5].ADDR 0x850 Configure the word-aligned start address of region 5 to protect
ACL[5].SIZE 0x854 Size of region to protect counting from address ACL[5].ADDR. Write '0' as no effect.
ACL[5].PERM 0x858 Access permissions for region 5 as defined by start address ACL[5].ADDR and size ACL[5].SIZE
ACL[5].UNUSED0 0x85C Reserved
ACL[6].ADDR 0x860 Configure the word-aligned start address of region 6 to protect
ACL[6].SIZE 0x864 Size of region to protect counting from address ACL[6].ADDR. Write '0' as no effect.
ACL[6].PERM 0x868 Access permissions for region 6 as defined by start address ACL[6].ADDR and size ACL[6].SIZE
ACL[6].UNUSED0 0x86C Reserved
ACL[7].ADDR 0x870 Configure the word-aligned start address of region 7 to protect
ACL[7].SIZE 0x874 Size of region to protect counting from address ACL[7].ADDR. Write '0' as no effect.
ACL[7].PERM 0x878 Access permissions for region 7 as defined by start address ACL[7].ADDR and size ACL[7].SIZE
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Register Offset Description
ACL[7].UNUSED0 0x87C Reserved
Table 25: Register overview
6.3.1.1 ACL[n].ADDR (n=0..7)
Address offset: 0x800 + (n × 0x10)
Configure the word-aligned start address of region n to protect
This register can only be written once.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW1 ADDR Valid word-aligned start address of region n to protect.
Address must point to a flash page boundary.
6.3.1.2 ACL[n].SIZE (n=0..7)
Address offset: 0x804 + (n × 0x10)
Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect.
This register can only be written once.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW1 SIZE Size of flash region n in bytes. Must be a multiple of the
flash page size, and the maximum region size is limited to
512 kB.
6.3.1.3 ACL[n].PERM (n=0..7)
Address offset: 0x808 + (n × 0x10)
Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE
This register can only be written once.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
B RW1 WRITE Configure write and erase permissions for region n. Write '0'
has no effect.
Enable 0 Allow write and erase instructions to region n
Disable 1 Block write and erase instructions to region n
C RW1 READ Configure read permissions for region n. Write '0' has no
effect.
Enable 0 Allow read instructions to region n
Disable 1 Block read instructions to region n
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6.4 CCM — AES CCM mode encryption
Cipher block chaining - message authentication code (CCM) mode is an authenticated encryption
algorithm designed to provide both authentication and confidentiality during data transfer. CCM combines
counter mode encryption and CBC-MAC authentication. The CCM terminology "Message authentication
code (MAC)" is called the "Message integrity check (MIC)" in Bluetooth terminology and also in this
document.
The CCM block generates an encrypted keystream that is applied to input data using the XOR operation
and generates the 4 byte MIC field in one operation. The CCM and radio can be configured to work
synchronously. The CCM will encrypt in time for transmission and decrypt after receiving bytes into
memory from the radio. All operations can complete within the packet RX or TX time. CCM on this device
is implemented according to Bluetooth requirements and the algorithm as defined in IETF RFC3610,
and depends on the AES-128 block cipher. A description of the CCM algorithm can also be found in NIST
Special Publication 800-38C. The Bluetooth specification describes the configuration of counter mode
blocks and encryption blocks to implement compliant encryption for BLE.
The CCM block uses EasyDMA to load key, counter mode blocks (including the nonce required), and to
read/write plain text and cipher text.
The AES CCM supports three operations: key-stream generation, packet encryption, and packet
decryption. All these operations are done in compliance with the Bluetooth specification.14
key-stream
generation
KSGEN
encryption / decryption
CRYPTENDKSGEN ENDCRYPT
SHORTCUT
Figure 29: Key-stream generation followed by encryption or decryption. The shortcut is optional.
6.4.1 Key-steam generation
A new key-stream needs to be generated before a new packet encryption or packet decryption operation
can be started.
A key-stream is generated by triggering the KSGEN task and an ENDKSGEN event will be generated when
the key-stream has been generated.
Key-stream generation, packet encryption, and packet decryption operations utilize the configuration
specified in the data structure pointed to by CNFPTR on page 121. It is necessary to configure this
pointer and its underlying data structure, and the MODE on page 120 register before the KSGEN task is
triggered.
The key-stream will be stored in the AES CCM’s temporary memory area, specified by the SCRATCHPTR on
page 121, where it will be used in subsequent encryption and decryption operations.
For default length packets (MODE.LENGTH = Default) the size of the generated key-stream is 27 bytes.
When using extended length packets (MODE.LENGTH = Extended) the MAXPACKETSIZE on page 122
register specifies the length of the key-stream to be generated. The length of the generated key-stream
must be greater or equal to the length of the subsequent packet payload to be encrypted or decrypted.
The maximum length of the key-stream in extended mode is 251 bytes, which means that the maximum
packet payload size is 251.
14 Bluetooth AES CCM 128 bit block encryption, see Bluetooth Core specification Version 4.0.
4413_417 v1.1 111
Peripherals
If a shortcut is used between ENDKSGEN event and CRYPT task, the INPTR on page 121 pointer and the
OUTPTR on page 121 pointers must also be configured before the KSGEN task is triggered.
6.4.2 Encryption
During packet encryption, the AES CCM will read the unencrypted packet located in RAM at the address
specified in the INPTR pointer, encrypt the packet and append a four byte long Message Integrity Check
(MIC) field to the packet.
Encryption is started by triggering the CRYPT task with the MODE on page 120 register set to
ENCRYPTION. An ENDCRYPT event will be generated when packet encryption is completed
The AES CCM will also modify the length field of the packet to adjust for the appended MIC field, that is,
add four bytes to the length, and store the resulting packet back into RAM at the address specified in the
OUTPTR on page 121 pointer, see Encryption on page 112.
Empty packets (length field is set to 0) will not be encrypted but instead moved unmodified through the
AES CCM.
The CCM supports different widths of the LENGTH field in the data structure for encrypted packets. This is
configured in the MODE on page 120 register.
AES CCM
H PLL RFU
H EPLL+4 RFU
Unencrypted packet
Encrypted packet
MIC
Scratch area
CCM data
structure
MODE = ENCRYPTION
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
INPTR
OUTPTR
SCRATCHPTR
CNFPTR
Figure 30: Encryption
6.4.3 Decryption
During packet decryption, the AES CCM will read the encrypted packet located in RAM at the address
specified in the INPTR pointer, decrypt the packet, authenticate the packet’s MIC field and generate the
appropriate MIC status.
Decryption is started by triggering the CRYPT task with the MODE on page 120 register set to
DECRYPTION. An ENDCRYPT event will be generated when packet decryption is completed
The AES CCM will also modify the length field of the packet to adjust for the MIC field, that is, subtract
four bytes from the length, and then store the decrypted packet into RAM at the address pointed to by the
OUTPTR pointer, see Decryption on page 113.
The CCM is only able to decrypt packet payloads that are at least 5 bytes long, that is, 1 byte or more
encrypted payload (EPL) and 4 bytes of MIC. The CCM will therefore generate a MIC error for packets
where the length field is set to 1, 2, 3 or 4.
Empty packets (length field is set to 0) will not be decrypted but instead moved unmodified through the
AES CCM, these packets will always pass the MIC check.
The CCM supports different widths of the LENGTH field in the data structure for decrypted packets. This is
configured in the MODE on page 120 register.
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Peripherals
AES CCM
H PLL RFU
H EPLL+4 RFU
Unencrypted packet
Encrypted packet
MIC
Scratch area
CCM data
structure
MODE = DECRYPTION
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
OUTPTR
INPTR
SCRATCHPTR
CNFPTR
Figure 31: Decryption
6.4.4 AES CCM and RADIO concurrent operation
The CCM module is able to encrypt/decrypt data synchronously to data being transmitted or received on
the radio.
In order for the CCM module to run synchronously with the radio, the data rate setting in the MODE on
page 120 register needs to match the radio data rate. The settings in this register apply whenever either
the KSGEN or CRYPT tasks are triggered.
The data rate setting of the MODE on page 120 register can also be overridden on-the-fly during an
ongoing encrypt/decrypt operation by the contents of the RATEOVERRIDE on page 122 register. The
data rate setting in this register applies whenever the RATEOVERRIDE task is triggered. This feature can be
useful in cases where the radio data rate is changed during an ongoing packet transaction.
6.4.5 Encrypting packets on-the-fly in radio transmit mode
When the AES CCM is encrypting a packet on-the-fly at the same time as the radio is transmitting it, the
radio must read the encrypted packet from the same memory location as the AES CCM is writing to.
The OUTPTR on page 121 pointer in the AES CCM must therefore point to the same memory location as
the PACKETPTR pointer in the radio, see Configuration of on-the-fly encryption on page 113.
AES CCM
H PLL RFU
H EPLL+4 RFU
Unencrypted packet
Encrypted packet
MIC
Scratch area
CCM data
structure
MODE = ENCRYPTION
RADIO
TXEN
To remote
receiver
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
INPTR
OUTPTR
&
PACKETPTR
SCRATCHPTR
CNFPTR
Figure 32: Configuration of on-the-fly encryption
In order to match the RADIO’s timing, the KSGEN task must be triggered early enough to allow the key-
stream generation to complete before the encryption of the packet shall start.
For short packets (MODE.LENGTH = Default) the KSGEN task must be triggered no later than when
the START task in the RADIO is triggered. In addition the shortcut between the ENDKSGEN event and
the CRYPT task must be enabled. This use-case is illustrated in On-the-fly encryption of short packets
(MODE.LENGTH = Default) using a PPI connection on page 114 using a PPI connection between the
READY event in the RADIO and the KSGEN task in the AES CCM.
For long packets (MODE.LENGTH = Extended) the key-stream generation will need to be started even
earlier, for example at the time when the TXEN task in the RADIO is triggered.
Important: Refer to Timing specification on page 123 for information about the time needed for
generating a key-stream.
4413_417 v1.1 113
Peripherals
RU P A H L RFU EPL MIC CRC
READY
TXEN END
key-stream
generation
KSGEN
encryption
ENDCRYPT
READY START
SHORTCUT
RADIO
AES CCM
RU: Ramp-up of RADIO
P: Preamble
A: Address
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
EPL: encrypted payload
CRYPTENDKSGEN
SHORTCUT
PPI
Figure 33: On-the-fly encryption of short packets (MODE.LENGTH = Default) using a PPI connection
6.4.6 Decrypting packets on-the-fly in radio receive mode
When the AES CCM is decrypting a packet on-the-fly at the same time as the RADIO is receiving it, the AES
CCM must read the encrypted packet from the same memory location as the RADIO is writing to.
The INPTR on page 121 pointer in the AES CCM must therefore point to the same memory location as
the PACKETPTR pointer in the RADIO, see Configuration of on-the-fly decryption on page 114.
AES CCM
H PLL RFU
H EPLL+4 RFU
Unencrypted packet
Encrypted packet
MIC
Scratch area
CCM data
structure
MODE = DECRYPTION
RADIO
RXEN
From remote
transmitter
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
PL: unencrypted payload
EPL: encrypted payload
OUTPTR
INPTR
&
PACKETPTR
SCRATCHPTR
CNFPTR
Figure 34: Configuration of on-the-fly decryption
In order to match the RADIO’s timing, the KSGEN task must be triggered early enough to allow the key-
stream generation to complete before the decryption of the packet shall start.
For short packets (MODE.LENGTH = Default) the KSGEN task must be triggered no later than when the
START task in the RADIO is triggered. In addition, the CRYPT task must be triggered no earlier than when
the ADDRESS event is generated by the RADIO.
If the CRYPT task is triggered exactly at the same time as the ADDRESS event is generated by the RADIO,
the AES CCM will guarantee that the decryption is completed no later than when the END event in the
RADIO is generated.
This use-case is illustrated in On-the-fly decryption of short packets (MODE.LENGTH = Default) using a
PPI connection on page 115 using a PPI connection between the ADDRESS event in the RADIO and the
CRYPT task in the AES CCM. The KSGEN task is triggered from the READY event in the RADIO through a PPI
connection.
For long packets (MODE.LENGTH = Extended) the key-stream generation will need to be started even
earlier, for example at the time when the RXEN task in the RADIO is triggered.
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Important: Refer to Timing specification on page 123 for information about the time needed for
generating a key-stream.
RU A H L RFU EPL MIC CRC
ADDRESS
RXEN END
key-stream
generation
KSGEN
decryption
CRYPT
PPI
ENDKSGEN ENDCRYPT
P
READY START
SHORTCUT
RADIO
AES CCM
RU: Ramp-up of RADIO
P: Preamble
A: Address
H: Header (S0)
L: Length
RFU: reserved for future use (S1)
EPL: encrypted payload
: RADIO receiving noise
READY
PPI
Figure 35: On-the-fly decryption of short packets (MODE.LENGTH = Default) using a PPI connection
6.4.7 CCM data structure
The CCM data structure is located in Data RAM at the memory location specified by the CNFPTR pointer
register.
Property Address offset Description
KEY 0 16 byte AES key
PKTCTR 16 Octet0 (LSO) of packet counter
17 Octet1 of packet counter
18 Octet2 of packet counter
19 Octet3 of packet counter
20 Bit 6 – Bit 0: Octet4 (7 most significant bits of packet counter, with Bit 6 being the most
significant bit) Bit7: Ignored
21 Ignored
22 Ignored
23 Ignored
24 Bit 0: Direction bit Bit 7 – Bit 1: Zero padded
IV 25 8 byte initialization vector (IV) Octet0 (LSO) of IV, Octet1 of IV, … , Octet7 (MSO) of IV
Table 26: CCM data structure overview
The NONCE vector (as specified by the Bluetooth Core Specification) will be generated by hardware based
on the information specified in the CCM data structure from CCM data structure overview on page 115 .
Property Address offset Description
HEADER 0 Packet Header
LENGTH 1 Number of bytes in unencrypted payload
RFU 2 Reserved Future Use
PAYLOAD 3 Unencrypted payload
Table 27: Data structure for unencrypted packet
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Property Address offset Description
HEADER 0 Packet Header
LENGTH 1 Number of bytes in encrypted payload including length of MIC
Important: LENGTH will be 0 for empty packets since the MIC is not added to empty
packets
RFU 2 Reserved Future Use
PAYLOAD 3 Encrypted payload
MIC 3 + payload length ENCRYPT: 4 bytes encrypted MIC
Important: MIC is not added to empty packets
Table 28: Data structure for encrypted packet
6.4.8 EasyDMA and ERROR event
The CCM implements an EasyDMA mechanism for reading and writing to the RAM.
In cases where the CPU and other EasyDMA enabled peripherals are accessing the same RAM block at the
same time, a high level of bus collisions may cause too slow operation for correct on the fly encryption. In
this case the ERROR event will be generated.
The EasyDMA will have finished accessing the RAM when the ENDKSGEN and ENDCRYPT events are
generated.
If the CNFPTR, SCRATCHPTR, INPTR and the OUTPTR are not pointing to the Data RAM region, an EasyDMA
transfer may result in a HardFault or RAM corruption. See Memory on page 20 for more information about
the different memory regions.
6.4.9 Registers
Base address Peripheral Instance Description Configuration
0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode
block encryption
Table 29: Instances
Register Offset Description
TASKS_KSGEN 0x000 Start generation of key-stream. This operation will stop by itself when completed.
TASKS_CRYPT 0x004 Start encryption/decryption. This operation will stop by itself when completed.
TASKS_STOP 0x008 Stop encryption/decryption
TASKS_RATEOVERRIDE 0x00C Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register
for any ongoing encryption/decryption
EVENTS_ENDKSGEN 0x100 Key-stream generation complete
EVENTS_ENDCRYPT 0x104 Encrypt/decrypt complete
EVENTS_ERROR 0x108 CCM error event Deprecated
SHORTS 0x200 Shortcuts between local events and tasks
INTENSET 0x304 Enable interrupt
INTENCLR 0x308 Disable interrupt
MICSTATUS 0x400 MIC check result
ENABLE 0x500 Enable
MODE 0x504 Operation mode
CNFPTR 0x508 Pointer to data structure holding AES key and NONCE vector
INPTR 0x50C Input pointer
OUTPTR 0x510 Output pointer
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Register Offset Description
SCRATCHPTR 0x514 Pointer to data area used for temporary storage
MAXPACKETSIZE 0x518 Length of key-stream generated when MODE.LENGTH = Extended.
RATEOVERRIDE 0x51C Data rate override setting.
Table 30: Register overview
6.4.9.1 TASKS_KSGEN
Address offset: 0x000
Start generation of key-stream. This operation will stop by itself when completed.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_KSGEN Start generation of key-stream. This operation will stop by
itself when completed.
Trigger 1 Trigger task
6.4.9.2 TASKS_CRYPT
Address offset: 0x004
Start encryption/decryption. This operation will stop by itself when completed.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_CRYPT Start encryption/decryption. This operation will stop by
itself when completed.
Trigger 1 Trigger task
6.4.9.3 TASKS_STOP
Address offset: 0x008
Stop encryption/decryption
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_STOP Stop encryption/decryption
Trigger 1 Trigger task
6.4.9.4 TASKS_RATEOVERRIDE
Address offset: 0x00C
Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any
ongoing encryption/decryption
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the
contents of the RATEOVERRIDE register for any ongoing
encryption/decryption
Trigger 1 Trigger task
6.4.9.5 EVENTS_ENDKSGEN
Address offset: 0x100
Key-stream generation complete
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_ENDKSGEN Key-stream generation complete
NotGenerated 0 Event not generated
Generated 1 Event generated
6.4.9.6 EVENTS_ENDCRYPT
Address offset: 0x104
Encrypt/decrypt complete
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_ENDCRYPT Encrypt/decrypt complete
NotGenerated 0 Event not generated
Generated 1 Event generated
6.4.9.7 EVENTS_ERROR ( Deprecated )
Address offset: 0x108
CCM error event
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_ERROR CCM error event Deprecated
NotGenerated 0 Event not generated
Generated 1 Event generated
6.4.9.8 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ENDKSGEN_CRYPT Shortcut between event ENDKSGEN and task CRYPT
Disabled 0 Disable shortcut
Enabled 1 Enable shortcut
6.4.9.9 INTENSET
Address offset: 0x304
Enable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ENDKSGEN Write '1' to enable interrupt for event ENDKSGEN
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW ENDCRYPT Write '1' to enable interrupt for event ENDCRYPT
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW ERROR Write '1' to enable interrupt for event ERROR Deprecated
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
6.4.9.10 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ENDKSGEN Write '1' to disable interrupt for event ENDKSGEN
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW ENDCRYPT Write '1' to disable interrupt for event ENDCRYPT
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW ERROR Write '1' to disable interrupt for event ERROR Deprecated
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
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6.4.9.11 MICSTATUS
Address offset: 0x400
MIC check result
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R MICSTATUS The result of the MIC check performed during the previous
decryption operation
CheckFailed 0 MIC check failed
CheckPassed 1 MIC check passed
6.4.9.12 ENABLE
Address offset: 0x500
Enable
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ENABLE Enable or disable CCM
Disabled 0 Disable
Enabled 2 Enable
6.4.9.13 MODE
Address offset: 0x504
Operation mode
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B B A
Reset 0x00000001 0 0000000000000000000000000000001
ID AccessField Value ID Value Description
A RW MODE The mode of operation to be used. The settings in this
register apply whenever either the KSGEN or CRYPT tasks
are triggered.
Encryption 0 AES CCM packet encryption mode
Decryption 1 AES CCM packet decryption mode
B RW DATARATE Radio data rate that the CCM shall run synchronous with
1Mbit 0 1 Mbps
2Mbit 1 2 Mbps
125Kbps 2 125 Kbps
500Kbps 3 500 Kbps
C RW LENGTH Packet length configuration
Default 0 Default length. Effective length of LENGTH field in
encrypted/decrypted packet is 5 bits. A key-stream for
packet payloads up to 27 bytes will be generated.
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C B B A
Reset 0x00000001 0 0000000000000000000000000000001
ID AccessField Value ID Value Description
Extended 1 Extended length. Effective length of LENGTH field in
encrypted/decrypted packet is 8 bits. A key-stream for
packet payloads up to MAXPACKETSIZE bytes will be
generated.
6.4.9.14 CNFPTR
Address offset: 0x508
Pointer to data structure holding AES key and NONCE vector
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW CNFPTR Pointer to the data structure holding the AES key and
the CCM NONCE vector (see Table 1 CCM data structure
overview)
6.4.9.15 INPTR
Address offset: 0x50C
Input pointer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW INPTR Input pointer
6.4.9.16 OUTPTR
Address offset: 0x510
Output pointer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW OUTPTR Output pointer
6.4.9.17 SCRATCHPTR
Address offset: 0x514
Pointer to data area used for temporary storage
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW SCRATCHPTR Pointer to a scratch data area used for temporary storage
during key-stream generation, MIC generation and
encryption/decryption.
The scratch area is used for temporary storage of data
during key-stream generation and encryption.
When MODE.LENGTH = Default, a space of 43 bytes
is required for this temporary storage. MODE.LENGTH
= Extended (16 + MAXPACKETSIZE) bytes of storage is
required.
6.4.9.18 MAXPACKETSIZE
Address offset: 0x518
Length of key-stream generated when MODE.LENGTH = Extended.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID AAAAAAAA
Reset 0x000000FB 0 0000000000000000000000011111011
ID AccessField Value ID Value Description
A RW MAXPACKETSIZE [0x001B..0x00FB] Length of key-stream generated when MODE.LENGTH
= Extended. This value must be greater or equal to the
subsequent packet payload to be encrypted/decrypted.
6.4.9.19 RATEOVERRIDE
Address offset: 0x51C
Data rate override setting.
Override value to be used instead of the setting of MODE.DATARATE. This override value applies when the
RATEOVERRIDE task is triggered.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW RATEOVERRIDE Data rate override setting.
1Mbit 0 1 Mbps
2Mbit 1 2 Mbps
125Kbps 2 125 Kbps
500Kbps 3 500 Kbps
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6.4.10 Electrical specification
6.4.10.1 Timing specification
Symbol Description Min. Typ. Max. Units
tkgen Time needed for key-stream generation (given priority
access to destination RAM block).
50 µs
6.5 COMP — Comparator
The comparator (COMP) compares an input voltage (VIN+) against a second input voltage (VIN-). VIN+ can
be derived from an analog input pin (AIN0-AIN7). VIN- can be derived from multiple sources depending on
the operation mode of the comparator.
Main features of the comparator are:
• Input range from 0 V to VDD
• Single-ended mode
• Fully flexible hysteresis using a 64-level reference ladder
• Differential mode
• Configurable 50 mV hysteresis
• Reference inputs (VREF):
• VDD
• External reference from AIN0 to AIN7 (between 0 V and VDD)
• Internal references 1.2 V, 1.8 V and 2.4 V
• Three speed/power consumption modes: low-power, normal and high-speed
• Single-pin capacitive sensor support
• Event generation on output changes
• UP event on VIN- > VIN+
• DOWN event on VIN- < VIN+
• CROSS event on VIN+ and VIN- crossing
• READY event on core and internal reference (if used) ready
4413_417 v1.1 123
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Comparator
core
UP
CROSS
DOWN
START
STOP
MODE
VIN-
MUX
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
VIN+
PSEL
RESULT
+ -
SAMPLE
READY
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
HYST
Figure 36: Comparator overview
Once enabled (using the ENABLE register), the comparator is started by triggering the START task and
stopped by triggering the STOP task. After a start-up time of tCOMP,START, the comparator will generate a
READY event to indicate that it is ready for use and that its output is correct. When the COMP module is
started, events will be generated every time VIN+ crosses VIN-.
Operation modes
The comparator can be configured to operate in two main operation modes, differential mode and single-
ended mode. See the MODE register for more information. In both operation modes, the comparator can
operate in different speed and power consumption modes (low-power, normal and high-speed). High-
speed mode will consume more power compared to low-power mode, and low-power mode will result in
slower response time compared to high-speed mode.
Use the PSEL register to select any of the AIN0-AIN7 pins as VIN+ input, irregardless of the operation mode
selected for the comparator. The source of VIN- depends on which operation mode is used:
• Differential mode: Derived directly from AIN0 to AIN7
• Single-ended mode: Derived from VREF. VREF can be derived from VDD, AIN0-AIN7 or internal 1.2 V,
1.8 V and 2.4 V references.
The selected analog pins will be acquired by the comparator once it is enabled.
An optional hysteresis on VIN+ and VIN- can be enabled when the module is used in differential mode
through the HYST register. In single-ended mode, VUP and VDOWN thresholds can be set to implement
a hysteresis using the reference ladder (see Comparator in single-ended mode on page 126). This
hysteresis is in the order of magnitude of 50 mV, and shall prevent noise on the signal to create unwanted
events. See Hysteresis example where VIN+ starts below VUP on page 127 for illustration of the effect of
an active hysteresis on a noisy input signal.
An upward crossing will generate an UP event and a downward crossing will generate a DOWN event. The
CROSS event will be generated every time there is a crossing, independent of direction.
The immediate value of the comparator can be sampled to RESULT register by triggering the SAMPLE task.
6.5.1 Differential mode
In differential mode, the reference input VIN- is derived directly from one of the AINx pins.
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Before enabling the comparator via the ENABLE register, the following registers must be configured for the
differential mode:
•PSEL
•MODE
•EXTREFSEL
Comparator
core
UP
CROSS
DOWN
START
STOP
MODE
MUX
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
VIN+
PSEL EXTREFSEL
RESULT
+ -
SAMPLE
READY
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
MUX
AIN1
AIN0
VIN-
AIN3
AIN2
AIN5
AIN4
AIN7
AIN6
Figure 37: Comparator in differential mode
Restriction: Depending on the device, not all the analog inputs may be available for each MUX. See
definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a
particular device.
When HYST register is turned on while in this mode, the output of the comparator (and associated events)
will change from ABOVE to BELOW whenever VIN+ becomes lower than VIN- - (VDIFFHYST / 2). It will also
change from BELOW to ABOVE whenever VIN+ becomes higher than VIN- + (VDIFFHYST / 2). This behavior is
illustrated in Hysteresis enabled in differential mode on page 125.
VIN+
t
BELOW
(VIN+ < (VIN- - VDIFFHYST /2))
ABOVE
(VIN+ > (VIN- + VDIFFHYST /2))
BELOW
ABOVE
(VIN+ > (VIN- + VDIFFHYST /2))
VIN- - (VDIFFHYST / 2)
VIN- + (VDIFFHYST / 2)
Output
Figure 38: Hysteresis enabled in differential mode
6.5.2 Single-ended mode
In single-ended mode, VIN- is derived from the reference ladder.
Before enabling the comparator via the ENABLE register, the following registers must be configured for the
single-ended mode:
•PSEL
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•MODE
•REFSEL
•EXTREFSEL
•TH
The reference ladder uses the reference voltage (VREF) to derive two new voltage references, VUP and
VDOWN. VUP and VDOWN are configured using THUP and THDOWN respectively in the TH register. VREF
can be derived from any of the available reference sources, configured using the EXTREFSEL and REFSEL
registers as illustrated in Comparator in single-ended mode on page 126. When AREF is selected in
the REFSEL register, the EXTREFSEL register is used to select one of the AIN0-AIN7 analog input pins as
reference input. The selected analog pins will be acquired by the comparator once it is enabled.
MUX
REFSEL
VDD
1V2
1V8
2V4
VREF
TH
Comparator
core
UP
CROSS
DOWN
START
STOP
MODE Reference
ladder
VIN-
MUX
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
VIN+
PSEL EXTREFSEL
RESULT
+ -
SAMPLE
MUX
VUP
VDOWN
0
1
READY
HYST
Output
0 = BELOW (VIN+ < VIN-)
1 = ABOVE (VIN+ > VIN-)
MUX
AIN1
AIN0
AREF
AIN3
AIN2
AIN5
AIN4
AIN7
AIN6
Figure 39: Comparator in single-ended mode
Restriction: Depending on the device, not all the analog inputs may be available for each MUX. See
definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a
particular device.
When the comparator core detects that VIN+ > VIN-, i.e. ABOVE as per the RESULT register, VIN- will switch
to VDOWN. When VIN+ falls below VIN- again, VIN- will be switched back to VUP. By specifying VUP larger
than VDOWN, a hysteresis can be generated as illustrated in Hysteresis example where VIN+ starts below
VUP on page 127 and Hysteresis example where VIN+ starts above VUP on page 127.
Writing to HYST has no effect in single-ended mode, and the content of this register is ignored.
4413_417 v1.1 126
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VIN+
t
START
CPU
1
UP
DOWN
VDOWN
VUP
Output
BELOW ( VIN+ < VIN-) ABOVE (VIN+ > VIN-) BELOW
VIN-
VUP VDOWN VUP
SAMPLE
2
RESULT
BELOW ABOVE
SAMPLE
3
READY
Figure 40: Hysteresis example where VIN+ starts below VUP
VIN+
t
START
CPU
1
UP
DOWN
Output
BELOW ( VIN+ < VIN-) ABOVE (VIN+ > VIN-) BELOW
VIN-
VUP VDOWN VUP
SAMPLE
2
RESULT
BELOW ABOVE
SAMPLE
3
READY
DOWN
ABOVE (VIN+ > VIN-)
ABOVE
VDOWN
VDOWN
VUP
Figure 41: Hysteresis example where VIN+ starts above VUP
6.5.3 Registers
Base address Peripheral Instance Description Configuration
0x40013000 COMP COMP General purpose comparator
Table 31: Instances
Register Offset Description
TASKS_START 0x000 Start comparator
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Register Offset Description
TASKS_STOP 0x004 Stop comparator
TASKS_SAMPLE 0x008 Sample comparator value
EVENTS_READY 0x100 COMP is ready and output is valid
EVENTS_DOWN 0x104 Downward crossing
EVENTS_UP 0x108 Upward crossing
EVENTS_CROSS 0x10C Downward or upward crossing
SHORTS 0x200 Shortcuts between local events and tasks
INTEN 0x300 Enable or disable interrupt
INTENSET 0x304 Enable interrupt
INTENCLR 0x308 Disable interrupt
RESULT 0x400 Compare result
ENABLE 0x500 COMP enable
PSEL 0x504 Pin select
REFSEL 0x508 Reference source select for single-ended mode
EXTREFSEL 0x50C External reference select
TH 0x530 Threshold configuration for hysteresis unit
MODE 0x534 Mode configuration
HYST 0x538 Comparator hysteresis enable
Table 32: Register overview
6.5.3.1 TASKS_START
Address offset: 0x000
Start comparator
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_START Start comparator
Trigger 1 Trigger task
6.5.3.2 TASKS_STOP
Address offset: 0x004
Stop comparator
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_STOP Stop comparator
Trigger 1 Trigger task
6.5.3.3 TASKS_SAMPLE
Address offset: 0x008
Sample comparator value
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A W TASKS_SAMPLE Sample comparator value
Trigger 1 Trigger task
6.5.3.4 EVENTS_READY
Address offset: 0x100
COMP is ready and output is valid
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_READY COMP is ready and output is valid
NotGenerated 0 Event not generated
Generated 1 Event generated
6.5.3.5 EVENTS_DOWN
Address offset: 0x104
Downward crossing
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_DOWN Downward crossing
NotGenerated 0 Event not generated
Generated 1 Event generated
6.5.3.6 EVENTS_UP
Address offset: 0x108
Upward crossing
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_UP Upward crossing
NotGenerated 0 Event not generated
Generated 1 Event generated
6.5.3.7 EVENTS_CROSS
Address offset: 0x10C
Downward or upward crossing
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW EVENTS_CROSS Downward or upward crossing
NotGenerated 0 Event not generated
Generated 1 Event generated
6.5.3.8 SHORTS
Address offset: 0x200
Shortcuts between local events and tasks
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW READY_SAMPLE Shortcut between event READY and task SAMPLE
Disabled 0 Disable shortcut
Enabled 1 Enable shortcut
B RW READY_STOP Shortcut between event READY and task STOP
Disabled 0 Disable shortcut
Enabled 1 Enable shortcut
C RW DOWN_STOP Shortcut between event DOWN and task STOP
Disabled 0 Disable shortcut
Enabled 1 Enable shortcut
D RW UP_STOP Shortcut between event UP and task STOP
Disabled 0 Disable shortcut
Enabled 1 Enable shortcut
E RW CROSS_STOP Shortcut between event CROSS and task STOP
Disabled 0 Disable shortcut
Enabled 1 Enable shortcut
6.5.3.9 INTEN
Address offset: 0x300
Enable or disable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW READY Enable or disable interrupt for event READY
Disabled 0 Disable
Enabled 1 Enable
B RW DOWN Enable or disable interrupt for event DOWN
Disabled 0 Disable
Enabled 1 Enable
C RW UP Enable or disable interrupt for event UP
Disabled 0 Disable
Enabled 1 Enable
D RW CROSS Enable or disable interrupt for event CROSS
Disabled 0 Disable
4413_417 v1.1 130
Peripherals
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
Enabled 1 Enable
6.5.3.10 INTENSET
Address offset: 0x304
Enable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW READY Write '1' to enable interrupt for event READY
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW DOWN Write '1' to enable interrupt for event DOWN
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW UP Write '1' to enable interrupt for event UP
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
D RW CROSS Write '1' to enable interrupt for event CROSS
Set 1 Enable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
6.5.3.11 INTENCLR
Address offset: 0x308
Disable interrupt
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW READY Write '1' to disable interrupt for event READY
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
B RW DOWN Write '1' to disable interrupt for event DOWN
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
C RW UP Write '1' to disable interrupt for event UP
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
4413_417 v1.1 131
Peripherals
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D C B A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
D RW CROSS Write '1' to disable interrupt for event CROSS
Clear 1 Disable
Disabled 0 Read: Disabled
Enabled 1 Read: Enabled
6.5.3.12 RESULT
Address offset: 0x400
Compare result
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A R RESULT Result of last compare. Decision point SAMPLE task.
Below 0 Input voltage is below the threshold (VIN+ < VIN-)
Above 1 Input voltage is above the threshold (VIN+ > VIN-)
6.5.3.13 ENABLE
Address offset: 0x500
COMP enable
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW ENABLE Enable or disable COMP
Disabled 0 Disable
Enabled 2 Enable
6.5.3.14 PSEL
Address offset: 0x504
Pin select
4413_417 v1.1 132
Peripherals
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A
Reset 0x00000000 0 0000000000000000000000000000000
ID AccessField Value ID Value Description
A RW PSEL Analog pin select
AnalogInput0 0 AIN0 selected as analog input
AnalogInput1 1 AIN1 selected as analog input
AnalogInput2 2 AIN2 selected as analog input
AnalogInput3 3 AIN3 selected as analog input
AnalogInput4 4 AIN4 selected as analog input
AnalogInput5 5 AIN5 selected as analog input
AnalogInput6 6 AIN6 selected as analog input
AnalogInput7<