TMS320DM641/TMS320DM640
Video/Imaging Fixed-Point Digital
Signal Processors
Data Manual
Literature Number: SPRS222F
June 2003 − Revised October 2010
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
This page intentionally left blank
Revision History
3
June 2003 − Revised October 2010 SPRS222F
Revision History
This data sheet revision history highlights the technical changes made to the SPRS222E device-specific data
sheet to make it an SPRS222F revision.
PAGE(s)
NO. ADDS/CHANGES/DELETES
82 Added note for VOH and VOL.
Contents
4June 2003 − Revised October 2010SPRS222F
Contents
Section Page
1 Device Overview 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Description 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Device Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Device Compatibility 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Functional Block Diagram 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 CPU (DSP Core) Description 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.1 CPU Core Registers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Memory Map Summary 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.1 L2 Architecture Expanded 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Bootmode 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Pin Assignments 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.1 Pin Map 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.2 Signal Groups Description 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.3 Terminal Functions 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Development 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.1 Development Support 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.2 Device Support 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.2.1 Device and Development-Support Tool Nomenclature 65. . . . . . . . .
1.10.2.2 Documentation Support 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.2.3 Device Silicon Revision 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Device Configurations 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Configurations at Reset 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Peripheral Selection at Device Reset 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Device Configuration at Device Reset 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Configurations After Reset 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Peripheral Selection After Device Reset 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Peripheral Configuration Lock 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Device Status Register Description 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Multiplexed Pin Configurations 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Debugging Considerations 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Configuration Examples 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Device Operating Conditions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Absolute Maximum Ratings Over Operating Case Temperature Range 82. . . . . . . . . . . . . . . . . .
3.2 Recommended Operating Conditions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 DM641/DM640 Peripheral Information and Electrical Specifications 84. . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Parameter Information 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Parameter Information Device-Specific Information 84. . . . . . . . . . . . . . . . . . . . . . .
4.1.1.1 Signal Transition Levels 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1.2 Signal Transition Rates 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
5
June 2003 − Revised October 2010 SPRS222F
Section Page
4.1.1.3 AC Transient Rise/Fall Time Specifications 85. . . . . . . . . . . . . . . . . .
4.1.1.4 Timing Parameters and Board Routing Analysis 85. . . . . . . . . . . . . .
4.2 Recommended Clock and Control Signal Transition Behavior 86. . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Power Supplies 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Power-Supply Sequencing 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Power-Supply Design Considerations 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Power-Supply Decoupling 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4 Peripheral Power-Down Operation 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5 Power-Down Modes Logic 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6 Triggering, Wake-up, and Effects 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.7 C64x Power-Down Mode with an Emulator 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Enhanced Direct Memory Access (EDMA) Controller 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 EDMA Device-Specific Information 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.1 EDMA Channel Synchronization Events 90. . . . . . . . . . . . . . . . . . . . .
4.4.2 EDMA Peripheral Register Description(s) 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Interrupts 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Interrupt Sources and Interrupt Selector 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Interrupts Peripheral Register Description(s) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 External Interrupts Electrical Data/Timing 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Reset 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 Reset Electrical Data/Timing 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Clock PLL 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1 Clock PLL Device-Specific Information 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 Clock PLL Electrical Data/Timing (Input and Output Clocks) 101. . . . . . . . . . . . . . .
4.8 External Memory Interface (EMIIF) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 EMIF Device-Specific Information 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2 EMIF Peripheral Register Description(s) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3 EMIF Electrical Data/Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.1 Asynchronous Memory Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.2 Programmable Synchronous Interface Timing 109. . . . . . . . . . . . . . .
4.8.3.3 Synchronous DRAM Timing 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.4 HOLD/HOLDA Timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.5 BUSREQ Timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Multichannel Audio Serial Port (McASP0) Peripheral 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1 McASP0 Device-Specific Information 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1.1 McASP Block Diagram 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.2 McASP0 Peripheral Register Description(s) 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.3 McASP0 Electrical Data/Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.3.1 Multichannel Audio Serial Port (McASP) Timing 125. . . . . . . . . . . . .
4.10 Inter-Integrated Circuit (I2C) 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.1 I2C Device-Specific Information 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.2 I2C Peripheral Register Description(s) 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.3 I2C Electrical Data/Timing 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.3.1 Inter-Integrated Circuits (I2C) Timing 131. . . . . . . . . . . . . . . . . . . . . . .
4.11 Host-Port Interface (HPI) [DM641 Only] 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11.1 HPI Peripheral Register Description(s) [DM641 Only] 133. . . . . . . . . . . . . . . . . . . .
4.11.2 Host-Port Interface (HPI) Electrical Data/Timing [DM641 Only] 133. . . . . . . . . . . .
Contents
6June 2003 − Revised October 2010SPRS222F
Section Page
4.12 Multichannel Buffered Serial Port (McBSP) 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.1 McBSP Peripheral Register Description(s) 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.2 McBSP Electrical Data/Timing 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.2.1 Multichannel Buffered Serial Port (McBSP) Timing 139. . . . . . . . . . .
4.13 Video Port 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.1 Video Port Device-Specific Information 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.2 Video Port Peripheral Register Description(s) 146. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.3 Video Port (VP0 [DM641/DM640], VP1 [DM641 Only]) Electrical
Data/Timing 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.3.1 VCLKIN Timing (Video Capture Mode) 149. . . . . . . . . . . . . . . . . . . . .
4.13.3.2 Video Data and Control Timing (Video Capture Mode) 150. . . . . . . .
4.13.3.3 VCLKIN Timing (Video Display Mode) 151. . . . . . . . . . . . . . . . . . . . . .
4.13.3.4 Video Control Input/Output and Video Display Data Output
Timing With Respect to VPxCLKINx and VPxCLKOUTx
(Video Display Mode) 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.3.5 Video Dual-Display Sync Mode Timing (With Respect to
VPxCLKINx) 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 VCXO Interpolated Control (VIC) 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.1 VIC Device-Specific Information 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.2 VIC Peripheral Register Description(s) 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.3 VIC Electrical Data/Timing 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.3.1 STCLK Timing 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Ethernet Media Access Controller (EMAC) 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15.1 EMAC Device-Specific Information 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15.2 EMAC Peripheral Register Description(s) 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15.3 EMAC Electrical Data/Timing 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Management Data Input/Output (MDIO) 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16.1 Device-Specific Information 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16.2 Peripheral Register Description(s) 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16.3 Management Data Input/Output (MDIO) Electrical Data/Timing 163. . . . . . . . . . . .
4.17 Timer 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17.1 Timer Device-Specific Information 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17.2 Timer Peripheral Register Description(s) 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17.3 Timer Electrical Data/Timing 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 General-Purpose Input/Output (GPIO) 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18.1 GPIO Device-Specific Information 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18.2 GPIO Peripheral Register Description(s) 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing 167. . . . . . . . . . . . .
4.19 JTAG 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.1 JTAG Device-Specific Information 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.1.1 IEEE 1149.1 JTAG Compatibility Statement 168. . . . . . . . . . . . . . . . .
4.19.1.2 JTAG ID Register Description 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.2 JTAG Peripheral Register Description(s) 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.3 JTAG Test-Port Electrical Data/Timing 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Mechanical Data 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Thermal Data 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
7
June 2003 − Revised October 2010 SPRS222F
List of Figures
Figure Page
1−1 Functional Block Diagram 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 TMS320C64x CPU (DSP Core) Data Paths 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 TMS320DM641/DM640 L2 Architecture Memory Configuration 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 DM641/DM640 Pin Map [Quadrant A] 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 CPU and Peripheral Signals 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 Peripheral Signals 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 TMS320DM64x DSP Device Nomenclature (Including the DM641 and DM640 Devices) 66. . . . . . . . . .
2−1 Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003] 70. . . .
2−2 VP1, VP0, McBSP1, and McBSP0 Pin Muxing 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 Peripheral Enable/Disable Flow Diagram 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses 73. . . . . . . .
2−5 Device Status Register (DEVSTAT) Description − 0x01B3 F004 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Configuration Example A for DM641 (2 8-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF) 78. . . . .
2−7 Configuration Example B for DM641 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) 79. . . . . . . . . . . . .
2−8 Configuration Example A for DM640 (1 8-Bit Video Port + 1 McASP0 + VIC + I2C0 + EMIF) 80. . . . . .
2−9 Configuration Example B for DM640 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) 81. . . . . . . . . . . . .
4−1 Test Load Circuit for AC Timing Measurements 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Input and Output Voltage Reference Levels for AC Timing Measurements 84. . . . . . . . . . . . . . . . . . . . . .
4−3 Rise and Fall Transition Time Voltage Reference Levels 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 AC Transient Specification Rise Time 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 AC Transient Specification Fall Time 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Board-Level Input/Output Timings 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Schottky Diode Diagram 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Power-Down Mode Logic 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 PWRD Field of the CSR Register 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 External/NMI Interrupt Timing 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Reset Timing 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode 100. . . . . . . . . . . . . . . . . . . . .
4−13 CLKIN Timing 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 CLKOUT4 Timing 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 CLKOUT6 Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 AECLKIN Timing for EMIFA 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 AECLKOUT1 Timing for the EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 AECLKOUT2 Timing for the EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 Asynchronous Memory Read Timing for EMIFA 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 Asynchronous Memory Write Timing for EMIFA 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) 110. . . . . . . . .
Figures
8June 2003 − Revised October 2010SPRS222F
Figure Page
4−22 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) 111. . . . . . . . .
4−23 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) 112. . . . . . . . .
4−24 SDRAM Read Command (CAS Latency 3) for EMIFA 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−25 SDRAM Write Command for EMIFA 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−26 SDRAM ACTV Command for EMIFA 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−27 SDRAM DCAB Command for EMIFA 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−28 SDRAM DEAC Command for EMIFA 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−29 SDRAM REFR Command for EMIFA 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−30 SDRAM MRS Command for EMIFA 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−31 SDRAM Self-Refresh Timing for EMIFA 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−32 HOLD/HOLDA Timing for EMIFA 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−33 BUSREQ Timing for EMIFA 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−34 McASP0 Configuration 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−35 McASP Input Timings 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−36 McASP Output Timings 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−37 I2C0 Module Block Diagram 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−38 I2C Receive Timings 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−39 I2C Transmit Timings 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−40 HPI16 Read Timing (HAS Not Used, Tied High) [DM641 Only] 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−41 HPI16 Read Timing (HAS Used) [DM641 Only] 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−42 HPI16 Write Timing (HAS Not Used, Tied High) [DM641 Only] 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−43 HPI16 Write Timing (HAS Used) [DM641 Only] 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−44 McBSP Timing 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−45 FSR Timing When GSYNC = 1 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−46 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 142. . . . . . . . . . . . . . . . . . . . . . . . . .
4−47 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 143. . . . . . . . . . . . . . . . . . . . . . . . . .
4−48 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 144. . . . . . . . . . . . . . . . . . . . . . . . . .
4−49 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 145. . . . . . . . . . . . . . . . . . . . . . . . . .
4−50 Video Port Capture VPxCLKINx TIming 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−51 Video Port Capture Data and Control Input Timing 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−52 Video Port Display VPxCLKINx Timing 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−53 Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−54 Video Port Dual-Display Sync Timing 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−55 STCLK Timing 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−56 MRCLK Timing (EMAC − Receive) 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−57 MTCLK Timing (EMAC − Transmit) 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−58 EMAC Receive Interface Timing 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−59 EMAC Transmit Interface Timing 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−60 MDIO Input Timing 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−61 MDIO Output Timing 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−62 Timer Timing 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
9
June 2003 − Revised October 2010 SPRS222F
Figure Page
4−63 GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−64 GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−65 GPIO Port Timing 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−66 JTAG ID Register Description − TMS320DM641/DM640 Register Value − 0x0007 902F 168. . . . . . . . .
4−67 JTAG Test-Port Timing 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
10 June 2003 − Revised October 2010SPRS222F
List of Tables
Table Page
1−1 Characteristics of the DM641 Processor 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 Characteristics of the DM640 Processor 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 Peripherals Available on the DM641 and DM640 Devices 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 L2 Cache Registers (C64x) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 TMS320DM641/DM640 Memory Map Summary 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 Terminal Functions 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 MAC_EN Peripheral Selection (EMAC and MDIO) 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 DM641/DM640 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], and
TOUT0/MAC_EN) 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 Peripheral Configuration (PERCFG) Register Selection Bit Descriptions 70. . . . . . . . . . . . . . . . . . . . . . . .
2−4 PCFGLOCK Register Selection Bit Descriptions − Read Accesses 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 PCFGLOCK Register Selection Bit Descriptions − Write Accesses 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Device Status (DEVSTAT) Register Selection Bit Descriptions 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 DM641/DM640 Device Multiplexed Pin Configurations 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Board-Level Timing Example 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Characteristics of the Power-Down Modes 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 TMS320DM641/DM640 EDMA Channel Synchronization Events 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 EDMA Registers (C64x) 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Quick DMA (QDMA) and Pseudo Registers 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 EDMA Parameter RAM (C64x) 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 DM641/DM640 DSP Interrupts 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Interrupt Selector Registers (C64x) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 Timing Requirements for External Interrupts 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 Timing Requirements for Reset 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Switching Characteristics Over Recommended Operating Conditions During Reset 97. . . . . . . . . . . . . .
4−12 TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical
Lock Time 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 Timing Requirements for CLKIN for −400 Devices 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 Timing Requirements for CLKIN for −500 Devices 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 Timing Requirements for CLKIN for −600 Devices 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 102. . . . . . . . . . . . .
4−17 Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 103. . . . . . . . . . . . .
4−18 Timing Requirements for AECLKIN for EMIFA 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 EMIFA Registers 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 106. . . . . . . . . . . . . . . . . . . .
4−23 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory
Cycles for EMIFA Module 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module 109. . . . . . .
4−25 Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
11
June 2003 − Revised October 2010 SPRS222F
Table Page
4−26 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module 113. . . . . . . . . . . . . . . . . . . . . .
4−27 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−28 Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module 119. . . . . . . . . . . . . . . . . . . . . . . .
4−29 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−30 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−31 McASP0 Control Registers 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−32 McASP0 Data Registers 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−33 Timing Requirements for McASP 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−34 Switching Characteristics Over Recommended Operating Conditions for McASP 126. . . . . . . . . . . . . . .
4−35 I2C0 Registers 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−36 Timing Requirements for I2C Timings 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−37 Switching Characteristics for I2C Timings 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−38 HPI Registers [DM641 Only] 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−39 Timing Requirements for Host-Port Interface Cycles [DM641 Only] 133. . . . . . . . . . . . . . . . . . . . . . . . . . .
4−40 Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface
Cycles [DM641 Only] 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−41 McBSP 0 Registers 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−42 McBSP 1 Registers 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−43 Timing Requirements for McBSP 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−44 Switching Characteristics Over Recommended Operating Conditions for McBSP 140. . . . . . . . . . . . . . .
4−45 Timing Requirements for FSR When GSYNC = 1 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−46 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 142. . . . . . . . . .
4−47 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−48 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 143. . . . . . . . . .
4−49 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 0 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−50 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 144. . . . . . . . . .
4−51 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−52 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 145. . . . . . . . . .
4−53 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−54 Video Port 0 and 1 (VP0 and VP1) Control Registers 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−55 Timing Requirements for Video Capture Mode for VPxCLKINx 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−56 Timing Requirements in Video Capture Mode for Video Data and Control Inputs 150. . . . . . . . . . . . . . . .
4−57 Timing Requirements for Video Display Mode for VPxCLKINx 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−58 Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to
VPxCLKINx and VPxCLKOUTx 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−59 Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx 152. . . . . .
4−60 Timing Requirements for Dual-Display Sync Mode for VPxCLKINx 153. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−61 VCXO Interpolated Control (VIC) Port Registers 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−62 Timing Requirments for STCLK 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−63 Ethernet MAC (EMAC) Control Registers 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−64 EMAC Statistics Registers 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−65 EMAC Wrapper 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
12 June 2003 − Revised October 2010SPRS222F
Table Page
4−66 EWRAP Registers 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−67 Timing Requirements for MRCLK 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−68 Timing Requirements for MTCLK 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−69 Timing Requirements for EMAC MII Receive 10/100 Mbit/s 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−70 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−71 MDIO Registers 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−72 Timing Requirements for MDIO Input 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−73 Switching Characteristics Over Recommended Operating Conditions for MDIO Output 163. . . . . . . . . .
4−74 Timer 0 Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−75 Timer 1 Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−76 Timer 2 Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−77 Timing Requirements for Timer Inputs 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−78 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs 165. . . . . . . . .
4−79 GP0 Registers 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−80 Timing Requirements for GPIO Inputs 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−81 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs 167. . . . . . . . .
4−82 JTAG ID Register Selection Bit Descriptions 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−83 JTAG ID Register 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−84 Timing Requirements for JTAG Test Port 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−85 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port 169. . . . . . . .
5−1 Thermal Resistance Characteristics (S-PBGA Package) [GDK] 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Thermal Resistance Characteristics (S-PBGA Package) [GNZ] 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
13
June 2003 − Revised October 2010 SPRS222F
This page intentionally left blank
Device Overview
14 June 2003 − Revised October 2010SPRS222F
1 Device Overview
1.1 Features
DHigh-Performance Digital Media Processor
(TMS320DM641/TMS320DM640)
− 2.5-, 2-, 1.67-ns Instruction Cycle Time
− 400-, 500-, 600-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 3200, 4000, 4800 MIPS
− Fully Software-Compatible With C64x™
DVelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2™ Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
DInstruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2™ Increased Orthogonality
DL1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible RAM/Cache Allocation)
DEndianess: Little Endian, Big Endian
D32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1024M-Byte Total Addressable External
Memory Space
DEnhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D10/100 Mb/s Ethernet MAC (EMAC)
− IEEE 802.3 Compliant
− Media Independent Interface (MII)
− 8 Independent Transmit (TX) Channels
and 1 Receive (RX) Channel
DManagement Data Input/Output (MDIO)
DTwo Configurable Video Ports (DM641)
DOne Configurable Video Port (DM640)
− Providing a Glueless I/F to Common
Video Decoder and Encoder Devices
− Supports Multiple Resolutions and Video
Standards
DVCXO Interpolated Control Port (VIC)
− Supports Audio/Video Synchronization
DHost-Port Interface (HPI) [16-Bit] (DM641)
DMultichannel Audio Serial Port (McASP)
− Four Serial Data Pins
− Wide Variety of I2S and Similar Bit
Stream Format
− Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats
DInter-Integrated Circuit (I2C) Bus
DTwo Multichannel Buffered Serial Ports
DThree 32-Bit General-Purpose Timers
DEight General-Purpose I/O (GPIO) Pins
DFlexible PLL Clock Generator
DIEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
D548-Pin Ball Grid Array (BGA) Package
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch
D548-Pin Ball Grid Array (BGA) Package
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
D0.13-μm/6-Level Cu Metal Process (CMOS)
D3.3-V I/O, 1.2-V Internal (-400, -500)
D3.3-V I/O, 1.4-V Internal (-600)
C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Description
15
June 2003 − Revised October 2010 SPRS222F
1.2 Description
The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641
(DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance,
advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas
Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a
code-compatible member of the C6000™ DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641
device offers cost-effective solutions to high-performance DSP programming challenges.
With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640
device offers cost-effective solutions to high-performance DSP programming challenges.
The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit
word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic
logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs)
per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of
4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The
DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000™ DSP platform devices.
The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1-Mbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one
configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output
(MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port
(McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs);
three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16) [DM641]; an 8-pin general-purpose
input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external
memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and
peripherals.
The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The
DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port
peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640
video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU−BT.656).
These video port peripherals are configurable and can support either video capture and/or video display
modes.
For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated
Control (VIC) Port Reference Guide (literature number SPRU629).
The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins
transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple
serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S)
format.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Description
16 June 2003 − Revised October 2010SPRS222F
In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,
CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user
data and channel status fields.
McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range.
The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to
up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port,
see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature
number SPRU629).
The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP
core processor and the network. The DM641/DM640 EMAC support both 10Base-T and 100Base-TX, or 10
Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of
service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that
allows e fficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP
Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference
Guide (literature number SPRU628).
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO
module transparently monitors its link state by reading the PHY status register. Link change events are stored
in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device
without continuously performing costly MDIO accesses. For more details on the MDIO, see the
TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628).
The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may
be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
Windows is a registered trademark of the Microsoft Corporation.
Device Characteristics
17
June 2003 − Revised October 2010 SPRS222F
1.3 Device Characteristics
Table 1−1 provides an overview of the DM641 DSP. The table shows significant features of the DM641 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 1−1. Characteristics of the DM641 Processor
HARDWARE FEATURES DM641
EMIFA (32-bit bus width)
(clock source = AECLKIN) 1
EDMA (64 independent channels) 1
McASP0 (uses Peripheral Clock [AUXCLK]) 1
Peripherals
I2C0 (uses Peripheral Clock) 1
Peripherals HPI (16-bit) 1 (HPI16)
Not all peripherals pins are
available at the same time
McBSPs
(internal clock source = CPU/4 clock frequency) 2
available at the same time
(For more detail, see the
Device Configuration
Configurable Video Ports (VP0 and VP1) 2
(For more detail, see the
Device Configuration
section).
10/100 Ethernet MAC (EMAC) 1
section).
Management Data Input/Output (MDIO) 1
VCXO Interpolated Control Port (VIC) 1
32-Bit Timers
(internal clock source = CPU/8 clock frequency) 3
General-Purpose Input/Output Port (GP0) 8
Size (Bytes) 160K
On-Chip Memory Organization 16K-Byte (16KB) L1 Program (L1P) Cache
16KB L1 Data (L1D) Cache
128KB Unified Mapped RAM/Cache (L2)
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01
JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F
Frequency MHz 500, 600
Cycle Time ns
2 ns (DM641-500)
[500-MHz CPU, 100 MHz EMIF†]
1.67 ns (DM641-600)
[600-MHz CPU, 133 MHz EMIF†]
Voltage
Core (V) 1.2 V (-500)
1.4 V (-600)
Voltage
I/O (V) 3.3 V
PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12
BGA Package
23 x 23 mm 548-Pin BGA (GDK and ZDK)
BGA Package
27 x 27 mm 548-Pin BGA (GNZ and ZNZ)
Process Technology μm 0.13 μm
Product Status‡Product Preview (PP), Advance Information (AI),
or Production Data (PD) PD
†On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
‡PRODUCTION D AT A information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Device Characteristics
18 June 2003 − Revised October 2010SPRS222F
Table 1−2 provides an overview of the DM640 DSP. The table shows significant features of the DM640 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 1−2. Characteristics of the DM640 Processor
HARDWARE FEATURES DM640
EMIFA (32-bit bus width)
(clock source = AECLKIN) 1
EDMA (64 independent channels) 1
McASP0 (uses Peripheral Clock [AUXCLK]) 1
Peripherals
I2C0 (uses Peripheral Clock) 1
Peripherals
Not all peripherals pins are
available at the same time
McBSPs
(internal clock source = CPU/4 clock frequency) 2
Not all peripherals pins are
available at the same time
(For more detail, see the
Configurable Video Port (VP0) 1
(For more detail, see the
Device Configuration 10/100 Ethernet MAC (EMAC) 1
Device Configuration
section). Management Data Input/Output (MDIO) 1
VCXO Interpolated Control Port (VIC) 1
32-Bit Timers
(internal clock source = CPU/8 clock frequency) 3
General-Purpose Input/Output Port (GP0) 8
Size (Bytes) 160K
On-Chip Memory Organization 16K-Byte (16KB) L1 Program (L1P) Cache
16KB L1 Data (L1D) Cache
128KB Unified Mapped RAM/Cache (L2)
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01
JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F
Frequency MHz 400
Cycle Time ns 2.5 ns (DM640-400)
[400-MHz CPU, 100 MHz EMIF†]
Voltage
Core (V) 1.2 V (-400)
Voltage
I/O (V) 3.3 V
PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12
BGA Package
23 x 23 mm 548-Pin BGA (GDK and ZDK)
BGA Package
27 x 27 mm 548-Pin BGA (GNZ and ZNZ)
Process Technology μm 0.13 μm
Product Status‡Product Preview (PP), Advance Information (AI),
or Production Data (PD) PD
†On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
‡PRODUCTION D AT A information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Device Compatibility
19
June 2003 − Revised October 2010 SPRS222F
1.4 Device Compatibility
The DM641/DM640 device is a code-compatible member of the C6000™ DSP platform.
The C64x™ DSP generation of devices has a diverse and powerful set of peripherals. The common peripheral
set and pin-compatibility that the DM641 and DM640 devices offer lead to easier system designs and faster
time to market.
The DM640 device is a sub-set of the DM641 device and does not support an HPI peripheral or a second Video
Port (VP1) peripheral. Table 1−3 identifies the peripherals that are available on the DM641 and DM640
devices.
Table 1−3. Peripherals Available on the DM641 and DM640 Devices†‡
PERIPHERALS/COPROCESSORS DM641 DM640
EMIFA (32-bit bus width) √ √
EDMA (64 independent channels) √ √
10/100 EMAC √ √
MDIO √ √
HPI (16-bit) √—
McBSPs (McBSP0, McBSP1) √ √
McASP (4-bit) √ √
8-bit Video Port (VP0) √ √
8-bit Video Port (VP1) √—
VIC √ √
I2C √ √
Timers (32-bit) [TIMER0, TIMER1, TIMER2] √ √
GPIOs (GP[7:0]) √ √
†— denotes peripheral/coprocessor is not available on this device.
‡Not all peripherals pins are available at the same time. (For more details, see the Device
Configuration section.)
1.5 Functional Block Diagram
Figure 1−1 shows the functional block diagram of the DM641/DM640 devices.
Functional Block Diagram
20 June 2003 − Revised October 2010SPRS222F
HPI†
Test
C64x DSP Core
Data Path B
B Register File
B31−B16
B15−B0
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
A Register File
A31−A16
A15−A0
Power-Down
Logic
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
32
SDRAM
FIFO
SBSRAM
SRAM
L1P Cache
Direct-Mapped
16K Bytes Total
Control
Registers
Control
Logic
L1D Cache 2-Way Set-Associative
16K Bytes Total
Advanced
In-Circuit
Emulation
Interrupt
Control
TMS320DM641/TMS320DM640
Enhanced
DMA
Controller
(EDMA)
L2
Cache
Memory
128KBytes
PLL
(x1, x6, x12)
Timer 2
EMIF A
ZBT SRAM Timer 1
Boot Configuration
ROM/FLASH
I/O Devices
McBSP1‡
OR
McASP0
Data
AND
EMAC
MDIO
GP0
I2C0
8
16
See Note A
McBSP0‡
OR
McASP0
Control
AND
Timer 0
8-Bit
VP0
8-Bit
VP1†
VCXO
Interpolated
Control Port
(VIC)
†HPI and VP1 are not supported on the DM640 device.
‡McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins (DM641/DM640). The Video
Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins (DM641 only). For more details on the
multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.
Figure 1−1. Functional Block Diagram
CPU (DSP Core) Description
21
June 2003 − Revised October 2010 SPRS222F
1.6 CPU (DSP Core) Description
The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x™ VelociTI.2™ extensions add enhancements to the TMS320C62x™ DSP
VelociTI™ architecture. These enhancements include:
•Register file enhancements
•Data path extensions
•Quad 8-bit and dual 16-bit extensions with data flow enhancements
•Additional functional unit hardware
•Increased orthogonality of the instruction set
•Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the
packed 16-bit and 32-/40-bit fixed-point data types found in the C62x™ VelociTI™ VLIW architecture, the
C64x™ register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional
units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP
core) diagram, and Figure 1−2]. The four functional units on each side of the CPU can freely share the 32
registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus
connected t o all the registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock
cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in
the same execute packet. All functional units in the C64x CPU can access operands via the data cross path.
Register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read
a register via a data cross path if that register was updated in the previous clock cycle.
In addition to the C62x™ DSP fixed-point instructions, the C64x™ DSP includes a comprehensive collection
of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2™ extensions allow the C64x CPU
to operate directly on packed data to streamline data flow and increase instruction set efficiency. This is a key
factor for video and imaging applications.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file.
The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single
instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits)
with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access
words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes
using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most
can access any one of the 64 registers. Some registers, however, are singled out to support specific
addressing modes or to hold the condition for conditional instructions (if the condition is not automatically
“true”).
TMS320C62x and C62x are trademarks of Texas Instruments.
CPU (DSP Core) Description
22 June 2003 − Revised October 2010SPRS222F
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 ×8-bit multiplies per clock cycle. The .M unit can also perform 1 6 ×32-bit multiply
operations, dual 16 ×16-bit multiplies with add/subtract operations, and quad 8 ×8-bit multiplies with add
operations. I n a ddition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x™ DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x™/TMS320C67x™ DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in
the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the
C64x™ DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the
NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective
functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After decoding, the instructions
simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock
cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes,
half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or
doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
•TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
•TMS320C64x Technical Overview (literature number SPRU395)
TMS320C67x is a trademark of Texas Instruments.
CPU (DSP Core) Description
23
June 2003 − Revised October 2010 SPRS222F
.L1
.S1
.M1
.D1
.D2
.M2
.S2
.L2
src1
long dst
88
src2
DA1 (Address)
ST1b (Store Data)
ST2a (Store Data)
Register
File A
(A0−A31)
8
8
88
dst
Data Path A
DA2 (Address)
Register
File B
(B0− B31)
LD2a (Load Data)
Data Path B
Control Register
File
ST2b (Store Data)
LD1b (Load Data)
8
8
2X
1X
ST1a (Store Data)
See Note A
See Note A
LD1a (Load Data)
LD2b (Load Data)
See Note A
See Note A
32 MSBs
32 LSBs
32 MSBs
32 LSBs
32 MSBs
32 LSBs
32 MSBs
32 LSBs
src2
src1
dst
long dst
long src
long src
long dst
dst
src1
src2
src1
src2
src2
src1
dst
src2
src1
dst
src2
long dst
src2
src1
dst
long dst
long dst
long src
long src
long dst
dst
dst
src2
src1
dst
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1−2. TMS320C64x™ CPU (DSP Core) Data Paths
CPU (DSP Core) Description
24 June 2003 − Revised October 2010SPRS222F
1.6.1 CPU Core Registers
Table 1−4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0184 0000 CCFG Cache configuration register
0184 0004 − 0184 0FFC − Reserved
0184 1000 EDMAWEIGHT L2 EDMA access control register
0184 1004 − 0184 1FFC − Reserved
0184 2000 L2ALLOC0 L2 allocation register 0
0184 2004 L2ALLOC1 L2 allocation register 1
0184 2008 L2ALLOC2 L2 allocation register 2
0184 200C L2ALLOC3 L2 allocation register 3
0184 2010 − 0184 3FFC − Reserved
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback invalidate base address register
0184 4014 L2WIWC L2 writeback invalidate word count register
0184 4018 L2IBAR L2 invalidate base address register
0184 401C L2IWC L2 invalidate word count register
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback invalidate base address register
0184 4034 L1DWIWC L1D writeback invalidate word count register
0184 4038 − 0184 4044 − Reserved
0184 4048 L1DIBAR L1D invalidate base address register
0184 404C L1DIWC L1D invalidate word count register
0184 4050 − 0184 4FFC − Reserved
0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback invalidate all register
0184 5008 − 0184 7FFC − Reserved
0184 8000 −0184 81FC MAR0 to
MAR127 Reserved
0184 8200 MAR128 Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
0184 8204 MAR129 Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
0184 8208 MAR130 Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
0184 820C MAR131 Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
0184 8210 MAR132 Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
0184 8214 MAR133 Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
0184 8218 MAR134 Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
0184 821C MAR135 Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
0184 8220 MAR136 Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
0184 8224 MAR137 Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
0184 8228 MAR138 Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
0184 822C MAR139 Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
0184 8230 MAR140 Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
0184 8234 MAR141 Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
CPU (DSP Core) Description
25
June 2003 − Revised October 2010 SPRS222F
Table 1−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 8238 MAR142 Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
0184 823C MAR143 Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
0184 826C MAR155 Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
0184 8278 MAR158 Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 − A0FF FFFF
0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 − A1FF FFFF
0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 − A2FF FFFF
0184 828C MAR163 Controls EMIFA CE2 range A300 0000 − A3FF FFFF
0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 − A4FF FFFF
0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 − A5FF FFFF
0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 − A6FF FFFF
0184 829C MAR167 Controls EMIFA CE2 range A700 0000 − A7FF FFFF
0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 − A8FF FFFF
0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 − A9FF FFFF
0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 − B0FF FFFF
0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 − B1FF FFFF
0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 − B2FF FFFF
0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 − B3FF FFFF
0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 − B4FF FFFF
0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 − B5FF FFFF
0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 − B6FF FFFF
0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 − B7FF FFFF
0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 − B8FF FFFF
CPU (DSP Core) Description
26 June 2003 − Revised October 2010SPRS222F
Table 1−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 − B9FF FFFF
0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
0184 8300 −0184 83FC MAR192 to
MAR255 Reserved
0184 8400 −0187 FFFF − Reserved
Memory Map Summary
27
June 2003 − Revised October 2010 SPRS222F
1.7 Memory Map Summary
Table 1−5 shows the memory map address ranges of the DM641/DM640 device. Internal memory is always
located at address 0 and can be used as both program and data memory. The external memory address
ranges in the DM641/DM640 device begin at the hex address location 0x8000 0000 for EMIFA.
Table 1−5. TMS320DM641/DM640 Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE
(BYTES) HEX ADDRESS RANGE
Internal RAM (L2) 128K 0000 0000 – 0001 FFFF
Reserved 768K 0004 0000 – 000F FFFF
Reserved 23M 0010 0000 – 017F FFFF
External Memory Interface A (EMIFA) Registers 256K 0180 0000 – 0183 FFFF
L2 Registers 256K 0184 0000 – 0187 FFFF
HPI Registers (DM641 only)†256K 0188 0000 – 018B FFFF
McBSP 0 Registers 256K 018C 0000 – 018F FFFF
McBSP 1 Registers 256K 0190 0000 – 0193 FFFF
Timer 0 Registers 256K 0194 0000 – 0197 FFFF
Timer 1 Registers 256K 0198 0000 – 019B FFFF
Interrupt Selector Registers 256K 019C 0000 – 019F FFFF
EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF
Reserved 512K 01A4 0000 – 01AB FFFF
Timer 2 Registers 256K 01AC 0000 – 01AF FFFF
GP0 Registers 256K − 4K 01B0 0000 – 01B3 EFFF
Device Configuration Registers 4K 01B3 F000 – 01B3 FFFF
I2C0 Data and Control Registers 16K 01B4 0000 – 01B4 3FFF
Reserved 32K 01B4 4000 – 01B4 BFFF
McASP0 Control Registers 16K 01B4 C000 – 01B4 FFFF
Reserved 192K 01B5 0000 – 01B7 FFFF
Reserved 256K 01B8 0000 – 01BB FFFF
Emulation 256K 01BC 0000 – 01BF FFFF
Reserved 256K 01C0 0000 – 01C3 FFFF
VP0 Control 16K 01C4 0000 – 01C4 3FFF
VP1 Control (DM641 only)†16K 01C4 4000 – 01C4 7FFF
Reserved 32K 01C4 8000 – 01C4 FFFF
Reserved 192K 01C5 0000 – 01C7 FFFF
EMAC Control 4K 01C8 0000 – 01C8 0FFF
EMAC Wrapper 8K 01C8 1000 – 01C8 2FFF
EWRAP Registers 2K 01C8 3000 – 01C8 37FF
MDIO Control Registers 2K 01C8 3800 – 01C8 3FFF
Reserved 3.5M 01C8 4000 – 01FF FFFF
QDMA Registers 52 0200 0000 – 0200 0033
Reserved 928M – 52 0200 0034 – 2FFF FFFF
McBSP 0 Data 64M 3000 0000 – 33FF FFFF
†For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals.
Memory Map Summary
28 June 2003 − Revised October 2010SPRS222F
Table 1−5. TMS320DM641/DM640 Memory Map Summary (Continued)
MEMORY BLOCK DESCRIPTION HEX ADDRESS RANGE
BLOCK SIZE
(BYTES)
McBSP 1 Data 64M 3400 0000 – 37FF FFFF
Reserved 64M 3800 0000 – 3BFF FFFF
McASP0 Data 1M 3C00 0000 – 3C0F FFFF
Reserved 64M − 1M 3C10 0000 – 3FFF FFFF
Reserved 832M 4000 0000 – 73FF FFFF
VP0 Channel A Data 32M 7400 0000 – 75FF FFFF
Reserved 32M 7600 0000 – 77FF FFFF
VP1 Channel A Data (DM641 only)†32M 7800 0000 – 79FF FFFF
Reserved 32M 7A00 0000 – 7BFF FFFF
Reserved 64M 7C00 0000 – 7FFF FFFF
EMIFA CE0 256M 8000 0000 – 8FFF FFFF
EMIFA CE1 256M 9000 0000 – 9FFF FFFF
EMIFA CE2 256M A000 0000 – AFFF FFFF
EMIFA CE3 256M B000 0000 – BFFF FFFF
Reserved 1G C000 0000 – FFFF FFFF
†For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals.
Memory Map Summary
29
June 2003 − Revised October 2010 SPRS222F
1.7.1 L2 Architecture Expanded
Figure 1−3 shows the detail of the L2 architecture on the TMS320DM641/DM640 devices. For more
information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the
TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610).
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ
011010001
0x0000 0000
000
L2 Memory Block Base Address
0x0001 8000
0x0001 0000
0x0002 0000
32K Cache
(4 Way)
64K Cache (4 Way)
128K Cache (4 Way)
128K SRAM (All)
96K SRAM
64K SRAM
64K-Byte RAM
32K-Byte RAM
0x0001 FFFF
32K-Byte RAM
†The L2MODE = 111b is not supported on the DM641/DM640 devices.
L2MODE†
Figure 1−3. TMS320DM641/DM640 L2 Architecture Memory Configuration
Bootmode
30 June 2003 − Revised October 2010SPRS222F
1.8 Bootmode
The DM641/DM640 device resets using the active-low signal RESET. While RESET is low, the device is held
in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET starts the processor running with the prescribed
device configuration and boot mode.
The DM641 has three types of boot modes while the DM640 has only two types of boot modes:
•Host boot [DM641 only]
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. For the DM641 device, the HPI peripheral is used for host boot. Once the
host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete
the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled”
state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU,
because i t o c c u r s w h i l e t h e C P U i s still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled”
state only if the host boot process is selected. All memory may be written to and read by the host. This
allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state,
the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
•EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be
stored in the endian format that the system is using. In this case, the EMIF automatically assembles
consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done
by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the “stalled” state and starts running from address 0.
•No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
Pin Assignments
31
June 2003 − Revised October 2010 SPRS222F
1.9 Pin Assignments
On Quadrants A, B, C, and D, shading denotes pin assignments that have different functionality between the
DM641 and DM640 devices [DM640 denoted within ( )]. See the Terminal Functions table for details.
1.9.1 Pin Map
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
13121110987654321
13121110987654321
CLKMODE1
CLKMODE0
PLLV
RESET
VDAC
HCNTL1
(RSV107)
HCS
(RSV109)
HAS
(RSV108)
HDS1
(RSV100)
HDS2
(RSV101)
HD15
(RSV125)
HD14
(RSV124)
HD13
(RSV123)
HD12
(RSV122)
HD11
(RSV121)
HD10
(RSV120)
HD9
(RSV119)
HD8
(RSV118)
HD7
(RSV117)
HD6
(RSV116)
HD4
(RSV114)
HD3
(RSV113)
HD2
(RSV112)
HD1
(RSV111)
HD0
(RSV110)
RSV54
(RSV60)
RSV55
(RSV61)
MDCLK
RSV56
(RSV62)
MDIO
STCLK
RSV19
(RSV25)
RSV20
(RSV26)
AXR0[3]
RSV18
(RSV24) AHCLKX0
RSV17
(RSV23)
AXR0[2]
AXR0[1]
AXR0[0]
RSV16
(RSV22)
RSV15
(RSV21)
VP1D[7]
(RSV20)
VP1D[6]/
CLKR1
VP1D[5]/
FSR1
VP1D[4]/
DR1
VP1D[3]/
CLKS1
VP1D[2]/
DX1
VP1D[1]/
FSX1
VP1D[0]/
CLKX1
RSV14
(RSV19)
RSV13
(RSV18)
VP1CLK1
(RSV14)
VP1CLK0
(RSV13)
VP1CTL2
(RSV17)
VP1CTL1
(RSV16)
VP1CTL0
(RSV15)
ACLKX0
AMUTE0
AMUTEIN0
VP0CLK1
AFSX0
RSV08
RSV06
RSV00
RSV01
RSV02
RSV03
RSV04
DVDD DVDD
DVDD
DVDD
DVDD
DVDD
DVDD DVDD
DVDD DVDD DVDD DVDD
DVDD
CVDD CVDD
CVDD
CVDD
CVDD
CVDD CVDD CVDD CVDD CVDD CVDD
CVDD CVDD VSS VSS VSS
VSS VSS VSS VSS VSS
CLKIN VSS
VSS VSS
VSS VSS VSS VSS
VSS VSS
VSS VSS VSS
VSS VSS
VSS VSS VSS
VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS VSS
VSS
VSS VSS VSS
HD5
(RSV115)
HCNTL0
(RSV106)
VSS
Figure 1−4. DM641/DM640 Pin Map [Quadrant A]
Pin Assignments
32 June 2003 − Revised October 2010SPRS222F
RSV84
(RSV90)
14 15 16 17 18 19 20 21 22 23 24 25 26
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
RSV93
(RSV99)
RSV92
(RSV98)
RSV91
(RSV97)
RSV90
(RSV96)
ABUSREQ
ASOE3
AEA22
AEA21 AEA20 AEA19AEA18
AEA17 AEA16 AEA15
AEA14 AEA13
AEA12 AEA11
AEA10 AEA9 AEA8
RSV89
(RSV95)
RSV88
(RSV94)
RSV87
(RSV93)
RSV86
(RSV92)
RSV85
(RSV91)
RSV83
(RSV89)
RSV82
(RSV88)
RSV81
(RSV87)
RSV80
(RSV86)
RSV79
(RSV85)
RSV78
(RSV84)
RSV77
(RSV83)
RSV76
(RSV82)
RSV75
(RSV81)
RSV74
(RSV80)
RSV73
(RSV79)
RSV72
(RSV78)
RSV71
(RSV77)
RSV70
(RSV76)
RSV69
(RSV75)
RSV68
(RSV74)
RSV67
(RSV73)
RSV66
(RSV72)
RSV65
(RSV71)
RSV64
(RSV70)
RSV63
(RSV69)
RSV62
(RSV68)
RSV61
(RSV67)
RSV60
(RSV66)
RSV59
(RSV65)
RSV58
(RSV64)
AHCLKR0
AFSR0
ACLKR0
RSV12
RSV11
VP0D[7]
VP0D[6]/
CLKR0
VP0D[5]/
FSR0
VP0D[4]/
DR0
VP0D[3]/
CLKS0
VP0D[2]/
DX0
VP0D[1]/
FSX0
VP0D[0]/
CLKX0
RSV10
RSV09VP0CLK0
VP0CTL2
VP0CTL1
VP0CTL0
DVDD
DVDD
DVDD
DVDD
DVDD
AHOLDDVDD DVDD
DVDD
DVDD DVDD
DVDD DVDD DVDD
DVDD DVDD
DVDD
DVDD
DVDD DVDD
DVDD
CVDD CVDD
CVDD
CVDD
CVDD
CVDD
CVDD CVDD CVDD CVDD CVDD CVDD
CVDD VSS
VSS VSS
VSS VSS
VSS VSS
VSS
VSS VSS
VSS VSS
VSS VSS
VSS
VSS VSS VSS VSS
VSS VSS
VSS
VSS VSS VSS
VSS
VSS VSS VSS
VSS VSS VSS VSS
CVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 1−4. DM641/DM640 Pin Map (Continued) [Quadrant B]
Pin Assignments
33
June 2003 − Revised October 2010 SPRS222F
RSV30
(RSV36)
N
M
L
K
J
H
G
F
E
D
C
B
A
CLKOUT6/
GP0[2]
NMI
GP0[7]/
EXT_INT7
GP0[6]/
EXT_INT6
GP0[5]/
EXT_INT5
GP0[4]/
EXT_INT4
RSV52
(RSV58)
RSV51
(RSV57)
RSV50
(RSV56)
RSV49
(RSV55)
RSV48
(RSV54)
RSV47
(RSV53)
RSV46
(RSV52)
GP0[3]
GP0[0]
RSV53
(RSV59)
HINT
(RSV103)
HHWIL
(RSV104)
HR/W
(RSV102)
HRDY
(RSV105)
MRCLK
MCRS
MRXER
MRXDV
MRXD3
MRXD2MRXD1
HD24/
AD24/
MRXD0
RSV57
(RSV63)
13121110987654321
MTCLK
MCOL
MTXENMTXD3
MTXD2MTXD1 MTXD0
RSV45
(RSV51)
RSV44
(RSV50)
RSV42
(RSV48)
RSV41
(RSV47)
RSV40
(RSV46)
RSV38
(RSV44)
RSV36
(RSV42)
RSV34
(RSV40)
RSV32
(RSV38)
RSV28
(RSV34)
RSV26
(RSV32)
RSV21
(RSV27)
RSV22
(RSV28)
RSV25
(RSV31)
TOUT1/
LENDIAN
TINP1
TOUT0/
MAC_EN
TINP0
SCL0
RSV07
DVDD
DVDD DVDD
DVDD
DVDD DVDD DVDD DVDD
DVDD DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CVDD CVDD
CVDD CVDD
CVDD
CVDD CVDD CVDD
CVDD
CVDD
CVDD
CVDD CVDD
VSS VSS VSS VSS VSS
VSS VSS VSS VSS
VSS VSS
VSS
VSS
VSS VSS VSS
VSS VSS VSS
VSS VSS VSS VSS VSS
VSS
VSS VSS
VSS VSS
VSS VSS
VSS
VSS VSS
VSS VSS
VSS VSS VSS
SDA0 DVDD
CLKOUT4/
GP0[1]
RSV24
(RSV30)
RSV27
(RSV33)
RSV31
(RSV37)
RSV35
(RSV41)
RSV39
(RSV45)
RSV43
(RSV49)
RSV23
(RSV29)
RSV29
(RSV35)
RSV33
(RSV39)
RSV37
(RSV43)
13121110987654321
Figure 1−4. DM641/DM640 Pin Map (Continued) [Quadrant C]
Pin Assignments
34 June 2003 − Revised October 2010SPRS222F
N
M
L
K
J
H
G
F
E
D
C
B
A
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
TMS
TDO
TDITCK
TRST EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
EMU1
EMU0
ACE3
ACE2 ACE1 ACE0
ABE3 ABE2
ABE1 ABE0
APDT
AHOLDA
AECLKIN
AAOE/
ASDRAS/
ASOE
AARDY
AECLKOUT1
AARE/
ASDCAS/
ASADS/
ASRE
AAWE/
ASDWE/
ASWE
ASDCKE
AEA7 AEA6 AEA5
AEA4AEA4 AEA3
AED31AED30
AED29AED28
AED27 AED26
AED25 AED24AED23 AED22
AED21 AED20AED19 AED18
AED17 AED16
AED15
AED14
AED13
AED12
AED11
AED10
AED9
AED8
AED7
AED6 AED4
AED3
AED5
AED2
AED1
AED0
RSV05
DVDD
VSS
VSS
DVDD DVDD DVDD
DVDD
DVDD VSS
DVDD
DVDD DVDD DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CVDD CVDD
CVDD CVDD CVDD CVDD CVDD
CVDD
CVDD
CVDD
CVDD
CVDD CVDD
VSS VSS VSS
VSS
VSS
VSS VSS VSS
VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS
VSS VSS VSS
AECLKOUT2
CVDD
Figure 1−4. DM641/DM640 Pin Map (Continued) [Quadrant D]
Pin Assignments
35
June 2003 − Revised October 2010 SPRS222F
1.9.2 Signal Groups Description
TRST
GP0[7]/EXT_INT7‡
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Reset and
Interrupts
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
NMI
GP0[6]/EXT_INT6‡
GP0[5]/EXT_INT5‡
GP0[4]/EXT_INT4‡
RESET
RSV01
RSV02
Clock/PLL
CLKIN
CLKMODE1
CLKMODE0
PLLV
EMU2
EMU3
EMU4
EMU5
GP0
(8-Bit)
General-Purpose Input/Output 0 (GP0) Port
GP0[7]/EXT_INT7‡
GP0[6]/EXT_INT6‡
GP0[5]/EXT_INT5‡
GP0[4]/EXT_INT4‡
GP0[3]
CLKOUT6/GP0[2]†
CLKOUT4/GP0[1]†
GP0[0]
CLKOUT6/GP0[2]†
CLKOUT4/GP0[1]†
EMU6
EMU7
EMU8
EMU9
EMU10
These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these
muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured.
For more details, see the Device Configurations section of this data sheet.
†
These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
‡
RSV00
EMU11
RSV92(124)
RSV93(125)
RSV91(123)
Peripheral
Control/Status TOUT0/MAC_EN
Figure 1−5. CPU and Peripheral Signals
Pin Assignments
36 June 2003 − Revised October 2010SPRS222F
ACE3 AECLKOUT1
AED[31:0]
ACE2
ACE1
ACE0
AEA[22:3] AARDY
Data
Memory Map
Space Select
Address
Byte Enables
32
20
External
Memory I/F
Control
EMIFA (32-bit)
AECLKIN
AHOLD
AHOLDA
ABUSREQ
Bus
Arbitration
AARE/ASDCAS/ASADS/ASR
E
ASDCKE
AECLKOUT2
ASOE3
ABE3
ABE2
ABE1
ABE0
AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE
APDT
VDAC
VCXO Interpolated
Control Port (VIC)
Data
HHWIL
HCNTL0
HCNTL1
Data
Register Select
Half-Word
Select
Control
HPI
(Host-Port Interface)
[DM641 only]
16
HD[15:0]
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
Figure 1−6. Peripheral Signals
Pin Assignments
37
June 2003 − Revised October 2010 SPRS222F
McBSPs
(Multichannel Buffered Serial Ports)
VP0D[0]/CLKX0†‡
VP0D[1]/FSX0†‡
VP0D[2]/DX0†‡
VP0D[6]/CLKR0†‡
VP0D[5]/FSR0†‡
VP0D[4]/DR0†‡
VP0D[3]/CLKS0†‡
Transmit
McBSP0
Receive
Clock
VP1D[0]/CLKX1†§
VP1D[1]/FSX1†§
VP1D[2]/DX1†§
VP1D[6]/CLKR1†§
VP1D[5]/FSR1†§
VP1D[4]/DR1†§
VP1D[3]/CLKS1†§
Transmit
McBSP1
Receive
Clock
TOUT0/MAC_EN
Timers
TINP0
TOUT1/LENDIAN Timer 1
TINP1
Timer 2
Timer 0
SCL0
I2C0
I2C0
SDA0
†For DM641, these McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and V ideo Port 0 (VP0) peripherals, respectively. By
default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins, see the Device Configurations section
of this data sheet.
‡For DM640, these McBSP0 pins are muxed with the Video Port 0 (VP0) peripheral. By default, these signals function as VP0. For more details
on these muxed pins, see the Device Configurations section of this data sheet.
§The DM640 device does not support the VP1 peripheral; therefore, the McBSP1 peripheral pins are standalone perpheral functions, not
muxed.
DM641/DM640
Figure 1−6. Peripheral Signals (Continued)
Pin Assignments
38 June 2003 − Revised October 2010SPRS222F
MCOL
MRXDV
MRXER
MTXEN
Ethernet MAC (EMAC)
and MDIO
MDIO
MDCLK
MDIO
Clock
MTXD0
MTXD1
MTXD2
MRXD1
MRXD2
MRXD3
EMAC
Transmit
MRXD0
MTXD3
Clocks
MRCLK
MTCLK
MCRS
Error Detect
and Control
Input/Output
Receive
Figure 1−6. Peripheral Signals (Continued)
Pin Assignments
39
June 2003 − Revised October 2010 SPRS222F
VP0D[0]/CLKX0
VP0D[1]/FSX0
VP0D[2]/DX0
VP0D[3]/CLKS0
VP0D[4]/DR0
VP0D[5]/FSR0
VP0D[6]/CLKR0
VP0D[7]
Capture/Display
Buffer
(2560 Bytes)
VP0CLK0
VP0CLK1
VP0CTL0
VP0CTL1
VP0CTL2
Timing and
Control Logic
Video Port 0 (VP0)
Channel A†
†Channel A supports: BT.656 (8-bit) display pipeline mode and BT.656 (8-bit) capture pipeline mode [TSI (8-bit) capture
pipeline mode].
STCLK
Figure 1−6. Peripheral Signals (Continued)
Pin Assignments
40 June 2003 − Revised October 2010SPRS222F
VP1D[0]/CLKX1
VP1D[1]/FSX1
VP1D[2]/DX1
VP1D[3]/CLKS1
VP1D[4]/DR1
VP1D[5]/FSR1
VP1D[6]/CLKR1
VP1D[7]
Capture/Display
Buffer
(2560 Bytes)
VP1CLK0
VP1CLK1
VP1CTL0
VP1CTL1
VP1CTL2
Timing and
Control Logic
Video Port 1 (VP1) [DM641 only]
Channel A†
†Channel A supports: BT.656 (8-bit) display pipeline mode and BT.656 (8-bit) capture pipeline mode [TSI (8-bit) capture
pipeline mode].
‡For DM641, the same STCLK signal is used for both video ports (VP0 and VP1).
STCLK‡
Figure 1−6. Peripheral Signals (Continued)
Pin Assignments
41
June 2003 − Revised October 2010 SPRS222F
McASP0
(Multichannel Audio Serial Port 0)
ACLKX0
AHCLKX0
Transmit
Clock
Generator
AMUTEIN0
Auto Mute
Logic AMUTE0
AFSX0
Transmit
Frame Sync
AFSR0 Receive
Frame Sync
ACLKR0
AHCLKR0 Receive Clock
Generator
AXR0[3]
AXR0[2]
AXR0[1]
AXR0[0] 8-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
Transmit
Clock Check
Circuit
Receive Clock
Check Circuit
Error Detect
(see Note A )
(Transmit/Receive Data Pins)(Transmit/Receive Data Pins)
(Receive Bit Clock) (Transmit Bit Clock)
(Receive Master Clock) (Transmit Master Clock)
(Receive Frame Sync or
Left/Right Clock) (Transmit Frame Sync or
Left/Right Clock)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 1−6. Peripheral Signals (Continued)
1.9.3 Terminal Functions
The terminal functions table (Table 1−6) identifies the external signal names, the associated pin (ball) numbers
along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
Pin Assignments
42 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions
SIGNAL
TYPE†
IPD/
IPU‡
DESCRIPTION
NAME DM641 DM640
TYPE†
IPD/
IPU‡
DESCRIPTION
CLOCK/PLL CONFIGURATION
CLKIN AC2 AC2 I Clock Input. This clock is the input to the on-chip PLL.
CLKOUT4/GP0[1]§ D6 D6 I/O/Z IPU Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 1 pin (I/O/Z).
CLKOUT6/GP0[2]§C6 C6 I/O/Z IPU Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 2 pin (I/O/Z).
CLKMODE1 AE4 AE4 I IPD Clock mode select
•Selects whether the CPU clock frequency = input clock frequency x1
(Bypass), x6, or x12.
CLKMODE0 AA2 AA2 I IPD
(Bypass), x6, or x12.
For mo r e d e t ails on the CLKMODE pins and the PLL multiply factors, see
the Clock PLL section of this data sheet.
PLLV¶V6 V6 A#PLL voltage supply
JTAG EMULATION
TMS E15 E15 I IPU JTAG test-port mode select
TDO B18 B18 O/Z IPU JTAG test-port data out
TDI A18 A18 I IPU JTAG test-port data in
TCK A16 A16 I IPU JTAG test-port clock
TRST D14 D14 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE
1149.1 JTAG compatibility statement portion of this data sheet.
EMU11 D17 D17 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected.
EMU10 C17 C17 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected.
EMU9 B17 B17 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected.
EMU8 D16 D16 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected.
EMU7 A17 A17 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected.
EMU6 C16 C16 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected.
EMU5 B16 B16 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU4 D15 D15 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3 C15 C15 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2 B15 B15 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
EMU1 C14 C14 I/O/Z IPU Emulation pin 1||
EMU0 A15 A15 I/O/Z IPU Emulation pin 0||
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
¶PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#A = Analog signal (PLL Filter)
|| The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ
resistor.
Pin Assignments
43
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL
TYPE†
IPD/
IPU‡
DESCRIPTION
NAME DM641 DM640
TYPE†
IPD/
IPU‡
DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET P4 P4 I Device reset
NMI B4 B4 I IPD
Nonmaskable interrupt, edge-driven (rising edge)
Note: Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the
NMI pin is not used, it is recommended that the NMI pin be grounded versus
relying on the IPD.
GP0[7]/EXT_INT7 E1 E1 I/O/Z IPU General-purpose input/output (GPIO) pins (I/O/Z) or external interrupt
s
(input only). The default after reset setting is GPIO enabled as input-only.
GP0[6]/EXT_INT6 F2 F2 I/O/Z IPU
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts
(input only). The default after reset setting is GPIO enabled as input-only
.
•
When these pins function as External Interrupts [by selecting the
GP0[5]/EXT_INT5 F3 F3 I/O/Z IPU
•When these pins function as External Interrupts [by selecting the
corresponding interrupt enable register bit (IER.[7:4])], they are
edge-driven and the polarity can be independently selected via the
GP0[4]/EXT_INT4 F4 F4 I/O/Z IPU
edge-driven and the polarity can be independently selected via the
External Interrupt Polarity Register bits (EXTPOL.[3:0]).
GP0[3] L5 L5 I/O/Z IPD The general-purpose 0 pin (GP0[3]) (I/O/Z).
GP0[0] M5 M5 I/O/Z IPD
GP0 0 pin (I/O/Z) [default]
This pin can be programmed as GPIO 0 (input only) [default] or as GP0[0]
(output only) pin or output as a general-purpose interrupt (GP0INT) signal
(output only).
Note: This pin must remain low during device reset.
CLKOUT6/
GP0[2]§C6 C6 I/O/Z IPU Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 2 pin (I/O/Z).
CLKOUT4/
GP0[1]§D6 D6 I/O/Z IPU Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 1 pin (I/O/Z).
HOST-PORT INTERFACE (HPI) [DM641 ONLY]
HINT N4 — I/O/Z Host interrupt from DSP to host (O) [default]
HCNTL1 P1 — I/O/Z Host control − selects between control, address, or data registers (I) [default]
HCNTL0 R3 — I/O/Z Host control − selects between control, address, or data registers (I) [default]
HHWIL N3 — I/O/Z Host half-word select − first or second half-word (not necessarily high or low
order) [For HPI16 bus width selection only] (I) [default]
HR/W M1 — I/O/Z Host read or write select (I) [default]
HAS P3 — I/O/Z Host address strobe (I) [default]
HCS R1 — I/O/Z Host chip select (I) [default]
HDS1 R2 — I/O/Z Host data strobe 1 (I) [default]
HDS2 T2 — I/O/Z Host data strobe 2 (I) [default]
HRDY N1 — I/O/Z Host ready from DSP to host (O) [default]
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
44 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
HOST-PORT INTERFACE (HPI) [DM641 ONLY] (CONTINUED)
HD15 T3 —
HD14 U1 —
HD13 U3 —
HD12 U2 —
HD11 U4 —
HD10 V1 —
Host-port data (I/O/Z) [DM641 Only]
HD9 V3 —
Host-port data (I/O/Z) [DM641 Only]
As HPI data bus
HD8 V2 —
I/O/Z
As HPI data bus
•Used for transfer of data, address, and control
HD7 W2 —
I/O/Z
•
Used for transfer of data, address, and control
HD6 W4 — For proper DM641 device operation, the HD5 pin at device reset must be
pulldown via a 10-k resistor.
HD5 Y1 —
For proper DM641 device operation, the HD5 pin at device reset must be
pulldown via a 10-kΩ resistor.
HD4 W3 —
HD3 Y2 —
HD2 Y4 —
HD1 AA1 —
HD0 Y3 —
EMIFA (32-BIT) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ACE3 L26 L26 O/Z IPU
EMIFA memory space enables
ACE2 K23 K23 O/Z IPU EMIFA memory space enables
•Enabled by bits 28 through 31 of the word address
ACE1 K24 K24 O/Z IPU •
Enabled by bits 28 through 31 of the word address
•
Only one pin is asserted during any external data access
ACE0 K25 K25 O/Z IPU
•Only one pin is asserted during any external data access
ABE3 M25 M25 O/Z IPU EMIFA byte-enable control
Decoded from the low-order address bits. The number of address bits
ABE2 M26 M26 O/Z IPU
EMIFA byte-enable control
•Decoded from the low-order address bits. The number of address bits
or byte enables used depends on the width of external memory.
ABE1 L23 L23 O/Z IPU
or byte enables used depends on the width of external memory.
•Byte-write enables for most types of memory
•Can be directly connected to SDRAM read and write mask
ABE0 L24 L24 O/Z IPU •
Can be directly connected to SDRAM read and write mask
signal (SDQM)
APDT M22 M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer between external
peripherals
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
45
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
EMIFA (32-BIT) − BUS ARBITRATION
AHOLDA N22 N22 O IPU EMIFA hold-request-acknowledge to the host
AHOLD W24 W24 I IPU EMIFA hold request from the host
ABUSREQ P22 P22 O IPU EMIFA bus request output
EMIFA (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
AECLKIN H25 H25 I IPD
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock,
or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the
AEA[20:19] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKOUT2 J23 J23 O/Z IPD EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN,
CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT1 J26 J26 O/Z IPD EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency].
AARE/
ASDCAS/
ASADS/ASRE J25 J25 O/Z IPU
EMIFA asynchronous memory read-enable/SDRAM column-address
strobe/programmable synchronous interface-address strobe or read-enable
•For programmable synchronous interface, the RENEN field in the CE
Space Secondary Control Register (CExSEC) selects between ASADS
and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS
signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE
signal.
AAOE/
ASDRAS/
ASOE J24 J24 O/Z IPU EMIFA asynchronous memory output-enable/SDRAM row-address
strobe/programmable synchronous interface output-enable
AAWE/
ASDWE/
ASWE K26 K26 O/Z IPU EMIFA asynchronous memory write-enable/SDRAM
write-enable/programmable synchronous interface write-enable
ASDCKE L25 L25 O/Z IPU EMIFA SDRAM clock-enable (used for self-refresh mode).
•If SDRAM is not in system, ASDCKE can be used as a general-purpose
output.
ASOE3 R22 R22 O/Z IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO
interface)
AARDY L22 L22 I IPU Asynchronous memory ready input
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
46 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
EMIFA (32-BIT) − ADDRESS
AEA22 U23 U23
EMIFA external address (doubleword address)
AEA21 V24 V24 EMIFA external address (doubleword address)
EMIFA address numbering for the DM641/DM640 devices start with AEA3 to
AEA20 V25 V25
EMIFA address numbering for the DM641/DM640 devices start with AEA3 to
maintain signal name compatibility with other C64x™ devices (e.g., C6414
,
AEA19 V26 V26
maintain signal name compatibility with other C64x devices (e.g., C6414,
C6415, and C6416) [see the 32-bit EMIF addressing scheme in the
TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide
AEA18 V23 V23 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guid
e
(literature number SPRU266)].
AEA17 U24 U24
(literature number SPRU266)].
Boot Configuration:
AEA16 U25 U25 Boot Configuration:
Controls initialization of DSP modes at reset (I) via pullup/pulldown
AEA15 U26 U26 •
Controls initialization of DSP modes at reset (I) via pullup/pulldown
resistors
AEA14 T24 T24
resistors
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
AEA13 T25 T25
O/Z
IPD
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
01 − HPI [DM641 only]; Reserved [For DM640 device]
AEA12 R23 R23
O/Z
IPD
01 − HPI [DM641 only]; Reserved [For DM640 device]
10 − Reserved
AEA11 R24 R24
10 − Reserved
11 − EMIFA 8−bit ROM boot
AEA10 P23 P23
11 − EMIFA 8−bit ROM boot
− EMIF clock select
AEA9 P24 P24
− EMIF clock select
AEA8 P26 P26 − AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
AEA7 N23 N23
− AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
AEA6 N24 N24
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
AEA5 N26 N26
10 − CPU/6 Clock Rate
11 − Reserved
AEA4 M23 M23
11 − Reserved
For more details, see the Device Configurations section of this data sheet.
AEA3 M24 M24
For more details, see the Device Configurations section of this data sheet.
EMIFA (32-BIT) − DATA
AED31 C26 C26
AED30 C25 C25
AED29 D26 D26
AED28 D25 D25
AED27 E24 E24
AED26 E25 E25
AED25 F24 F24
AED24 F25 F25
AED23 F23 F23
I/O/Z
IPU
EMIFA external data
AED22 F26 F26
I/O/Z
IPU
EMIFA external data
AED21 G24 G24
AED20 G25 G25
AED19 G23 G23
AED18 G26 G26
AED17 H23 H23
AED16 H24 H24
AED15 C19 C19
AED14 D19 D19
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
47
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
EMIFA (32-BIT) − DATA (CONTINUED)
AED13 A20 A20
AED12 D20 D20
AED11 B20 B20
AED10 C20 C20
AED9 A21 A21
AED8 D21 D21
AED7 B21 B21
I/O/Z
IPU
EMIFA external data
AED6 C21 C21
I/O/Z
IPU
EMIFA external data
AED5 A23 A23
AED4 C22 C22
AED3 B22 B22
AED2 B23 B23
AED1 A24 A24
AED0 B24 B24
MANAGEMENT DATA INPUT/OUTPUT (MDIO)
MDCLK R5 R5 I/O/Z IPD MDIO serial clock input/output (I/O/Z).
MDIO P5 P5 I/O/Z IPU MDIO serial data input/output (I/O/Z).
VCX0 INTERPOLATED CONTROL PORT (VIC)
VDAC AD1 AD1 O/Z IPD VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter
(VDAC) output [output only].
VIDEO PORTS (VP0 [DM641/DM640] AND VP1 [DM641 ONLY])
STCLK AC1 AC1 I IPD The STCLK signal drives the hardware counter on the video ports.
8-BIT VIDEO PORT 1 (VP1) [DM641 ONLY]
VP1D[7] AC8 —
Video port 1 (VP1) data input/output (I/O/Z) or McBSP1 data input/output
VP1D[6]/CLKR1§AD8 ***
Video port 1 (VP1) data input/output (I/O/Z) or McBSP1 data input/output
(I/O/Z) [default] [DM641 only]
VP1D[5]/FSR1§AC7 ***
(I/O/Z) [default] [DM641 only]
*** − The DM640 device does not support the VP1 peripheral; therefore, the
VP1D[4]/DR1§AD7 ***
I/O/Z
IPD
*** − The DM640 device does not support the VP1 peripheral; therefore, the
McBSP1 peripheral pins are standalone peripheral functions, not muxed.
VP1D[3]/CLKS1§AE7 ***
I/O/Z
IPD
McBSP1 peripheral pins are standalone peripheral functions, not muxed.
VP1D[2]/DX1§AC6 *** For more details on the McBSP1 pin functions [for both the DM641 and
DM640 devices], see McBSP1 section of this table and the Device
VP1D[1]/FSX1§AD6 ***
For more details on the McBSP1 pin functions [for both the DM641 and
DM640 devices], see McBSP1 section of this table and the Device
Configurations section of this data sheet.
VP1D[0]/CLKX1§AE6 ***
Configurations section of this data sheet.
VP1CLK1 AF10 — I/O/Z IPD VP1 clock 1 (I/O/Z)
VP1CLK0 AF8 — I IPD VP1 clock 0 (I)
VP1CTL2 AD5 — VP1 control 2 (I/O/Z)
VP1CTL1 AE5 — I/O/Z IPD VP1 control 1 (I/O/Z)
VP1CTL0 AF4 —
I/O/Z
IPD
VP1 control 0 (I/O/Z)
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
48 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
8-BIT VIDEO PORT 0 (VP0) [DM641 AND DM640]
VP0D[7] AD15 AD15
VP0D[6]/CLKR0§AE15 AE15
VP0D[5]/FSR0§AB16 AB16 Video port 0 (VP0) data input/output (I/O/Z) or McBSP0 data input/output
(I/O/Z) [default]
VP0D[4]/DR0§AC16 AC16
I/O/Z
IPD
Video port 0 (VP0) data input/output (I/O/Z) or McBSP0 data input/output
(I/O/Z) [default]
VP0D[3]/CLKS0§AD16 AD16
I/O/Z
IPD
For more details on the McBSP0 pin functions, see McBSP0 section of this
VP0D[2]/DX0§AE16 AE16
For more details on the McBSP0 pin functions, see McBSP0 section of this
table and the Device Configurations section of this data sheet.
VP0D[1]/FSX0§AF16 AF16
table and the Device Configurations section of this data sheet.
VP0D[0]/CLKX0§AF17 AF17
VP0CLK1 AF12 AF12 I/O/Z IPD VP0 clock 1 (I/O/Z)
VP0CLK0 AF14 AF14 I IPD VP0 clock 0 (I)
VP0CTL2 AD17 AD17 VP0 control 2 (I/O/Z)
VP0CTL1 AC17 AC17 I/O/Z IPD VP0 control 1 (I/O/Z)
VP0CTL0 AE17 AE17
I/O/Z
IPD
VP0control 0 (I/O/Z)
TIMER 2
— — No external pins. The timer 2 peripheral pins are not pinned out as external
pins.
TIMER 1
TOUT1/LENDIAN B5 B5 O/Z IPU
Timer 1 output (O/Z)
Boot Configuration: Device endian mode [LENDIAN] (I).
Controls initialization of DSP modes at reset via pullup/pulldown resistors
− Device Endian mode
0 – Big Endian
1 − Little Endian (default)
For more details on LENDIAN, see the Device Configurations section of this
data sheet.
TINP1 A5 A5 I IPD Timer 1 or general-purpose input
TIMER 0
TOUT0/MAC_EN C5 C5 O/Z IPD
Timer 0 output (O/Z)
Boot Configuration: MAC enable pin [MAC_EN] (I)
The MAC_EN pin controls the selection (enable/disable) of the EMAC and
MDIO peripherals.
For more details, see the Device Configurations section of this data sheet.
TINP0 A4 A4 I IPD Timer 0 or general-purpose input
INTER-INTEGRATED CIRCUIT 0 (I2C0)
SCL0 E4 E4 I/O/Z — I2C0 clock.
SDA0 D3 D3 I/O/Z — I2C0 data.
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
49
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) [DM641 ONLY]
VP1D[6]/CLKR1§AD8 — I/O/Z IPD Video Port 1 (VP1) input/output data 6 pin (I/O/Z) or McBSP1 receive clock
(I/O/Z) [default]
VP1D[5]/FSR1§AC7 — I/O/Z IPD VP1 input/output data 5 pin (I/O/Z) or McBSP1 receive frame sync (I/O/Z)
[default]
VP1D[4]/DR1§AD7 — I IPD VP1 input/output data 4 pin (I/O/Z) or McBSP1 receive data (I) [default]
VP1D[3]/CLKS1§AE7 — I IPD VP1 input/output data 3 pin (I/O/Z) or McBSP1 external clock source (I)
(as opposed to internal) [default]
VP1D[2]/DX1§AC6 — I/O/Z IPD VP1 input/output data 2 pin (I/O/Z) or McBSP1 transmit data (O/Z) [default]
VP1D[1]/FSX1§AD6 — I/O/Z IPD VP1 input/output data 1 pin (I/O/Z) or McBSP1 transmit frame sync (I/O/Z)
[default]
VP1D[0]/CLKX1§AE6 — I/O/Z IPD VP1 input/output data 0 pin (I/O/Z) or McBSP1 transmit clock (I/O/Z) [default]
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) [DM640 ONLY]
CLKR1 — AD8 I/O/Z IPD McBSP1 receive clock (I/O/Z)
FSR1 — AC7 I/O/Z IPD McBSP1 receive frame sync (I/O/Z)
DR1 — AD7 I IPD McBSP1 receive data (I)
CLKS1 — AE7 I IPD McBSP1 external clock source (I) (as opposed to internal)
DX1 — AC6 I/O/Z IPD McBSP1 transmit data (O/Z)
FSX1 — AD6 I/O/Z IPD McBSP1 transmit frame sync (I/O/Z)
CLKX1 — AE6 I/O/Z IPD McBSP1 transmit clock (I/O/Z)
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
VP0D[6]/CLKR0§AE15 AE15 I/O/Z IPD Video Port 0 (VP0) input/output data 6 pin (I/O/Z) or McBSP0 receive clock
(I/O/Z) [default]
VP0D[5]/FSR0§AB16 AB16 I/O/Z IPD VP0 input/output data 5 pin (I/O/Z) or McBSP0 receive frame sync (I/O/Z)
[default]
VP0D[4]/DR0§AC16 AC16 I IPD VP0 input/output data 4 pin (I/O/Z) or McBSP0 receive data (I) [default]
VP0D[3]/CLKS0§AD16 AD16 I IPD VP0 input/output data 3 pin (I/O/Z) or McBSP0 external clock source (I)
(as opposed to internal) [default]
VP0D[2]/DX0§AE16 AE16 O/Z IPD VP0 input/output data 2 pin (I/O/Z) or McBSP0 transmit data (O/Z) [default]
VP0D[1]/FSX0§AF16 AF16 I/O/Z IPD VP0 input/output data 1 pin (I/O/Z) or McBSP0 transmit frame sync (I/O/Z)
[default]
VP0D[0]/CLKX0§AF17 AF17 I/O/Z IPD VP0 input/output data 0 pin (I/O/Z) or McBSP0 transmit clock (I/O/Z) [default]
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
50 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
ETHERNET MAC (EMAC)
MRCLK G1 G1 I EMAC Media Independent I/F (MII) data, clocks, and control pins for
Transmit/Receive.
MCRS H3 H3 I
EMAC Media Independent I/F (MII) data, clocks, and control pins for
Transmit/Receive.
MII transmit clock (MTCLK),
MRXER G2 G2 I
MII transmit clock (MTCLK),
Transmit clock source from the attached PHY.
MII transmit data (MTXD[3:0]),
MRXDV J4 J4 I
MII transmit data (MTXD[3:0]),
Transmit data nibble synchronous with transmit clock (MTCLK).
MII transmit enable (MTXEN),
MRXD3 H2 H2 I MII transmit enable (MTXEN),
This signal indicates a valid transmit data on the transmit data pins
(MTDX[3:0]).
MRXD2 J3 J3 I
This signal indicates a valid transmit data on the transmit data pins
(MTDX[3:0]).
MII collision sense (MCOL)
MRXD1 J1 J1 I
MII collision sense (MCOL)
Assertion of this signal during half-duplex operation indicates network
collision.
MRXD0 K4 K4 I
collision.
During full-duplex operation, transmission of new frames will not begin if
this pin is asserted.
MTCLK L4 L4 I
During full-duplex operation, transmission of new frames will not begin if
this pin is asserted.
MII carrier sense (MCRS)
MCOL K2 K2 I
MII carrier sense (MCRS)
Indicates a frame carrier signal is being received.
MII receive data (MRXD[3:0]),
MTXEN L3 L3 O/Z
MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
MII receive clock (MRCLK),
MTXD3 L2 L2 O/Z
MII receive clock (MRCLK),
Receive clock source from the attached PHY.
MII receive data valid (MRXDV),
MTXD2 M4 M4 O/Z
Receive clock source from the attached PHY.
MII receive data valid (MRXDV),
This signal indicates a valid data nibble on the receive data pins
MTXD1 M2 M2 O/Z
This signal indicates a valid data nibble on the receive data pins
(MRDX[3:0]).
MII receive error (MRXER),
MTXD0 M3 M3 O/Z
MII receive error (MRXER),
Indicates reception of a coding error on the receive data.
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL
AHCLKX0 AC12 AC12 I/O/Z IPD McASP0 transmit high-frequency master clock (I/O/Z).
AFSX0 AD12 AD12 I/O/Z IPD McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z).
ACLKX0 AB13 AB13 I/O/Z IPD McASP0 transmit bit clock (I/O/Z).
AMUTE0 AC13 AC13 O/Z IPD McASP0 mute output (O/Z).
AMUTEIN0 AD13 AD13 I/O/Z IPD McASP0 mute input (I/O/Z).
AHCLKR0 AB14 AB14 I/O/Z IPD McASP0 receive high-frequency master clock (I/O/Z).
AFSR0 AC14 AC14 I/O/Z IPD McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z).
ACLKR0 AD14 AD14 I/O/Z IPD McASP0 receive bit clock (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA
AXR0[3] AE11 AE11
AXR0[2] AC10 AC10
I/O/Z
IPD
McASP0 TX/RX data pins [3:0] (I/O/Z).
AXR0[1] AD10 AD10
I/O/Z
IPD
McASP0 TX/RX data pins [3:0] (I/O/Z).
AXR0[0] AC9 AC9
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Pin Assignments
51
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL
TYPE†
IPD/
IPU‡
DESCRIPTION
NAME DM641 DM640
TYPE†
IPD/
IPU‡
DESCRIPTION
RESERVED FOR TEST
RSV E2 E2 I IPD Reserved. For proper DM641/DM640 device operation, this pin at device
reset must be pulled down via a 10-kΩ resistor.
RSV — Y1 I/O/Z — Reserved [for DM640 Only]. For proper DM640 device operation, this pin at
device reset must be pulled down via a 10-kΩ resistor.
RSV H7 H7 A — Reserved. This pin must be connected directly to CVDD for proper device
operation.
RSV R6 R6 A — Reserved. This pin must be connected directly to DVDD for proper device
operation.
ADDITIONAL RESERVED FOR TEST
A7 A7 I IPD
A9 A9 I/O/Z IPD
A10 A10 I/O/Z IPD
A11 A11 I/O/Z IPD
A13 A13 I/O/Z IPD
Reserved (leave unconnected, do not connect to power or ground)
B8 B8 I/O/Z IPD
Reserved (leave unconnected, do not connect to power or ground)
B9 B9 I/O/Z IPD
B10 B10 I/O/Z IPD
B11 B11 I/O/Z IPD
B12 B12 I/O/Z IPD
C1 C1 I/O/Z — Pull down via a 10-kΩ resistor
C7 C7 I/O/Z IPD
C8 C8 I/O/Z IPD
C9 C9 I/O/Z IPD
C10 C10 I/O/Z IPD
RSV C11 C11 I/O/Z IPD
RSV
C12 C12 I/O/Z IPD
D7 D7 I/O/Z IPD
D8 D8 I/O/Z IPD
Reserved (leave unconnected, do not connect to power or ground)
D9 D9 I/O/Z IPD
Reserved (leave unconnected, do not connect to power or ground)
D10 D10 I/O/Z IPD
D11 D11 I/O/Z IPD
D12 D12 I/O/Z IPD
E11 E11 I/O/Z IPD
E12 E12 I/O/Z IPD
E13 E13 I/O/Z IPD
E14 E14 I IPD
F1 F1 I/O/Z —
G3 G3 I/O/Z —
Pull down via a 10-kΩ resistor
G4 G4 I/O/Z —
Pull down via a 10-k
Ω
resistor
H4 H4 I/O/Z —
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
52 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
J2 J2 I/O/Z —
K1 K1 I/O/Z — Pull down via a 10-kΩ resistor
K3 K3 I/O/Z —
Pull down via a 10-kΩ resistor
R4 R4 I IPU
R25 R25 O/Z IPU
R26 R26 O/Z IPU
Reserved (leave unconnected, do not connect to power or ground)
T4 T4 O IPD
Reserved (leave unconnected, do not connect to power or ground)
T22 T22 O/Z IPU
T23 T23 O/Z IPU
V4 V4 I/O/Z — Pull down via a 10-kΩ resistor
W7 W7 A —
W23 W23 I/O/Z IPU
Y23 Y23 I/O/Z IPU
Y24 Y24 I/O/Z IPU
Y25 Y25 I/O/Z IPU
Y26 Y26 I/O/Z IPU
AA3 AA3 A —
AA23 AA23 I/O/Z IPU
AA24 AA24 I/O/Z IPU
RSV AA25 AA25 I/O/Z IPU
RSV
AA26 AA26 I/O/Z IPU
AB3 AB3 I —
AB11 AB11 I/O/Z IPD
AB12 AB12 I/O/Z IPD
AB15 AB15 I/O/Z IPD
Reserved (leave unconnected, do not connect to power or ground)
AB23 AB23 I/O/Z IPU
Reserved (leave unconnected, do not connect to power or ground)
AB24 AB24 I/O/Z IPU
AB25 AB25 I/O/Z IPU
AC4 AC4 O/Z —
AC11 AC11 I/O/Z IPD
AC15 AC15 I/O/Z IPD
AC19 AC19 I/O/Z IPU
AC20 AC20 I/O/Z IPU
AC21 AC21 I/O/Z IPU
AC25 AC25 I/O/Z IPU
AC26 AC26 I/O/Z IPU
AD3 AD3 O/Z —
AD9 AD9 I/O/Z IPD
AD11 AD11 I/O/Z IPD
AD19 AD19 I/O/Z IPU
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
53
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
AD20 AD20 I/O/Z IPU
AD21 AD21 I/O/Z IPU
AD22 AD22 I/O/Z IPU
AD23 AD23 I/O/Z IPU
AD25 AD25 I/O/Z IPU
AD26 AD26 I/O/Z IPU
AE9 AE9 I/O/Z IPD
AE18 AE18 I/O/Z IPD
AE20 AE20 I/O/Z IPU
AE21 AE21 I/O/Z IPU
Reserved (leave unconnected, do not connect to power or ground)
AE22 AE22 I/O/Z IPU
Reserved (leave unconnected, do not connect to power or ground)
AE23 AE23 I/O/Z IPU
AF3 AF3 O IPU
AF5 AF5 I/O/Z IPD
AF6 AF6 I/O/Z IPD
AF18 AF18 I/O/Z IPD
AF20 AF20 I/O/Z IPU
AF21 AF21 I/O/Z IPU
AF23 AF23 I/O/Z IPU
RSV AF24 AF24 I/O/Z IPU
RSV
— M1 I/O/Z — Pull up via a 10-kΩ resistor
— N1 I/O/Z — Pull down via a 10-kΩ resistor
— N3 I/O/Z —
— N4 I/O/Z —
— P1 I/O/Z —
— P3 I/O/Z —
Pull up via a 10-kΩ resistor
— R1 I/O/Z —
Pull up via a 10-k
Ω
resistor
— R2 I/O/Z —
— R3 I/O/Z —
— T2 I/O/Z —
— T3 I/O/Z —
— U1 I/O/Z —
— U2 I/O/Z —
— U3 I/O/Z —
— U4 I/O/Z —
Pull down via a 10-kΩ resistor
— V1 I/O/Z —
Pull down via a 10-k
Ω
resistor
— V2 I/O/Z —
— V3 I/O/Z —
— W2 I/O/Z —
— W3 I/O/Z —
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
54 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
— W4 I/O/Z —
— Y2 I/O/Z —
— Y3 I/O/Z — Pull down via a 10-kΩ resistor
— Y4 I/O/Z —
Pull down via a 10-kΩ resistor
— AA1 I/O/Z —
RSV — AC8 I/O/Z IPD
RSV
— AD5 I/O/Z IPD
— AE5 I/O/Z IPD
Reserved (leave unconnected, do not connect to power or ground)
— AF4 I/O/Z IPD
Reserved (leave unconnected, do not connect to power or ground)
— AF8 I IPD
— AF10 I/O/Z IPD
SUPPLY VOLTAGE PINS
A2 A2
A25 A25
B1 B1
B2 B2
B14 B14
B25 B25
B26 B26
C3 C3
C24 C24
D4 D4
DVDD
D23 D23
S
3.3-V supply voltage
DV
DD E5 E5
S
3.3-V supply voltage
E7 E7
E8 E8
E10 E10
E17 E17
E19 E19
E20 E20
E22 E22
F9 F9
F12 F12
F15 F15
F18 F18
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
55
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
SUPPLY VOLTAGE PINS (CONTINUED)
G5 G5
G22 G22
H5 H5
H22 H22
J6 J6
J21 J21
K5 K5
K22 K22
M6 M6
M21 M21
N2 N2
P25 P25
R21 R21
U5 U5
U22 U22
DV
V21 V21
S
3.3-V supply voltage
DVDD W5 W5 S3.3-V supply voltage
W22 W22
W25 W25
Y5 Y5
Y22 Y22
AA9 AA9
AA12 AA12
AA15 AA15
AA18 AA18
AB5 AB5
AB7 AB7
AB8 AB8
AB10 AB10
AB17 AB17
AB19 AB19
AB20 AB20
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
56 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
SUPPLY VOLTAGE PINS (CONTINUED)
AB22 AB22
AC23 AC23
AD24 AD24
AE1 AE1
DVDD
AE2 AE2
S
3.3-V supply voltage
DV
DD AE13 AE13
S
3.3-V supply voltage
AE25 AE25
AE26 AE26
AF2 AF2
AF25 AF25
F6 F6
F7 F7
F20 F20
F21 F21
G6 G6
G7 G7
G8 G8
G10 G10
G11 G11
G13 G13
G14 G14
CVDD
G16 G16
S
1.2-V supply voltage (-400, -500 devices)
CV
DD G17 G17
S
1.2-V supply voltage (-400, -500 devices)
1.4-V supply voltage (-600 device)
G19 G19
G20 G20
G21 G21
H20 H20
K7 K7
K20 K20
L7 L7
L20 L20
M12 M12
M14 M14
N7 N7
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
57
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
SUPPLY VOLTAGE PINS (CONTINUED)
N13 N13
N15 N15
N20 N20
P7 P7
P12 P12
P14 P14
P20 P20
R13 R13
R15 R15
T7 T7
T20 T20
U7 U7
U20 U20
W20 W20
CVDD
Y6 Y6
S
1.2-V supply voltage (-400, -500 devices)
CV
DD Y7 Y7
S
1.2-V supply voltage (-400, -500 devices)
1.4-V supply voltage (-600 device)
Y8 Y8
Y10 Y10
Y11 Y11
Y13 Y13
Y14 Y14
Y16 Y16
Y17 Y17
Y19 Y19
Y20 Y20
Y21 Y21
AA6 AA6
AA7 AA7
AA20 AA20
AA21 AA21
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
58 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
GROUND PINS
A1 A1
A3 A3
A6 A6
A8 A8
A12 A12
A14 A14
A19 A19
A22 A22
A26 A26
B3 B3
B6 B6
B7 B7
B13 B13
B19 B19
C2 C2
C4 C4
VSS
C13 C13
GND
Ground pins
V
SS C18 C18
GND
Ground pins
C23 C23
D1 D1
D2 D2
D5 D5
D13 D13
D18 D18
D22 D22
D24 D24
E3 E3
E6 E6
E9 E9
E16 E16
E18 E18
E21 E21
E23 E23
E26 E26
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
59
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
GROUND PINS (CONTINUED)
F5 F5
F8 F8
F10 F10
F11 F11
F13 F13
F14 F14
F16 F16
F17 F17
F19 F19
F22 F22
G9 G9
G12 G12
G15 G15
G18 G18
H1 H1
H6 H6
VSS
H21 H21
GND
Ground pins
V
SS H26 H26
GND
Ground pins
J5 J5
J7 J7
J20 J20
J22 J22
K6 K6
K21 K21
L1 L1
L6 L6
L21 L21
M7 M7
M13 M13
M15 M15
M20 M20
N5 N5
N6 N6
N12 N12
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
60 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
GROUND PINS (CONTINUED)
N14 N14
N21 N21
N25 N25
P2 P2
P6 P6
P13 P13
P15 P15
P21 P21
R7 R7
R12 R12
R14 R14
R20 R20
T1 T1
T5 T5
T6 T6
T21 T21
VSS
T26 T26
GND
Ground pins
V
SS U6 U6
GND
Ground pins
U21 U21
V5 V5
V7 V7
V20 V20
V22 V22
W1 W1
W6 W6
W21 W21
W26 W26
Y9 Y9
Y12 Y12
Y15 Y15
Y18 Y18
AA4 AA4
AA5 AA5
AA8 AA8
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
61
June 2003 − Revised October 2010 SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
GROUND PINS (CONTINUED)
AA10 AA10
AA11 AA11
AA13 AA13
AA14 AA14
AA16 AA16
AA17 AA17
AA19 AA19
AA22 AA22
AB1 AB1
AB2 AB2
AB4 AB4
AB6 AB6
AB9 AB9
AB18 AB18
AB21 AB21
V
AB26 AB26
GND
Ground pins
VSS AC3 AC3 GND Ground pins
AC5 AC5
AC18 AC18
AC22 AC22
AC24 AC24
AD2 AD2
AD4 AD4
AD18 AD18
AE3 AE3
AE8 AE8
AE10 AE10
AE12 AE12
AE14 AE14
AE19 AE19
AE24 AE24
AF1 AF1
AF7 AF7
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Pin Assignments
62 June 2003 − Revised October 2010SPRS222F
Table 1−6. Terminal Functions (Continued)
SIGNAL DESCRIPTION
IPD/
IPU‡
TYPE†
NAME DESCRIPTION
IPD/
IPU‡
TYPE†
DM640DM641
GROUND PINS (CONTINUED)
AF9 AF9
AF11 AF11
AF13 AF13
VSS AF15 AF15 GND Ground pins
VSS
AF19 AF19
GND
Ground pins
AF22 AF22
AF26 AF26
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor . To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
Development
63
June 2003 − Revised October 2010 SPRS222F
1.10 Development
1.10.1 Development Support
TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000™ DSP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000™ DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
Development
64 June 2003 − Revised October 2010SPRS222F
1.10.2 Device Support
1.10.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or T MS
(e.g., TMS320DM641GDK600). Texas Instruments recommends two of three possible prefix designators for
its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, GDK), the temperature range (for example, blank is the default commercial temperature
range), and the device speed range in megahertz (for example, -600 is 600 MHz). Figure 1−7 provides a
legend for reading the complete device name for any DSP platform member.
The ZDK package, like the GDK package, is a 548-ball plastic BGA only with Pb-free balls. The ZNZ package
is the Pb−free version of the GNZ package.
For device part numbers and further ordering information for TMS320DM641/DM640 in the GDK, GNZ, ZDK
and ZNZ package types, see the TI website (http://www.ti.com) or contact your TI sales representative.
Development
65
June 2003 − Revised October 2010 SPRS222F
DM64x DSP:
643
642
641
640
PREFIX DEVICE SPEED RANGE
TMS 320 DM641 GDK 600
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMX = Experimental device, MIL
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
DEVICE FAMILY
320 = TMS320t DSP family PACKAGE TYPE‡§
GDK = 548-pin plastic BGA
GNZ = 548-pin plastic BGA
ZDK = 548-pin plastic BGA, with Pb-free soldered balls
ZNZ = 548-pin plastic BGA, with Pb-free soldered balls
DEVICE¶
†The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices.
For more details, see the recommended operating conditions portion of this data sheet.
‡BGA = Ball Grid Array
§The ZDK and ZNZ mechanical package designators represent the version of the GDK and GNZ packages with Pb-free balls. For
more detailed information, see the Mechanical Data section of this document.
¶For actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)†
( )
Blank = 0°C to 90°C, commercial temperature
A = −40°C to 105°C, extended temperature
400 (400-MHz CPU, 100-MHz EMIF)
500 (500-MHz CPU, 100-MHz EMIF)
600 (600-MHz CPU, 133-MHz EMIF)
Figure 1−7. TMS320DM64x™ DSP Device Nomenclature (Including the DM641 and DM640 Devices)
1.10.2.2 Documentation Support
Extensive documentation supports all TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets, such as this document, with design specifications; complete user’s reference guides for all devices
and tools; technical briefs; development-support tools; on-line help; and hardware and software applications.
The following is a brief, descriptive list of support documentation specific to the C6000™ DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000™ DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an
overview and briefly describes the functionality of the peripherals available on the C6000™ DSP platform of
devices. This document also includes a table listing the peripherals available on the C6000 devices along with
literature numbers and hyperlinks to the associated peripheral documents.
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x™
digital signal processor, and discusses the application areas that are enhanced by the C64x™ DSP
VelociTI.2™ VLIW architecture.
The TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number
SPRU629) describes the functionality of the Video Port and VIC Port peripherals.
The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU041) describes the functionality of the McASP peripheral.
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
describes the functionality of the I2C peripheral.
TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628) describes the functionality of the EMAC and MDIO
peripherals.
Development
66 June 2003 − Revised October 2010SPRS222F
The TMS320DM641/TMS320DM640 Digital Signal Processors Silicon Errata (literature number SPRZ201)
describes the known exceptions to the functional specifications for particular silicon revisions of the
TMS320DM641 and TMS320DM640 devices.
The TMS320DM64x Power Consumption Summary application report (literature number SPRA962)
discusses the power consumption for user applications with the TMS320DM641/DM640 DSP devices.
The TMS320DM640/1 Hardware Designer’s Resource Guide (literature number SPRAA50) is organized by
development flow and functional areas to make design efforts as seamless as possible. This document
includes getting started, board design, system testing, and checklists to aid in initial designs and debug efforts.
Each section of this document includes pointers to valuable information including: technical documentation,
models, symbols, and reference designs for use in each phase of design. Particular attention is given to
peripheral interfacing and system-level design concerns.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio™ Integrated
Development Environment (IDE). For a complete listing of C6000™ DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
1.10.2.3 Device Silicon Revision
The device silicon revision can be determined by the “Die PG code” marked on the top of the package. For
more detailed information on the DM641/DM640 silicon revision, package markings, and the known
exceptions to the functional specifications as well as any usage notes, refer to the device-specific silicon
errata: TMS320DM641, TMS320DM640 Digital Signal Processors Silicon Errata (literature number
SPRZ201).
Device Configurations
67
June 2003 − Revised October 2010 SPRS222F
2 Device Configurations
On the DM641/DM640 device, bootmode and certain device configurations/peripheral selections are
determined at device reset, while other device configurations/peripheral selections are software-configurable
via the peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.
2.1 Configurations at Reset
For proper device operation; the following external pins must be configured correctly:
•For proper DM641 device operation, the HD5 [pin Y1] at device reset must be pulled down via a 10-kΩ
resistor.
•For proper DM641/DM640 device operation, the reserved (RSV) [E2] pin at device reset must be pulled
down via a 10-kΩ resistor.
•For proper DM641/DM640 device operation, the GP0[0] [pin M5] (IPD) must remain low at device reset.
2.1.1 Peripheral Selection at Device Reset
On the DM641/DM640 devices there are NO peripherals sharing the same pins (internally muxed, yet mutually
exclusive) that are controlled via external pins.
•EMAC and MDIO peripherals
The MAC_EN pin is latched at reset. This pin determines specific peripheral selection, summarized in
Table 2−1.
Table 2−1. MAC_EN Peripheral Selection (EMAC and MDIO)
PERIPHERAL SELECTION PERIPHERALS SELECTED
MAC_EN
Pin [C5] HPI Data
(16-Bit) [DM641 Only] EMAC and MDIO
0√Disabled
1√ √
Device Configurations
68 June 2003 − Revised October 2010SPRS222F
2.1.2 Device Configuration at Device Reset
Table 2−2 describes the DM641/DM640 device configuration pins, which are set up via external
pullup/pulldown resistors through the specified EMIFA address bus pins (AEA[22:19]) and the
TOUT1/LENDIAN pin (all of which are latched during device reset).
Table 2−2. DM641/DM640 Device Configuration Pins
(TOUT1/LENDIAN, AEA[22:19], and TOUT0/MAC_EN)
CONFIGURATION
PIN NO. FUNCTIONAL DESCRIPTION
TOUT1/LENDIAN B5 Device Endian mode (LEND)
0 – System operates in Big Endian mode
1 − System operates in Little Endian mode (default)
AEA[22:21] [U23,
V24]
Bootmode [1:0]
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
01 − HPI [DM641 only]; Reserved [For DM640 device]
10 − Reserved
11 − EMIFA 8−bit ROM boot
AEA[20:19] [V25,
V26]
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
TOUT0/MAC_EN C5
Peripheral Selection
1 − EMAC and MDIO enabled
0 − EMAC and MDIO disabled
2.2 Configurations After Reset
2.2.1 Peripheral Selection After Device Reset
Video Ports, McBSP1, McBSP0, McASP0, and I2C0
The DM641/DM640 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
Video Ports (VP0 and VP1 [DM641 only]) McBSP0, McBSP1, McASP0, and I2C0 peripherals. For more
detailed information on the PERCFG register control bits, see Figure 2−1 and Table 2−3.
Device Configurations
69
June 2003 − Revised October 2010 SPRS222F
31 24
Reserved
R-0
23 16
Reserved
R-0
15 8
Reserved
R-0
76543210
Reserved Reserved VP1EN†VP0EN I2C0EN MCBSP1EN MCBSP0EN MCASP0EN
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
†The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved.
Figure 2−1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003]
Table 2−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
BIT NAME DESCRIPTION
31:6 Reserved Reserved. Read-only, writes have no effect.
5 VP1EN
VP1 Enable bit [DM641 only].
Determines whether the VP1 peripheral is enabled or disabled.
0 = VP1 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
1 = VP1 is enabled.
The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved.
4 VP0EN
VP0 Enable bit.
Determines whether the VP0 peripheral is enabled or disabled.
0 = VP0 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
1 = VP0 is enabled.
3 I2C0EN
Inter-integrated circuit 0 (I2C0) enable bit.
Selects whether I2C0 peripheral is enabled or disabled (default).
0 = I2C0 is disabled, and the module is powered down (default).
1 = I2C0 is enabled.
2 MCBSP1EN
Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit.
Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0 = VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the
remaining VP1 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit
settings.
1 = McBSP1 is enabled, VP1 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 2−2.
Device Configurations
70 June 2003 − Revised October 2010SPRS222F
Table 2−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions (Continued)
DESCRIPTIONNAMEBIT
1 MCBSP0EN
Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit.
Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0 = VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the
remaining VP0 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit
settings.
1 = McBSP0 is enabled, VP0 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 2−2.
0 MCASP0EN
McASP0 select bit.
Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled.
0 = Reserved [default].
1 = McASP0 is enabled.
For proper DM641/DM640 device operation, the pin must be set to a “1”.
1
0
VP0 Data (8 pins)
VP0 (Channel A)
McBSP0
McBSP0EN [PERCFG.1]
1
0
VP1 Data (8 pins)
VP1 (Channel A) [DM641 Only]
McBSP1
McBSP1EN [PERCFG.2]
VP0D[6:0] Muxed†
VP0D[7] Standalone
VP1D[6:0] Muxed‡
VP1D[7] Standalone
†Consists of: VP0D[6]/CLKR0, VP0D[5]/FSR0, VP0D[4]/DR0, VP0D[3]/CLKS0, VP0D[2]/DX0, VP0D[1]/FSX0, VP0D[0]/CLKX0.
‡Consists of: VP1D[6]/CLKR1, VP1D[5]/FSR1, VP1D[4]/DR1, VP1D[3]/CLKS1, VP1D[2]/DX1, VP1D[1]/FSX1, VP1D[0]/CLKX1.
Figure 2−2. VP1, VP0, McBSP1, and McBSP0 Pin Muxing
Device Configurations
71
June 2003 − Revised October 2010 SPRS222F
2.3 Peripheral Configuration Lock
By default, the McASP0, VP0, VP1 [DM641 only], and I2C peripherals are disabled on power up. In order to
use these peripherals on the DM641/DM640 device, the peripheral must first be enabled in the Peripheral
Configuration register (PERCFG). Software muxed pins should not be programmed to switch
functionalities during run-time. Care should also be taken to ensure that no accesses are being
performed before disabling the peripherals. To help minimize power consumption in the DM641/DM640
device, unused peripherals may be disabled.
Figure 2−3 shows the flow needed to enable (or disable) a given peripheral on the DM641/DM640 devices.
Unlock the PERCFG Register
Using the PCFGLOCK Register
Write to
PERCFG Register
to Enable/Disable Peripherals
Read from
PERCFG Register
Wait 128 CPU Cycles Before
Accessing Enabled Peripherals
Figure 2−3. Peripheral Enable/Disable Flow Diagram
A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register
(PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register
determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked (LOCKSTAT
bit = 0), see Figure 2−4. A peripheral can only be enabled when the PERCFG register is “unlocked”
(LOCKSTAT bit = 0).
Device Configurations
72 June 2003 − Revised October 2010SPRS222F
Read Accesses
31 10
Reserved LOCKSTAT
R-0 R-1
Write Accesses
31 0
LOCK
W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2−4. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses
Table 2−4. PCFGLOCK Register Selection Bit Descriptions − Read Accesses
BIT NAME DESCRIPTION
31:1 Reserved Reserved. Read-only, writes have no effect.
0 LOCKSTAT
Lock status bit.
Determines whether the PERCFG register is locked or unlocked.
0 = Unlocked, read accesses to the PERCFG register allowed.
1 = Locked, write accesses to the PERCFG register do not modify the register state [default].
Reads are unaffected by Lock Status.
Table 2−5. PCFGLOCK Register Selection Bit Descriptions − Write Accesses
BIT NAME DESCRIPTION
31:0 LOCK Lock bits.
0x10C0010C = Unlocks PERCFG register accesses.
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary
overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the
PERCFG register with the necessary enable bits set.
Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between
the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG
register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur.
Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU
cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a
peripheral while it is disabled.
Device Configurations
73
June 2003 − Revised October 2010 SPRS222F
2.4 Device Status Register Description
The device status register depicts the status of the device peripheral selection. For the actual register bit
names and their associated bit field descriptions, see Figure 2−5 and Table 2−6.
31 24
Reserved
R-0
23 16
Reserved
R-0
15 14 13 12 11 10 9 8
Reserved MAC_EN Reserved Reserved Reserved
R-0 R-x R-0 R-x R-0
76543210
Reserved CLKMODE1 CLKMODE0 LENDIAN BOOTMODE1 BOOTMODE0 AECLKINSEL1 AECLKINSEL0
R-x R-x R-x R-x R-x R-x R-x R-x
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2−5. Device Status Register (DEVSTAT) Description − 0x01B3 F004
Table 2−6. Device Status (DEVSTAT) Register Selection Bit Descriptions
BIT NAME DESCRIPTION
31:12 Reserved Reserved. Read-only, writes have no effect.
11 MAC_EN
EMAC enable bit.
Shows the status of whether EMAC peripheral is enabled or disabled (default).
0 = EMAC is disabled, and the module is powered down (default).
1 = EMAC is enabled.
10:7 Reserved Reserved. Read-only, writes have no effect.
6 CLKMODE1
Clock mode select bits
Shows the status of whether the CPU clock frequency equals the input clock frequency X1 (Bypass), x6,
or x12.
Clock mode select for CPU clock frequency (CLKMODE[1:0])
00 – Bypass (x1) (default mode)
5 CLKMODE0
00 – Bypass (x1) (default mode)
01 − x6
10 − x12
11 − Reserved
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this
data sheet.
4 LENDIAN
Device Endian mode (LEND)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default).
0 – System is operating in Big Endian mode
1 − System is operating in Little Endian mode (default)
3 BOOTMODE1 Bootmode configuration bits
Shows the status of what device bootmode configuration is operational.
Bootmode [1:0]
00 – No boot (default mode)
2 BOOTMODE0
00 – No boot (default mode)
01 − HPI [DM641 only]; Reserved [For DM640 device]
10 − Reserved
11 − EMIFA 8−bit ROM boot
Device Configurations
74 June 2003 − Revised October 2010SPRS222F
Table 2−6. Device Status (DEVSTAT) Register Selection Bit Descriptions (Continued)
DESCRIPTIONNAMEBIT
1 AECLKINSEL1 EMIFA input clock select
Shows the status of what clock mode is enabled or disabled for the EMIF.
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
0 AECLKINSEL0
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
Device Configurations
75
June 2003 − Revised October 2010 SPRS222F
2.5 Multiplexed Pin Configurations
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some
of these pins are configured by software, and the others are configured by external pullup/pulldown resistors
only at reset. Those muxed pins that are configured by software should not be programmed to switch
functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors
are mutually exclusive; only one peripheral has primary control of the function of these pins after reset.
Table 2−7 identifies the multiplexed pins on the DM641/DM640 device; shows the default (primary) function
and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific
multiplexed functions.
Table 2−7. DM641/DM640 Device Multiplexed Pin Configurations
MULTIPLEXED PINS
DEFAULT
DEFAULT
DESCRIPTION
NAME NO.
DEFAULT
FUNCTION
DEFAULT
SETTING
DESCRIPTION
CLKOUT4/GP0[1] D6 CLKOUT4 GP1EN = 0 (disabled) These pins are software-configurable. To use these pins a
s
GPIO pins, the GPxEN bits in the GPIO Enable Register and
the GPxDIR bits in the GPIO Direction Register must be
properly configured.
CLKOUT6/GP0[2] C6 CLKOUT6 GP2EN = 0 (disabled)
properly configured.
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
VP1D[6]/CLKR1 AD8 Muxed on the DM641 device only
[The DM640 device does not support the VP1 peripheral;
VP1D[5]/FSR1 AC7
Muxed on the DM641 device only
[The DM640 device does not support the VP1 periphera
l;
therefore, the McBSP1 peripheral pins are standalone
VP1D[4]/DR1 AD7
McBSP1
VP1EN bit = 0
(disabled)
therefore, the McBSP1 peripheral pins are standalone
peripheral functions, not muxed.]
VP1D[3]/CLKS1 AE7 McBSP1
functions
VP1EN bit = 0
(disabled)
MCBSP1EN bit = 1
peripheral functions, not muxed.]
By default, the McBSP1 peripheral, function is enabled upon
VP1D[2]/DX1 AC6
functions
MCBSP1EN bit = 1
(enabled)
By default, the McBSP1 peripheral, function is enabled upon
reset (MCBSP1EN bit = 1).
VP1D[1]/FSX1 AD6
(enabled)
reset (MCBSP1EN bit = 1).
To enable the Video Port 1 data pins, the VP1EN bit in the
VP1D[0]/CLKX1 AE6
To enable the Video Port 1 data pins, the VP1EN bit in the
PERCFG register must be set to a 1.
VP0D[6]/CLKR0 AE15
VP0D[5]/FSR0 AB16
VP0D[4]/DR0 AC16
McBSP0
VP0EN bit = 0
(disabled)
By default, the McBSP0 peripheral function is enabled upon
reset (MCBSP0EN bit = 1).
VP0D[3]/CLKS0 AD16 McBSP0
functions
VP0EN bit = 0
(disabled)
MCBSP0EN bit = 1
By default, the McBSP0 peripheral function is enabled upon
reset (MCBSP0EN bit = 1).
To enable the Video Port 0 data pins, the VP0EN bit in the
VP0D[2]/DX0 AE16
functions
MCBSP0EN bit = 1
(enabled)
To enable the Video Port 0 data pins, the VP0EN bit in the
PERCFG register must be set to a 1.
VP0D[1]/FSX0 AF16
(enabled)
PERCFG register must be set to a 1.
VP0D[0]/CLKX0 AF17
Device Configurations
76 June 2003 − Revised October 2010SPRS222F
2.6 Debugging Considerations
It is recommended that external connections be provided to device configuration pins, including
TOUT1/LENDIAN, AEA[22:19] and TOUT0/MAC_EN. Although internal pullup/pulldown resistors exist on
these pins, providing external connectivity adds convenience to the user in debugging and flexibility in
switching operating modes.
Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:0]). Do not
oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown
resistors. If an external controller provides signals to these non-configuration pins, these signals must be
driven to the default state of the pins at reset, or not be driven at all.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
2.7 Configuration Examples
Figure 2−6 through Figure 2−9 illustrate examples of peripheral selections that are configurable on the DM641
and DM640 devices.
Device Configurations
77
June 2003 − Revised October 2010 SPRS222F
Shading denotes a peripheral module not available for this configuration.
HPI
(16-Bit)
EMAC
MDIO
VP0
(8-Bit)
McBSP0
McASP0 Data
McBSP1
EMIFA
Clock
and
System
GP0
and
EXT_INT
I2C0
TIMER0
TIMER1
TIMER2
McASP0 Control
16
HD[15:0]
MTXD[3:0], MTXEN
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
MDIO, MDCLK
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[7:0]
VP1
(8-Bit)
VP1CLK0
VP1CLK1,
VP1CTL[2:0],
VP1D[7:0]
AED[31:0]
32
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0]
,
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE
,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
CLKOUT4, CLKOUT6, PLL
V
SCL0
SDA0
TINP0
TOUT0/MAC_EN
TINP1
TOUT1/LENDIAN
HRDY, HINT
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
GP0[3:0]
GP0[7:4]
STCLK†
STCLK†
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0,
AHCLKR0, AFSR0,
ACLKR0
AXR0[3:0]
†STCLK supports both video ports (VP1 and VP0).
PERCFG Register Value: 0x0000 0039
Extenal Pins: TOUT0/MAC_EN = 1
VIC VDAC
Figure 2−6. Configuration Example A for DM641
(2 8-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF)
[TBD Application]
Device Configurations
78 June 2003 − Revised October 2010SPRS222F
Shading denotes a peripheral module not available for this configuration.
HPI
(16-Bit)
EMAC
MDIO
VP0
(8-Bit)
McBSP0
McASP0 Data
McBSP1
EMIFA
Clock
and
System
GP0
and
EXT_INT
I2C0
TIMER0
TIMER1
TIMER2
McASP0 Control
16
HD[15:0]
MTXD[3:0], MTXEN
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
MDIO, MDCLK
VP1
(8-Bit)
AED[31:0]
32
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0]
,
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE
,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
CLKOUT4, CLKOUT6, PLL
V
SCL0
SDA0
TINP0
TOUT0/MAC_EN
TINP1
TOUT1/LENDIAN
HRDY, HINT
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
GP0[3:0]
GP0[7:4]
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0, AHCLKR0,
AFSR0, ACLKR0
AXR0[3:0]
PERCFG Register Value: 0x0000 000F
Extenal Pins: TOUT0/MAC_EN = 1
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
CLKX1
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKX0
VIC VDAC
Figure 2−7. Configuration Example B for DM641
(1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF)
[TBD Application]
Device Configurations
79
June 2003 − Revised October 2010 SPRS222F
Shading denotes a peripheral module not available for this configuration.
EMAC
MDIO
VP0
(8-Bit)
McBSP0
McASP0 Data
McBSP1
EMIFA
Clock
and
System
GP0
and
EXT_INT
I2C0
TIMER0
TIMER1
TIMER2
McASP0 Control
MTXD[3:0], MTXEN
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
MDIO, MDCLK
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[7:0]
AED[31:0]
32
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0]
,
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE
,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
CLKOUT4, CLKOUT6, PLL
V
SCL0
SDA0
TINP0
TOUT0/MAC_EN
TINP1
TOUT1/LENDIAN
GP0[3:0]
GP0[7:4]
STCLK
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0,
AHCLKR0, AFSR0,
ACLKR0
AXR0[3:0]
PERCFG Register Value: 0x0000 0019
Extenal Pins: TOUT0/MAC_EN = 1
VIC VDAC
Figure 2−8. Configuration Example A for DM640
(1 8-Bit Video Port + 1 McASP0 + VIC + I2C0 + EMIF)
[TBD Application]
Device Configurations
80 June 2003 − Revised October 2010SPRS222F
Shading denotes a peripheral module not available for this configuration.
EMAC
MDIO
VP0
(8-Bit)
McBSP0
McASP0 Data
McBSP1
EMIFA
Clock
and
System
GP0
and
EXT_INT
I2C0
TIMER0
TIMER1
TIMER2
McASP0 Control
MTXD[3:0], MTXEN
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
MDIO, MDCLK
AED[31:0]
32
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0]
,
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE
,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
CLKOUT4, CLKOUT6, PLL
V
SCL0
SDA0
TINP0
TOUT0/MAC_EN
TINP1
TOUT1/LENDIAN
GP0[3:0]
GP0[7:4]
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0, AHCLKR0,
AFSR0, ACLKR0
AXR0[3:0]
PERCFG Register Value: 0x0000 000F
Extenal Pins: TOUT0/MAC_EN = 1
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
CLKX1
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKX0
VIC VDAC
Figure 2−9. Configuration Example B for DM640
(1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF)
[TBD Application]
Device Operating Conditions
81
June 2003 − Revised October 2010 SPRS222F
3 Device Operating Conditions
3.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)†
Supply voltage ranges: CVDD (see Note 1) − 0.3 V to 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVDD (see Note 1) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage ranges: VI−0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage ranges: VO−0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature ranges, TC: (default) 0_C to 90_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
3.2 Recommended Operating Conditions
MIN NOM MAX UNIT
CVDD
Supply voltage, Core (-400 and -500 devices)‡1.14 1.2 1.26 V
CV
DD Supply voltage, Core (-600 device)‡1.36 1.4 1.44 V
DVDD Supply voltage, I/O 3.14 3.3 3.46 V
VSS Supply ground 0 0 0 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VOS Maximum voltage during overshoot (see Figure 4−4) 4.3§V
VUS Maximum voltage during undershoot (see Figure 4−5) −1.0§V
TCOperating case temperature 0 90 _C
‡Future variants of the C64x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.
TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V
with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples
of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not
incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C64x devices.
§The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
Device Operating Conditions
82 June 2003 − Revised October 2010SPRS222F
3.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
VOH High-level output voltage DVDD = MIN, IOH = MAX¶2.4 V
VOL Low-level output voltage DVDD = MIN, IOL = MAX¶0.4 V
IIInput current VI = VSS to DVDD no opposing internal
resistor ±10 uA
II
Input current
VI = VSS to DVDD opposing internal
pullup resistor‡50 100 150 uA
I
I
Input current
VI = VSS to DVDD opposing internal
pulldown resistor‡−150 −100 −50 uA
EMIF, CLKOUT4, CLKOUT6, EMUx −16 mA
IOH High-level output current Video Ports, Timer, TDO, GPIO
(Excluding GP0[2,1]), McBSP −8 mA
HPI [DM641] −0.5 mA
EMIF, CLKOUT4, CLKOUT6, EMUx 16 mA
I
OL
Low-level output current Video Ports, Timer, TDO, GPIO
(Excluding GP0[2,1]), McBSP 8 mA
IOL
Low-level output current
SCL0 and SDA0 3 mA
HPI [DM641] 1.5 mA
IOZ Off-state output current VO = DVDD or 0 V ±10 uA
CVDD = 1.4 V, CPU clock = 600 MHz 890 mA
I
CDD
Core supply current§CVDD = 1.2 V, CPU clock = 500 MHz 620 mA
ICDD
Core supply current
CVDD = 1.2 V, CPU clock = 400 MHz 510 mA
DVDD = 3.3 V, CPU clock = 600 MHz 210 mA
I
DDD
I/O supply current§DVDD = 3.3 V, CPU clock = 500 MHz 165 mA
IDDD
I/O supply current
DVDD = 3.3 V, CPU clock = 400 MHz 160 mA
CiInput capacitance 10 pF
CoOutput capacitance 10 pF
†For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
§Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for -600 speed (100-MHz EMIF for
-500 and -400 speeds). This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing
low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power Consumption
Summary application report (literature number SPRA962).
¶Single pin driving IOH/IOL = MAX.
DM641/DM640 Peripheral Information and Electrical Specifications
83
June 2003 − Revised October 2010 SPRS222F
4 DM641/DM640 Peripheral Information and Electrical Specifications
4.1 Parameter Information
4.1.1 Parameter Information Device-Specific Information
Transmission Line
4.0 pF 1.85 pF
Z0 = 50 Ω
(see note)
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line ef fect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
42 Ω3.5 nH
Device Pin
(see note)
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 4−1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
4.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 4−2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX
and VOH MIN for output clocks.
Vref = VIL MAX (or VOL MAX)
Vref = VIH MIN (or VOH MIN)
Figure 4−3. Rise and Fall Transition Time Voltage Reference Levels
4.1.1.2 Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
Parameter Information
84 June 2003 − Revised October 2010SPRS222F
4.1.1.3 AC Transient Rise/Fall Time Specifications
Figure 4−4 and Figure 4−5 show the AC transient specifications for Rise and Fall Time. For device-specific
information on these values, refer to the Recommended Operating Conditions section of this Data Sheet.
VOS (max)
VIH (min)
Minimum
Risetime
Waveform
Valid Region
t = 0.3 tc (max)†
Ground
Figure 4−4. AC Transient Specification Rise Time
†tc = the peripheral cycle time in nanoseconds (ns).
t = 0.3 tc(max)†
VIL (max)
Ground
VUS (max)
Figure 4−5. AC Transient Specification Fall Time
†tc = the peripheral cycle time in nanoseconds (ns).
4.1.1.4 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device
and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time
margin, but also tends to improve the input hold time margins (see Table 4−1 and Figure 4−6).
Figure 4−6 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Power Supplies
85
June 2003 − Revised October 2010 SPRS222F
Table 4−1. Board-Level Timing Example (see Figure 4−6)
NO. DESCRIPTION
1Clock route delay
2Minimum DSP hold time
3Minimum DSP setup time
4External device hold time requirement
5External device setup time requirement
6Control signal route delay
7External device hold time
8External device access time
9DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
1
2
3
4
5
6
7
8
10
11
ECLKOUTx
(Output from DSP)
ECLKOUTx
(Input to External Device)
Control Signals†
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals‡
(Output from External Device)
Data Signals‡
(Input to DSP)
9
† Control signals include data for Writes.
‡Data
signals are generated during Reads from an external device.
Figure 4−6. Board-Level Input/Output Timings
4.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
4.3 Power Supplies
For more information regarding TI’s power management products and suggested devices to power TI DSPs,
visit www.ti.com/dsppower.
4.3.1 Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
Power Supplies
86 June 2003 − Revised October 2010SPRS222F
4.3.2 Power-Supply Design Considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 4−7).
DVDD
CVDD
VSS
C6000
DSP
Schottky
Diode
I/O Supply
Core Supply
GND
Figure 4−7. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
4.3.3 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the
core supply and 30 for the I/O supply. These caps need to be close to the DSP power pins, no more than
1.25 cm maximum distance to be ef fective. Physically smaller caps, such as 0402, are better because of their
lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF)
should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small
package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply (32 total)
be placed immediately next to the BGA vias, using the “interior” BGA space and at least the corners of the
“exterior”.
Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on the
order of 100 μF) should be furthest away (but still as close as possible). No less than 4 large caps per supply
(8 total) should be placed outside of the BGA.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any
component, verification of capacitor availability over the product’s production lifetime should be considered.
Power Supplies
87
June 2003 − Revised October 2010 SPRS222F
4.3.4 Peripheral Power-Down Operation
The DM641/DM640 device can be powered down in three ways:
•Power-down due to pin configuration
•Power-down due to software configuration − relates to the default state of the peripheral configuration bits
in the PERCFG register.
•Power-down during run-time via software configuration
On the DM641/DM640 device, the EMAC and MDIO peripherals are controlled (selected) at the pin level
during chip reset (e.g., using the MAC_EN pin).
The McASP0, McBSP0, McBSP1, VP0, VP1 [DM641 only], and I2C0 peripheral functions are selected via the
peripheral configuration (PERCFG) register bits.
For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the
Device Configurations section of this document.
4.3.5 Power-Down Modes Logic
Figure 4−8 shows the power-down mode logic on the DM641/DM640.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN RESET
CLKOUT6
PD3
Internal
Peripherals
CLKOUT4
Clock
and Dividers
Distribution
†External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
TMS320DM641/DM640
Figure 4−8. Power-Down Mode Logic†
Power Supplies
88 June 2003 − Revised October 2010SPRS222F
4.3.6 Triggering, Wake-up, and Effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 4−9 and described in
Table 4−2. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should
be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
31 16
15 14 13 12 11 10 9 8
Reserved Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake PD3 PD2 PD1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 4−9. PWRD Field of the CSR Register
A delay o f u p t o n ine c lock cycles may o ccur after the i nstruction that s ets the P WRD b its i n t he C SR b efore t he
PD mode takes effect. As best prac tice, NOPs should be padded after the PWRD bits are set in the CSR to
account for this delay.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where
PD1 t ook e ffect. I f P D1 m ode i s t erminated b y an e nabled i nterrupt, t he i nterrupt s ervice routine w ill b e e xecuted
first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled
interrupt, t he GIE b it in t he C SR and t he NMIE b it i n t he interrupt enable register (IER) m ust also b e s et in o rder
for the i nterrupt service routine t o e xecute; otherwise, e xecution returns t o t he i nstruction where P D1 t ook e f fect
upon PD1 mode termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 4−2 summarizes all the power-down modes.
Enhanced Direct Memory Access (EDMA) Controller
89
June 2003 − Revised October 2010 SPRS222F
Table 4−2. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10) POWER-DOWN
MODE WAKE-UP METHOD EFFECT ON CHIP’S OPERATION
000000 No power-down — —
001001 PD1 Wake by an enabled interrupt CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
010001 PD1 Wake by an enabled or
non-enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. Du r i ng P D 1 , EDMA transactions can proceed between
peripherals and internal memory.
011010 PD2†Wake by a device reset
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
011100 PD3†Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when t he P LL c lock is t urned o ff. F ollowing r eset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
All others Reserved — —
†When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
4.3.7 C64x Power-Down Mode with an Emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed
from the header . If power measurements are to be performed when in a power-down mode, the emulator cable
should be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail.
A DSP reset will be required to get the DSP out of PD2/PD3.
4.4 Enhanced Direct Memory Access (EDMA) Controller
The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and the
device peripherals on the DM641/DM640 DSP. These data transfers include cache servicing, non-cacheable
memory accesses, user-programmed data transfers, and host accesses.
4.4.1 EDMA Device-Specific Information
4.4.1.1 EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 4−3 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the DM641/DM640 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the EDMA
event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL,
EERH). The priority of each event can be specified independently in the transfer parameters stored in the
EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are
enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced
Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
Enhanced Direct Memory Access (EDMA) Controller
90 June 2003 − Revised October 2010SPRS222F
Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events†
EDMA
CHANNEL EVENT NAME EVENT DESCRIPTION
0 DSP_INT HPI-to-DSP interrupt [For DM641 Only; “None” for DM640]
1 TINT0 Timer 0 interrupt
2 TINT1 Timer 1 interrupt
3 SD_INTA EMIFA SDRAM timer interrupt
4 GPINT4/EXT_INT4 GP0 event 4/External interrupt pin 4
5 GPINT5/EXT_INT5 GP0 event 5/External interrupt pin 5
6 GPINT6/EXT_INT6 GP0 event 6/External interrupt pin 6
7 GPINT7/EXT_INT7 GP0 event 7/External interrupt pin 7
8 GPINT0 GP0 event 0
9 GPINT1 GP0 event 1
10 GPINT2 GP0 event 2
11 GPINT3 GP0 event 3
12 XEVT0 McBSP0 transmit event
13 REVT0 McBSP0 receive event
14 XEVT1 McBSP1 transmit event
15 REVT1 McBSP1 receive event
16 VP0EVTYA VP0 Channel A Y event DMA request
17 VP0EVTUA VP0 Channel A Cb event DMA request
18 VP0EVTVA VP0 Channel A Cr event DMA request
19 TINT2 Timer 2 interrupt
20−31 – None
32 AXEVTE0 McASP0 transmit even event
33 AXEVTO0 McASP0 transmit odd event
34 AXEVT0 McASP0 transmit event
35 AREVTE0 McASP0 receive even event
36 AREVTO0 McASP0 receive odd event
37 AREVT0 McASP0 receive event
38−43 – None
44 ICREVT0 I2C0 receive event
45 ICXEVT0 I2C0 transmit event
46−47 – None
48 GPINT8 GP0 event 8
49 GPINT9 GP0 event 9
50 GPINT10 GP0 event 10
51 GPINT11 GP0 event 11
52 GPINT12 GP0 event 12
53 GPINT13 GP0 event 13
54 GPINT14 GP0 event 14
55 GPINT15 GP0 event 15
56 VP1EVTYA VP1 Channel A Y event DMA request [For DM641 Only; “None” for DM640]
†In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
Enhanced Direct Memory Access (EDMA) Controller
91
June 2003 − Revised October 2010 SPRS222F
Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events† (Continued)
EDMA
CHANNEL EVENT DESCRIPTIONEVENT NAME
57 VP1EVTUA VP1 Channel A Cb event DMA request [For DM641 Only; “None” for DM640]
58 VP1EVTVA VP1 Channel A Cr event DMA request [For DM641 Only; “None” for DM640]
59−63 – None
†In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
4.4.2 EDMA Peripheral Register Description(s)
Table 4−4. EDMA Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0800 − 01A0 FF98 − Reserved
01A0 FF9C EPRH Event polarity high register
01A0 FFA4 CIPRH Channel interrupt pending high register
01A0 FFA8 CIERH Channel interrupt enable high register
01A0 FFAC CCERH Channel chain enable high register
01A0 FFB0 ERH Event high register
01A0 FFB4 EERH Event enable high register
01A0 FFB8 ECRH Event clear high register
01A0 FFBC ESRH Event set high register
01A0 FFC0 PQAR0 Priority queue allocation register 0
01A0 FFC4 PQAR1 Priority queue allocation register 1
01A0 FFC8 PQAR2 Priority queue allocation register 2
01A0 FFCC PQAR3 Priority queue allocation register 3
01A0 FFDC EPRL Event polarity low register
01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPRL Channel interrupt pending low register
01A0 FFE8 CIERL Channel interrupt enable low register
01A0 FFEC CCERL Channel chain enable low register
01A0 FFF0 ERL Event low register
01A0 FFF4 EERL Event enable low register
01A0 FFF8 ECRL Event clear low register
01A0 FFFC ESRL Event set low register
01A1 0000 − 01A3 FFFF – Reserved
Enhanced Direct Memory Access (EDMA) Controller
92 June 2003 − Revised October 2010SPRS222F
Table 4−5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0200 0000 QOPT QDMA options parameter register
0200 0004 QSRC QDMA source address register
0200 0008 QCNT QDMA frame count register
0200 000C QDST QDMA destination address register
0200 0010 QIDX QDMA index register
0200 0014 − 0200 001C Reserved
0200 0020 QSOPT QDMA pseudo options register
0200 0024 QSSRC QDMA psuedo source address register
0200 0028 QSCNT QDMA psuedo frame count register
0200 002C QSDST QDMA destination address register
0200 0030 QSIDX QDMA psuedo index register
Enhanced Direct Memory Access (EDMA) Controller
93
June 2003 − Revised October 2010 SPRS222F
Table 4−6. EDMA Parameter RAM (C64x)†
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
01A0 0000 − 01A0 0017 −Parameters for Event 0 (6 words) Parameters for Event 0
(6 words) or Reload/Link
Parameters for other Event
01A0 0018 − 01A0 002F −Parameters for Event 1 (6 words)
01A0 0030 − 01A0 0047 −Parameters for Event 2 (6 words)
01A0 0048 − 01A0 005F −Parameters for Event 3 (6 words)
01A0 0060 − 01A0 0077 −Parameters for Event 4 (6 words)
01A0 0078 − 01A0 008F −Parameters for Event 5 (6 words)
01A0 0090 − 01A0 00A7 −Parameters for Event 6 (6 words)
01A0 00A8 − 01A0 00BF −Parameters for Event 7 (6 words)
01A0 00C0 − 01A0 00D7 − Parameters for Event 8 (6 words)
01A0 00D8 − 01A0 00EF −Parameters for Event 9 (6 words)
01A0 00F0 − 01A0 00107 −Parameters for Event 10 (6 words)
01A0 0108 − 01A0 011F −Parameters for Event 11 (6 words)
01A0 0120 − 01A0 0137 −Parameters for Event 12 (6 words)
01A0 0138 − 01A0 014F −Parameters for Event 13 (6 words)
01A0 0150 − 01A0 0167 −Parameters for Event 14 (6 words)
01A0 0168 − 01A0 017F −Parameters for Event 15 (6 words)
01A0 0150 − 01A0 0167 −Parameters for Event 16 (6 words)
01A0 0168 − 01A0 017F −Parameters for Event 17 (6 words)
... ...
01A0 05D0 − 01A0 05E7 −Parameters for Event 62 (6 words)
01A0 05E8 − 01A0 05FF −Parameters for Event 63 (6 words)
01A0 0600 − 01A0 0617 −Reload/link parameters for Event 0 (6 words) Reload/Link Parameters for
other Event 0−15
01A0 0618 − 01A0 062F −Reload/link parameters for Event 1 (6 words)
... ...
01A0 07E0 − 01A0 07F7 −Reload/link parameters for Event 20 (6 words)
01A0 07F8 − 01A0 080F −Reload/link parameters for Event 21 (6 words)
01A0 0810 − 01A0 0827 −Reload/link parameters for Event 22 (6 words)
... ...
01A0 13C8 − 01A0 13DF −Reload/link parameters for Event 147 (6 words)
01A0 13E0 − 01A0 13F7 −Reload/link parameters for Event 148 (6 words)
01A0 13F8 − 01A0 13FF −Scratch pad area (2 words)
01A0 1400 − 01A3 FFFF − Reserved
†The DM641/DM640 device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each]
that can be used to reload/link EDMA transfers.
Interrupts
94 June 2003 − Revised October 2010SPRS222F
4.5 Interrupts
4.5.1 Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 4−7. The highest-priority
interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 4−7. The interrupt source for interrupts 4−15 can be
programmed b y modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector
Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 4−7. DM641/DM640 DSP Interrupts
CPU
INTERRUPT
NUMBER
INTERRUPT
SELECTOR
CONTROL
REGISTER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT INTERRUPT SOURCE
INT_00†− − RESET
INT_01†− − NMI
INT_02†− − Reserved Reserved. Do not use.
INT_03†− − Reserved Reserved. Do not use.
INT_04‡MUXL[4:0] 00100 GPINT4/EXT_INT4 GP0 interrupt 4/External interrupt pin 4
INT_05‡MUXL[9:5] 00101 GPINT5/EXT_INT5 GP0 interrupt 5/External interrupt pin 5
INT_06‡MUXL[14:10] 00110 GPINT6/EXT_INT6 GP0 interrupt 6/External interrupt pin 6
INT_07‡MUXL[20:16] 00111 GPINT7/EXT_INT7 GP0 interrupt 7/External interrupt pin 7
INT_08‡MUXL[25:21] 01000 EDMA_INT EDMA channel (0 through 63) interrupt
INT_09‡MUXL[30:26] 01001 EMU_DTDMA EMU DTDMA
INT_10‡MUXH[4:0] 00011 SD_INTA EMIFA SDRAM timer interrupt
INT_11‡MUXH[9:5] 01010 EMU_RTDXRX EMU real-time data exchange (RTDX) receive
INT_12‡MUXH[14:10] 01011 EMU_RTDXTX EMU RTDX transmit
INT_13‡MUXH[20:16] 00000 DSP_INT HPI-to-DSP interrupt [DM641 Only]
INT_14‡MUXH[25:21] 00001 TINT0 Timer 0 interrupt
INT_15‡MUXH[30:26] 00010 TINT1 Timer 1 interrupt
− − 01100 XINT0 McBSP0 transmit interrupt
− − 01101 RINT0 McBSP0 receive interrupt
− − 01110 XINT1 McBSP1 transmit interrupt
− − 01111 RINT1 McBSP1 receive interrupt
− − 10000 GPINT0 GP0 interrupt 0
− − 10001 Reserved Reserved. Do not use.
− − 10010 Reserved Reserved. Do not use.
− − 10011 TINT2 Timer 2 interrupt
− − 10100 Reserved Reserved. Do not use.
− − 10101 Reserved Reserved. Do not use.
− − 10110 ICINT0 I2C0 interrupt
− − 10111 Reserved Reserved. Do not use.
− − 11000 EMAC_MDIO_INT EMAC/MDIO interrupt
− − 11001 VPINT0 VP0 interrupt
†Interrupts INT_00 through INT_03 are non-maskable and fixed.
‡Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 4−7 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
Reset
95
June 2003 − Revised October 2010 SPRS222F
Table 4−7. DM641/DM640 DSP Interrupts (Continued)
CPU
INTERRUPT
NUMBER INTERRUPT SOURCE
INTERRUPT
EVENT
SELECTOR
VALUE
(BINARY)
INTERRUPT
SELECTOR
CONTROL
REGISTER
− − 11010 VPINT1 VP1 interrupt [DM641 Only]
− − 11011 Reserved Reserved. Do not use.
− − 11100 AXINT0 McASP0 transmit interrupt
− − 11101 ARINT0 McASP0 receive interrupt
− − 11110 − 11111 Reserved Reserved. Do not use.
†Interrupts INT_00 through INT_03 are non-maskable and fixed.
‡Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 4−7 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
4.5.2 Interrupts Peripheral Register Description(s)
Table 4−8. Interrupt Selector Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
019C 000C − 019F FFFF − Reserved
4.5.3 External Interrupts Electrical Data/Timing
Table 4−9. Timing Requirements for External Interrupts† (see Figure 4−10)
NO.
−400
−500
−600 UNIT
MIN MAX
1
tw(ILOW)
Width of the NMI interrupt pulse low 4P ns
1
t
w(ILOW) Width of the EXT_INT interrupt pulse low 8P ns
2
tw(IHIGH)
Width of the NMI interrupt pulse high 4P ns
2
t
w(IHIGH) Width of the EXT_INT interrupt pulse high 8P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
EXT_INTx, NMI
Figure 4−10. External/NMI Interrupt Timing
4.6 Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power-up.
Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
Reset
96 June 2003 − Revised October 2010SPRS222F
For information on peripheral selection at the rising edge of RESET, see the Device Configuration section of
this data manual.
4.6.1 Reset Electrical Data/Timing
Table 4−10. Timing Requirements for Reset (see Figure 4−11)
NO.
−400
−500
−600 UNIT
MIN MAX
1 tw(RST) Width of the RESET pulse 250 μs
16 tsu(boot) Setup time, boot configuration bits valid before RESET high†4E or 4C‡ns
17 th(boot) Hold time, boot configuration bits valid after RESET high†4P§ns
†AEA[22:19], LENDIAN, and HD5 are the boot configuration pins during device reset.
‡E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.
Select the MIN parameter value, whichever value is larger.
§P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Table 4−11. Switching Characteristics Over Recommended Operating Conditions During Reset§¶#
(see Figure 4−11)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
2 td(RSTL-ECKI) Delay time, RESET low to AECLKIN synchronized internally 2E 3P + 20E ns
3 td(RSTH-ECKI) Delay time, RESET high to AECLKIN synchronized internally 2E 8P + 20E ns
4 td(RSTL-ECKO1HZ) Delay time, RESET low to AECLKOUT1 high impedance 2E ns
5 td(RSTH-ECKO1V) Delay time, RESET high to AECLKOUT1 valid 8P + 20E ns
6 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z high impedance 2E 3P + 4E ns
7 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z valid 16E 8P + 20E ns
8 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid 2E ns
9 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid 8P + 20E ns
10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid 2E ns
11 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid 8P + 20E ns
12 td(RSTL-LOWIV) Delay time, RESET low to low group invalid 0 ns
13 td(RSTH-LOWV) Delay time, RESET high to low group valid 11P ns
14 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 0 ns
15 td(RSTH-ZV) Delay time, RESET high to Z group valid 2P 8P ns
§P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
¶E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
#EMIF Z group consists of: AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low)
Low group consists of:
Z group consists of: HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC,
GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and
VP0D[4,3].
VP1 signals apply to DM641 only:
VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3].
Reset
97
June 2003 − Revised October 2010 SPRS222F
AECLKOUT2
17
14
1
CLKOUT4
CLKOUT6
RESET
AECLKIN
Boot and Device
Configuration Inputs§
16
15
32
10
8
11
9
76
13
12
AECLKOUT1
54
Low Group†
Z Group†‡
EMIF Z Group†‡
EMIF High Group†
EMIF Low Group†
†EMIF Z group consists of: AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low)
Low group consists of:
Z group consists of: HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC,
GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and
VP0D[4,3].
VP1 signals apply to DM641 only:
VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3].
‡If AEA[22:19], LENDIAN, and HD5 pins are actively driven, care must be taken to ensure
no timing contention between parameters 6, 7, 14, 15, 16, and 17.
§Boot and Device Configurations Inputs (during reset) include: AEA[22:19], LENDIAN, and HD5.
Figure 4−11. Reset Timing†
Clock PLL
98 June 2003 − Revised October 2010SPRS222F
4.7 Clock PLL
The PLL controller features hardware-configurable PLL multiplier controller, dividers (/2, /4, /6, and /8), and
reset controller. The PLL controller accepts an input clock, as determined by the logic state on the
CLKMODE[1:0] pins, from the CLKIN pin. The resulting clock outputs are passed to the DSP core, peripherals,
and other modules inside the C6000™ DSP.
4.7.1 Clock PLL Device-Specific Information
Most o f the internal C64x™ DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed.
Figure 4−12 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x™ DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electricals
section).
Clock PLL
99
June 2003 − Revised October 2010 SPRS222F
PLLMULT
1
0
PLLCLK
CLKMODE0
CLKMODE1
CLKIN
C2C1
EMI
filter
3.3 V
/2
/8
/4
/6
00 01 10
CPU Clock
Peripheral Bus, EDMA
Clock
Timer Internal Clock
CLKOUT4, Peripheral Clock
(AUXCLK for McASP),
McBSP Internal Clock
CLKOUT6
/2
/4
EMIF 00 01 10 EK2RATE
(GBLCTL.[19,18])
ECLKOUT2ECLKOUT1
PLL
x6, x12
10 μF 0.1 μF
AEA[20:19]
(For the PLL Options, CLKMODE Pins Setup, and
PLL Clock Frequency Ranges, see Table 9.)
Internal to DM641/DM640
PLLV
ECLKIN
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000™ DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 4−12. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
Clock PLL
100 June 2003 − Revised October 2010SPRS222F
Table 4−12. TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time†‡
GDK and ZDK PACKAGES − 23 x 23 mm BGA,
GNZ and ZNZ PACKAGES − 27 x 27 mm BGA
CLKMODE1 CLKMODE0 CLKMODE
(PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT4
RANGE (MHz) CLKOUT6
RANGE (MHz)
TYPICAL
LOCK TIME
(μs)§
0 0 Bypass (x1) 30−75 30−75 7.5−18.8 5−12.5 N/A
0 1 x6 30−75 180−450 45−112.5 30−75
75
1 0 x12 30−50 360−600 90−150 60−100
75
1 1 Reserved − − − − −
†These clock frequency range values are applicable to a DM641−600 speed device. For −400, −500 device speed values, see the CLKIN timing
requirements table for the specific device speed.
‡Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM641/DM640 device to one of the valid PLL
multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode
is x1 (bypass).
§Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 μs, the maximum value may be as long as 250 μs.
4.7.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 4−13. Timing Requirements for CLKIN for −400 Devices†‡§ (see Figure 4−13)
−400
NO
.
PLL MODE x12 PLL MODE x6 x1 (BYPASS) UNIT
NO.
MIN MAX MIN MAX MIN MAX
UNIT
1 tc(CLKIN) Cycle time, CLKIN 30 33.3 13.3 33.3 13.3 33.3 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C 0.45C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 1 ns
5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
Table 4−14. Timing Requirements for CLKIN for −500 Devices†‡§ (see Figure 4−13)
−500
NO
.
PLL MODE x12 PLL MODE x6 x1 (BYPASS) UNIT
NO.
MIN MAX MIN MAX MIN MAX
UNIT
1 tc(CLKIN) Cycle time, CLKIN 24 33.3 13.3 33.3 13.3 33.3 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C 0.45C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 1 ns
5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
Clock PLL
101
June 2003 − Revised October 2010 SPRS222F
Table 4−15. Timing Requirements for CLKIN for −600 Devices†‡§ (see Figure 4−13)
−600
NO
.
PLL MODE x12 PLL MODE x6 x1 (BYPASS) UNIT
NO.
MIN MAX MIN MAX MIN MAX
UNIT
1 tc(CLKIN) Cycle time, CLKIN 20 33.3 13.3 33.3 13.3 33.3 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C 0.45C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 1 ns
5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
2
3
4
4
51
Figure 4−13. CLKIN Timing
Table 4−16. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4†‡§
(see Figure 4−14)
NO.
PARAMETER
−400
−500
−600
UNIT
NO.
PARAMETER
CLKMODE = x1, x6, x12
UNIT
MIN MAX
1 tw(CKO4H) Pulse duration, CLKOUT4 high 2P − 0.7 2P + 0.7 ns
2 tw(CKO4L) Pulse duration, CLKOUT4 low 2P − 0.7 2P + 0.7 ns
3 tt(CKO4) Transition time, CLKOUT4 1 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
§P = 1/CPU clock frequency in nanoseconds (ns)
CLKOUT4
1
2
3
3
Figure 4−14. CLKOUT4 Timing
Clock PLL
102 June 2003 − Revised October 2010SPRS222F
Table 4−17. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6†‡§
(see Figure 4−15)
NO.
PARAMETER
−400
−500
−600
UNIT
NO.
PARAMETER
CLKMODE = x1, x6, x12
UNIT
MIN MAX
1 tw(CKO6H) Pulse duration, CLKOUT6 high 3P − 0.7 3P + 0.7 ns
2 tw(CKO6L) Pulse duration, CLKOUT6 low 3P − 0.7 3P + 0.7 ns
3 tt(CKO6) Transition time, CLKOUT6 1 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
§P = 1/CPU clock frequency in nanoseconds (ns)
CLKOUT6
1
2
3
3
Figure 4−15. CLKOUT6 Timing
Table 4−18. Timing Requirements for AECLKIN for EMIFA†‡§ (see Figure 4−16)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tc(EKI) Cycle time, AECLKIN 6¶16P ns
2 tw(EKIH) Pulse duration, AECLKIN high 2.7 ns
3 tw(EKIL) Pulse duration, AECLKIN low 2.7 ns
4 tt(EKI) Transition time, AECLKIN 3 ns
5 tJ(EKI) Period jitter, AECLKIN 0.02E ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
§E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
¶Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600 device, 133-MHz
operation is achievable if the requirements of the EMIF Device Speed section are met. On the 400 and 500 devices, 100-MHz operation is
achievable if the requirements of the EMIF Device Speed section are met.
AECLKIN
2
3
4
4
51
Figure 4−16. AECLKIN Timing for EMIFA
Clock PLL
103
June 2003 − Revised October 2010 SPRS222F
Table 4−19. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module§#|| (see Figure 4−17)
NO
.
PARAMETER
−400
−500
−600 UNIT
MIN MAX
1 tw(EKO1H) Pulse duration, AECLKOUT1 high EH − 0.7 EH + 0.7 ns
2 tw(EKO1L) Pulse duration, AECLKOUT1 low EL − 0.7 EL + 0.7 ns
3 tt(EKO1) Transition time, AECLKOUT1 1 ns
4 td(EKIH-EKO1H) Delay time, AECLKIN high to AECLKOUT1 high 1 8 ns
5 td(EKIL-EKO1L) Delay time, AECLKIN low to AECLKOUT1 low 1 8 ns
§E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
#The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
|| EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
kThis cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
4512
AECLKIN
AECLKOUT1
33
Figure 4−17. AECLKOUT1 Timing for the EMIFA Module
Table 4−20. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module†‡ (see Figure 4−18)
NO
.
PARAMETER
−400
−500
−600 UNIT
MIN MAX
1 tw(EKO2H) Pulse duration, AECLKOUT2 high 0.5NE − 0.7 0.5NE + 0.7 ns
2 tw(EKO2L) Pulse duration, AECLKOUT2 low 0.5NE − 0.7 0.5NE + 0.7 ns
3 tt(EKO2) Transition time, AECLKOUT2 1 ns
4 td(EKIH-EKO2H) Delay time, AECLKIN high to AECLKOUT2 high 1 8 ns
5 td(EKIL-EKO2L) Delay time, AECLKIN low to AECLKOUT2 low 1 8 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
§This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
4512
AECLKIN
AECLKOUT2
33
Figure 4−18. AECLKOUT2 Timing for the EMIFA Module
External Memory Interface (EMIIF)
104 June 2003 − Revised October 2010SPRS222F
4.8 External Memory Interface (EMIIF)
EMIF supports a glueless interface to a variety of external devices, including:
•Pipelined synchronous-burst SRAM (SBSRAM)
•Synchronous DRAM (SDRAM)
•Asynchronous devices, including SRAM, ROM, and FIFOs
•An external shared-memory device
4.8.1 EMIF Device-Specific Information
EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets th e
following requirements:
•1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
•up to 1 CE space of buffers connected to EMIF
•EMIF trace lengths between 1 and 3 inches
•166-MHz SDRAM for 133-MHz operation
•143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buf fer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
For more detailed information on the DM641/DM640 EMIF peripheral, see the TMS320C6000 DSP External
Memory Interface (EMIF) Reference Guide (literature number SPRU266).
4.8.2 EMIF Peripheral Register Description(s)
Table 4−21. EMIFA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0180 0000 GBLCTL EMIFA global control
0180 0004 CECTL1 EMIFA CE1 space control
0180 0008 CECTL0 EMIFA CE0 space control
0180 000C − Reserved
0180 0010 CECTL2 EMIFA CE2 space control
0180 0014 CECTL3 EMIFA CE3 space control
0180 0018 SDCTL EMIFA SDRAM control
0180 001C SDTIM EMIFA SDRAM refresh control
0180 0020 SDEXT EMIFA SDRAM extension
0180 0024 − 0180 003C − Reserved
0180 0040 PDTCTL Peripheral device transfer (PDT) control
0180 0044 CESEC1 EMIFA CE1 space secondary control
0180 0048 CESEC0 EMIFA CE0 space secondary control
0180 004C − Reserved
0180 0050 CESEC2 EMIFA CE2 space secondary control
0180 0054 CESEC3 EMIFA CE3 space secondary control
0180 0058 − 0183 FFFF – Reserved
External Memory Interface (EMIIF)
105
June 2003 − Revised October 2010 SPRS222F
4.8.3 EMIF Electrical Data/Timing
4.8.3.1 Asynchronous Memory Timing
Table 4−22. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module†‡
(see Figure 4−19 and Figure 4−20)
NO.
−400
−500
−600 UNIT
MIN MAX
3 tsu(EDV-AREH) Setup time, AEDx valid before AARE high 6.5 ns
4 th(AREH-EDV) Hold time, AEDx valid after AARE high 1 ns
6 tsu(ARDY-EKO1H) Setup time, AARDY valid before AECLKOUTx high 3 ns
7 th(EKO1H-ARDY) Hold time, AARDY valid after AECLKOUTx high 2.5 ns
†To ensure data setup time, simply program the strobe width wide enough. AARDY is internally synchronized. The AARDY signal is only
recognized two cycles before the end of the programmed strobe time and while AARDY is low, the strobe time is extended cycle-by-cycle. When
AARDY is recognized low, the end of the strobe time is two cycles after AARDY is recognized high. To use AARDY as an asynchronous input,
the pulse width of the AARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
Table 4−23. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module‡§¶ (see Figure 4−19 and Figure 4−20)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
1 tosu(SELV-AREL) Output setup time, select signals valid to AARE low RS * E − 1.8 ns
2 toh(AREH-SELIV) Output hold time, AARE high to select signals invalid RH * E − 1.9 ns
5 td(EKO1H-AREV) Delay time, AECLKOUTx high to AARE valid 1 7 ns
8 tosu(SELV-AWEL) Output setup time, select signals valid to AAWE low WS * E − 2.0 ns
9 toh(AWEH-SELIV) Output hold time, AAWE high to select signals invalid WH * E − 2.5 ns
10 td(EKO1H-AWEV) Delay time, AECLKOUTx high to AAWE valid 1.3 7.1 ns
‡RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§E = AECLKOUT1 period in ns for EMIFA
¶Select signals for EMIFA include: ACEx, ABE[3:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0].
External Memory Interface (EMIIF)
106 June 2003 − Revised October 2010SPRS222F
77
66
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
1
1
1
1
5
4
AARDY
5
AECLKOUTx
ACEx
AEA[22:3]
AED[31:0]
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/ASRE†
ABE[3:0]
AAWE/ASDWE/ASWE†
2
2
2
2
3
Read Data
†AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AA WE/ASDWE/ASWE operate as AAOE (identified under select signals), AARE,
and AAWE, respectively, during asynchronous memory accesses.
Figure 4−19. Asynchronous Memory Read Timing for EMIFA
External Memory Interface (EMIIF)
107
June 2003 − Revised October 2010 SPRS222F
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Write Data
10
10
8
8
8
8
77 6
6
AECLKOUTx
ACEx
AEA[22:3]
AED[31:0]
ABE[3:0]
AARDY
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/ASRE†
AAWE/ASDWE/ASWE†
9
9
9
9
†AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AA WE/ASDWE/ASWE operate as AAOE (identified under select signals), AARE,
and AAWE, respectively, during asynchronous memory accesses.
Figure 4−20. Asynchronous Memory Write T iming for EMIFA
External Memory Interface (EMIIF)
108 June 2003 − Revised October 2010SPRS222F
4.8.3.2 Programmable Synchronous Interface Timing
Table 4−24. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 4−21)
NO.
−400
−500 −600
UNIT
NO.
MIN MAX MIN MAX
UNIT
6 tsu(EDV-EKOxH) Setup time, read AEDx valid before AECLKOUTx high 3.1 2 ns
7 th(EKOxH-EDV) Hold time, read AEDx valid after AECLKOUTx high 1.8 1.5 ns
Table 4−25. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module† (see Figure 4−21−Figure 4−23)
NO.
PARAMETER
−400
−500 −600
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(EKOxH-CEV) Delay time, AECLKOUTx high to ACEx valid 1.1 6.4 1.1 4.9 ns
2 td(EKOxH-BEV) Delay time, AECLKOUTx high to ABEx valid 6.4 4.9 ns
3 td(EKOxH-BEIV) Delay time, AECLKOUTx high to ABEx invalid 1.1 1.1 ns
4 td(EKOxH-EAV) Delay time, AECLKOUTx high to AEAx valid 6.4 4.9 ns
5 td(EKOxH-EAIV) Delay time, AECLKOUTx high to AEAx invalid 1.1 1.1 ns
8 td(EKOxH-ADSV) Delay time, AECLKOUTx high to ASADS/ASRE valid 1.1 6.4 1.1 4.9 ns
9 td(EKOxH-OEV) Delay time, AECLKOUTx high to ASOE valid 1.1 6.4 1.1 4.9 ns
10 td(EKOxH-EDV) Delay time, AECLKOUTx high to AEDx valid 6.4 4.9 ns
11 td(EKOxH-EDIV) Delay time, AECLKOUTx high to AEDx invalid 1.1 1.1 ns
12 td(EKOxH-WEV) Delay time, AECLKOUTx high to ASWE valid 1.1 6.4 1.1 4.9 ns
†The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
External Memory Interface (EMIIF)
109
June 2003 − Revised October 2010 SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
AARE/ASDCAS/ASADS/
ASRE§
AAOE/ASDRAS/ASOE§
AAWE/ASDWE/ASWE§
BE1 BE2 BE3 BE4
Q1 Q2 Q3 Q4
9
1
45
8
9
67
3
1
2BE1 BE2 BE3 BE4
EA1 EA2 EA4
8
READ latency = 2
EA3
†The read latency and the length of ACEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
‡The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
§AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 4−21. Programmable Synchronous Interface Read Timing for EMIFA
(With Read Latency = 2)†‡
External Memory Interface (EMIIF)
110 June 2003 − Revised October 2010SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
AARE/ASDCAS/ASADS/ASRE§
AAOE/ASDRAS/ASOE§
AAWE/ASDWE/ASWE§
BE1 BE2 BE3 BE4
Q1 Q2 Q3 Q4
12
11
3
1
12
10
4
2
1
8
5
8
EA1 EA2 EA3 EA4
10
†The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF A CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.
‡The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
§AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 4−22. Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 0)†‡§
External Memory Interface (EMIIF)
111
June 2003 − Revised October 2010 SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
AARE/ASDCAS/ASADS/
ASRE§
AAOE/ASDRAS/ASOE§
AAWE/ASDWE/ASWE§
BE1 BE2 BE3 BE4
Q1 Q2 Q3 11
3
12
10
4
2
1
8
5
8
EA1 EA2 EA3 EA4
10
Write
Latency =
1‡
1
Q4
12
†The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF A CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
‡The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
− Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
§AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 4−23. Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 1)†‡
External Memory Interface (EMIIF)
112 June 2003 − Revised October 2010SPRS222F
4.8.3.3 Synchronous DRAM Timing
Table 4−26. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 4−24)
NO.
−400
−500 −600
UNIT
NO.
MIN MAX MIN MAX
UNIT
6 tsu(EDV-EKO1H) Setup time, read AEDx valid before AECLKOUTx high 2.1 0.6 ns
7 th(EKO1H-EDV) Hold time, read AEDx valid after AECLKOUTx high 2.8 2.1 ns
Table 4−27. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module (see Figure 4−24−Figure 4−31)
NO.
PARAMETER
−400
−500 −600
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(EKO1H-CEV) Delay time, AECLKOUTx high to ACEx valid 1.3 6.4 1.3 4.9 ns
2 td(EKO1H-BEV) Delay time, AECLKOUTx high to ABEx valid 6.4 4.9 ns
3 td(EKO1H-BEIV) Delay time, AECLKOUTx high to ABEx invalid 1.3 1.3 ns
4 td(EKO1H-EAV) Delay time, AECLKOUTx high to AEAx valid 6.4 4.9 ns
5 td(EKO1H-EAIV) Delay time, AECLKOUTx high to AEAx invalid 1.3 1.3 ns
8 td(EKO1H-CASV) Delay time, AECLKOUTx high to ASDCAS valid 1.3 6.4 1.3 4.9 ns
9 td(EKO1H-EDV) Delay time, AECLKOUTx high to AEDx valid 6.4 4.9 ns
10 td(EKO1H-EDIV) Delay time, AECLKOUTx high to AEDx invalid 1.3 1.3 ns
11 td(EKO1H-WEV) Delay time, AECLKOUTx high to ASDWE valid 1.3 6.4 1.3 4.9 ns
12 td(EKO1H-RAS) Delay time, AECLKOUTx high to ASDRAS valid 1.3 6.4 1.3 4.9 ns
13 td(EKO1H-ACKEV) Delay time, AECLKOUTx high to ASDCKE valid 1.3 6.4 1.3 4.9 ns
14 td(EKO1H-PDTV) Delay time, AECLKOUTx high to APDT valid 1.3 6.4 1.3 4.9 ns
External Memory Interface (EMIIF)
113
June 2003 − Revised October 2010 SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[12:3]
AED[31:0]
AEA13
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
AEA[22:14]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
8
7
6
5
5
5
1
3
2
8
4
4
4
1
READ
APDT‡1414
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
‡APDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For APDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to the
data phase of a read transaction. The latency of the APDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10,
or 11, respectively. PDTRL equals 00 (zero latency) in Figure 4−24.
Figure 4−24. SDRAM Read Command (CAS Latency 3) for EMIFA
External Memory Interface (EMIIF)
114 June 2003 − Revised October 2010SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[12:3]
AED[31:0]
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
AEA13
AEA[22:14]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
APDT‡1414
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
‡APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For APDT write,
data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to
the data phase of a write transaction. The latency of the APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL
to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 4−25.
Figure 4−25. SDRAM Write Command for EMIFA
External Memory Interface (EMIIF)
115
June 2003 − Revised October 2010 SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14]
AED[31:0]
AEA13
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
Bank Activate
Row Address
Row Address
12
5
5
5
1
AEA[12:3]
ACTV
12
4
4
4
1
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−26. SDRAM ACTV Command for EMIFA
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14, 12:3]
AED[31:0]
AEA13
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
11
12
5
1
DCAB
11
12
4
1
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−27. SDRAM DCAB Command for EMIFA
External Memory Interface (EMIIF)
116 June 2003 − Revised October 2010SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14]
AED[31:0]
AEA13
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
AEA[12:3]
Bank
11
12
5
5
1
DEAC
11
12
4
4
1
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−28. SDRAM DEAC Command for EMIFA
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14, 12:3]
AED[31:0]
AEA13
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
8
12
1
REFR
8
12
1
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−29. SDRAM REFR Command for EMIFA
External Memory Interface (EMIIF)
117
June 2003 − Revised October 2010 SPRS222F
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
AAOE/ASDRAS/
ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
MRS value
11
8
12
5
1
MRS
11
8
12
4
1
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−30. SDRAM MRS Command for EMIFA
End Self-Refresh
Self Refresh
13
13
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14, 12:3]
AEA13
AED[31:0]
AAOE/ASDRAS/ASOE†
AAWE/ASDWE/ASWE†
ASDCKE
≥ TRAS cycles
AARE/ASDCAS/ASADS/
ASRE†
†AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−31. SDRAM Self-Refresh Timing for EMIFA
External Memory Interface (EMIIF)
118 June 2003 − Revised October 2010SPRS222F
4.8.3.4 HOLD/HOLDA Timing
Table 4−28. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module† (see Figure 4−32)
NO.
−400
−500
−600 UNIT
MIN MAX
3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E ns
†E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Table 4−29. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module†‡§ (see Figure 4−32)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIFA Bus high impedance 2E ¶ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2E ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 2E 7E ns
5 td(EMLZ-HOLDAH) Delay time, EMIFA Bus low impedance to HOLDA high 0 2E ns
6 td(HOLDL-EKOHZ) Delay time, HOLD low to AECLKOUTx high impedance 2E ¶ns
7 td(HOLDH-EKOLZ) Delay time, HOLD high to AECLKOUTx low impedance 2E 7E ns
†E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
‡EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
§The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−32.
¶All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus†
DSP Owns Bus External Requestor
Owns Bus DSP Owns Bus
DM641/DM640 DM641/DM640
1
3
25
4
AECLKOUTx‡
(EKxHZ = 0)
AECLKOUTx‡
(EKxHZ = 1)
67
†EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
‡The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−32.
Figure 4−32. HOLD/HOLDA Timing for EMIFA
External Memory Interface (EMIIF)
119
June 2003 − Revised October 2010 SPRS222F
4.8.3.5 BUSREQ Timing
Table 4−30. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 4−33)
NO.
PARAMETER
−400
−500 −600
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 td(AEKO1H-ABUSRV) Delay time, AECLKOUTx high to ABUSREQ valid 0.6 7.1 1 5.5 ns
AECLKOUTx
1
ABUSREQ
1
Figure 4−33. BUSREQ Timing for EMIFA
Multichannel Audio Serial Port (McASP0) Peripheral
120 June 2003 − Revised October 2010SPRS222F
4.9 Multichannel Audio Serial Port (McASP0) Peripheral
The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio
applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S)
protocols, and intercomponent digital audio interface transmission (DIT).
4.9.1 McASP0 Device-Specific Information
The TMS320DM641/DM640 device includes one multichannel audio serial port (McASP) interface peripheral
(McASP0). The McASP is a serial port optimized for the needs of multichannel audio applications.
The McASP consists of a transmit and receive section. These sections can operate completely independently
with dif ferent data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit
and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that
may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous
serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,
IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial
format.
The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format
at a time. All transmit shift registers use the same format and all receive shift registers use the same format.
However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio
data (for example, passing control information between two DSPs).
The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as
well as error management.
For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP
Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041).
4.9.1.1 McASP Block Diagram
Figure 4−34 illustrates the major blocks along with external signals of the TMS320DM641/DM640 McASP0
peripheral; and shows the 8 serial data [AXR] pins. The McASP also includes full general-purpose I/O (GPIO)
control, so any pins not needed for serial transfers can be used for general-purpose I/O.
Multichannel Audio Serial Port (McASP0) Peripheral
121
June 2003 − Revised October 2010 SPRS222F
Receive
Clock
Generator
AHCLKR0
ACLKR0
Clock Check
Transmit
Generator
Clock
Transmit
ACLKX0
AHCLKX0
DIT
RAM
Transmit
Generator
Frame Sync AFSX0
Detect
Error
Receive
Frame Sync
GeneratorFormatter
Transmit
Data
AMUTE0
AMUTEIN0
AFSR0
Serializer 0
Serializer 1
Serializer 3
Serializer 2
Serializer 6
Serializer 7
Serializer 5
Serializer 4
(High-
Frequency)
Receive
Clock Check
(High-
Frequency)
Receive
Formatter
Data
McASP0
DMA Transmit
DMA Receive
INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO
Control
GPIO
AXR0[0]
AXR0[1]
AXR0[3]
AXR0[2]
Figure 4−34. McASP0 Configuration
Multichannel Audio Serial Port (McASP0) Peripheral
122 June 2003 − Revised October 2010SPRS222F
4.9.2 McASP0 Peripheral Register Description(s)
Table 4−31. McASP0 Control Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B4 C000 PID Peripheral Identification register [Register value: 0x0010 0101]
01B4 C004 PWRDEMU Power down and emulation management register
01B4 C008 − Reserved
01B4 C00C − Reserved
01B4 C010 PFUNC Pin function register
01B4 C014 PDIR Pin direction register
01B4 C018 PDOUT Pin data out register
01B4 C01C PDIN/PDSET Pin data in / data set register
Read returns: PDIN
Writes affect: PDSET
01B4 C020 PDCLR Pin data clear register
01B4 C024 − 01B4 C040 − Reserved
01B4 C044 GBLCTL Global control register
01B4 C048 AMUTE Mute control register
01B4 C04C DLBCTL Digital Loop-back control register
01B4 C050 DITCTL DIT mode control register
01B4 C054 − 01B4 C05C − Reserved
01B4 C060 RGBLCTL Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset
independently from receive.
01B4 C064 RMASK Receiver format unit bit mask register
01B4 C068 RFMT Receive bit stream format register
01B4 C06C AFSRCTL Receive frame sync control register
01B4 C070 ACLKRCTL Receive clock control register
01B4 C074 AHCLKRCTL High-frequency receive clock control register
01B4 C078 RTDM Receive TDM slot 0−31 register
01B4 C07C RINTCTL Receiver interrupt control register
01B4 C080 RSTAT Status register − Receiver
01B4 C084 RSLOT Current receive TDM slot register
01B4 C088 RCLKCHK Receiver clock check control register
01B4 C08C − 01B4 C09C − Reserved
01B4 C0A0 XGBLCTL Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset
independently from receive.
01B4 C0A4 XMASK Transmit format unit bit mask register
01B4 C0A8 XFMT Transmit bit stream format register
01B4 C0AC AFSXCTL Transmit frame sync control register
01B4 C0B0 ACLKXCTL Transmit clock control register
01B4 C0B4 AHCLKXCTL High-frequency Transmit clock control register
01B4 C0B8 XTDM Transmit TDM slot 0−31 register
01B4 C0BC XINTCTL Transmit interrupt control register
01B4 C0C0 XSTAT Status register − Transmitter
01B4 C0C4 XSLOT Current transmit TDM slot
01B4 C0C8 XCLKCHK Transmit clock check control register
Multichannel Audio Serial Port (McASP0) Peripheral
123
June 2003 − Revised October 2010 SPRS222F
Table 4−31. McASP0 Control Registers (Continued)
HEX ADDRESS RANGE REGISTER NAMEACRONYM
01B4 C0CC XEVTCTL Transmitter DMA control register
01B4 C0D0 − 01B4 C0FC − Reserved
01B4 C100 DITCSRA0 Left (even TDM slot) channel status register file
01B4 C104 DITCSRA1 Left (even TDM slot) channel status register file
01B4 C108 DITCSRA2 Left (even TDM slot) channel status register file
01B4 C10C DITCSRA3 Left (even TDM slot) channel status register file
01B4 C110 DITCSRA4 Left (even TDM slot) channel status register file
01B4 C114 DITCSRA5 Left (even TDM slot) channel status register file
01B4 C118 DITCSRB0 Right (odd TDM slot) channel status register file
01B4 C11C DITCSRB1 Right (odd TDM slot) channel status register file
01B4 C120 DITCSRB2 Right (odd TDM slot) channel status register file
01B4 C124 DITCSRB3 Right (odd TDM slot) channel status register file
01B4 C128 DITCSRB4 Right (odd TDM slot) channel status register file
01B4 C12C DITCSRB5 Right (odd TDM slot) channel status register file
01B4 C130 DITUDRA0 Left (even TDM slot) user data register file
01B4 C134 DITUDRA1 Left (even TDM slot) user data register file
01B4 C138 DITUDRA2 Left (even TDM slot) user data register file
01B4 C13C DITUDRA3 Left (even TDM slot) user data register file
01B4 C140 DITUDRA4 Left (even TDM slot) user data register file
01B4 C144 DITUDRA5 Left (even TDM slot) user data register file
01B4 C148 DITUDRB0 Right (odd TDM slot) user data register file
01B4 C14C DITUDRB1 Right (odd TDM slot) user data register file
01B4 C150 DITUDRB2 Right (odd TDM slot) user data register file
01B4 C154 DITUDRB3 Right (odd TDM slot) user data register file
01B4 C158 DITUDRB4 Right (odd TDM slot) user data register file
01B4 C15C DITUDRB5 Right (odd TDM slot) user data register file
01B4 C160 − 01B4 C17C − Reserved
01B4 C180 SRCTL0 Serializer 0 control register
01B4 C184 SRCTL1 Serializer 1 control register
01B4 C188 SRCTL2 Serializer 2 control register
01B4 C18C SRCTL3 Serializer 3 control register
01B4 C190 − 01B4 C1FC − Reserved
01B4 C200 XBUF0 Transmit Buffer for Serializer 0
01B4 C204 XBUF1 Transmit Buffer for Serializer 1
01B4 C208 XBUF2 Transmit Buffer for Serializer 2
01B4 C20C XBUF3 Transmit Buffer for Serializer 3
01B4 C210 − 01B4 C27C − Reserved
01B4 C280 RBUF0 Receive Buffer for Serializer 0
01B4 C284 RBUF1 Receive Buffer for Serializer 1
01B4 C288 RBUF2 Receive Buffer for Serializer 2
01B4 C28C RBUF3 Receive Buffer for Serializer 3
01B4 C290 − 01B4 FFFF − Reserved
Multichannel Audio Serial Port (McASP0) Peripheral
124 June 2003 − Revised October 2010SPRS222F
Table 4−32. McASP0 Data Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
3C00 0000 − 3C0F FFFF RBUF/XBUFx McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT
registers, respectively].)
4.9.3 McASP0 Electrical Data/Timing
4.9.3.1 Multichannel Audio Serial Port (McASP) Timing
Table 4−33. Timing Requirements for McASP (see Figure 4−35 and Figure 4−36)
NO.
−400
−500
−600 UNIT
MIN MAX
1 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns
2 tw(AHCKRX) Pulse duration, AHCLKR/X high or low 10 ns
3 tc(CKRX) Cycle time, ACLKR/X ACLKR/X ext 33 ns
4 tw(CKRX) Pulse duration, ACLKR/X high or low ACLKR/X ext 16.5 ns
5
tsu(FRXC-KRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
ACLKR/X int 5 ns
5
t
su(FRXC-KRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
ACLKR/X ext 5 ns
6
th(CKRX-FRX)
Hold time, AFSR/X input valid after ACLKR/X latches data
ACLKR/X int 5 ns
6
t
h(CKRX-FRX)
Hold time, AFSR/X input valid after ACLKR/X latches data
ACLKR/X ext 5 ns
7
tsu(AXR-CKRX)
Setup time, AXR input valid before ACLKR/X latches data
ACLKR/X int 5 ns
7
t
su(AXR-CKRX)
Setup time, AXR input valid before ACLKR/X latches data
ACLKR/X ext 5 ns
8
th(CKRX-AXR)
Hold time, AXR input valid after ACLKR/X latches data
ACLKR/X int 5 ns
8
t
h(CKRX-AXR)
Hold time, AXR input valid after ACLKR/X latches data
ACLKR/X ext 5 ns
Multichannel Audio Serial Port (McASP0) Peripheral
125
June 2003 − Revised October 2010 SPRS222F
Table 4−34. Switching Characteristics Over Recommended Operating Conditions for McASP
(see Figure 4−35 and Figure 4−36)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
9 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns
10 tw(AHCKRX) Pulse duration, AHCLKR/X high or low 10 ns
11 tc(CKRX) Cycle time, ACLKR/X ACLKR/X int 33 ns
12 tw(CKRX) Pulse duration, ACLKR/X high or low ACLKR/X int 16.5 ns
13
td(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X int −1 5 ns
13
t
d(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X ext 0 10 ns
14
td(CKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKX int −1 5 ns
14
t
d(CKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKX ext 0 10 ns
15
tdis(CKRX−AXRHZ)
Disable time, AXR high impedance following last data bit from
ACLKR/X int 0 10 ns
15
t
dis(CKRX−AXRHZ)
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge ACLKR/X ext 0 10 ns
Multichannel Audio Serial Port (McASP0) Peripheral
126 June 2003 − Revised October 2010SPRS222F
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
8
7
4
4
3
2
21
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
6
5
ACLKR/X (CLKRP = CLKXP = 0)†
ACLKR/X (CLKRP = CLKXP = 1)‡
†For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling
edge (to shift data in).
‡For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising
edge (to shift data in).
Figure 4−35. McASP Input Timings
Multichannel Audio Serial Port (McASP0) Peripheral
127
June 2003 − Revised October 2010 SPRS222F
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
15
14
13
13
13
13
13
13
13
12
12
11
10
10
9
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
ACLKR/X (CLKRP = CLKXP = 0)‡
ACLKR/X (CLKRP = CLKXP = 1)†
†For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising
edge (to shift data in).
‡For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling
edge (to shift data in).
Figure 4−36. McASP Output Timings
Inter-Integrated Circuit (I2C)
128 June 2003 − Revised October 2010SPRS222F
4.10 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between a TMS320C6000™ DSP and other
devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected
by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit
data to/from the DSP through the I2C module.
4.10.1 I2C Device-Specific Information
The I2C module on the TMS320DM641/DM640 may be used by the DSP to control local peripherals ICs
(DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to
implement a user interface.
The I2C port supports:
•Compatible with Philips I2C Specification Revision 2.1 (January 2000)
•Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
•Noise Filter to Remove Noise 50 ns or less
•Seven- and Ten-Bit Device Addressing Modes
•Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
•Events: DMA, Interrupt, or Polling
•Slew-Rate Limited Open-Drain Output Buffers
Figure 4−37 is a block diagram of the I2C0 module.
Clock
Prescale
I2CPSCx
Peripheral Clock
(CPU/4)
I2CCLKHx
Generator
Bit Clock
I2CCLKLx
Noise
Filter
SCL
I2CXSRx
I2CDXRx
Transmit
Transmit
Shift
Transmit
Buffer
I2CDRRx
Shift
I2CRSRx
Receive
Buffer
Receive
Receive
Filter
SDA
I2C Data Noise
I2COARx
I2CSARx Slave
Address
Control
Address
Own
I2CMDRx
I2CCNTx
Mode
Data
Count
Source
Interrupt
Interrupt
Status
I2CISRCx
I2CSTRx
Enable
Interrupt
I2CIERx
Interrupt/DMA
I2C0 Module
NOTE A: Shading denotes control/status registers.
I2C Clock
Figure 4−37. I2C0 Module Block Diagram
Inter-Integrated Circuit (I2C)
129
June 2003 − Revised October 2010 SPRS222F
For more detailed information on the I2C peripheral, see the TMS320C6000 DSP Inter -Integrated Circuit (I2C)
Module Reference Guide (literature number SPRU175).
4.10.2 I2C Peripheral Register Description(s)
Table 4−35. I2C0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B4 0000 I2COAR0 I2C0 own address register
01B4 0004 I2CIER0 I2C0 interrupt enable register
01B4 0008 I2CSTR0 I2C0 interrupt status register
01B4 000C I2CCLKL0 I2C0 clock low-time divider register
01B4 0010 I2CCLKH0 I2C0 clock high-time divider register
01B4 0014 I2CCNT0 I2C0 data count register
01B4 0018 I2CDRR0 I2C0 data receive register
01B4 001C I2CSAR0 I2C0 slave address register
01B4 0020 I2CDXR0 I2C0 data transmit register
01B4 0024 I2CMDR0 I2C0 mode register
01B4 0028 I2CISRC0 I2C0 interrupt source register
01B4 002C − Reserved
01B4 0030 I2CPSC0 I2C0 prescaler register
01B4 0034 I2CPID10 I2C0 Peripheral Identification register 1 [Value: 0x0000 0101]
01B4 0038 I2CPID20 I2C0 Peripheral Identification register 2 [Value: 0x0000 0005]
01B4 003C − 01B4 3FFF − Reserved
Inter-Integrated Circuit (I2C)
130 June 2003 − Revised October 2010SPRS222F
4.10.3 I2C Electrical Data/Timing
4.10.3.1 Inter-Integrated Circuits (I2C) Timing
Table 4−36. Timing Requirements for I2C Timings† (see Figure 4−38)
NO.
−400
−500
−600
UNIT
NO. STANDARD
MODE FAST
MODE
UNIT
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 10 2.5 μs
2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START
condition) 4.7 0.6 μs
3 th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated
START condition) 4 0.6 μs
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 μs
5 tw(SCLH) Pulse duration, SCL high 4 0.6 μs
6 tsu(SDAV-SDLH) Setup time, SDA valid before SCL high 250 100‡ns
7 th(SDA-SDLL) Hold time, SDA valid after SCL low (For I2C bus™ devices) 0§0§0.9¶μs
8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 μs
9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb#300 ns
10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb#300 ns
11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb#300 ns
12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb#300 ns
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 μs
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
15 Cb#Capacitive load for each bus line 400 400 pF
†The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
‡A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA−SCLH) ≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA−SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-Bus Specification) before the SCL line is released.
§A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
¶The maximum th(SDA−SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
#Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
10
84
3712
5
614
2
3
13
Stop Start Repeated
Start Stop
SDA
SCL
1
11 9
Figure 4−38. I2C Receive Timings
Inter-Integrated Circuit (I2C)
131
June 2003 − Revised October 2010 SPRS222F
Table 4−37. Switching Characteristics for I2C Timings† (see Figure 4−39)
NO.
PARAMETER
−400
−500
−600
UNIT
NO. PARAMETER STANDARD
MODE FAST
MODE
UNIT
MIN MAX MIN MAX
16 tc(SCL) Cycle time, SCL 10 2.5 μs
17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 μs
18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated
START condition) 4 0.6 μs
19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 μs
20 tw(SCLH) Pulse duration, SCL high 4 0.6 μs
21 td(SDAV-SDLH) Delay time, SDA valid to SCL high 250 100 ns
22 tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus™ devices) 0 0 0.9 μs
23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 μs
24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb†300 ns
25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb†300 ns
26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb†300 ns
27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb†300 ns
28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 μs
29 CpCapacitance for each I2C pin 10 10 pF
†Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
25
23 19
18 22 27
20
21
17
18
28
Stop Start Repeated
Start Stop
SDA
SCL
16
26 24
Figure 4−39. I2C Transmit Timings
Host-Port Interface (HPI) [DM641 Only]
132 June 2003 − Revised October 2010SPRS222F
4.11 Host-Port Interface (HPI) [DM641 Only]
The HPI is a parallel port through which a host processor can directly access the CPU memory space. The
host device functions as a master to the interface, which increases ease of access. The host and CPU can
exchange information via internal or external memory. The host also has direct access to memory-mapped
peripherals. Connectivity to the CPU memory space is provided through the enhanced DMA (EDMA)
controller. Both the host and the CPU can access the HPI control register (HPIC) and the HPI address register
(HPIA). The host can access the HPI data register (HPID) and the HPIC by using the external data and
interface control signals.
For more detailed information on the HPI peripheral, see the TMS320C6000 DSP Host Port Interface (HPI)
Reference Guide (literature number SPRU578).
4.11.1 HPI Peripheral Register Description(s) [DM641 Only]
Table 4−38. HPI Registers [DM641 Only]
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
−HPID HPI data register Host read/write access only
0188 0000 HPIC HPI control register HPIC has both Host/CPU read/write access
0188 0004 HPIA
(HPIAW)†HPI address register
(Write)
HPIA has both Host/CPU read/write access
0188 0008 HPIA
(HPIAR)†HPI address register
(Read)
HPIA has both Host/CPU read/write access
0188 000C − 0189 FFFF − Reserved
018A 0000 HPI_TRCTL HPI transfer request control
register
018A 0004 − 018B FFFF − Reserved
†Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
4.11.2 Host-Port Interface (HPI) Electrical Data/Timing [DM641 Only]
Table 4−39. Timing Requirements for Host-Port Interface Cycles†‡ (see Figure 4−40 through Figure 4−43)
[DM641 Only]
NO.
−400
−500
−600 UNIT
MIN MAX
1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low 5 ns
2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low 2.4 ns
3 tw(HSTBL) Pulse duration, HSTROBE low 4P¶ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns
10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low 5 ns
11 th(HASL-SELV) Hold time, select signals§ valid after HAS low 2 ns
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2.8 ns
14 th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly. 2 ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2.1 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§Select signals include: HCNTL[1:0], HR/W, and HHWIL.
¶Select the parameter value of 4P or 12.5 ns, whichever is larger.
Host-Port Interface (HPI) [DM641 Only]
133
June 2003 − Revised October 2010 SPRS222F
Table 4−40. Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles†‡ (see Figure 4−40 through Figure 4−43) [DM641 Only]
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#1.3 4P + 8 ns
7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low −3 ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 1.5 ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 12 ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only) 4P + 8 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
#This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling edge of
HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal
address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full.
1st half-word 2nd half-word
86
15
916
15
97
4
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (output)
HRDY
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 4−40. HPI16 Read Timing (HAS Not Used, Tied High) [DM641 Only]
Host-Port Interface (HPI) [DM641 Only]
134 June 2003 − Revised October 2010SPRS222F
HAS†
HCNTL[1:0]
HR/W
HHWIL
HSTROBE‡
HCS
HD[15:0] (output)
HRDY
1st half-word 2nd half-word
86
15
916
15
97
4
3
11
10
11
10
11
10
11
10
11
1011
10 19 19
18
18
†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 4−41. HPI16 Read Timing (HAS Used) [DM641 Only]
1st half-word 2nd half-word
13
12
13
12
4
14
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (input)
HRDY
3
6
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 4−42. HPI16 Write T iming (HAS Not Used, Tied High) [DM641 Only]
Host-Port Interface (HPI) [DM641 Only]
135
June 2003 − Revised October 2010 SPRS222F
1st half-word 2nd half-word
13
12
13
12
4
14
3
11
10
11
10
11
10
11
10
11
10
11
10
HAS†
HCNTL[1:0]
HR/W
HHWIL
HSTROBE‡
HCS
HD[15:0] (input)
HRDY
1919
18 18
6
†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 4−43. HPI16 Write T iming (HAS Used) [DM641 Only]
Multichannel Buffered Serial Port (McBSP)
136 June 2003 − Revised October 2010SPRS222F
4.12 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
•Full-duplex communication
•Double-buffered data registers, which allow a continuous data stream
•Independent framing and clocking for receive and transmit
•Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected
analog-to-digital (A/D) and digital-to-analog (D/A) devices
•External shift clock or an internal, programmable frequency shift clock for data transfer
For more detailed information on the McBSP peripheral, see the TMS320C6000 DSP Multichannel Buffered
Serial Port (McBSP) Reference Guide (literature number SPRU580).
4.12.1 McBSP Peripheral Register Description(s)
Table 4−41. McBSP 0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
018C 0000 DRR0 McBSP0 data receive register via Configuration Bus The CPU and EDMA controller
can only read this register; they
cannot write to it.
0x3000 0000 − 0x33FF FFFF DRR0 McBSP0 data receive register via Peripheral Bus
018C 0004 DXR0 McBSP0 data transmit register via Configuration Bus
0x3000 0000 − 0x33FF FFFF DXR0 McBSP0 data transmit register via Peripheral Bus
018C 0008 SPCR0 McBSP0 serial port control register
018C 000C RCR0 McBSP0 receive control register
018C 0010 XCR0 McBSP0 transmit control register
018C 0014 SRGR0 McBSP0 sample rate generator register
018C 0018 MCR0 McBSP0 multichannel control register
018C 001C RCERE00 McBSP0 enhanced receive channel enable register 0
018C 0020 XCERE00 McBSP0 enhanced transmit channel enable register 0
018C 0024 PCR0 McBSP0 pin control register
018C 0028 RCERE10 McBSP0 enhanced receive channel enable register 1
018C 002C XCERE10 McBSP0 enhanced transmit channel enable register 1
018C 0030 RCERE20 McBSP0 enhanced receive channel enable register 2
018C 0034 XCERE20 McBSP0 enhanced transmit channel enable register 2
018C 0038 RCERE30 McBSP0 enhanced receive channel enable register 3
018C 003C XCERE30 McBSP0 enhanced transmit channel enable register 3
018C 0040 − 018F FFFF – Reserved
Multichannel Buffered Serial Port (McBSP)
137
June 2003 − Revised October 2010 SPRS222F
Table 4−42. McBSP 1 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0190 0000 DRR1 McBSP1 data receive register via Configuration Bus The CPU and EDMA controller
can only read this register; they
cannot write to it.
0x3400 0000 − 0x37FF FFFF DRR1 McBSP1 data receive register via peripheral bus
0190 0004 DXR1 McBSP1 data transmit register via configuration bus
0x3400 0000 − 0x37FF FFFF DXR1 McBSP1 data transmit register via peripheral bus
0190 0008 SPCR1 McBSP1 serial port control register
0190 000C RCR1 McBSP1 receive control register
0190 0010 XCR1 McBSP1 transmit control register
0190 0014 SRGR1 McBSP1 sample rate generator register
0190 0018 MCR1 McBSP1 multichannel control register
0190 001C RCERE01 McBSP1 enhanced receive channel enable register 0
0190 0020 XCERE01 McBSP1 enhanced transmit channel enable register 0
0190 0024 PCR1 McBSP1 pin control register
0190 0028 RCERE11 McBSP1 enhanced receive channel enable register 1
0190 002C XCERE11 McBSP1 enhanced transmit channel enable register 1
0190 0030 RCERE21 McBSP1 enhanced receive channel enable register 2
0190 0034 XCERE21 McBSP1 enhanced transmit channel enable register 2
0190 0038 RCERE31 McBSP1 enhanced receive channel enable register 3
0190 003C XCERE31 McBSP1 enhanced transmit channel enable register 3
0190 0040 − 0193 FFFF – Reserved
Multichannel Buffered Serial Port (McBSP)
138 June 2003 − Revised October 2010SPRS222F
4.12.2 McBSP Electrical Data/Timing
4.12.2.1 Multichannel Buffered Serial Port (McBSP) Timing
Table 4−43. Timing Requirements for McBSP† (see Figure 4−44)
NO.
−400
−500
−600 UNIT
MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 4P or 6.67‡§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1¶ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 9
ns
5
t
su(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext 1.3
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 6
ns
6
t
h(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext 3
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 8
ns
7
t
su(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext 0.9
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 3
ns
8
t
h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext 3.1
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 9
ns
10
t
su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext 1.3
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 6
ns
11
t
h(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext 3
ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The
minimum CLK R/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
requirements.
¶This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
Multichannel Buffered Serial Port (McBSP)
139
June 2003 − Revised October 2010 SPRS222F
Table 4−44. Switching Characteristics Over Recommended Operating Conditions for McBSP†‡
(see Figure 4−44)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input 1.4 10 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 4P or 6.67§¶# ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1|| C + 1|| ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2.1 3 ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int −1.7 3
ns
9
t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext 1.7 9
ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
CLKX int −3.9 4
ns
12
t
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high CLKX ext −2.1 9
ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int −3.9 + D1k4 + D2k
ns
13
t
d(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX ext −2.1 + D1k9 + D2k
ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid FSX int −2.3 + D1h5.6 + D2h
ns
14
t
d(FXH-DXV) ONLY applies when in data
delay 0 (XDATDLY = 00b) mode FSX ext 1.9 + D1h9 + D2h
ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
¶P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
#Use whichever value is greater.
|| C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
kExtra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
hExtra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
Multichannel Buffered Serial Port (McBSP)
140 June 2003 − Revised October 2010SPRS222F
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
12
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
†Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
13†
13†
Figure 4−44. McBSP Timing
Table 4−45. Timing Requirements for FSR When GSYNC = 1 (see Figure 4−45)
NO.
−400
−500
−600 UNIT
MIN MAX
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 4−45. FSR Timing When GSYNC = 1
Multichannel Buffered Serial Port (McBSP)
141
June 2003 − Revised October 2010 SPRS222F
Table 4−46. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 0†‡ (see Figure 4−46)
NO.
−400
−500
−600
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 12P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 24P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−47. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 4−46)
NO.
PARAMETER
−400
−500
−600
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T − 2 T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L − 2.5 L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −2 4 12P + 2.8 20P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit
from CLKX low L − 2 L + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit
from FSX high 4P + 3 12P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 1.8 16P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI Master , FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 4−46. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Multichannel Buffered Serial Port (McBSP)
142 June 2003 − Revised October 2010SPRS222F
Table 4−48. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 0†‡ (see Figure 4−47)
NO.
−400
−500
−600
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 12P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 24P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−49. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 4−47)
NO.
PARAMETER
−400
−500
−600
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L − 2 L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T − 2.5 T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −2 4 12P + 3 20P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low −2 4 12P + 3 20P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H − 2 H + 4 8P + 2 16P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI Master , FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
Figure 4−47. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Multichannel Buffered Serial Port (McBSP)
143
June 2003 − Revised October 2010 SPRS222F
Table 4−50. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1†‡ (see Figure 4−48)
NO.
−400
−500
−600
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 12P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 24P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−51. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 4−48)
NO.
PARAMETER
−400
−500
−600
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T − 2 T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H − 2.5 H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −2 4 12P + 3 20P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit
from CLKX high H − 2 H + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit
from FSX high 4P + 3 12P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 2 16P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI Master , FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
Figure 4−48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Multichannel Buffered Serial Port (McBSP)
144 June 2003 − Revised October 2010SPRS222F
Table 4−52. Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 1†‡ (see Figure 4−49)
NO.
−400
−500
−600
UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 12P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 24P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−53. Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 4−49)
NO.
PARAMETER
−400
−500
−600
UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H − 2 H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T − 2.5 T + 1.5 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −2 4 12P + 3 20P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit
from CLKX high −2 4 12P + 3 20P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L − 2 L + 4 8P + 2 16P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI Master , FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
Figure 4−49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
Video Port
145
June 2003 − Revised October 2010 SPRS222F
4.13 Video Port
Each Video Port is capable of sending and receiving digital video data. The Video Ports are also capable of
capturing/displaying RAW data. The Video Port peripherals follow video standards such as CCIR601 and
ITU-BT.656.
4.13.1 Video Port Device-Specific Information
The TMS320DM641 device has two video port peripherals [VP0 and VP1]. The TMS320DM640 device only
supports one video port peripheral [VP0].
The video port peripheral can operate as a video capture port, video display port, or as a transport stream
interface (TSI) capture port.
The port consists of a single channel A. A 2560-byte capture/display buffer is utilized on this channel. The port
is always configured for either video capture or display only. Separate data pipelines control the parsing and
formatting of video capture or display data for each of the BT.656, raw video, and TSI modes.
For video capture operation, the video port may operate as a single channel of 8-bit BT.656, 8-bit raw video,
or 8-bit TSI.
For video display operation, the video port may operate as 8-bit BT.656 or 8-bit raw video.
For more detailed information on the DM641 and DM640 Video Port peripherals, see the TMS320C64x DSP
Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).
4.13.2 Video Port Peripheral Register Description(s)
Table 4−54. Video Port 0 and 1 (VP0 and VP1) Control Registers
HEX ADDRESS RANGE
VP0 VP1
[DM641 ONLY] ACRONYM DESCRIPTION
01C4 0000 01C4 4000 VP_PIDx Video Port Peripheral Identification Register
01C4 0004 01C4 4004 VP_PCRx Video Port Peripheral Control Register
01C4 0008 01C4 4008 − Reserved
01C4 000C 01C4 400C − Reserved
01C4 0020 01C4 4020 VP_PFUNCx Video Port Pin Function Register
01C4 0024 01C4 4024 VP_PDIRx Video Port Pin Direction Register
01C4 0028 01C4 4028 VP_PDINx Video Port Pin Data Input Register
01C4 002C 01C4 402C VP_PDOUTx Video Port Pin Data Output Register
01C4 0030 01C4 4030 VP_PDSETx Video Port Pin Data Set Register
01C4 0034 01C4 4034 VP_PDCLRx Video Port Pin Data Clear Register
01C4 0038 01C4 4038 VP_PIENx Video Port Pin Interrupt Enable Register
01C4 003C 01C4 403C VP_PIPOx Video Port Pin Interrupt Polarity Register
01C4 0040 01C4 4040 VP_PISTATx Video Port Pin Interrupt Status Register
01C4 0044 01C4 4044 VP_PICLRx Video Port Pin Interrupt Clear Register
01C4 00C0 01C4 40C0 VP_CTLx Video Port Control Register
01C4 00C4 01C4 40C4 VP_STATx Video Port Status Register
01C4 00C8 01C4 40C8 VP_IEx Video Port Interrupt Enable Register
01C4 00CC 01C4 40CC VP_ISx Video Port interrupt Status Register
01C4 0100 01C4 4100 VC_STATx Video Capture Channel A Status Register
Video Port
146 June 2003 − Revised October 2010SPRS222F
Table 4−54. Video Port 0 and 1 (VP0 and VP1) Control Registers (Continued)
HEX ADDRESS RANGE DESCRIPTIONACRONYM
VP0 DESCRIPTIONACRONYM
VP1
[DM641 ONLY]
01C4 0104 01C4 4104 VC_CTLx Video Capture Channel A Control Register
01C4 0108 01C4 4108 VC_ASTRTx Video Capture Channel A Field 1 Start Register
01C4 010C 01C4 410C VC_ASTOPx Video Capture Channel A Field 2 Stop Register
01C4 0110 01C4 4110 VC_ASTRTx Video Capture Channel A Field 2 Start Register
01C4 0114 01C4 4114 VC_ASTOPx Video Capture Channel A Field 1 Stop Register
01C4 0118 01C4 4118 VC_AVINTx Video Capture Channel A Vertical Interrupt Register
01C4 011C 01C4 411C VC_ATHRLDx Video Capture Channel A Threshold Register
01C4 0120 01C4 4120 VC_AEVTCTx Video Capture Channel A Event Count Register
01C4 0180 01C4 4180 TSI_CTLx TCI Capture Control Register
01C4 0184 01C4 4184 TSI_CLKINITLx TCI Clock Initialization LSB Register
01C4 0188 01C4 4188 TSI_CLKINITMx TCI Clock Initialization MSB Register
01C4 018C 01C4 418C TSI_STCLKLx TCI System Time Clock LSB Register
01C4 0190 01C4 4190 TSI_STCLKMx TCI System Time Clock MSB Register
01C4 0194 01C4 4194 TSI_STCMPLx TCI System Time Clock Compare LSB Register
01C4 0198 01C4 4198 TSI_STCMPMx TCI System Time Clock Compare MSB Register
01C4 019C 01C4 419C TSI_STMSKLx TCI System Time Clock Compare Mask LSB Register
01C4 01A0 01C4 41A0 TSI_STMSKMx TCI System Time Clock Compare Mask MSB Register
01C4 01A4 01C4 41A4 TSI_TICKSx TCI System Time Clock Ticks Interrupt Register
01C4 0200 01C4 4200 VD_STATx Video Display Status Register
01C4 0204 01C4 4204 VD_CTLx Video Display Control Register
01C4 0208 01C4 4208 VD_FRMSZx Video Display Frame Size Register
01C4 020C 01C4 420C VD_HBLNKx Video Display Horizontal Blanking Register
01C4 0210 01C4 4210 VD_VBLKS1x Video Display Field 1 Vertical Blanking Start Register
01C4 0214 01C4 4214 VD_VBLKE1x Video Display Field 1 Vertical Blanking End Register
01C4 0218 01C4 4218 VD_VBLKS2x Video Display Field 2 Vertical Blanking Start Register
01C4 021C 01C4 421C VD_VBLKE2x Video Display Field 2 Vertical Blanking End Register
01C4 0220 01C4 4220 VD_IMGOFF1x Video Display Field 1 Image Offset Register
01C4 0224 01C4 4224 VD_IMGSZ1x Video Display Field 1 Image Size Register
01C4 0228 01C4 4228 VD_IMGOFF2x Video Display Field 2 Image Offset Register
01C4 022C 01C4 422C VD_IMGSZ2x Video Display Field 2 Image Size Register
01C4 0230 01C4 4230 VD_FLDT1x Video Display Field 1 Timing Register
01C4 0234 01C4 4234 VD_FLDT2x Video Display Field 2 Timing Register
01C4 0238 01C4 4238 VD_THRLDx Video Display Threshold Register
01C4 023C 01C4 423C VD_HSYNCx Video Display Horizontal Synchronization Register
01C4 0240 01C4 4240 VD_VSYNS1x Video Display Field 1 Vertical Synchronization Start Register
01C4 0244 01C4 4244 VD_VSYNE1x Video Display Field 1 Vertical Synchronization End Register
01C4 0248 01C4 4248 VD_VSYNS2x Video Display Field 2 Vertical Synchronization Start Register
01C4 024C 01C4 424C VD_VSYNE2x Video Display Field 2 Vertical Synchronization End Register
01C4 0250 01C4 4250 VD_RELOADx Video Display Counter Reload Register
01C4 0254 01C4 4254 VD_DISPEVTx Video Display Display Event Register
Video Port
147
June 2003 − Revised October 2010 SPRS222F
Table 4−54. Video Port 0 and 1 (VP0 and VP1) Control Registers (Continued)
HEX ADDRESS RANGE DESCRIPTIONACRONYM
VP0 DESCRIPTIONACRONYM
VP1
[DM641 ONLY]
01C4 0258 01C4 4258 VD_CLIPx Video Display Clipping Register
01C4 025C 01C4 425C VD_DEFVALx Video Display Default Display Value Register
01C4 0260 01C4 4260 VD_VINTx Video Display Vertical Interrupt Register
01C4 0264 01C4 4264 VD_FBITx Video Display Field Bit Register
01C4 0268 01C4 4268 VD_VBIT1x Video Display Field 1Vertical Blanking Bit Register
01C4 026C 01C4 426C VD_VBIT2x Video Display Field 2Vertical Blanking Bit Register
7400 000 7800 0000 Y_RSCA Y FIFO Source Register A
7400 0008 7800 0008 CB_SRCA CB FIFO Source Register A
7400 0010 7800 0010 CR_SRCA CR FIFO Source Register A
7400 0020 7800 0020 Y_DSTA Y FIFO Destination Register A
7400 0028 7800 0028 CB_DST CB FIFO Destination Register A
7400 0030 7800 0030 CR_DST CR FIFO Destination Register A
Video Port
148 June 2003 − Revised October 2010SPRS222F
4.13.3 Video Port (VP0 [DM641/DM640], VP1 [DM641 Only]) Electrical Data/Timing
4.13.3.1 VCLKIN Timing (Video Capture Mode)
Table 4−55. Timing Requirements for Video Capture Mode for VPxCLKINx† (see Figure 4−50)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tc(VKI) Cycle time, VPxCLKINx 12.5 ns
2 tw(VKIH) Pulse duration, VPxCLKINx high 5.4 ns
3 tw(VKIL) Pulse duration, VPxCLKINx low 5.4 ns
4 tt(VKI) Transition time, VPxCLKINx 3 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
VPxCLKINx
23
14
4
Figure 4−50. Video Port Capture VPxCLKINx TIming
Video Port
149
June 2003 − Revised October 2010 SPRS222F
4.13.3.2 Video Data and Control Timing (Video Capture Mode)
Table 4−56. Timing Requirements in Video Capture Mode for Video Data and Control Inputs
(see Figure 4−51)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tsu(VDATV-VKIH) Setup time, VPxDx valid before VPxCLKINx high 2.9 ns
2 th(VDATV-VKIH) Hold time, VPxDx valid after VPxCLKINx high 0.5 ns
3 tsu(VCTLV-VKIH) Setup time, VPxCTLx valid before VPxCLKINx high 2.9 ns
4 th(VCTLV-VKIH) Hold time, VPxCTLx valid after VPxCLKINx high 0.5 ns
VPxCLKINx
VPxD[7:0] (Input)
VPxCTLx (Input)
1
2
3
4
Figure 4−51. Video Port Capture Data and Control Input Timing
Video Port
150 June 2003 − Revised October 2010SPRS222F
4.13.3.3 VCLKIN Timing (Video Display Mode)
Table 4−57. Timing Requirements for Video Display Mode for VPxCLKINx† (see Figure 4−52)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tc(VKI) Cycle time, VPxCLKINx 9 ns
2 tw(VKIH) Pulse duration, VPxCLKINx high 4.1 ns
3 tw(VKIL) Pulse duration, VPxCLKINx low 4.1 ns
4 tt(VKI) Transition time, VPxCLKINx 3 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
VPxCLKINx
23
14
4
Figure 4−52. Video Port Display VPxCLKINx Timing
4.13.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx (Video Display Mode)
Table 4−58. Timing Requirements in Video Display Mode for Video Control Input Shown With
Respect to VPxCLKINx and VPxCLKOUTx (see Figure 4−53)
NO
.
−400
−500
−600 UNIT
MIN MAX
13 tsu(VCTLV-VKIH) Setup time, VPxCTLx valid before VPxCLKINx high 2.9 ns
14 th(VCTLV-VKIH) Hold time, VPxCTLx valid after VPxCLKINx high 0.5 ns
15 tsu(VCTLV-VKOH) Setup time, VPxCTLx valid before VPxCLKOUTx high‡7.4 ns
16 th(VCTLV-VKOH) Hold time, VPxCTLx valid after VPxCLKOUTx high‡−0.9 ns
‡Assuming non-inverted VPxCLKOUTx signal.
Video Port
151
June 2003 − Revised October 2010 SPRS222F
Table 4−59. Switching Characteristics Over Recommended Operating Conditions in Video
Display Mode for Video Data and Control Output Shown With Respect to
VPxCLKINx and VPxCLKOUTx†‡ (see Figure 4−53)
NO
.
PARAMETER
−400
−500
−600 UNIT
MIN MAX
1 tc(VKO) Cycle time, VPxCLKOUTx V − 0.7 V + 0.7 ns
2 tw(VKOH) Pulse duration, VPxCLKOUTx high VH − 0.7 VH + 0.7 ns
3 tw(VKOL) Pulse duration, VPxCLKOUTx low VL − 0.7 VL + 0.7 ns
4 tt(VKO) Transition time, VPxCLKOUTx 1.8 ns
5 td(VKIH-VKOH) Delay time, VPxCLKINx high to VPxCLKOUTx high§1.1 5.7 ns
6 td(VKIL-VKOL) Delay time, VPxCLKINx low to VPxCLKOUTx low§1.1 5.7 ns
7 td(VKIH-VKOL) Delay time, VPxCLKINx high to VPxCLKOUTx low 1.1 5.7 ns
8 td(VKIL-VKOH) Delay time, VPxCLKINx low to VPxCLKOUTx high 1.1 5.7 ns
9 td(VKIH-VPOUTV) Delay time, VPxCLKINx high to VPxOUT valid¶9 ns
10 td(VKIH-VPOUTIV) Delay time, VPxCLKINx high to VPxOUT invalid¶1.7 ns
11 td(VKOH-VPOUTV) Delay time, VPxCLKOUTx high to VPxOUT valid†¶ 4.3 ns
12 td(VKOH-VPOUTIV) Delay time, VPxCLKOUTx high to VPxOUT invalid†¶ −0.2 ns
†V = the video input clock (VPxCLKINx) period in ns.
‡VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
§Assuming non-inverted VPxCLKOUTx signal.
¶VPxOUT consists of VPxCTLx and VPxD[7:0]
VPxCLKINx
VPxCLKOUTx
[VCLK2P = 0]
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
VPxCTLx,
VPxD[7:0]
(Outputs)
VPxCTLx
(Input)
5
7
13
2
6
8
9
13
10
14
11 12
15 16
4
4
Figure 4−53. Video Port Display Data Output Timing and Control Input/Output Timing
With Respect to VPxCLKINx and VPxCLKOUTx
Video Port
152 June 2003 − Revised October 2010SPRS222F
4.13.3.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)
Table 4−60. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 4−54)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tskr(VKI) Skew rate, VPxCLKINx before VPyCLKINy ±500 ps
1
VPxCLKINx
VPyCLKINy
Figure 4−54. Video Port Dual-Display Sync Timing
VCXO Interpolated Control (VIC)
153
June 2003 − Revised October 2010 SPRS222F
4.14 VCXO Interpolated Control (VIC)
The VIC can be used in conjunction with the Video Ports (VPs) to maintain synchronization of a video stream.
The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port.
4.14.1 VIC Device-Specific Information
The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9-bits
to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).
Typical D/A converters provide a discrete output level for every value of the digital word that is being converted.
This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by
choosing a few widely spaced output levels and interpolating values between them. The interpolating
mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output
represents the value of input code.
In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to
interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependent
on the resolution needed.
When t h e video port is used in transport stream interface (TSI) mode, the VIC port is used to control the system
clock, VCXO, for MPEG transport stream.
The VIC supports the following features:
•Single interpolation for D/A conversion
•Programmable precision from 9-to-16 bits
•Interface for register accesses
For more detailed information on the DM641 and DM640 VCXO interpolated control (VIC) peripheral, see the
TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number
SPRU629).
4.14.2 VIC Peripheral Register Description(s)
Table 4−61. VCXO Interpolated Control (VIC) Port Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01C4 C000 VICCTL VIC control register
01C4 C004 VICIN VIC input register
01C4 C008 VPDIV VIC clock divider register
01C4 C00C − 01C4 FFFF − Reserved
VCXO Interpolated Control (VIC)
154 June 2003 − Revised October 2010SPRS222F
4.14.3 VIC Electrical Data/Timing
4.14.3.1 STCLK Timing
Table 4−62. Timing Requirments for STCLK† (see Figure 4−55)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tc(STCLK) Cycle time, STCLK 33.3 ns
2 tw(STCLKH) Pulse duration, STCLK high 16 ns
3 tw(STCLKL) Pulse duration, STCLK low 16 ns
4 tt(STCLK) Transition time, STCLK 3 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
STCLK
23
14
4
Figure 4−55. STCLK Timing
Ethernet Media Access Controller (EMAC)
155
June 2003 − Revised October 2010 SPRS222F
4.15 Ethernet Media Access Controller (EMAC)
The EMAC controls the flow of packet data from the DSP to the PHY.
4.15.1 EMAC Device-Specific Information
The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP
core processor and the network. The DM641/DM640 EMAC support both 10Base-T and 100Base-TX, or 10
Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of
service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that
allows efficient data transmission and reception.
The EMAC controls the flow of packet data from the DSP to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows efficient
data transmission and reception. This custom interface is referred to as the EMAC control module, and is
considered integral to the EMAC/MDIO peripheral. The control module is also used to control device reset,
interrupts, and system priority.
The TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628) describes the DM641/DM640 EMAC peripheral in
detail. Some of the features documented in this peripheral reference guide are not supported on the
DM641/DM640 at this time. The DM641/DM640 supports one receive channel and does not support receive
quality of service (QOS). For a list of supported registers and register fields, see Table 4−63 [Ethernet MAC
(EMAC) Control Registers] and Table 4−64 [EMAC Statistics Registers] in this data manual.
4.15.2 EMAC Peripheral Register Description(s)
Table 4−63. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01C8 0000 TXIDVER Transmit Identification and Version Register
01C8 0004 TXCONTROL Transmit Control Register
01C8 0008 TXTEARDOWN Transmit Teardown Register
01C8 000C − Reserved
01C8 0010 RXIDVER Receive Identification and Version Register
01C8 0014 RXCONTROL Receive Control Register
01C8 0018 RXTEARDOWN Receive Teardown Register
(RXTDNCH field only supports writes of 0.)
01C8 001C − 01C8 00FF − Reserved
01C8 0100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register
(The RXQOSEN field is reserved and only supports writes of 0. The
PROMCH, BROADCH, and MUCTCH bit fields only support writes of 0.)
01C8 0104 RXUNICASTSET Receive Unicast Set Register
(Bits 7−1 are reserved and only support writes of 0.)
01C8 0108 RXUNICASTCLEAR Receive Unicast Clear Register
(Bits 7−1 are reserved and only support writes of 0.)
01C8 010C RXMAXLEN Receive Maximum Length Register
01C8 0110 RXBUFFEROFFSET Receive Buffer Offset Register
01C8 0114 RXFILTERLOWTHRESH Receive Filter Low Priority Packets Threshold Register
01C8 0118 − 01C8 011F − Reserved
01C8 0120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register
Ethernet Media Access Controller (EMAC)
156 June 2003 − Revised October 2010SPRS222F
Table 4−63. Ethernet MAC (EMAC) Control Registers (Continued)
HEX ADDRESS RANGE REGISTER NAMEACRONYM
01C8 0124 RX1FLOWTHRESH
01C8 0128 RX2FLOWTHRESH
01C8 012C RX3FLOWTHRESH
01C8 0130 RX4FLOWTHRESH Reserved. Do not write.
01C8 0134 RX5FLOWTHRESH
Reserved. Do not write.
01C8 0138 RX6FLOWTHRESH
01C8 013C RX7FLOWTHRESH
01C8 0140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register
01C8 0144 RX1FREEBUFFER
01C8 0148 RX2FREEBUFFER
01C8 014C RX3FREEBUFFER
01C8 0150 RX4FREEBUFFER Reserved. Do not write.
01C8 0154 RX5FREEBUFFER
Reserved. Do not write.
01C8 0158 RX6FREEBUFFER
01C8 015C RX7FREEBUFFER
01C8 0160 MACCONTROL MAC Control Register
01C8 0164 MACSTATUS MAC Status Register (RXQOSACT field is reserved.)
01C8 0168 − 01C8 016C − Reserved
01C8 0170 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register
01C8 0174 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register
01C8 0178 TXINTMASKSET Transmit Interrupt Mask Set Register
01C8 017C TXINTMASKCLEAR Transmit Interrupt Mask Clear Register
01C8 0180 MACINVECTOR MAC Input Vector Register
01C8 0184 − 01C8 018F − Reserved
01C8 0190 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register
(Bits 7−1 are reserved.)
01C8 0194 RXINTSTATMASKED Receive Interrupt Status (Masked) Register
(Bits 7−1 are reserved.)
01C8 0198 RXINTMASKSET Receive Interrupt Mask Set Register
(Bits 7−1 are reserved and only support writes of 0.)
01C8 019C RXINTMASKCLEAR Receive Interrupt Mask Clear Register
(Bits 7−1 are reserved and only support writes of 0.)
01C8 01A0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register
01C8 01A4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register
01C8 01A8 MACINTMASKSET MAC Interrupt Mask Set Register
01C8 01AC MACINTMASKCLEAR MAC Interrupt Mask Clear Register
01C8 01B0 MACADDRL0 MAC Address Channel 0 Lower Byte Register
01C8 01B4 MACADDRL1
01C8 01B8 MACADDRL2
01C8 01BC MACADDRL3
01C8 01C0 MACADDRL4 Reserved. Do not write.
01C8 01C4 MACADDRL5
Reserved. Do not write.
01C8 01C8 MACADDRL6
01C8 01CC MACADDRL7
01C8 01D0 MACADDRM MAC Address Middle Byte Register
Ethernet Media Access Controller (EMAC)
157
June 2003 − Revised October 2010 SPRS222F
Table 4−63. Ethernet MAC (EMAC) Control Registers (Continued)
HEX ADDRESS RANGE REGISTER NAMEACRONYM
01C8 01D4 MACADDRH MAC Address High Bytes Register
01C8 01D8 MACHASH1 MAC Address Hash 1 Register
01C8 01DC MACHASH2 MAC Address Hash 2 Register
01C8 01E0 BOFFTEST Backof f Test Register
01C8 01E4 TPACETEST Transmit Pacing Test Register
01C8 01E8 RXPAUSE Receive Pause Timer Register
01C8 01EC TXPAUSE Transmit Pause Timer Register
01C8 01F0 − 01C8 01FF − Reserved
01C8 0200 − 01C8 05FF (see Table 4−64) EMAC Statistics Registers
01C8 0600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register
01C8 0604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register
01C8 0608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register
01C8 060C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register
01C8 0610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register
01C8 0614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register
01C8 0618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register
01C8 061C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register
01C8 0620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register
01C8 0624 RX1HDP
01C8 0628 RX2HDP
01C8 062C RX3HDP
01C8 0630 RX4HDP Reserved. Do not write.
01C8 0634 RX5HDP
Reserved. Do not write.
01C8 0638 RX6HDP
01C8 063C RX7HDP
01C8 0640 TX0INTACK Transmit Channel 0 Interrupt Acknowledge Register
01C8 0644 TX1INTACK Transmit Channel 1 Interrupt Acknowledge Register
01C8 0648 TX2INTACK Transmit Channel 2 Interrupt Acknowledge Register
01C8 064C TX3INTACK Transmit Channel 3 Interrupt Acknowledge Register
01C8 0650 TX4INTACK Transmit Channel 4 Interrupt Acknowledge Register
01C8 0654 TX5INTACK Transmit Channel 5 Interrupt Acknowledge Register
01C8 0658 TX6INTACK Transmit Channel 6 Interrupt Acknowledge Register
01C8 065C TX7INTACK Transmit Channel 7 Interrupt Acknowledge Register
01C8 0660 RX0INTACK Receive Channel 0 Interrupt Acknowledge Register
01C8 0664 RX1INTACK
01C8 0668 RX2INTACK
01C8 066C RX3INTACK
01C8 0670 RX4INTACK Reserved. Do not write.
01C8 0674 RX5INTACK
Reserved. Do not write.
01C8 0678 RX6INTACK
01C8 067C RX7INTACK
01C8 0680 − 01C8 0FFF − Reserved
Ethernet Media Access Controller (EMAC)
158 June 2003 − Revised October 2010SPRS222F
Table 4−64. EMAC Statistics Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01C8 0200 RXGOODFRAMES Good Receive Frames Register
01C8 0204 RXBCASTFRAMES Broadcast Receive Frames Register
01C8 0208 RXMCASTFRAMES Multicast Receive Frames Register
01C8 020C RXPAUSEFRAMES Pause Receive Frames Register
01C8 0210 RXCRCERRORS Receive CRC Errors Register
01C8 0214 RXALIGNCODEERRORS Receive Alignment/Code Errors Register
01C8 0218 RXOVERSIZED Receive Oversized Frames Register
01C8 021C RXJABBER Receive Jabber Frames Register
01C8 0220 RXUNDERSIZED Receive Undersized Frames Register
01C8 0224 RXFRAGMENTS Receive Frame Fragments Register
01C8 0228 RXFILTERED Filtered Receive Frames Register
01C8 022C RXQOSFILTERED Reserved
01C8 0230 RXOCTETS Receive Octet Frames Register
01C8 0234 TXGOODFRAMES Good Transmit Frames Register
01C8 0238 TXBCASTFRAMES Broadcast Transmit Frames Register
01C8 023C TXMCASTFRAMES Multicast Transmit Frames Register
01C8 0240 TXPAUSEFRAMES Pause Transmit Frames Register
01C8 0244 TXDEFERRED Deferred Transmit Frames Register
01C8 0248 TXCOLLISION Collision Register
01C8 024C TXSINGLECOLL Single Collision Transmit Frames Register
01C8 0250 TXMULTICOLL Multiple Collision Transmit Frames Register
01C8 0254 TXEXCESSIVECOLL Excessive Collisions Register
01C8 0258 TXLATECOLL Late Collisions Register
01C8 025C TXUNDERRUN Transmit Underrun Register
01C8 0260 TXCARRIERSLOSS Transmit Carrier Sens e Errors Regist er
01C8 0264 TXOCTETS Transmit Octet Frames Register
01C8 0268 FRAME64 Transmit and Receive 64 Octet Frames Register
01C8 026C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register
01C8 0270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register
01C8 0274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register
01C8 0278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register
01C8 027C FRAME1024TUP Transmit and Receive 1024 or Above Octet Frames
Register
01C8 0280 NETOCTETS Network Octet Frames Register
01C8 0284 RXSOFOVERRUNS Receive Start of Frame Overruns Register
01C8 0288 RXMOFOVERRUNS Receive Middle of Frame Overruns Register
01C8 028C RXDMAOVERRUNS Receive DMA Overruns Register
01C8 0290 − 01C8 05FF − Reserved
Table 4−65. EMAC W rapper
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01C8 1000 − 01C8 1FFF EMAC Control Module Descriptor Memory
01C8 2000 − 01C8 2FFF − Reserved
Ethernet Media Access Controller (EMAC)
159
June 2003 − Revised October 2010 SPRS222F
Table 4−66. EWRAP Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01C8 3000 EWTRCTRL TR control
01C8 3004 EWCTL Interrupt control register
01C8 3008 EWINTTCNT Interrupt timer count
01C8 300C − 01C8 37FF − Reserved
4.15.3 EMAC Electrical Data/Timing
Table 4−67. Timing Requirements for MRCLK (see Figure 4−56)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tc(MRCLK) Cycle time, MRCLK 40 ns
2 tw(MRCLKH) Pulse duration, MRCLK high 14 ns
3 tw(MRCLKL) Pulse duration, MRCLK low 14 ns
MRCLK
23
1
Figure 4−56. MRCLK Timing (EMAC − Receive)
Table 4−68. Timing Requirements for MTCLK (see Figure 4−56)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tc(MTCLK) Cycle time, MTCLK 40 ns
2 tw(MTCLKH) Pulse duration, MTCLK high 14 ns
3 tw(MTCLKL) Pulse duration, MTCLK low 14 ns
MTCLK
23
1
Figure 4−57. MTCLK Timing (EMAC − Transmit)
Ethernet Media Access Controller (EMAC)
160 June 2003 − Revised October 2010SPRS222F
Table 4−69. Timing Requirements for EMAC MII Receive 10/100 Mbit/s† (see Figure 4−58)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns
2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns
†Receive selected signals include: MRXD3−MRXD0, MRXDV, and MRXER.
MRCLK (Input)
1
2
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 4−58. EMAC Receive Interface Timing
Table 4−70. Switching Characteristics Over Recommended Operating Conditions for EMAC
MII Transmit 10/100 Mbit/s‡ (see Figure 4−59)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid 5 25 ns
‡Transmit selected signals include: MTXD3−MTXD0, and MTXEN.
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 4−59. EMAC Transmit Interface Timing
Management Data Input/Output (MDIO)
161
June 2003 − Revised October 2010 SPRS222F
4.16 Management Data Input/Output (MDIO)
The MDIO module controls PHY configuration and status monitoring.
4.16.1 Device-Specific Information
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module
to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation
results, and configure required parameters in the EMAC module for correct operation. The module is designed
to allow almost transparent operation of the MDIO interface, with very little maintenance from the core
processor.
The TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628) describes the DM641/DM640 MDIO peripheral in
detail. Some of the features documented in this peripheral reference guide are not supported on the
DM641/DM640 at this time. The DM641/DM640 only supports one EMAC module. For a list of supported
registers and register fields, see Table 4−71 [MDIO Registers] in this data manual.
4.16.2 Peripheral Register Description(s)
Table 4−71. MDIO Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01C8 3800 VERSION MDIO Version Register
01C8 3804 CONTROL MDIO Control Register
01C8 3808 ALIVE MDIO PHY Alive Indication Register
01C8 380C LINK MDIO PHY Link Status Register
01C8 3810 LINKINTRAW MDIO Link Status Change Interrupt Register
(MAC1 field is reserved and only supports writes of 0.)
01C8 3814 LINKINTMASKED MDIO Link Status Change Interrupt (Masked) Register
(MAC1 field is reserved and only supports writes of 0.)
01C8 3818 USERINTRAW MDIO User Command Complete Interrupt Register
(MAC1 field is reserved and only supports writes of 0.)
01C8 381C USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register
(MAC1 field is reserved and only supports writes of 0.)
01C8 3820 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register
(MAC1 field is reserved and only supports writes of 0.)
01C8 3824 USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register
(MAC1 field is reserved and only supports writes of 0.)
01C8 3828 USERACCESS0 MDIO User Access Register 0
01C8 382C USERACCESS1 Reserved. Do not write.
01C8 3830 USERPHYSEL0 MDIO User PHY Select Register 0
01C8 3834 USERPHYSEL1 Reserved. Do not write.
01C8 3838 − 01C8 3FFF − Reserved
Management Data Input/Output (MDIO)
162 June 2003 − Revised October 2010SPRS222F
4.16.3 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 4−72. Timing Requirements for MDIO Input (see Figure 4−60 and Figure 4−61)
NO
.
−400
−500
−600 UNIT
MIN MAX
1 tc(MDCLK) Cycle time, MDCLK 400 ns
2 tw(MDCLK) Pulse duration, MDCLK high/low 180 ns
3 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 10 ns
4 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high 0 ns
1
34
MDCLK
MDIO
(input)
Figure 4−60. MDIO Input Timing
Table 4−73. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 4−61)
NO
.
−400
−500
−600 UNIT
MIN MAX
7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid −10 100 ns
1
7
MDCLK
MDIO
(output)
Figure 4−61. MDIO Output Timing
Timer
163
June 2003 − Revised October 2010 SPRS222F
4.17 Timer
The C6000™ DSP device has 32-bit general-purpose timers that can be used to:
•Time events
•Count events
•Generate pulses
•Interrupt the CPU
•Send synchronization events to the DMA
The timers have two signaling modes and can be clocked by an internal or an external source. The timers have
an input pin and an output pin. The input and output pins (TINP and TOUT) can function as timer clock input
and clock output. They can also be respectively configured for general-purpose input and output.
With an internal clock, for example, the timer can signal an external A/D converter to start a conversion, or
it can trigger the DMA controller to begin a data transfer. With an external clock, the timer can count external
events and interrupt the CPU after a specified number of events.
4.17.1 Timer Device-Specific Information
The DM641/DM640 device has a total of three 32-bit general-purpose timers (Timer0, Ti mer1, and Timer2).
Timer2 is not externally pinned out.
For more detailed information, see the TMS320C6000 DSP 32-Bit Timer Reference Guide (literature number
SPRU582).
4.17.2 Timer Peripheral Register Description(s)
Table 4−74. Timer 0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0194 0000 CTL0 Timer 0 control register Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter.
0194 000C − 0197 FFFF − Reserved
Table 4−75. Timer 1 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0198 0000 CTL1 Timer 1 control register Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter.
0198 000C − 019B FFFF − Reserved
Table 4−76. Timer 2 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
01AC 0000 CTL2 Timer 2 control register Determines the operating mode of the timer, monitors the
timer status.
01AC 0004 PRD2 Timer 2 period register Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
01AC 0008 CNT2 Timer 2 counter register Contains the current value of the incrementing counter.
01AC 000C − 01AF FFFF − Reserved
Timer
164 June 2003 − Revised October 2010SPRS222F
4.17.3 Timer Electrical Data/Timing
Table 4−77. Timing Requirements for Timer Inputs† (see Figure 4−62)
NO.
−400
−500
−600 UNIT
MIN MAX
1 tw(TINPH) Pulse duration, TINP high 8P ns
2 tw(TINPL) Pulse duration, TINP low 8P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Table 4−78. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs†
(see Figure 4−62)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
3 tw(TOUTH) Pulse duration, TOUT high 8P−3 ns
4 tw(TOUTL) Pulse duration, TOUT low 8P−3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
TINPx
TOUTx
4
3
2
1
Figure 4−62. Timer Timing
General-Purpose Input/Output (GPIO)
165
June 2003 − Revised October 2010 SPRS222F
4.18 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or
outputs. When configured as an output, you can write to an internal register to control the state driven on the
output pin. When configured as an input, you can detect the state of the input by reading the state of an internal
register.
In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event
generation modes.
4.18.1 GPIO Device-Specific Information
To use the GP[7:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN = 1 GP[x] pin is enabled
GPxDIR = 0 GP[x] pin is an input
GPxDIR = 1 GP[x] pin is an output
where “x” represents one of the 7 through 0 GPIO pins
Figure 4−63 shows the GPIO enable bits in the GPEN register for the DM641/DM640 device. To use any of
the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1”
(enabled). Default values are device-specific, so refer to Figure 4−63 for the DM641/DM640 default
configuration.
31 24 23 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6543210
Reserved GP7
EN GP6
EN GP5
EN GP4
EN GP3
EN GP2
EN GP1
EN GP0
EN
R/W-0000 0000 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 4−63. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
Figure 4−64 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO
pin is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register.
By default, all the GPIO pins are configured as input pins.
31 24 23 16
Reserved
R-0
15 14 13 12 11 10 9876543210
Reserved GP7
DIR GP6
DIR GP5
DIR GP4
DIR GP3
DIR GP2
DIR GP1
DIR GP0
DIR
R/W-0000 0000 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 4−64. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
General-Purpose Input/Output (GPIO)
166 June 2003 − Revised October 2010SPRS222F
4.18.2 GPIO Peripheral Register Description(s)
Table 4−79. GP0 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B0 0000 GPEN GP0 enable register
01B0 0004 GPDIR GP0 direction register
01B0 0008 GPVAL GP0 value register
01B0 000C − Reserved
01B0 0010 GPDH GP0 delta high register
01B0 0014 GPHM GP0 high mask register
01B0 0018 GPDL GP0 delta low register
01B0 001C GPLM GP0 low mask register
01B0 0020 GPGC GP0 global control register
01B0 0024 GPPOL GP0 interrupt polarity register
01B0 0028 − 01B3 EFFF − Reserved
4.18.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing
Table 4−80. Timing Requirements for GPIO Inputs†‡ (see Figure 4−65)
NO.
−400
−500
−600 UNIT
MIN MAX
1 tw(GPIH) Pulse duration, GPIx high 8P ns
2 tw(GPIL) Pulse duration, GPIx low 8P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
Table 4−81. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs†
(see Figure 4−65)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
3 tw(GPOH) Pulse duration, GPOx high 24P − 8‡ns
4 tw(GPOL) Pulse duration, GPOx low 24P − 8‡ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
‡This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO
is dependent upon internal bus activity.
GPIx
GPOx
4
3
2
1
Figure 4−65. GPIO Port Timing
JTAG
167
June 2003 − Revised October 2010 SPRS222F
4.19 JTAG
The JTAG interface is used for BSDL testing and emulation of the DM641/DM640 device.
4.19.1 JTAG Device-Specific Information
4.19.1.1 IEEE 1149.1 JTAG Compatibility Statement
The TMS320DM641/DM640 DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
resets are required for proper operation.
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a
JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be
released i n order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan
instructions work correctly independent of current state of RESET.
The TMS320DM641/DM640 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However,
some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor
on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and
externally drive TRST high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and
EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode.
For more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the TMS320DM641/DM640 BSDL file contains information and
constraints regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the DM641 and DM640 JTAG emulation, see the TMS320C6000 DSP
Designing for JTAG Emulation Reference Guide (literature number SPRU641).
4.19.1.2 JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
DM641/DM640 device, the JTAG ID register resides at address location 0x01B3 F008. The register hex value
for the DM641/DM640 device is: 0x0007 902F. For the actual register bit names and their associated bit field
descriptions, see Figure 4−66 and Table 4−82.
31−28 27−12 11−1 0
VARIANT (4-Bit) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB
R-0000 R-0000 0000 0111 1001 R-0000 0010 111 R-1
Legend: R = Read only; -n = value after reset
Figure 4−66. JTAG ID Register Description − TMS320DM641/DM640 Register Value − 0x0007 902F
JTAG
168 June 2003 − Revised October 2010SPRS222F
Table 4−82. JTAG ID Register Selection Bit Descriptions
BIT NAME DESCRIPTION
31:28 VARIANT Variant (4-Bit) value. DM641/DM640 value: 0000.
27:12 PART NUMBER Part Number (16-Bit) value. DM641/DM640 value: 0000 0000 0111 1001.
11−1 MANUFACTURER Manufacturer (11-Bit) value. DM641/DM640 value: 0000 0010 111.
0 LSB LSB. This bit is read as a “1” for DM641/DM640.
4.19.2 JTAG Peripheral Register Description(s)
Table 4−83. JTAG ID Register
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
01B3 F008 JTAGID JTAG Identification Register Read-only. Provides 32-bit
JTAG ID of the device.
4.19.3 JTAG Test-Port Electrical Data/Timing
Table 4−84. Timing Requirements for JTAG Test Port (see Figure 4−67)
NO.
−400
−500
−600 UNIT
MIN MAX
1 tc(TCK) Cycle time, TCK 35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns
Table 4−85. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 4−67)
NO. PARAMETER
−400
−500
−600 UNIT
MIN MAX
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 18 ns
TCK
TDO
TDI/TMS/TRST
1
2
34
2
Figure 4−67. JTAG Test-Port Timing
Mechanical Data
169
June 2003 − Revised October 2010 SPRS222F
5 Mechanical Data
The following table(s) show the thermal resistance characteristics for the PBGA − GDK, GNZ, ZDK and ZNZ
mechanical packages.
5.1 Thermal Data
Table 5−1. Thermal Resistance Characteristics (S-PBGA Package) [GDK]
NO °C/W Air Flow (m/s†)
1 RΘJC Junction-to-case 3.3 N/A
2 RΘJB Junction-to-board 7.92 N/A
3 18.2 0.00
4
RΘJA
Junction-to-free air
15.3 0.5
5
R
ΘJA
Junction-to-free air
13.7 1.0
6 12.2 2.00
70.37 0.00
8
PsiJT
Junction-to-package top
0.47 0.5
9
Psi
JT
Junction-to-package top
0.57 1.0
10 0.7 2.00
11 11.4 0.00
12
PsiJB
Junction-to-board
11 0.5
13
Psi
JB
Junction-to-board
10.7 1.0
14 10.2 2.00
†m/s = meters per second
Table 5−2. Thermal Resistance Characteristics (S-PBGA Package) [ZDK]
NO °C/W Air Flow (m/s†)
1 RΘJC Junction-to-case 3.3 N/A
2 RΘJB Junction-to-board 7.92 N/A
3 18.2 0.00
4
RΘJA
Junction-to-free air
15.3 0.5
5
R
ΘJA
Junction-to-free air
13.7 1.0
6 12.2 2.00
70.37 0.00
8
PsiJT
Junction-to-package top
0.47 0.5
9
Psi
JT
Junction-to-package top
0.57 1.0
10 0.7 2.00
11 11.4 0.00
12
PsiJB
Junction-to-board
11 0.5
13
Psi
JB
Junction-to-board
10.7 1.0
14 10.2 2.00
†m/s = meters per second
Mechanical Data
170 June 2003 − Revised October 2010SPRS222F
Table 5−3. Thermal Resistance Characteristics (S-PBGA Package) [GNZ]
NO °C/W Air Flow (m/s†)
1 RΘJC Junction-to-case 3.3 N/A
2 RΘJB Junction-to-board 7.46 N/A
3 17.4 0.00
4
RΘJA
Junction-to-free air
14.0 0.5
5
R
ΘJA
Junction-to-free air
12.3 1.0
6 10.8 2.00
70.37 0.00
8
PsiJT
Junction-to-package top
0.47 0.5
9
Psi
JT
Junction-to-package top
0.57 1.0
10 0.7 2.00
11 11.4 0.00
12
PsiJB
Junction-to-board
11 0.5
13
Psi
JB
Junction-to-board
10.7 1.0
14 10.2 2.00
†m/s = meters per second
Table 5−4. Thermal Resistance Characteristics (S-PBGA Package) [ZNZ]
NO °C/W Air Flow (m/s†)
1 RΘJC Junction-to-case 3.3 N/A
2 RΘJB Junction-to-board 7.46 N/A
3 17.4 0.00
4
RΘJA
Junction-to-free air
14.0 0.5
5
R
ΘJA
Junction-to-free air
12.3 1.0
6 10.8 2.00
70.37 0.00
8
PsiJT
Junction-to-package top
0.47 0.5
9
Psi
JT
Junction-to-package top
0.57 1.0
10 0.7 2.00
11 11.4 0.00
12
PsiJB
Junction-to-board
11 0.5
13
Psi
JB
Junction-to-board
10.7 1.0
14 10.2 2.00
†m/s = meters per second
Mechanical Data
171
June 2003 − Revised October 2010 SPRS222F
The following mechanical package diagram(s) reflect the most up-to-date mechanical data released for these
designated device(s).
PACKAGE OPTION ADDENDUM
www.ti.com 21-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320DM640AGDK4 ACTIVE FC/CSP GDK 548 60 TBD SNPB Level-4-220C-72 HR
TMS320DM640AGNZ4 ACTIVE FCBGA GNZ 548 40 TBD SNPB Level-4-220C-72 HR
TMS320DM640AGNZA4 ACTIVE FCBGA GNZ 548 40 TBD SNPB Level-4-220C-72 HR
TMS320DM640AZDK4 ACTIVE FCBGA ZDK 548 60 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320DM640AZDKA4 ACTIVE FCBGA ZDK 548 60 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320DM640AZNZ4 ACTIVE FCBGA ZNZ 548 40 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320DM640AZNZA4 ACTIVE FCBGA ZNZ 548 40 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320DM640GDK400 OBSOLETE FC/CSP GDK 548 TBD Call TI Call TI
TMS320DM640GNZ400 OBSOLETE FCBGA GNZ 548 TBD Call TI Call TI
TMS320DM640ZDK400 OBSOLETE FCBGA ZDK 548 TBD Call TI Call TI
TMS320DM641AGDK5 ACTIVE FC/CSP GDK 548 60 TBD SNPB Level-4-220C-72 HR
TMS320DM641AGDK6 ACTIVE FC/CSP GDK 548 60 TBD SNPB Level-4-220C-72 HR
TMS320DM641AGNZ5 OBSOLETE FCBGA GNZ 548 TBD Call TI Call TI
TMS320DM641AGNZ6 ACTIVE FCBGA GNZ 548 40 TBD SNPB Level-4-220C-72 HR
TMS320DM641AZDK6 ACTIVE FCBGA ZDK 548 60 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320DM641AZNZ5 ACTIVE FCBGA ZNZ 548 40 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320DM641AZNZ6 ACTIVE FCBGA ZNZ 548 40 Pb-Free (RoHS
Exempt) SNAGCU Level-4-260C-72HR
TMS320DM641GDK500 OBSOLETE FC/CSP GDK 548 TBD Call TI Call TI
TMS320DM641GDK600 OBSOLETE FC/CSP GDK 548 TBD Call TI Call TI
TMS320DM641GNZ500 OBSOLETE FCBGA GNZ 548 TBD Call TI Call TI
TMS320DM641GNZ600 OBSOLETE FCBGA GNZ 548 TBD Call TI Call TI
TMS320DM641ZNZ500 OBSOLETE FCBGA ZNZ 548 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM
www.ti.com 21-Aug-2012
Addendum-Page 2
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MPBG301 – JULY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GDK (S–PBGA–N548) PLASTIC BALL GRID ARRAY
A1 Corner
Bottom View
0,10 0,12
0,80
0,80
SQ
20,90
21,10
AF AE
AD AC
AB AA
YW
VU
TR
PN
ML
KJ
HG
FE
DC
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
31
2,80 MAX
B
2
SQ
23,10
22,90
0,45
0,35
20,00 TYP
0,40
0,40
A
0,45
0,55
Seating Plane
0,50 NOM
4203481-3/B 07/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only .
MPBG314A – OCTOBER 2002 – REVISED DECEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GNZ (S–PBGA–N548) PLASTIC BALL GRID ARRAY
1,00
1,00
0,50
0,50
2321191713 15
AE
AF
AC
AD
AA
AB
W
U
V
Y
11975
P
R
M
N
K
L
H
J
3
F
D
E
1
A
B
C
G
T
25,00 TYP
25262420 22161412 18106842
Seating Plane
0,15
Bottom View
4202595-5\E 12/02
27,20
SQ
26,80
24,80
25,20
A1 Corner
SQ
0,40
0,60
0,70
0,50 0,10
0,50 NOM 2,80 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only.
D. Substrate color may vary.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
