
  
  
SCES622 – JANUARY 2005
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DMember of the Texas Instruments
Widebus+ Family
DHigh-Bandwidth Data Path
(Up to 500 MHz)
D5-V-Tolerant I/Os with Device Powered Up
or Powered Down
DLow and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 5 Typical)
DRail-to-Rail Switching on Data I/O Ports
− 0- to 5-V Switching With 3.3-V VCC
− 0- to 3.3-V Switching With 2.5-V VCC
DBidirectional Data Flow, With Near-Zero
Propagation Delay
DLow Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 4 pF Typical)
DFast Switching Frequency
(fOE = 20 MHz Max)
For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI
application report, CBT-C, CB3T, and CB3Q
Signal-Switch Families, literature number SCDA008.
DData and Control Inputs Provide
Undershoot Clamp Diodes
DLow Power Consumption
(ICC = 2 mA Typical)
DVCC Operating Range From 2.3 V to 3.6 V
DData I/Os Support 0- to 5-V Signaling
Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,
5 V)
DControl Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
DSupports Both Digital and Analog
Applications: PCI Interface, Differential
Signal Interface, Memory Interleaving, Bus
Isolation, Low-Distortion Signal Gating
description/ordering information
The SN74CB3Q32245 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage
of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance
allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. Th e
device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data
bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q32245 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q32245 is organized as four 8-bit bus switches with separate output-enable (1OE, 2OE, 3OE,
4OE) inputs. It can be used as four 8-bit bus switches, two 16-bit bus switches, or as one 32-bit bus switch. When
OE is lo w, the associated 8-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional
data flow between ports. When OE is high, the associated 8-bit bus switch is OFF, and a high-impedance state
exists between the A and B ports.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 85°C
LFBGA − GKE Tape and reel SN74CB3Q32245GKER
BZ245
−40
°
C to 85
°
C
LFBGA − ZKE (Pb-free) Tape and reel SN74CB3Q32245ZKER
BZ245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
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SCES622 – JANUARY 2005
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 8-bit bus switch)
INPUT
INPUT/OUTPUT
FUNCTION
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L B A port = B port
H Z Disconnect
terminal assignments
123456
A1B2 1B1 NC 1OE 1A1 1A2
B1B4 1B3 GND GND 1A3 1A4
C1B6 1B5 VCC VCC 1A5 1A6
D1B8 1B7 GND GND 1A7 1A8
E2B2 2B1 GND GND 2A1 2A2
F2B4 2B3 VCC VCC 2A3 2A4
G2B6 2B5 GND GND 2A5 2A6
H2B7 2B8 NC 2OE 2A8 2A7
J3B2 3B1 NC 3OE 3A1 3A2
K3B4 3B3 GND GND 3A3 3A4
L3B6 3B5 VCC VCC 3A5 3A6
M3B8 3B7 GND GND 3A7 3A8
N4B2 4B1 GND GND 4A1 4A2
P4B4 4B3 VCC VCC 4A3 4A4
R4B6 4B5 GND GND 4A5 4A6
T4B7 4B8 NC 4OE 4A8 4A7
NC − No internal connection
GKE PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
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logic diagram (positive logic)
1A1 SW 1B1
1A8
1OE
SW 1B8
3A1 SW 3B1
3A8
3OE
SW 3B8
A5
D6
A4
J5
M6
J4
A2
D1
J2
M1
2A1 SW 2B1
2A8
2OE
SW 2B8
4A1 SW 4B1
4A8
4OE
SW 4B8
E5
H5
H4
N5
T5
T4
E2
H2
N2
T2
simplified schematic, each FET switch (SW)
A
EN
B
EN is the internal enable signal applied to the switch.
Charge
Pump
VCC
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range, VIN (see Notes 1 and 2) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, IIK (VIN < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port clamp current, II/OK (VI/O < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-state switch current, II/O (see Note 4) ±64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND terminals ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 5) 40°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground, unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
VIH
High-level control input voltage
VCC = 2.3 V to 2.7 V 1.7 5.5
V
VIH High-level control input voltage VCC = 2.7 V to 3.6 V 2 5.5 V
VIL
Low-level control input voltage
VCC = 2.3 V to 2.7 V 0 0.7
V
VIL Low-level control input voltage VCC = 2.7 V to 3.6 V 0 0.8 V
VI/O Data input/output voltage 0 5.5 V
TAOperating free-air temperature −40 85 °C
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIK VCC = 3.6 V, II = −18 mA −1.8 V
IIN Control inputs VCC = 3.6 V, VIN = 0 to 5.5 V ±1µA
IOZVCC = 3.6 V, VO = 0 to 5.5 V,
VI = 0, Switch OFF,
VIN = VCC or GND ±1µA
Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 1µA
ICC VCC = 3.6 V, II/O = 0,
Switch ON or OFF, VIN = VCC or GND 2 4 mA
ICC§Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 30 µA
ICCD
Per control
input
VCC = 3.6 V, A and B ports open,
0.15
0.25
mA/
I
CCD
Per control
input Control input switching at 50% duty cycle
0.15
0.25
MHz
Cin Control inputs VCC = 3.3 V, VIN = 5.5 V, 3.3 V, or 0 3.5 5 pF
Cio(OFF) VCC = 3.3 V, Switch OFF,
VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 4 6 pF
Cio(ON) VCC = 3.3 V, Switch ON,
VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 10 13 pF
VCC = 2.3 V,
VI = 0, IO = 30 mA 6 8
ron#
VCC = 2.3 V,
TYP at VCC = 2.5 V VI = 1.7 V, IO = −15 mA 5 10
r
on
#
VCC = 3 V
VI = 0, IO = 30 mA 6 8
V
CC
= 3 V
VI = 2.4 V, IO = −15 mA 5 9
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
§This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2).
#Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
fOE|| OE A or B 10 20 MHz
tpdkA or B B or A 0.18 0.3 ns
ten OE A or B 1.5 8 1.5 7 ns
tdis OE A or B 1 8 1 7 ns
|| Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL 1 M, CL = 0)
kThe propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).

  
  
SCES622 – JANUARY 2005
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ron− ON−State Resistance −
VI − V
VCC = 3.3 V
TA = 25°C
IO = −15 mA
Figure 1. Typical ron vs VI
0
2
4
6
8
10
12
02468101214161820
OE Switching Frequency − MHz
CC
I − mA
VCC = 3.3 V
TA = 25°C
A and B ports Open
One OE Switching
Figure 2. Typical ICC vs OE Switching Frequency
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  
SCES622 – JANUARY 2005
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
tPLH tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOH
VOL
0 V
VOL + V
VOH − V
0 V
Output
Control
(VIN)
VCC
VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns
.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
50
VG1
V
CC
DUT
50
VIN
50
VG2 50
VI
TEST RL
S1 V
CL
2.5 V ±0.2 V
3.3 V ±0.3 V
VCC VI
tPHZ/tPZH
tPLZ/tPZL
tpd(s)
2.5 V ±0.2 V
3.3 V ±0.3 V
2.5 V ±0.2 V
3.3 V ±0.3 V
Open
Open
2 × VCC
2 × VCC
GND
GND
500
500
500
500
500
500
VCC or GND
VCC or GND
GND
GND
VCC
VCC
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2 VCC/2
VCC/2
VO
Figure 3. Test Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74CB3Q32245GKER NRND LFBGA GKE 96 1000 TBD SNPB Level-2-235C-1 YEAR
SN74CB3Q32245ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS &
no Sb/Br) SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Oct-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74CB3Q32245GKER LFBGA GKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1
SN74CB3Q32245ZKER LFBGA ZKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74CB3Q32245GKER LFBGA GKE 96 1000 333.2 345.9 31.8
SN74CB3Q32245ZKER LFBGA ZKE 96 1000 333.2 345.9 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2011
Pack Materials-Page 2
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