MC56F8145E
Rev. 0, 11/2004
©Freescale Semiconductor, Inc., 2004. All rights reserved.
56F814
5
Freescale Semiconductor
Preliminary Chip Errata
56F8145 Hybrid Controller
This docum ent re port s errata information on chip revis ion C. E rrata numbers ar e in the form n.m, where n
is the number of the errata item and m identifie s the docu me nt rev is ion number. This docu me nt is a pre-
publication draft.
Chip Revision C Errata Information:
The following errata items apply only to Revision C 56F8145 devices. The se par ts are ei ther m arked with
dat e codes of 0437 or greater (bottom line of marking).
Errata
Number Descripti on Impac t and Work Arou nd
1.0 OCCS shutdown function is
restricted to only when the
Loss of Reference interrupt is
active.
Impact:
The RTL code allows the shutdown function to be activated when any OCCS
interrup t, LOLI0, LO LI1 or LOCI is active. CH MPTRI =1 a nd 0xDEAD must
be written to the SHUTDOWN register for all clocks to be stopped.
Work Around:
The OCCS ISR should explicitly check for a loss of reference clock status bit
set prior to shutting down the OCCS.
2.0 Unable to read COP counter
register when th e PLL is not
on.
Impact:
Software does not read the current value of the COP counter register. 0xFFFF
is read as the current value in the count er register.
Work Around:
Read COP coun ter when PLL is in use.
3.0 Command conflict when
setting CCIF in the Flash
Module.
Impact:
If the CCIF is set at the exact same time the CBEIF bit is cleared, only the set
will occur. This gives the impression that a command has complete d when in
fact it is active.
This can only occur on the very last cycle of a pipe line operation.
Work Around:
Use driver software to avoid issue.
4.0 Flash program/errase
operatio ns can cause other
peripheral register access to
be duplicated.
Impact:
This condition can cause issues with the transmit/receive registers and
quadrature de coder hold registers.
Work Around:
Avoid reading or writing to a peripheral register except the Flash Module for 2
CPU cycles prior to writing to a flash memory over its system bus interfa ce.
256F8145 Preliminary Technical Data
5.0 Th e LVI interrupt signal
polarity in STOP mode is
inverted.
Impact:
Same as description
Work Arou nd :
Disabl e the L VI interr upt wh ile in STOP.
6.0 Wait mode operation is
inconsistent in debug mode. Impact:
WAIT appears to work properly when the device is in mission mode. In debug
mode, the WAIT instruction sometimes has no effect.
Work Arou nd :
Test WAIT mode o peratio n outside of the d e bug environment.
7.0 EOnCE registers use the
wrong clock. I/O fails in
presence of holdoffs.
Impact:
Real-time debugging not available. EOnCE reads will fail in the presence of
holdoffs.
Work Ar ou nd :
For EOnCE writes use NOP padding.
No workaround for EOnCE reads in presence of holdoffs.
8.0 Software breakpoint in
uninterruptable code can
cause the debugger to execute
instructions in the wrong
order.
Impact:
Use work around .
For example, a conditional branch followed by two single word instructions
with DBGHALT replaces the first instruction after the cond itio n al bran ch.
Work Ar ou nd :
CodeWarrior has implemented a workaround which utilizes NOP padding.
9.0 The SCI TI DLE fl ag ma y not
be cleared immediat ely upon
transmission of a break
character via the SBK bit of
the SCI control register.
Impact:
This can result in a premature transmitter IDLE interrupt. This only occurs
when using the SBK bit of the SCICR to transmit break characters.
Workaround:
Poll the TIDLE bit of the SCI status register. Do not enable interrupts until
TIDLE goes low. IF polling for TIDLE high, make sure that it is seen going
low first before responding to TIDLE high.
Make sure that T I DLE i s cl eared and then later set after transmitting break
characters.
10.0 The interrupt controller uses
the COP reset vector at
startup if th e COPR b it in the
SIM_RSTSTS register is set,
even if the current reset is not
COP reset.
Impact:
Same as description
Workaround:
Clear the SIM_RSTSTS as part of the startup procedure.
Chip Revision C Errata Information:
The following errata items apply only to Revision C 56F8145 devices. The se parts a re eit her m arked with
date codes of 0437 or greater (bottom line of marking).
Errata
Number Description Impact and Work Around
56F8145 Preliminary Technical Data 3
1 1 .0 The EOnCE OPDBR re gi ster
will not work properly if
there is more than one JTAG
serial ly connected device
used in a scan chain
configurations.
Impact:
This register is used for executing instructions shifted in by the host through
the JTAG when th e d evice is in debu g mode . The inten ded in struction will no t
be execute d un de r this cond itio n.
Note: This does not affect boundary-scan operation, which will still work
properly no matte r what position the device is plac ed in the boundar y-scan
chain.
Workarounds:
1. Each device must be on a separate scan chain for debu gging purposes.
2. If there is only one 56800E device on a scan chain, th en the EOnCE
OPDRB register will work properl y as long as the 56800E device is the first
device on the scan ch ain.
12.0 The CodeWarrior debugger is
not sensitive enough to the
operation frequency of the
devi ce. Memo ry co de may be
corrupted when setting/
clearing.
Impact:
Once the PLL i s engaged, th e device ma y be under erased /programmed when
setting and clearin g brea kp oints.
Workaround:
flash.cfg file should contain the following entry:
set_hf mclkd 0x14
This sets the on-chi p flas h in terface un it to use the maxim u m prog ra m time at
4MHz system rat e. At 40MHz, program/erase times will be less than desi red,
but appear ope ra tio nal un de r oth erwise normal conditions. Use of hardware
breakpoints also eliminates this issue.
13.0 The setting of the CHNCFG
bits in the ADCR1 register
for the mux channels
associated with converter 0
override the settings for the
mux channels associated
with converter 1.
Impact:
This problem effects scans wit h a mix of si ngle ended and differenti al mode
conversions.
If AN0/2-AN1/3 is set for single ended then AN4/6-AN5/7 can't properly
execute differential conversions and vise vers a if AN0 /2-AN1/3 is set for
differential mode AN4/6-AN5/7 can't properly execute single ended
conversions. Settings for differential mode for converter 1 also adversely
effect single en ded conversions in converter 0.
Work Arou nd :
Restrict conversion types so that the cases descri bed do not occur.
14.0 With a Quad Timer counter,
when usin g a s i ng le com p are
register to generate timing
intervals an d clocking the
timer at a rate ot her than at
the IPbus_clock rate the timer
may co unt inc orrectly when
the compare register is
changed.
Impact:
When th e co m pa r e re gis ter matches th e co un te r r e gi ster and is up da te d b e f ore
the next timer clock the co unter increment s/decrement s in stead of reloadi ng.
Work Arou nd :
1. Use both compare registers, such that the compare register that is not active
is updated for use in the next count period.
2. Instead of updating the compare register, architect the software so the
LOAD register can be updated, with the compa r e re gister held constant.
A more in dep th FAQ can be found on the Freescale website. freescale.com
Chip Revision C Errata Information:
The following errata items apply only to Revision C 56F8145 devices. The se parts a re eit her m arked with
date codes of 0437 or greater (bottom line of marking).
Errata
Number Description Impact and Work Around
Freescale™ and the Free scale logo are trademar ks of Freescal e Semiconductor, Inc.
All other product or service names are the property of their respective owners. This
product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2004
MC56F8145E
Rev. 0
11/2004
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and
software imp lementers to use Free scale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Sem iconductor reser ves the right t o make changes w ithout further
notice to any product s h erein. F reescale Semico nductor m akes no w arra nty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising o ut of the appli catio n or use of an y pr oduct or circui t, a nd sp ecific ally
disclaims any and all liability, including without limitation consequential or
incident al damages. “T yp ical” p aramet ers that ma y be provide d in Free scale
Semiconducto r data sheet s and/or specifica tions can and do vary i n different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical exper ts. Fre escale S em iconduct or d oes
not convey any license under its patent rights nor the rights of others.
Freescale S emiconductor product s are not designe d, intended, or au thorized
for use as component s in systems intended for surgical implant into the body ,
or other applications intended to support or sustain life, or for any other
application i n which the failure of the Free scale Semiconductor produ ct could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconduc tor product s for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors h armless ag ainst all claims , costs, damages, and expenses, and
reasonable atto rney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, ev en if su ch clai m a lleges that Fr eescal e Semico nductor was negligent
regarding the design or manufacture of the part.
