Freescale Semiconductor MC56F8145E Rev. 0, 11/2004 56F8145 Preliminary Chip Errata 56F8145 Hybrid Controller This document reports errata information on chip revision C. Errata numbers are in the form n.m, where n is the number of the errata item and m identifies the document revision number. This document is a prepublication draft. Chip Revision C Errata Information: The following errata items apply only to Revision C 56F8145 devices. These parts are either marked with date codes of 0437 or greater (bottom line of marking). Errata Number 1.0 Description Impact and Work Around OCCS shutdown function is restricted to only when the Loss of Reference interrupt is active. Impact: The RTL code allows the shutdown function to be activated when any OCCS interrupt, LOLI0, LOLI1 or LOCI is active. CHMPTRI =1 and 0xDEAD must be written to the SHUTDOWN register for all clocks to be stopped. Work Around: The OCCS ISR should explicitly check for a loss of reference clock status bit set prior to shutting down the OCCS. 2.0 Unable to read COP counter register when the PLL is not on. Impact: Software does not read the current value of the COP counter register. 0xFFFF is read as the current value in the counter register. Work Around: Read COP counter when PLL is in use. 3.0 Command conflict when setting CCIF in the Flash Module. Impact: If the CCIF is set at the exact same time the CBEIF bit is cleared, only the set will occur. This gives the impression that a command has completed when in fact it is active. This can only occur on the very last cycle of a pipeline operation. Work Around: Use driver software to avoid issue. 4.0 Flash program/errase operations can cause other peripheral register access to be duplicated. Impact: This condition can cause issues with the transmit/receive registers and quadrature decoder hold registers. Work Around: Avoid reading or writing to a peripheral register except the Flash Module for 2 CPU cycles prior to writing to a flash memory over its system bus interface. (c)Freescale Semiconductor, Inc., 2004. All rights reserved. Chip Revision C Errata Information: The following errata items apply only to Revision C 56F8145 devices. These parts are either marked with date codes of 0437 or greater (bottom line of marking). Errata Number 5.0 Description The LVI interrupt signal polarity in STOP mode is inverted. Impact and Work Around Impact: Same as description Work Around: Disable the LVI interrupt while in STOP. 6.0 Wait mode operation is inconsistent in debug mode. Impact: WAIT appears to work properly when the device is in mission mode. In debug mode, the WAIT instruction sometimes has no effect. Work Around: Test WAIT mode operation outside of the debug environment. 7.0 EOnCE registers use the wrong clock. I/O fails in presence of holdoffs. Impact: Real-time debugging not available. EOnCE reads will fail in the presence of holdoffs. Work Around: For EOnCE writes use NOP padding. No workaround for EOnCE reads in presence of holdoffs. 8.0 Software breakpoint in uninterruptable code can cause the debugger to execute instructions in the wrong order. Impact: Use work around. For example, a conditional branch followed by two single word instructions with DBGHALT replaces the first instruction after the conditional branch. Work Around: CodeWarrior has implemented a workaround which utilizes NOP padding. 9.0 10.0 2 The SCI TIDLE flag may not be cleared immediately upon transmission of a break character via the SBK bit of the SCI control register. The interrupt controller uses the COP reset vector at startup if the COPR bit in the SIM_RSTSTS register is set, even if the current reset is not COP reset. Impact: This can result in a premature transmitter IDLE interrupt. This only occurs when using the SBK bit of the SCICR to transmit break characters. Workaround: Poll the TIDLE bit of the SCI status register. Do not enable interrupts until TIDLE goes low. IF polling for TIDLE high, make sure that it is seen going low first before responding to TIDLE high. Make sure that TIDLE is cleared and then later set after transmitting break characters. Impact: Same as description Workaround: Clear the SIM_RSTSTS as part of the startup procedure. 56F8145 Preliminary Technical Data Chip Revision C Errata Information: The following errata items apply only to Revision C 56F8145 devices. These parts are either marked with date codes of 0437 or greater (bottom line of marking). Errata Number 11.0 Description Impact and Work Around The EOnCE OPDBR register will not work properly if there is more than one JTAG serially connected device used in a scan chain configurations. Impact: This register is used for executing instructions shifted in by the host through the JTAG when the device is in debug mode. The intended instruction will not be executed under this condition. Note: This does not affect boundary-scan operation, which will still work properly no matter what position the device is placed in the boundary-scan chain. Workarounds: 1. Each device must be on a separate scan chain for debugging purposes. 2. If there is only one 56800E device on a scan chain, then the EOnCE OPDRB register will work properly as long as the 56800E device is the first device on the scan chain. 12.0 The CodeWarrior debugger is not sensitive enough to the operation frequency of the device. Memory code may be corrupted when setting/ clearing. Impact: Once the PLL is engaged, the device may be under erased/programmed when setting and clearing breakpoints. Workaround: flash.cfg file should contain the following entry: set_hfmclkd 0x14 This sets the on-chip flash interface unit to use the maximum program time at 4MHz system rate. At 40MHz, program/erase times will be less than desired, but appear operational under otherwise normal conditions. Use of hardware breakpoints also eliminates this issue. 13.0 The setting of the CHNCFG bits in the ADCR1 register for the mux channels associated with converter 0 override the settings for the mux channels associated with converter 1. Impact: This problem effects scans with a mix of single ended and differential mode conversions. If AN0/2-AN1/3 is set for single ended then AN4/6-AN5/7 can't properly execute differential conversions and vise versa if AN0/2-AN1/3 is set for differential mode AN4/6-AN5/7 can't properly execute single ended conversions. Settings for differential mode for converter 1 also adversely effect single ended conversions in converter 0. Work Around: Restrict conversion types so that the cases described do not occur. 14.0 With a Quad Timer counter, when using a single compare register to generate timing intervals and clocking the timer at a rate other than at the IPbus_clock rate the timer may count incorrectly when the compare register is changed. Impact: When the compare register matches the counter register and is updated before the next timer clock the counter increments/decrements instead of reloading. Work Around: 1. Use both compare registers, such that the compare register that is not active is updated for use in the next count period. 2. Instead of updating the compare register, architect the software so the LOAD register can be updated, with the compare register held constant. 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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc. 2004 MC56F8145E Rev. 0 11/2004