PRELIMINARY
UltraLogicTM 32-Macrocell ISRTM CPLD
CY37032V
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA95134 • 408-943-2600
January 5, 1999
5
6V
Features
• 32 macrocells in two logic blocks
• 3.3V In-S ystem Reprogrammable™ (ISR™)
—JTAG-complian t on-boar d programm ing
—Design changes don’t cause pinout changes
—Design changes don’t cause t iming changes
• IEEE standard 3.3V operation
—3.3V ISR
—5V tolerant
• Up to 32 I/Os
—plus 5 dedicated inputs including 4 clock inputs
• High speed
—fMAX = 143 MHz
—tPD = 8.5 ns
—tS = 5.0 ns
—tCO = 6 .0 ns
• Product- term clocking
• IEEE 1149.1 JTAG bounda ry scan
• Programmable slew rate control on individual I/Os
• Low power option on individual log ic bl ock basis
• User-Programmable Bus Hold capabilities on all I/Os
• Si mple Timing Model
• PCI compliant[1]
• Availabl e in 44-pin TQ FP, 44-pin PLCC
• Pinout compatible with the CY37032, CY37064/37064V
Selection G uide CY37032V-143 CY37032V-100
Max imum Propagation Delay, tPD (ns ) 8 .5 12
Minimum Set-Up, tS (n s) 5 .0 7.0
Maximum Clock to Output, tCO (ns) 6.0 6.5
Typical Supply Current, ICC (mA) in Low Power Mode 15 15
Note:
1. Due to the 5V tolerant nature of the I/Os, the I/Os are not clamped to VCC.
Logic Block Dia gram
LOGIC
BLOCK
B
LOGIC
BLOCK
A
36
16
36
16
Input Clock/Input
16 I/Os 16 I/Os
I/O0−I/O15 I/O16−I/O31
4
4
4
16
16
TDI
TCLK
TMS TDO
JTAG Tap
Controller
1
37032V-1
PIM
37032V-2
I/O27/TDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
I/O23
I/O22
I/O21
I/O5/TCLK
I/O6
I/O7
JTAGEN
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
GND
I/O20
I/O2
GND
VCC
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
65 34 2
8
9
7
10
11
144
18
15
16
14
13
12
17 19 20 2221 23 24 2726 2825
31
30
29
32
33
34
39
37
38
36
35
43 42 4041
I/O2
GND
VCC
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O27/TDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
I/O23
I/O22
I/O21
GND
I/O20
VCC
I/O18
I/O17
I/O16
I/O15
I/O14
I/O12
I/O5/TCLK
I/O6
I/O7
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
8
9
7
10
11
3
4
2
5
6
1
18 19 20 222113 14 15 171612
31
30
29
32
33
26
25
24
27
28
23
44 43 42 4041 39 38 37 3536 34
37032V–3
44-pin PLCC
Top View 44-pin TQFP
Top View
/TMS
/TDO
I/O13/TMS
I/O19/TDO
JTAGEN
Pin Configurations
CLK2/I0
CLK3/I2CLK3/I2
CLK2/I0
VCC
CY37032V
PRELIMINARY
2
Functional Description
The CY37032 V is a n In-Sys tem Reprog ram mable (ISR) Com-
plex Programmable Logic Device (CPLD) and is part of the
Ultra37000™ family of high-density, high-speed CPLDs. Li ke
all members of the Ultra37000 family, the CY37032V is de-
signed to bring the ease of use and high perfor mance of the
22V10 to high-density PLDs.
The CY37032V is rich in I/O resources. Each macrocell in the
device features an associated I/O pin, resul ting in 32 I/O pins
on the CY37032V.
For a more detailed description of the architecture and fea-
tures of the CY3 7032V see the Ultra37000 family data sheet .
Fully Routable with 100% Logic Utili zation
The CY37032V is designed with a robust routing architecture
which allows utili zation of the ent ire de vice wi th a fixed pi nout.
This mak es Ul tra3 7000 optimal f o r impl ement ing on -boa rd de-
sign changes using ISR without changing pinouts.
Simple Timing Model
The CY37032V features a very simple tim ing m odel with pre-
dict able dela ys. Unlike other high-densi ty CPLD architec tures ,
ther e are no hidden spe ed dela ys such as f anout eff ects, inte r-
connect delays, or expander delays. The timing model allows
for design changes with I SR without causing changes to sys-
tem performance.
Low-Power Operation
Each Logic Block of the CY37032V can be configured as either
High-Speed (default) or Low-Power. In the Low-Power mode,
the logic bl ock consumes approximately 50% less power and
slows down by tLP
.
Output Slew Rate Cont rol
Each output can be configured with either a fast edge rate
(default ) for high perfor mance, or a slow edge rate for added
noise reduction. In the fast edge rate mode, outputs switch at
3V/ns m ax. and in the slow edge rate mode, out puts switch a t
1V/ns max. There is a nominal delay for I/Os using the slow
edge rate mode.
In-System Reprogramming
The CY37032V can be programmed in system using IEEE
1149.1 compliant JTAG programming protocol. The
CY37032V ca n also be prog rammed on a nu mber of tr aditional
parallel programmers including Cypress’s
Impulse3
pro-
grammer and industry standard thi rd-party programmers. For
an ov erview of ISR prog ramming, refer to the Ult ra37000 F am-
ily data sheet and for UltraISR cable and software specifica-
tions, refer to InSRkit: ISR Programming data sheet
(CY3600i).
User-Programm able Bus Hold
All out puts of the CY37032 V can either be conf igure d into b us
hold mode or l eft floating. Wh en in b us hold mode, t he undriv-
en outpu ts retai n their last value with a wea k latch. This f eature
allo ws the design er the flexibility of eith er eliminating or includ -
ing external pull-up/pull-down resistors. Enabling this feature
affects all I/Os si multaneously.
Design Tools
Development soft w are f or t he CY37032V is av ai lab le fr om Cy-
pre ss’s
Warp
or t hird- party bol t-i n sof tw are pa c kages as w ell
as a numbe r of third-party de velopment packages. Please re-
fer to the
Warp
or third- par ty tool suppor t data sheet s for fur-
ther informatio n .
CY37032V
PRELIMINARY
3
Maximum Ratings
(Above whi ch the useful lif e may be impair ed. For user guide-
li nes, not tested.)
Sto ra g e Tempe ra tu r e ......... .... ..... ........ ..... ..– 6 5 °C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage .............. ..... ............ ..... ........–0.5V to +7.0V
DC Program Voltage...........................................3.0V to 3.6V
Current into Outputs...................................................... 8 mA
Static Discharge Voltage ..... ...... .. ................... .. ...... .. .>2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current.. ........................ ........................ ...>200 mA
Notes:
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 family devices see the Ultra37000 family data sheet.
3. IOH = –2 mA, IOL = 2 mA for TDO.
4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
5. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect these parameters.
Operating Range[2]
Range Ambient
Temperature[2] Junction
Temperature VCC
Commercial 0°C to +70°C 0°C to +90°C 3.3V ± 0.3V
Industrial –40°C to +85°C –40°C to +125°C 3.3V ± 0.3V
Electrica l Characte ristics Over the Oper ati ng Rang e
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = –4 mA (Co m’l)[3] 2.4 V
VOL Output LOW Voltage VCC = Min. IOL = 8 mA (Com’l)[3] 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage for
all inputs[4] 2.0 VCCmax V
VIL Input LOW Voltage Guaranteed Inp ut Logic al LOW v oltage f or
all inputs[4] –0.5 0.8 V
IIX Input Load Curren t VI = GND OR VCC –10 10 µA
IOZ Out put Leakage Curr ent VO = GND or VCC, Output Disabled –50 50 µA
IOS Out put Short Circuit Curr ent[5, 6] VCC = Max., VOUT = 0.5V –30 –160 mA
IBHL Input Bus Hold LOW Sustaining
Current VCC = Min., VIL = 0.8V +75 µA
IBHH Input Bus Hold HIGH Sustai ning
Current VCC = Min., VIH = 2.0V –75 µA
IBHLO Input Bus Hold LOW Overdrive
Current VCC = Max. +500 µA
IBHHO Input Bus Hold HIGH Over drive
Current VCC = Max. –500 µA
Inductance[6]
Parameter Description Test Conditi ons 44-lead TQFP 44-lead PLCC Unit
LMaxi mum Pin Inductance VIN = 3.3V at f = 1 MHz 2 5 nH
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CI/O Input/Ou tput Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C 8pF
CCLK Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25°C12 pF
CY37032V
PRELIMINARY
4
Note:
7. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Endurance Chara cteristics [6]
Parameter Description Test Conditions Min. Typ. Unit
NMinimum Reprogramming Cycles Normal Programming Condi tions[2] 1,000 10,000 Cycles
AC Te st Loads and Waveform s
37032V-5
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2 ns
OUTPUT
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
236Ω(MIL)
99Ω(COM'L)
136Ω(MIL)
Equivalent to: THÉVENIN EQUIVALENT
2.08V (COM 'L)
2.13V (MI L)
238Ω(COM'L)
319Ω(MIL)
170Ω(COM'L)
236Ω(MIL) <2 ns
(c)
5 OR 35 p F
37032V-4
37032V-7
37032V-6
Parameter[7] VXOutput W aveform−Measurem ent Level
tER(–) 1.5V
tER(+) 2.6V
tEA(+) 1.5V
tEA(–) Vthe
(d) Test Waveforms
VOH VX
0.5V 37032V-8
VOL VX
0.5V
37032V-9
VXVOH
0.5V
37032V-10
VXVOL
0.5V 37032V-11
CY37032V
PRELIMINARY
5
Swi tch ing C h ara cter i sti cs Over the Operat ing Range[8]
37032V-143 37032V-100
Parameter Description Min. Max. Min. Max. Unit
Co mb in a tor ia l M o d e Para m e te rs
tPD[9 , 1 0] Input to Combinatorial Output 8.5 12 ns
tPDL[9, 10] Input to Output Thr ough Tr ansparent Input or Out put Latch 12 16.5 ns
tPDLL[9, 10] Input to Output Through Transparent Input and Output
Latches 13.5 17 ns
tEA[9, 10] Input to Output Enable 13 16 ns
tER[9] Input to Output Disable 13 16 ns
Input Register Parameters
tWL Clock or Latch Enabl e Input LOW Time[6] 2.5 3ns
tWH Clock or Latch Enable Input HIGH Time[6] 2.5 3ns
tIS Input Register or Latch Set-Up Time 2 2.5 ns
tIH Input Register or Latch Hold Time 2 2.5 ns
tICO[9, 10 ] Input Register Clock or Latch Enable to Combinatorial
Output 12.5 16 ns
tICOL[9, 10] Input Regi ster Clock or Latch Enable to Output Through
Transparent Output Latch 14 18 ns
Synchronous Clocking Param eters
tCO[10] Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch
Enable to Output 6 6 ns
tS[9] Set-Up Time from Inp ut t o Synchronous Clock (CLK0,
CLK1, C L K 2, or CLK3) or Latc h En able 57ns
tHRegister or Latch Data Hold Time 0 0ns
tCO2[9, 10] Output Sync hron ous Cloc k (CLK 0, C LK1, CL K 2, or CLK3)
or Latch Enable to Combinatorial Output Delay (Thr ough
Logic Arr ay)
12 16 ns
tSCS[9] Outpu t Synchron ous Cloc k (CLK 0, CLK1, CLK 2, o r CLK3)
or Latch Enable to Output Synchr onous Clock (CLK0,
CLK1, C L K 2, or CLK3) or Latch Enable (Through Logic
Array)
710 ns
tSL[9] Set-Up Time from Input Through Transparent Latch to Out-
put Register Synchronous Clock (CLK0, CL K 1, CLK 2, o r
CLK3) or Latch Enable
912 ns
tHL Hold Time for Input Through Transparent Latch from Out-
put Register Synchronous Clock (CLK0, CL K 1, CLK 2, o r
CLK3) or Latch Enable
00ns
Product Term Cloc king Parameter s
tCOPT[9 , 10 ] Product Term Clock or Latch Enable (PTCLK) to Output 13 13 ns
tSPT Set-Up Time f rom Input to Product Term Clock or Latch
Enable (PTCLK) 3 3 ns
tHPT Register or Lat ch Data Hold Time 3 3ns
tCO2PT[9, 10] Product Term Clock or Latch Enable (PTCLK) to Output
Delay (Through Logic Ar ray) 19 21 ns
Notes:
8. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
9. Logic Blocks operating in low power mode , add tLP to this spec.
10. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
CY37032V
PRELIMINARY
6
Pipelined Mode Parameters
tICS[9] Input Regist er Sy nchr onous Cl oc k ( CLK 0, CLK1, CLK2, or
CLK3) to Output Register Synchronous Clock (CLK0,
CLK1, C L K 2, or CLK3)
710 ns
Operating Frequency Parameters
fMAX1 Maxi m um Frequency with Inte rnal Feedbac k
(Lesser of 1/tSCS, 1/(t S + tH), or 1/tCO)[6] 143 100 MHz
fMAX2 Maximum Frequency Data Path in Output Regis-
tered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH),
or 1/t CO)
167 143 MHz
fMAX3 Maxi m um Frequency with External Feedback
(Lesser of 1/(tCO + tS) or 1/(tWL + tWH)) 91 80 MHz
fMAX4 Maxi m um Frequen cy in Pip eli ned Mode (Lesser of 1/(t CO
+ tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS)125 100 MHz
Reset/Preset Parameters
tRW Async hronous Reset Width[6] 812 ns
tRR[9] Asynchronous Reset Recovery Time[6] 10 14 ns
tRO[9, 10] Asynchronous Reset to Output 14 18 ns
tPW Async hronous Preset Wi dth[6] 812 ns
tPR[9] Asynchronous Preset Recovery Time[6] 10 14 ns
tPO[9, 10] Asynchronous Pre set to Outpu t 14 18 ns
User O p tion Para meters
tLP Low Power Adder 4 4ns
tSLEW Slow Output Sle w Rate Adder 2 2ns
JTAG Timing Parameters
tS JTA G Se t -U p tim e fro m T D I and TMS to TCK 0 0ns
tH JTAG Hold Time on TDI and TMS 20 20 ns
tCO JTAG Falling Edge of TCK to TDO 20 20 ns
fJTAG Maxi m um JTAG Tap Controller Frequency 20 20 MHz
Swi tch ing C h ara cter i sti cs Over the Operat ing Range[8] (cont inued)
37032V-143 37032V-100
Parameter Description Min. Max. Min. Max. Unit
CY37032V
PRELIMINARY
7
Typ i cal I cc Ch ara cter i sti cs
0
5
10
15
20
25
30
0 20406080100120140160
Freq uency (MH z)
Icc (mA)
Low Powe r
High S peed
The typical pattern is a 16 bit up counter, per logic block, with outputs disabled.
Vcc = 3.3V, TA = Room Temperature
CY37032V
PRELIMINARY
8
Swi tch ing Waveforms
tPD
37032V-12
INPUT
COMBINATORIAL
OUTPUT
Combinatorial Output
Registered Output with Synchronous Clocking
tS
37032V-13
INPUT
SYNCHRONOUS
tCO
REGISTERED
OUTPUT
tH
SYNCHRONOUS
tWL
tWH
tCO2
REGISTERED
OUTPUT
CLOCK
CLOCK
Registered Output with Produ ct Term Clocki ng
tSPT
37032V-14
INPUT
PRODUCT TERM
tCOPT
REGISTERED
OUTPUT
tHPT
PRODUCT TERM
tWL
tWH
CLOCK
CLOCK
Input Going Through the Array
CY37032V
PRELIMINARY
9
Swi tch ing Waveforms (continued)
Registered Output with Produ ct Term Clocking
tISPT
37032V-15
INPUT
PRODUCT TERM
tCO2PT
REGISTERED
OUTPUT
tIHPT
PRODUCT TERM
tWL
tWH
CLOCK
CLOCK
Input Coming From Adjacent Buried Register
Latched Output
tSL
37032V-16
INPUT
LATCH ENABLE
tCO
LATCHED
OUTPUT
tHL
tPDL
Registered Input
tIS
37032V-17
REGISTERED
INPUT
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tIH
CLOCK
tWL
tWH
CY37032V
PRELIMINARY
10
Swi tch ing Waveforms (continued)
Clock to Clock
37032V-18
INPUT REGISTER
CLOCK
OUTPUT
REGISTER CLOCK
tSCS
tICS
Latched Input
tIS
37032V-19
LATCHED INPUT
LATCH ENABLE
tICO
COMBINATORIAL
OUTPUT
tIH
tPDL
tWL
tWH
LATCH ENABLE
Latched Input and Output
tICS
37032V-20
LATCHED INPUT
OUTPUT LATCH
ENABLE
LATCHED
OUTPUT
tPDLL
LATCH ENABLE
tWL
tWH
tICOL
INPUT LATCH
ENABLE
tSL tHL
CY37032V
PRELIMINARY
11
Swi tch ing Waveforms (continued)
Asynchronous Reset
37032V-21
INPUT
tRO
REGISTERED
OUTPUT
CLOCK
tRR
tRW
Asynchronous Preset
37032V-22
INPUT
tPO
REGISTERED
OUTPUT
CLOCK
tPR
tPW
OutputEnable/Disable
37032V–23
INPUT
tER
OUTPUTS
tEA
CY37032V
PRELIMINARY
12
In-System Reprogrammable, ISR, UltraLogic, Ultra37000, InSRkit,
Warp
, and
Impulse3
are trademarks of Cypress Semiconductor
Corporation.
Warp2
and
Warp3
are registered trademarks of Cypress Semiconductor Corporation.
Document #: 38−00713-A
Orde ring Information
Speed
(MHz) Ordering Code Package
Name P ackage Type Operating
Range
143 CY37032VP44-143AC A44 44-Pin Thin Quad Flatpack Commercial
CY37032VP44-143JC J67 44-Pin Plastic Leaded Chip Carrier
100 CY37032VP44-100AC A44 44-Pin Thin Quad Flatpack Commercial
CY37032VP44-100JC J67 44-Pin Plastic Leaded Chip Carrier
CY37032VP44-100AI A44 44-Pin Thin Quad Flatpack Industrial
CY37032VP44-100JI J67 44-Pin Plast ic Leaded Chip Carrier
Package Diagra m s
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-B
CY37032V
PRELIMINARY
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconductor pr oduct. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to res ult in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all c harges.
Package Diagra m s (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-A
