56V PRELIMINARY CY37032V UltraLogicTM 32-Macrocell ISRTM CPLD -- tPD = 8.5 ns Features -- tS = 5.0 ns * 32 macrocells in two logic blocks * 3.3V In-System ReprogrammableTM (ISRTM) -- JTAG-compliant on-board programming * * * * * * * * * -- Design changes don't cause pinout changes -- Design changes don't cause timing changes * IEEE standard 3.3V operation -- 3.3V ISR -- 5V tolerant * Up to 32 I/Os -- plus 5 dedicated inputs including 4 clock inputs * High speed -- fMAX = 143 MHz Input Logic Block Diagram 1 -- tCO = 6.0 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis User-Programmable Bus Hold capabilities on all I/Os Simple Timing Model PCI compliant[1] Available in 44-pin TQFP, 44-pin PLCC Pinout compatible with the CY37032, CY37064/37064V Clock/Input 4 TDI TCLK TMS 36 LOGIC BLOCK A 36 PIM 16 LOGIC BLOCK B 16 16 37032V-1 16 I/O27 /TDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I 2 I/O23 I/O22 I/O21 I/O5 /TCLK I/O6 I/O7 CLK2/I 0 JTAGEN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 I/O28 I/O29 I/O31 I/O30 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 I/O27 /TDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I 2 I/O23 I/O22 I/O21 37032V-3 I/O12 I/O13 /TMS I/O14 I/O15 V CC GND I/O16 I/O17 I/O18 I/O19 /TDO I/O20 GND I/O16 I/O17 I/O18 37032V-2 44 43 42 41 40 39 38 37 36 35 34 33 32 2 3 31 4 30 5 29 6 28 27 7 1 I/O19 /TDO I/O20 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O /TMS 13 I/O14 I/O15 VCC 7 8 9 10 11 12 13 14 15 16 17 I/O2 I/O4 I/O3 I/O28 I/O29 44-pin TQFP Top View I/O31 I/O30 I/O 1 I/O 0 GND VCC I/O 2 I/O 4 I/O 3 44-pin PLCC Top View 6 5 4 3 2 1 44 43 42 41 40 I/O5 /TCLK I/O6 I/O7 CLK2 /I 0 JTAGEN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 16 I/Os I/O16-I/O31 I/O1 I/O0 GND VCC Pin Configurations TDO 4 4 16 I/Os I/O0-I/O15 JTAG Tap Controller Selection Guide CY37032V-143 CY37032V-100 Maximum Propagation Delay, tPD (ns) 8.5 12 Minimum Set-Up, tS (ns) 5.0 7.0 Maximum Clock to Output, tCO (ns) Typical Supply Current, ICC (mA) in Low Power Mode 6.0 6.5 15 15 Note: 1. Due to the 5V tolerant nature of the I/Os, the I/Os are not clamped to VCC. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA95134 * 408-943-2600 January 5, 1999 PRELIMINARY CY37032V Functional Description Output Slew Rate Control The CY37032V is an In-System Reprogrammable (ISR) Complex Programmable Logic Device (CPLD) and is part of the Ultra37000TM family of high-density, high-speed CPLDs. Like all members of the Ultra37000 family, the CY37032V is designed to bring the ease of use and high performance of the 22V10 to high-density PLDs. Each output can be configured with either a fast edge rate (default) for high performance, or a slow edge rate for added noise reduction. In the fast edge rate mode, outputs switch at 3V/ns max. and in the slow edge rate mode, outputs switch at 1V/ns max. There is a nominal delay for I/Os using the slow edge rate mode. The CY37032V is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY37032V. In-System Reprogramming The CY37032V can be programmed in system using IEEE 1149.1 compliant JTAG programming protocol. The CY37032V can also be programmed on a number of traditional parallel programmers including Cypress's Impulse3 programmer and industry standard third-party programmers. For an overview of ISR programming, refer to the Ultra37000 Family data sheet and for UltraISR cable and software specifications, refer to InSRkit: ISR Programming data sheet (CY3600i). For a more detailed description of the architecture and features of the CY37032V see the Ultra37000 family data sheet. Fully Routable with 100% Logic Utilization The CY37032V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout. This makes Ultra37000 optimal for implementing on-board design changes using ISR without changing pinouts. User-Programmable Bus Hold Simple Timing Model All outputs of the CY37032V can either be configured into bus hold mode or left floating. When in bus hold mode, the undriven outputs retain their last value with a weak latch. This feature allows the designer the flexibility of either eliminating or including external pull-up/pull-down resistors. Enabling this feature affects all I/Os simultaneously. The CY37032V features a very simple timing model with predictable delays. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. The timing model allows for design changes with ISR without causing changes to system performance. Design Tools Low-Power Operation Development software for the CY37032V is available from Cypress's Warp or third-party bolt-in software packages as well as a number of third-party development packages. Please refer to the Warp or third-party tool support data sheets for further information. Each Logic Block of the CY37032V can be configured as either High-Speed (default) or Low-Power. In the Low-Power mode, the logic block consumes approximately 50% less power and slows down by tLP. 2 PRELIMINARY CY37032V Maximum Ratings DC Voltage Applied to Outputs in High Z State................................................-0.5V to +7.0V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage ............................................-0.5V to +7.0V DC Program Voltage........................................... 3.0V to 3.6V Storage Temperature ................................. -65C to +150C Current into Outputs ...................................................... 8 mA Ambient Temperature with Power Applied ............................................. -55C to +125C Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Supply Voltage to Ground Potential ............... -0.5V to +4.6V Latch-Up Current..................................................... >200 mA Operating Range[2] Range Commercial Industrial Ambient Temperature[2] Junction Temperature VCC 0C to +70C 0C to +90C 3.3V 0.3V -40C to +85C -40C to +125C 3.3V 0.3V Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage Test Conditions Min. [3] VCC = Min. IOH = -4 mA (Com'l) [3] IOL = 8 mA (Com'l) Max. Unit 2.4 V VOL Output LOW Voltage VCC = Min. 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage for all inputs[4] 2.0 VCCmax V VIL Input LOW Voltage Guaranteed Input Logical LOW voltage for all inputs[4] -0.5 0.8 V IIX Input Load Current VI = GND OR VCC -10 10 A IOZ Output Leakage Current VO = GND or VCC, Output Disabled -50 50 A IOS Output Short Circuit Current[5, 6] -30 -160 mA IBHL Input Bus Hold LOW Sustaining Current VCC = Max., VOUT = 0.5V VCC = Min., VIL = 0.8V +75 A IBHH Input Bus Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V -75 A IBHLO Input Bus Hold LOW Overdrive Current VCC = Max. +500 A IBHHO Input Bus Hold HIGH Overdrive Current VCC = Max. -500 A Inductance[6] Parameter L Description Maximum Pin Inductance Test Conditions 44-lead TQFP 44-lead PLCC Unit 2 5 nH VIN = 3.3V at f = 1 MHz Capacitance[6] Max. Unit CI/O Parameter Input/Output Capacitance Description VIN = 3.3V at f = 1 MHz at TA = 25C Test Conditions 8 pF CCLK Clock Signal Capacitance VIN = 3.3V at f = 1 MHz at TA = 25C 12 pF Notes: 2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 family devices see the Ultra37000 family data sheet. 3. IOH = -2 mA, IOL = 2 mA for TDO. 4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 5. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. 3 PRELIMINARY CY37032V Endurance Characteristics[6] Parameter N Description Test Conditions [2] Minimum Reprogramming Cycles Normal Programming Conditions Min. Typ. Unit 1,000 10,000 Cycles AC Test Loads and Waveforms 238 (COM'L) 319 (MIL) 238 (COM'L) 319 (MIL) 5V 5V OUTPUT 170 (COM'L) 236 (MIL) 35 pF (a) 90% OUTPUT 170 (COM'L) GND 236 (MIL) <2 ns 5 pF INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE 37032V-4 ALL INPUT PULSES 3.0V (b) THEVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V (COM'L) OUTPUT 2.13V (MIL) 5 OR 35 pF 37032V-7 VX tER(-) 1.5V Output Waveform-Measurement Level VOH 0.5V VX 37032V-8 tER(+) 2.6V VOL VX 0.5V 37032V-9 tEA(+) 1.5V VX VOH 0.5V 37032V-10 tEA(-) Vthe VX 0.5V VOL 37032V-11 (d) Test Waveforms Note: 7. tER measured with 5-pF AC Test Load and t EA measured with 35-pF AC Test Load. 4 10% <2 ns (c) 37032V-5 Equivalent to: Parameter[7] 90% 10% 37032V-6 PRELIMINARY CY37032V Switching Characteristics Over the Operating Range[8] 37032V-143 Parameter Description Min. Max. 37032V-100 Min. Max. Unit Combinatorial Mode Parameters tPD[9, 10] tPDL [9, 10] tPDLL [9, 10] Input to Combinatorial Output 8.5 12 ns Input to Output Through Transparent Input or Output Latch 12 16.5 ns 13.5 17 ns Input to Output Through Transparent Input and Output Latches tEA[9, 10] Input to Output Enable 13 16 ns [9] Input to Output Disable 13 16 ns tER Input Register Parameters Clock or Latch Enable Input LOW Time[6] tWL [6] 2.5 3 ns 2.5 3 ns tWH Clock or Latch Enable Input HIGH Time tIS Input Register or Latch Set-Up Time 2 2.5 ns tIH Input Register or Latch Hold Time 2 2.5 ns tICO[9, 10] Input Register Clock or Latch Enable to Combinatorial Output tICOL[9, 10] Input Register Clock or Latch Enable to Output Through Transparent Output Latch 12.5 16 ns 14 18 ns 6 6 ns Synchronous Clocking Parameters tCO[10] Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output tS[9] Set-Up Time from Input to Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable 5 7 ns Register or Latch Data Hold Time 0 0 ns tH tCO2 [9, 10] 12 Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output Delay (Through Logic Array) 16 ns tSCS[9] Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array) 7 10 ns tSL[9] Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable 9 12 ns tHL Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable 0 0 ns Product Term Clocking Parameters tCOPT[9, 10] Product Term Clock or Latch Enable (PTCLK) to Output tSPT Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) 3 3 ns Register or Latch Data Hold Time 3 3 ns tHPT tCO2PT [9, 10] Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) Notes: 8. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 9. Logic Blocks operating in low power mode, add tLP to this spec. 10. Outputs using Slow Output Slew Rate, add tSLEW to this spec. 5 13 19 13 21 ns ns PRELIMINARY CY37032V Switching Characteristics Over the Operating Range[8] (continued) 37032V-143 Parameter Max. 37032V-100 Description Min. Min. Max. Unit Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) 7 10 ns Pipelined Mode Parameters tICS[9] Operating Frequency Parameters fMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[6] 143 100 MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) 167 143 MHz fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)) 91 80 MHz fMAX4 Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 125 100 MHz 8 12 ns 10 14 ns Reset/Preset Parameters tRW tRR [9] tRO[9, 10] Asynchronous Reset Width[6] [6] Asynchronous Reset Recovery Time Asynchronous Reset to Output 14 [6] 18 ns tPW Asynchronous Preset Width 8 12 ns tPR[9] Asynchronous Preset Recovery Time[6] 10 14 ns tPO[9, 10] Asynchronous Preset to Output 14 18 ns User Option Parameters tLP Low Power Adder 4 4 ns tSLEW Slow Output Slew Rate Adder 2 2 ns JTAG Timing Parameters tS JTAG Set-Up time from TDI and TMS to TCK 0 0 20 ns tH JTAG Hold Time on TDI and TMS tCO JTAG Falling Edge of TCK to TDO 20 20 ns fJTAG Maximum JTAG Tap Controller Frequency 20 20 MHz 6 20 ns PRELIMINARY CY37032V Typical Icc Characteristics 30 H igh S peed 25 Low P ow e r Icc (mA) 20 15 10 5 0 0 20 40 60 80 10 0 12 0 14 0 Freq uen cy (M H z) The typical pattern is a 16 bit up counter, per logic block, with outputs disabled. Vcc = 3.3V, TA = Room Temperature 7 16 0 PRELIMINARY CY37032V Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT 37032V-12 Registered Output with Synchronous Clocking INPUT tS tH SYNCHRONOUS CLOCK tCO REGISTERED OUTPUT tCO2 REGISTERED OUTPUT tWH tWL SYNCHRONOUS CLOCK 37032V-13 Registered Output with Product Term Clocking Input Going Through the Array INPUT tSPT tHPT PRODUCT TERM CLOCK tCOPT REGISTERED OUTPUT tWH tWL PRODUCT TERM CLOCK 37032V-14 8 PRELIMINARY CY37032V Switching Waveforms (continued) Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT tISPT tIHPT PRODUCT TERM CLOCK tCO2PT REGISTERED OUTPUT tWH tWL PRODUCT TERM CLOCK 37032V-15 Latched Output INPUT tHL tSL LATCH ENABLE tPDL tCO LATCHED OUTPUT 37032V-16 Registered Input REGISTERED INPUT tIS tIH INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWL tWH CLOCK 37032V-17 9 PRELIMINARY CY37032V Switching Waveforms (continued) Clock to Clock INPUT REGISTER CLOCK tICS tSCS OUTPUT REGISTER CLOCK 37032V-18 Latched Input LATCHED INPUT tIS tIH LATCH ENABLE tPDL tICO COMBINATORIAL OUTPUT tWH tWL LATCH ENABLE 37032V-19 Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL INPUT LATCH ENABLE tHL tICS OUTPUT LATCH ENABLE tWL tWH LATCH ENABLE 37032V-20 10 PRELIMINARY CY37032V Switching Waveforms (continued) Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK 37032V-21 Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK 37032V-22 Output Enable/Disable INPUT tER tEA OUTPUTS 37032V-23 11 PRELIMINARY CY37032V Ordering Information Speed (MHz) 143 100 Ordering Code CY37032VP44-143AC Package Name Package Type A44 44-Pin Thin Quad Flatpack CY37032VP44-143JC J67 44-Pin Plastic Leaded Chip Carrier CY37032VP44-100AC A44 44-Pin Thin Quad Flatpack CY37032VP44-100JC J67 44-Pin Plastic Leaded Chip Carrier CY37032VP44-100AI A44 44-Pin Thin Quad Flatpack CY37032VP44-100JI J67 44-Pin Plastic Leaded Chip Carrier Operating Range Commercial Commercial Industrial In-System Reprogrammable, ISR, UltraLogic, Ultra37000, InSRkit, Warp, and Impulse3 are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. Document #: 38-00713-A Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 51-85064-B 12 PRELIMINARY CY37032V Package Diagrams (continued) 44-Lead Plastic Leaded Chip Carrier J67 51-85003-A (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.