M41T11M6TR - STMicroelectronics - searchdatasheet.com

1/24December 2004

M41T11

512 bit (64 bit x8) Serial Access TIMEKEEPER® SRAM

FEATURES SUMMARY

■2.0 TO 5 .5 V C L O C K O PER AT IN G VOLTAGE

■COUNTERS FOR SECONDS, MINUTES,

HOURS, DAY, DATE, MONT H, YEARS AND

CENTURY

■YEAR 2000 COMP LIANT

■SOFT WARE CLOCK CALIBRATION

■AUTOMATIC SWITCH-OVER AND

DESELECT CIRCUITRY

■I2C BUS C OMPATIBLE

■56 BYTES of GENERAL PUR PO SE RA M

■ULTRA-L OW BA TTERY SUPP LY CURRENT

OF 1µA

■LOW OP ER ATIN G CURRENT OF 300µA

■BATTERY OR SUPER- C AP BACK-UP

■BATTERY BA CK-UP NOT RECOM MENDED

FOR 3.0V APPLICATIONS (CAPACITOR

BACK-UP ONL Y)

■OP ERAT ING TEMPER ATURE OF –40 TO

85°C

■AUTOMAT IC L EAP YEAR C OMP EN SATION

■SPECIAL SOFTWARE PROGRAMMABLE

OUTPUT

■PACKAGING INCL UDES a 28-LEAD SOIC

and SNAPHAT® TOP (to be ordered

sep arately; 3.3V to 5.0V supply voltage only)

Figu re 1. 8- pi n S OI C Package

Figu re 2. 28- pi n S OI C Package

SO8 (M)

SNAPHAT (SH)

Battery & Crystal

SOH28 (MH)

M41T11

2/24

TABLE OF CONTENTS

FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 8-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. 28-pin SOIC Packag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUM MARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logi c Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signa l Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. 8-pin SOIC Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. 28-pin S O IC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2-Wire Bus Chara cteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Stop data transfe r.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Acknowl edge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. S erial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 8. A c knowledg eme nt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 9. B us Timing Requireme nts Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 10.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 12.Alternate READ Mode Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WRITE M ode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Re tention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Figure 13.WRITE Mode Seq uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK O PERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock C alibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Prefe rred Initial Power -on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 14.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 15.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Absolute Maximum Rati ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DC AND AC PARAM ETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Operating a nd AC Measurement Cond itions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3/24

M41T11

Figure 16.AC Testing Input/Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 17.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PACKAGE MECHANICAL INFORMATIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 18.SO8 – 8-lead Plastic Small Outline Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. SO8 – 8-lead Plast ic Small Outline Package M ec hanical Data. . . . . . . . . . . . . . . . . . . . 18

Figure 19.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT P ackage Out lin e . . . . . . . . 19

Table 12. SOH28 – 28-lea d Plastic Small Outline, Battery SNAPHAT Package Me ch . Data. . . . . 19

Figure 20.SH – 4-pin SNAPHA T Housing for 48mAh Ba ttery & Crystal Package Outline . . . . . . . 20

Table 13. SH – 4-pin SNAPHA T Housing for 48mAh Battery & Crystal, Package Mech. Data . . . . 20

Figure 21.SH – 4-pin SNAPHA T Housing for 120mAh B attery & Crystal, P ack age Ou tline . . . . . . 21

Table 14. SH – 4-pin SNAPHA T Housing for 120mAh Battery & Crystal, P ack age M ech. Data . . . 21

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. Ordering Inform ation Schem e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 16. SNAPHAT Battery Tab le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REVISION HISTO RY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 17. Document Re vision Histo ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

M41T11

4/24

S UM MARY DESCRIPTION

Th e M41T11 TIMEKEEPER® RAM is a low power

512-bit, static CMOS RAM organized as 64 words

by 8 bits. A built-in 32 .768kHz oscillator (exte rnal

crystal controlled) and the first 8 bytes of the RAM

are used for the clock/calendar function and are

configured in bina ry cod ed dec imal (BCD) form at.

Addresses and data are transferred serially via a

two-line bi-directional bus. The built-in address

write or read data byte.

The M41T11 clock has a built-in power sense cir-

cuit which detects power failures and automatical-

ly switches to the battery supply during power

failures. The energy needed to sustain the RAM

and clock operations can be s uppl ied from a sm all

lithiu m coin cell.

Typical data ret ent ion time is i n ex ces s of 5 years

with a 50mA/h 3V lithium cell . The M41T11 is sup-

plied in 8 lead Plast ic Small Outline pack age or 28

lead SNAPHAT® pack age.

The 28-pin, 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHA T housing cont ain-

ing the battery and crystal. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process. Inser-

tion of the SNAPHAT housing after reflow pre-

vents pote ntial b attery and crystal dam age due to

the high temperatures required for device surface-

mounting. The SNA PHAT housing is k ey ed to pre-

vent reverse i nsertion. The SOIC and batt er y/crys-

tal packages are shipped separ ately in plastic anti-

static tubes or in Tape & Reel form.

For the 28-lead SOIC, the battery/cry stal package

(i.e. SNAPHAT) part number is “M4Txx-BR12S H”

(see Table 16., page 22 ).

Caution: Do not place the SNAPHAT battery/crys-

tal package “M4T xx-BR12S H” i n conductive foam

since this wil l drain the lithium butt on-cell battery.

Figure 3. Logic Diagram Tabl e 1. Signal Names

AI01000

OSCI

VCC

M41T11

VSS

SCL

OSCO

SDA

FT/OUT

VBAT OSCI Oscillator Input

OCSO Oscillator Output

FT/OUT Frequency Test / Output Driver

(Open drain)

SDA Serial Data Address Input / Output

SCL Serial Clock

VBAT Battery Supply Voltage

VCC Supply Vo ltage

VSS Ground

5/24

M41T11

Figu re 4. 8- pi n S OI C Co nn e ct io ns Figu re 5. 28- pi n S O I C C onnecti ons

Figu re 6. Blo ck Diagram

SDAVSS SCL

FT/OUTOSCO

OSCI VCC

VBAT

AI01001

M41T11

AI03606

VSS

NC VCC

M41T11

NC NC

SDA

SCL

FT/OUT

AI02566

SECONDS

OSCILLATOR

32.768 kHz

VOLTAGE

SENSE

and

SWITCH

CIRCUITRY

SERIAL

BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

MINUTES

CENTURY/HOURS

DAY

DATE

MONTH

YEAR

CONTROL

RAM

(56 x 8)

OSCI

OSCO

FT/OUT

VCC

VSS

VBAT

SCL

SDA

1 Hz

M41T11

6/24

OPERATION

The M41T 11 clock operates as a s lave device on

the serial bus . Access is obtained by implementing

a start condition f ollowed by the correc t slave ad-

dress (D0h). The 64 bytes contained i n the device

can then be accessed sequentially in t he foll owing

order:

1. Seconds Register

2. Min utes Register

3. Centur y/Hours Regi ster

4. Day Register

5. D ate Register

6. Month Regist er

7. Yea rs Register

8. Control Register

9 to 64.RAM

The M41T11 clock c ont inually monitors VCC for an

out of tolerance condition. Should VCC fall below

VSO, the de vice te rminates an ac ces s in progress

and resets the device address counter. Inputs to

the device will not be recognized at this time to

prevent erroneous data from being written to the

device from an out of tolerance system. When VCC

falls below VSO, the device automatically switches

over to the battery and powers down into an ultra

low current m ode of operation to conserve batt ery

life. Upon power-up, the devi ce swit ches from bat-

tery to VCC at VSO and recognizes inputs.

2-Wire Bus Characteristics

This bus is intended for communication between

different ICs. It c onsists of t wo lines: one bi-direc-

tional f or dat a si gnals (SDA) and one for clock sig-

nals (SCL). Both the SDA and the SCL lines must

be connected to a positive supply voltage via a

pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the bus

is not busy.

– During dat a transfer, the data line m ust rema in

stable whenever the clock line is High.

– Changes in the data line while the clock line is

High will be i nterpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer . A change in the state of the

data li ne, from Hi gh to Low, while t he clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data valid. The state of the data line represents

valid data when after a start condition, the dat a line

is stable for the duration of the High period o f the

clock signal. T he data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condi tion

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver ack nowl-

edges with a ninth bit.

By definition, a device t hat gives out a message is

called “transmitter”, the receiving device t hat g ets

the message is called “receiver”. The device that

controls the message is called “master”. The de-

vices that are controlled by th e ma ster are called

“slaves”.

Acknowledge. E ac h byte of eig ht bits is foll owed

by one Acknowledge B it. Thi s Acknowledge Bit is

a low level put on the bus by the receiver, whereas

the master generates an extra ac knowled ge relat-

ed clock pulse.

A slave receiver which is a ddressed is obliged to

generate an acknowledge after the reception of

each byte. Also, a master receiver must generate

an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times mus t

be taken int o account. A master recei ver must sig-

nal an end-of-data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. I n this case, the

transmitter must l eave the data l ine High to enable

the mast er to generate the S TOP condition.

7/24

M41T11

Figure 7. Serial Bus Data Transfer Sequen ce

Figure 8. Acknowledgement Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

M41T11

8/24

Figure 9. Bus Timing Requirements Sequence

Note : P = ST O P and S = START

Table 2. AC Characteristics

Note: 1. Valid for Ambien t Operat in g T em pera t ure: TA = –40 to 85°C; VCC = 2. 0 t o 5.5V (e xcept where noted).

2. Transmitter must intern ally provide a h old time to bridge the undefined region (300ns max.) of the falling edge of SCL.

Symbol Parameter(1) Min Max Unit

fSCL SCL Clock Frequency 0 100 kHz

tLOW Clock Low Period 4.7 µs

tHIGH Clock High Period 4 µs

tRSDA and SCL Rise Time 1 µs

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 4µs

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 4.7 µs

tSU:DAT Data Setup Time 250 ns

tHD:DAT(1) Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 4.7 µs

tBUF Time the bus must be free before a new transmission can start 4.7 µs

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

9/24

M41T11

READ Mode

In this mode, the mast er rea ds the M41T 11 slave

after setting the slave address (see Figure 10).

Following the write Mode Cont rol Bit (R/W = 0) and

the Ackno wledge B it, the word address An is w rit-

ten to the on-chip address pointer. Next the

START condit ion and slave address are repeated,

followed by the READ Mode Control Bit (R/W =1).

At this point, the master transmitter becomes the

master receiver. The data byte which was ad-

dressed will be transm itted and the mas ter receiv-

er will send an Acknowledge Bit to the slave

transmitter. The address point er is only increment-

ed on reception of an Acknowledge Bit. The

M41 T11 slave transmitter will now pl ace the data

byte at address An + 1 on the bus. The maste r re-

ceiver reads and ackno wledge s the n ew by te and

the addres s pointer is incremented to An + 2.

This cycle of reading consecutive addresses will

continue until the master receiver se nds a STOP

condition to the slave transmitter.

An alternate READ mode may al so be implement-

ed, whereby the master reads the M41T11 slave

without first w ri tin g to the (volatile) addres s point-

er. The first address that is read is the last one

stored in the p ointer (see Figure 12. , page 10).

Figure 10. Slave Address L ocation

Figure 11. RE AD Mode Se qu e nce

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

M41T11

10/24

Figu re 12 . Al te rnat e R E A D Mo de S equence

WRITE Mod e

In this mode the master transmitter transmits to

the M41T11 slav e receiver. Bus prot ocol is shown

in Figure 10. Following the START condition and

slave address, a logic '0' (R/W = 0) is placed on the

bus and indicates to the addressed device that

word addres s A n will follow and is to be written t o

the on -chi p address pointer. The data word t o be

written t o the memory is strobed in next and the in-

ternal address pointer is incremented to the next

memory location within the RAM on the reception

of an acknowledge clock. The M41T11 slave re-

ceiver will send an acknowledge clock to the mas-

ter transmitter after it has received the slave

address and again after it has received the word

address and each data byte (see Figure

9., page 8).

Data Reten tion Mode

With valid VCC applied, the M41T11 can be ac-

cessed as d escribed a bove with read or write cy-

cles. Should the supply voltage decay, the

M41 T11 will aut oma tical ly des ele ct, writ e prot ect-

ing itself when V CC falls (see Fig ure 17).

Figure 13. WRI TE Mode Se qu e nce

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

11/24

M41T11

C LOCK OP ERATION

The eight byte clock register (see Table 3) is used

to both set t he clock and to read the date and time

from the clock, in a bin ary coded decimal format.

Seconds, Minutes, and Hours are c ont ained within

the first three registers. Bits D6 and D7 of clock

ENABLE Bit (CEB) and the CENTURY Bit (CB).

Setting CEB to a '1' will cause CB to toggle, either

from ' 0' to '1' or from '1' to ' 0' at the turn of the cen-

tury (depending upon i ts initial state). I f CEB is set

to a '0', CB will not toggle. Bits D0 through D2 of

4, 5 and 6 contain the Date (day of month), Month

and Years. The f inal registe r is the C ontrol Regis-

ter (this is described in the Clock Calibration sec-

tion). Bit D7 of register 0 contains the STOP Bit

(ST). Setting this bit to a '1' will cause the oscillator

to stop. If the device is expected to spend a signif -

icant amount of time on the shelf, the oscillator

may be stopped to reduce current drain. When re-

set to a '0' the oscillator restarts within one second.

Note: In order to guarantee oscillator start-up after

the initial power-up, set the ST Bit to a '1,' then re-

set this bit to a '0.' This sequence enabl es a “kick

start” circuit which aids the o sc illator start-up dur-

ing worst case c ondition s of voltage and tem pera-

ture.

The seven Clock Registers may be read one byte

at a time, or in a sequential block. The Control

dependently. Provision has been made to assure

that a cloc k update does not occur while any of the

seven clock addresses are being read. If a clock

address is being read, an update of t he clock reg-

isters will be delayed by 250ms to allow the read

to be completed before the update occurs. This

will pr ev e nt a trans it io n o f data du r ing t he re a d.

Note: This 250ms del ay affec ts only the clock reg-

ister update and does not alter the actual clock

time.

Table 3. Register Map

Keys: S = SIGN Bit

FT = FREQUENCY TEST Bit

ST = STOP Bit

OUT = Output level

X = Do n’t care

CE B = C entury Enable Bit

CB = Centur y Bi t

Note: 1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the in itial value set).

When CEB is s et to '0', CB will no t toggle.

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 Seconds Seconds Seconds 00-59

1 X 10 Minutes Minutes Minutes 00-59

2CEB (1) CB 10 Hours Hours Century/Hours 0-1/00-23

3 XXXXX Day Day 01-07

4 X X 10 Date Date Date 01-31

5 X X X 10 M. Month Month 01-12

6 10 Years Years Year 00-99

7 OUT FT S Calibration Control

M41T11

12/24

Clock Calibration

The M41T11 i s driven by a quartz controlled oscil-

lator with a nominal frequency of 32,768Hz. The

devices are tested not to exceed 35 ppm (part s per

million) oscillator frequency error at 25°C, which

equates to about ±1.53 minutes per month. With

the calibration bits properly set, the accuracy of

each M41T11 improves to better than ±2 ppm at

25°C.

The oscillation rate of any crystal changes with

temperature (see Figure 14., page 13). Most clo ck

chips compensate for crystal frequency and tem-

perature shift error with cumbersome tr im capaci-

tors. The M41T11 design, however, employs

periodic count er corre ction. The cal ibration circuit

adds or subtracts counts from the oscillator divider

circuit at the divide by 256 stage, as shown in Fig-

ure 15., page 13 . T he num ber of ti me s pulses are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five-bit Calibration byte found

in the Control Register. Adding counts speeds the

clock up, subtracting count s slows the clock down.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control register (Addr 7). This

byte can be s et t o represent any value betwee n 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64minute

cycle. The firs t 62 minutes i n the cycle m ay, once

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minutes in the 64 minute cycle will b e modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibration register. Assum ing that

the oscillator is in fact running at exactly 32,768Hz ,

each of the 31 increments in the Calibration byte

would represent +10.7 or –5.35 seconds per

month which c orresponds to a total range of +5.5

or –2.75 minutes per month.

Two methods are available for ascertaining how

much calibration a given M41T11 may require.

The first involves simply setting the clock, l etting it

run for a month and compari ng i t to a known accu-

rate reference (like WWV broadcasts). While that

may seem crude, it allows the designer to give the

end user the abi lity t o cali brate his clock as hi s en-

vironment may require, even after the final product

is p acka ged in a non-user service able enclosure.

All the designer has to do is provide a simpl e utility

that accessed the Calibration byte.

The second approach is better suited to a m anu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) Bit, the seventh-most significant bit in the

Control Register, is set to a '1', and the oscillator is

running at 32,768Hz, the FT/OUT pin of the device

will toggle at 512Hz. Any deviation from 512Hz in-

dicates the degree and direction of oscillator fre-

quency shif t at the test temperature.

For example , a reading o f 512 .01024Hz woul d in-

dicate a +20 ppm oscillator frequency error, requir-

ing a –10(XX001010) to be loaded into the

Calibration Byte for correction. Note that setting or

changing the Calibration Byte does not affect the

Frequenc y test output frequency.

Output Driver Pin

When the FT Bit is not set, the FT/OUT pin be-

comes an output driver that reflects the contents of

D7 of the control register. In other words, when D6

of location 7 is a zero and D7 of location 7 is a zero

and then the FT/OUT pin will be driven low.

Note: The FT/OUT pin is open drain which re-

quires an external pull-up resistor.

Preferred I nit ia l Power-on Defaults

Upon initial application of power to the device, the

FT Bit will be set to a '0' and the OUT Bit will be set

to a '1'. All other Register bits will initial ly power-on

in a random state.

13/24

M41T11

Figure 14. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 15 . Cl ock C al ib r at i on

AI00999b

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= K x (T –TO)2

K = –0.036 ppm/°C2 ± 0.006 ppm/°C2

TO = 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41T11

14/24

MAXI MUM RAT IN G

Stressing the device above t he rating l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 4. Absolute Maximum Ratings

Note: 1. F or S O packag e, s tandard (SnPb) lead fini sh: Re flow at pe ak t emperature of 225°C (total thermal budget not to excee d 180°C for

betw een 90 t o 150 sec o nds) .

2. F or S O package, Lead-free (Pb-free) lead finish: Reflow at p eak temperatu re of 260 °C (total thermal budget not to exceed 245°C

for greater than 30 seconds).

CAUTION: N egative undershoots be l ow –0.3V are not allowed on any pin while in the Batt ery B ack- up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPH AT so ckets.

Symbol Parameter Value Unit

TAAmbient Operating Temperature –40 to 85 °C

TSTG Storage Temperature (VCC Off, Oscillator Off SNAPHAT®–40 to 85 °C

SOIC –55 to 125

TSLD (1) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltages –0.3 to 7 V

VCC Supply Voltage –0.3 to 7 V

IOOutput Current 20 mA

PDPower Dissipation 0.25 W

15/24

M41T11

DC AND AC PARAM ETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests pe rf ormed unde r t he Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 5. Operating and AC Measurem en t Conditions

Note: Output Hi -Z is defi n ed as the poi nt where data is no l onger dri ven.

1. Supply V ol t age for SO H28 is 3.3V to 5.5V.

Figu re 16. AC Tes ti ng I np ut / Output Waveform

Table 6. Capacitance

Note: 1. Ef fectiv e capacit ance me asured wi t h powe r supply at 5V; sampled only , not 100% te sted.

2. At 25°C, f = 1M Hz.

3. Outputs deselect ed.

Parameter M41T11 Unit

Supply Vo ltage (VCC)2.0 to 5.5(1) V

Ambient Operating Temperature (TA)–40 to 85 °C

Load Capacitance (CL)100 pF

Input Rise and Fall Times ≤ 50 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC V

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance (SCL) 7 pF

COUT(3) Output Capacitance (SDA, FT/OUT) 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 250 1000 ns

M41T11

16/24

Table 7. DC Characteristics

Note: 1. Valid for Ambien t Operat in g T em pera t ure: TA = –40 to 85°C; VCC = 2. 0 t o 5.5V (e xcept where noted).

2. STM i croelectro ni cs recom m ends the R AYOVAC BR1225 or BR1632 (or equivalent) as the batt ery sup pl y.

3. Af t er switc hover (V SO), VBAT(m i n) can be 2. 0V for crystal w i th RS = 40KΩ.

4. F or rechargeable back-up, VBAT(max) may be c o nside red VCC.

Table 8. Crystal Electrical Characteristics

Note: 1. These values are externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/

1TC 252E1 27, Tunin g Fo rk Type (t hru- hole ) o r the DM X-26 S: 1 TJS1 25F H2A2 12, ( S MD) qu art z c rysta l fo r in dus trial te mper atur e

operations. KDS can be contacted at kouhou@kdsj.co.jp or htt p://ww w.kdsj.co.jp fo r furthe r i nformation on this cryst a l ty pe.

2. Load capacitor s are integrated wi thin the M41T1 1. Circuit board layout considerations for the 32.768kHz cry stal of mi ni m um trace

leng ths and isolation f rom RF gen erating signals should be ta ken into accoun t.

3. All SNAPHAT® battery /cryst al tops meet these spe cificat i ons.

Symbol Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Switch Frequency = 100kHz 300 µA

ICC2 Supply Current (Standby) SCL, SDA = VCC – 0.3V 70 µA

VIL Input Lo w Voltage –0.3 0.3VCC V

VIH Input High Voltage 0.7VCC VCC + 0.5 V

VOL Output Low Voltage IOL = 3mA 0.4 V

Pull-up Supply Voltage

(Open Drain) FT/OUT 5.5 V

VBAT(2) Battery Supply Voltage 2.5(3) 33.5(4) V

IBAT Battery Supply Current TA = 25°C, VCC = 0V,

Oscillator ON, VBAT = 3V 0.8 1 µA

Symbol Parameter(1,2,3) Min Typ Max Unit

fOResonant Frequency 32.768 kHz

RSSeries Resistance 60 kΩ

CLLoad Capacitance 12.5 pF

17/24

M41T11

Figure 17. Power Down /U p Mode AC Waveform s

Table 9. Power Down/U p AC Characteri stics

Note: 1. Valid for Ambien t Operat in g T em pera t ure: TA = –40 to 85°C; VCC = 2. 0 t o 5.5V (e xcept where noted).

2. VCC f al l tim e should not exceed 5mV/µs.

Table 10. Power Down/U p Trip Points DC Characteristic s

Note: 1. Valid for Ambien t Operat in g T em pera t ure: TA = –40 to 85°C; VCC = 2. 0 t o 5.5V (e xcept where noted).

2. All voltages re ferenced to VSS.

3. In 3.3V applic ation, if initial ba ttery voltage is ≥ 3 .4V, it ma y be ne ce ssar y to re duce b atte ry vo lta ge (i .e., th ro ugh wav e sol d erin g

the bat tery) in o rder to avo i d i nadvert ent swit chover /deselection f or VCC – 10% op eration.

4. Sw i tch-over and deselect point.

Symbol Parameter(1) Min Max Unit

tPD(2) SCL and SDA at VIH before Power Down 0ns

tREC SCL and SDA at VIH after Power Up 10 µs

Symbol Parameter(1,2) Min Typ Max(3) Unit

VSO(4) Battery Back-up Switchover Voltage VBAT – 0.80 VBAT – 0.50 VBAT – 0.30 V

AI00596

VCC

tREC

tPD

VSO

SDA

SCL DON'T CARE

M41T11

18/24

P ACKAGE MECHANICAL INFO RMATION

Figure 18. SO8 – 8-l ead P lastic S mal l Out l ine Package Outline

No te : Drawing is not to scale.

Table 11. SO8 – 8-lead Plastic Small Outline Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27– –0.050– –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

SO-a

LA1 α

h x 45˚

19/24

M41T11

Figure 19. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT Packag e Outlin e

No te : Drawing is not to scale.

Table 12. SOH28 – 28-lead Plastic Small Outl ine, Battery SNAPHAT Package Mech. Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N 28 28

CP 0.10 0.004

SOH-A

LA1 α

M41T11

20/24

Figure 20. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal Package Outline

No te : Drawing is not to scale.

Table 13. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, P ack age M ech. Data

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

21/24

M41T11

Figure 21. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

No te : Drawing is not to scale.

Table 14. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech . Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-B

A1 A

M41T11

22/24

PART NUMBERING

Table 15. Ordering Information Scheme

Note: 1. SOH28 Su pply Voltage is 3. 3V to 5.5V.

2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under the part number “M4Txx-

BR12SHx” i n pl astic tube or “M4 T xx-BR12SHxTR” in Ta pe & Reel fo rm (see Tabl e 16).

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-

tery.

For other options, or for more information on any aspec t of t his device, pl ease contact the ST Sales Of fice

nearest you.

Table 16. SNAPHAT Battery Table

Example: M41T 11 M 6 E

Device Type

M41T

Supply Voltag e

11 = VCC = 2.0 to 5.5V(1)

Package

M = SO8 (150mil width)

MH(2) = SOH28

Temperature Range

6 = –40 to 85°C

Shipping Method

For SO8:

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

For SOH28:

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

23/24

M41T11

REVISION HISTORY

Table 17. Document Revi sion History

M41T11, 41T11, T11, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,

NVR AM, N VRAM , NVR AM, N VRAM , NVRAM , NVR AM, NVRAM , NVRAM , NV RAM, NVRA M, NVRA M, NV RAM, NVRA M, NV RAM, NV RAM, NVRA M, NV RAM, NVRA M,

NVRAM, NVRA M, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRA M, NVRAM, NVRAM, NV RAM, NVRA M, NVRAM, NVRAM, NV RAM, TIME-

KEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, T IM EKEEPER, TIMEKEEPER, TIMEKEEPER , TIMEKEEPER, TIMEKEEPER,

TIMEKEEPER, TIMEKEE PER, TIMEKEEPER, TIMEKEEPER, TIMEKEEP ER, TIMEKE EPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIME KEEPER, TIME-

KEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, Serial, Serial, Serial, Serial , Serial, Serial, Serial, Serial, Serial, Serial, Seri al, Serial , Ser ial , S eri al, Se rial, Serial,

Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, S eria l, S er ial, Seri al, Se rial, Seria l, Ser ial, Seri al, Se rial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,

Serial, Serial, Se rial, S er ial, Serial, Serial, Serial, Ser ial, Serial, Seria l, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, A c-

cess, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access,

Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-

cess, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access,

Access, Access, Access, Access, Access, SRAM, SRAM , SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SR AM, SRAM, SRAM, SRAM, SRAM , SR AM,

SRAM , SRAM , SRA M, S RA M, SR AM, SRAM, SRAM, SRAM , SR AM, SRA M, S RAM, SR AM, SRAM, SRAM, SRAM , SR AM, SRA M, S RAM, SR AM, SRAM, SRAM,

SRAM , SRAM, SRAM, SR AM, SRA M, SRAM , SR AM, SRAM, I2C , I2C, I2C , I2C, I2C , I2C, I2C , I2C, I2C , I2C, I2C, I2C, I2C, I2C , I2C, I2C , I2C, I2C, I2C, I2C, I2C, I2C,

I2C, I2C, I2C, I2C , I2 C, I2C , I2C, I2 C, I2C , I2C, I2 C, I2C, I2C, I2 C, I2C, I2C, I2 C, I2C, I2C , I2 C, I2C, I2C , I2 C, Lea p year, L eap y ear , Le ap year , Le ap y e ar , Le ap ye ar ,

softwa re, sof tw ar e, so ftwar e , soft war e, so ftw are, softw a re, sof tw are, so ftw are, s oft ware, s of twar e, so ftwar e , soft war e, so ftw are, softw a re, s of twar e, so ftwar e, soft ware ,

softwar e, software, software , software, software, software , software, software, software, software, software , software, software, soft ware, software, so ftware, clock,clock,

clock, clock, clock, clock, clock, clock, clock, clo ck, clock, clock, clock, clock, clock, clock, clock, clo ck, clock, clock, clock, clock, clock, clock, clock, clock, clock, clo ck,

clock, clo ck, clo ck, clock, Microprocessor, Microprocessor, M icroprocessor, Micr op ro cessor, M icroprocessor, Micr op rocessor, M icro processor, Micr oprocessor, Micro-

processor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, M icroprocessor, Microprocessor, Microprocessor, Microprocessor, Micro-

processor, Microprocessor, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial,

Industrial, Industrial, Tem perature, Temperature, Tem perature, T emperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Tem-

perature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature,

Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature , T em p er ature, T emper a-

ture, T emp erature , T emperature , T emp erature, T emp erature, Temperature, Tem per ature, Wri te Protec t, Write Protect, Write Prote ct, Write Pro tect, Write Protect, Write

Protect, W ri te Pr otect, Wri te Protec t, Wri te Prote c t, W r it e Pr ot ec t, Wri te Protect, W ri te Protec t, W r it e Pr o tec t, Wri te Protect, Write Protect, Write Protect, Write Protect,

W r i te Protec t, Write Protect, Writ e Pro tect, Writ e Pr otect, Wri te Protec t, Wri te Protec t, Write Protect, Writ e Protect , Power-fail, Power-fail, Power-fail, Power-fail, Power-

fail, Power-fail, Power-fail, Powe r-fail, Power-f ail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Com para tor, C ompa rator , Comp ara tor,

Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Compar-

at or, Co mpara tor , Comp arat or, Co mpar ator, Comp arat or, C ompa rator, Com para tor, Compa rat or, Co mpara tor , Comp arator, Co mpar ator, Comparator, Comparator, Com-

parator , Comp arator, Battery , Batt ery, Batte ry, Bat tery, Ba ttery, Battery, B atter y, Batte ry, Bat tery, B attery , Battery, B atter y, Batte ry, Bat tery, B attery , Batte ry , Bat tery,

Battery, Batter y, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, Battery, Back-up, Back-up, Back-up, Back-up, Back-up, Back-up, Back-up, Back-up, Ba ck-u p, Back-up, B ack- up, Back- up, Ba ck-up, Back-up, Ba ck-up,

Back- u p, Ba ck -u p, Bac k-u p, Bac k- up , Back -up, SNAPHAT , SNA PH AT, SN AP HA T , SN APHAT , SN AP H AT, SN APH A T, SNAPH AT , SN AP HA T, SN APH AT, SNAPHAT,

SNAPH A T, SNAPH AT , SNAPHAT, SN APH AT , SNA PHAT , SN AP HA T, SN APH AT, SNAPH AT, SN AP HA T , SN APHAT , SN A PH AT, SN AP HA T, SNAPH AT , SNAPHAT,

SNAPHAT, SNAPHAT, SNAPH AT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPH AT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SO-

IC, SOIC, SOIC, SOIC , SOIC, SOIC , SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,

5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5 V , 5V, 2V, 2V, 2V, 2V, 2V, 2 V, 2V, 2V, 2V, 2V, 2V,

2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V , 2V, 2V, 2V, 2V, 2V

Date Version Revision Details

March 1999 1.0 First Issue

12/23/99 1.1 SOH28 package added

07/25/00 1.2 Crystal Electrical Characteristics: RS Max changed (Table 8)

12/12/00 1.3 Edit VSO (Table 10)

01/24/01 2.0 Reformatted

2/27/01 3.0 Document Status changed

07/17/01 3.1 Change to DC and AC Characteristics (Tables 7, 2); added temp/voltage info. to tables

(Table 6, 7, 8, 2, 9, 10); added SNAPHAT Battery table (Table 16).

11/27/01 3.2 Features, (page 1); DC Characteristics (Table 7); Crystal Electrical (Table 8); Power Down/

Up Trip Points (Table 10) changes; add table footnotes (Table 5, 10, 15)

01/21/ 02 3.3 Fix table footn otes (Table 7, 8)

05/01/02 3.4 Modify reflow time and temperature footnote (Table 4)

07/03/02 3.5 Modify “Clock Operation” text, Crystal Electrical Characteristics table footnote (Table 8)

11/07/02 3.6 Correct figure name (Figure 1)

15-Jun-04 4.0 Reformatted; added Lead-free information; updated characteristics (Figure 14; Table 4, 7,

15)

14-Dec-04 5.0 Correct footnote (Table 8)

M41T11

24/24

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